Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index ff8d2d7..ce12c3b 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -409,7 +409,7 @@
The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */
/* Delay between EEPROM clock transitions.
- No extra delay is needed with 33Mhz PCI, but future 66Mhz
+ No extra delay is needed with 33MHz PCI, but future 66MHz
access may need a delay. */
#define eeprom_delay(ee_addr) INL(dev, ee_addr)
diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c
index a2d61af..198f73d 100644
--- a/drivers/net/ns8382x.c
+++ b/drivers/net/ns8382x.c
@@ -445,7 +445,7 @@
Read and write MII registers using software-generated serial MDIO
protocol. See the MII specifications or DP83840A data sheet for details.
- The maximum data clock rate is 2.5 Mhz. To meet minimum timing we
+ The maximum data clock rate is 2.5 MHz. To meet minimum timing we
must flush writes to the PCI bus with a PCI read. */
#define mdio_delay(mdio_addr) INL(dev, mdio_addr)
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index d378ce3..db8a727 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -287,7 +287,7 @@
/*
Delay between EEPROM clock transitions.
- No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
+ No extra delay is needed with 33MHz PCI, but 66MHz may change this.
*/
#define eeprom_delay() inl(ee_addr)
diff --git a/drivers/net/tigon3.c b/drivers/net/tigon3.c
index ab448b0..e4e004e 100644
--- a/drivers/net/tigon3.c
+++ b/drivers/net/tigon3.c
@@ -2247,7 +2247,7 @@
REG_WR (pDevice, Grc.Mode, Value32);
/* Setup the timer prescalar register. */
- REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */
+ REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66MHz. */
/* Set up the MBUF pool base address and size. */
REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
