commit 9aea95307fdb0ffe0d3a98a17ac73e5040c9756a
author wdenk <wdenk> Sun Aug 01 23:02:45 2004 +0000
committer wdenk <wdenk> Sun Aug 01 23:02:45 2004 +0000
tree 812e59d74bb6ab942f7c797b6bbcc5e7c2ad4a8f
parent 281e00a3be453a169d854f824a460359d10f92bb

Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
  STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads

cpu/mpc85xx/pci.c

diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 11f0c3e..60c1e61 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -32,34 +32,10 @@
 
 #if defined(CONFIG_PCI)
 
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc85xxads_config_table[] = {
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
-	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
-				     PCI_ENET0_MEMADDR,
-				     PCI_COMMAND_MEMORY |
-				     PCI_COMMAND_MASTER}},
-	{}
-};
-#endif
-
-struct pci_controller local_hose = {
-#ifndef CONFIG_PCI_PNP
-	config_table: pci_mpc85xxads_config_table,
-#endif
-};
-
-
-void pci_init_board (void)
+void
+pci_mpc85xx_init(struct pci_controller *hose)
 {
-	struct pci_controller *hose = (struct pci_controller *) &local_hose;
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
 	volatile ccsr_pcix_t *pcix = &immap->im_pcix;
 
 	u16 reg16;
@@ -67,39 +43,45 @@
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
 
-	pci_set_region (hose->regions + 0,
-			CFG_PCI1_MEM_BASE,
-			CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI1_MEM_BASE,
+		       CFG_PCI1_MEM_PHYS,
+		       CFG_PCI1_MEM_SIZE,
+		       PCI_REGION_MEM);
 
-	pci_set_region (hose->regions + 1,
-			CFG_PCI1_IO_BASE,
-			CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI1_IO_BASE,
+		       CFG_PCI1_IO_PHYS,
+		       CFG_PCI1_IO_SIZE,
+		       PCI_REGION_IO);
 
 	hose->region_count = 2;
 
-	pci_setup_indirect (hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
+	pci_setup_indirect(hose,
+			   (CFG_IMMR+0x8000),
+			   (CFG_IMMR+0x8004));
 
-	pci_read_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, &reg16);
+	pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
 	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, reg16);
+	pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
 
 	/*
 	 * Clear non-reserved bits in status register.
 	 */
-	pci_write_config_word (PCI_BDF (0, 0, 0), PCI_STATUS, 0xffff);
-	pci_write_config_byte (PCI_BDF (0, 0, 0), PCI_LATENCY_TIMER, 0x80);
+	pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+	pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
 
-	pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
-	pcix->potear1 = 0x00000000;
-	pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+	pcix->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+	pcix->potear1  = 0x00000000;
+	pcix->powbar1  = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
 	pcix->powbear1 = 0x00000000;
-	pcix->powar1 = 0x8004401c;	/* 512M MEM space */
+	pcix->powar1   = 0x8004401c;	/* 512M MEM space */
 
-	pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
-	pcix->potear2 = 0x00000000;
-	pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
+	pcix->potar2   = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
+	pcix->potear2  = 0x00000000;
+	pcix->powbar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
 	pcix->powbear2 = 0x00000000;
-	pcix->powar2 = 0x80088017;	/* 16M IO space */
+	pcix->powar2   = 0x80088017;	/* 16M IO space */
 
 	pcix->pitar1 = 0x00000000;
 	pcix->piwbar1 = 0x00000000;
@@ -108,8 +90,8 @@
 	/*
 	 * Hose scan.
 	 */
-	pci_register_hose (hose);
-	hose->last_busno = pci_hose_scan (hose);
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
 }
 
 #endif /* CONFIG_PCI */