Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
  STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads

include/e500.h

diff --git a/include/e500.h b/include/e500.h
index 5489ba2..8e3bf8c 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -20,14 +20,29 @@
  * initial memory mapping like legacy BAT registers do. Usually we
  * use four MAS registers(MAS0-3) to operate on TLB1 entries.
  *
+ * While there are 16 Entries with variable Page Sizes in TLB1,
+ * there are also 256 Entries with fixed 4K pages in TLB0.
+ *
  * We also need LAWs(Local Access Window) to associate a range of
  * the local 32-bit address space with a particular target interface
  * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
  *
  * We put TLB1/LAW code here because memory mapping is board-specific
  * instead of cpu-specific.
+ *
+ * While these macros are all nominally for TLB1 by name, they can
+ * also be used for TLB0 as well.
  */
 
+
+/*
+ * Convert addresses to Effective and Real Page Numbers.
+ * Grab the high 20-bits and shift 'em down, dropping the "byte offset".
+ */
+#define E500_TLB_EPN(addr)	(((addr) >> 12) & 0xfffff)
+#define E500_TLB_RPN(addr)	(((addr) >> 12) & 0xfffff)
+
+
 /* MAS0
  * tlbsel(TLB Select):0,1
  * esel(Entry Select): 0,1,2,...,15 for TLB1