Merge branch 'master' of git://git.denx.de/u-boot-samsung
diff --git a/MAINTAINERS b/MAINTAINERS
index 9485070..4b91b0f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -262,10 +262,6 @@
debris MPC8245
KVME080 MPC8245
-Thomas Lange <thomas@corelatus.se>
-
- GTH MPC860
-
Robert Lazarski <robertlazarski@gmail.com>
ATUM8548 MPC8548
@@ -428,6 +424,7 @@
sc3 PPC405GP
suen3 ARM926EJS (Kirkwood SoC)
uc101 MPC5200
+ ve8313 MPC8313
Peter De Schrijver <p2@mind.be>
@@ -447,6 +444,7 @@
MPC8349E-mITX MPC8349
MPC8349E-mITX-GP MPC8349
+ P1022DS P1022
Erik Theisen <etheisen@mindspring.com>
@@ -490,6 +488,10 @@
JSE PPC405GPr
+Ilya Yanok <yanok@emcraft.com>
+
+ MPC8308RDB MPC8308
+
Roy Zang <tie-fei.zang@freescale.com>
mpc7448hpc2 MPC7448
@@ -550,7 +552,7 @@
Dirk Behme <dirk.behme@gmail.com>
- omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC)
+ omap3_beagle ARM ARMV7 (OMAP3530 SoC)
Eric Benard <eric@eukrea.com>
@@ -616,11 +618,11 @@
Vaibhav Hiremath <hvaibhav@ti.com>
- am3517_evm ARM CORTEX-A8 (AM35x SoC)
+ am3517_evm ARM ARMV7 (AM35x SoC)
Grazvydas Ignotas <notasas@gmail.com>
- omap3_pandora ARM CORTEX-A8 (OMAP3xx SoC)
+ omap3_pandora ARM ARMV7 (OMAP3xx SoC)
Gary Jennejohn <garyj@denx.de>
@@ -650,12 +652,12 @@
Minkyu Kang <mk7.kang@samsung.com>
- s5p_goni ARM CORTEX-A8 (S5PC110 SoC)
- SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
+ s5p_goni ARM ARMV7 (S5PC110 SoC)
+ SMDKC100 ARM ARMV7 (S5PC100 SoC)
Frederik Kriewitz <frederik@kriewitz.eu>
- devkit8000 ARM CORTEX-A8 (OMAP3530 SoC)
+ devkit8000 ARM ARMV7 (OMAP3530 SoC)
Sergey Kubushyn <ksi@koi8.net>
@@ -680,8 +682,8 @@
Nishanth Menon <nm@ti.com>
- omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC)
- omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
+ omap3_sdp3430 ARM ARMV7 (OMAP3xx SoC)
+ omap3_zoom1 ARM ARMV7 (OMAP3xx SoC)
David Müller <d.mueller@elsoft.ch>
@@ -719,7 +721,7 @@
Manikandan Pillai <mani.pillai@ti.com>
- omap3_evm ARM CORTEX-A8 (OMAP3xx SoC)
+ omap3_evm ARM ARMV7 (OMAP3xx SoC)
Stelian Pop <stelian.pop@leadtechdesign.com>
@@ -731,7 +733,7 @@
Tom Rix <Tom.Rix@windriver.com>
- omap3_zoom2 ARM CORTEX-A8 (OMAP3xx SoC)
+ omap3_zoom2 ARM ARMV7 (OMAP3xx SoC)
John Rigby <jcrigby@gmail.com>
@@ -750,7 +752,9 @@
Steve Sakoman <sakoman@gmail.com>
- omap3_overo ARM CORTEX-A8 (OMAP3xx SoC)
+ omap3_overo ARM ARMV7 (OMAP3xx SoC)
+ omap4_panda ARM ARMV7 (OMAP4xx SoC)
+ omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC)
Jens Scharsig <esw@bus-elektronik.de>
@@ -869,9 +873,6 @@
PCI5441 Nios-II
PK1C20 Nios-II
- EP1C20 Nios-II
- EP1S10 Nios-II
- EP1S40 Nios-II
nios2-generic Nios-II
#########################################################################
@@ -998,6 +999,8 @@
BF548-EZKIT BF548
BF561-EZKIT BF561
+ BF527-AD7160-EVAL BF527
+
Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
diff --git a/MAKEALL b/MAKEALL
index 4637390..2133559 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -118,7 +118,6 @@
GEN860T \
GEN860T_SC \
GENIETV \
- GTH \
hermes \
IAD210 \
ICU862_100MHz \
@@ -360,6 +359,7 @@
LIST_83xx=" \
caddy2 \
kmeter1 \
+ MPC8308RDB \
MPC8313ERDB_33 \
MPC8313ERDB_NAND_66 \
MPC8315ERDB \
@@ -380,6 +380,7 @@
sbc8349 \
SIMPC8313_LP \
TQM834x \
+ ve8313 \
vme8349 \
"
@@ -408,6 +409,7 @@
MPC8569MDS_NAND \
MPC8572DS \
MPC8572DS_36BIT \
+ P1022DS \
P2020DS \
P2020DS_36BIT \
P1011RDB \
@@ -644,9 +646,9 @@
"
#########################################################################
-## ARM Cortex-A8 Systems
+## ARMV7 Systems
#########################################################################
-LIST_ARM_CORTEX_A8=" \
+LIST_ARMV7=" \
am3517_evm \
devkit8000 \
mx51evk \
@@ -657,6 +659,8 @@
omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
+ omap4_panda \
+ omap4_sdp4430 \
s5p_goni \
smdkc100 \
"
@@ -702,6 +706,7 @@
LIST_pxa=" \
cerf250 \
+ colibri_pxa270 \
cradle \
csb226 \
delta \
@@ -711,10 +716,13 @@
polaris \
pxa255_idp \
trizepsiv \
+ vpac270_nor \
+ vpac270_onenand \
wepep250 \
xaeniax \
xm250 \
xsengine \
+ zipitz2 \
zylonite \
"
@@ -739,7 +747,7 @@
${LIST_ARM9} \
${LIST_ARM10} \
${LIST_ARM11} \
- ${LIST_ARM_CORTEX_A8} \
+ ${LIST_ARMV7} \
${LIST_at91} \
${LIST_pxa} \
${LIST_ixp} \
@@ -824,9 +832,6 @@
#########################################################################
LIST_nios2=" \
- EP1C20 \
- EP1S10 \
- EP1S40 \
PCI5441 \
PK1C20 \
nios2-generic \
@@ -892,6 +897,7 @@
LIST_blackfin=" \
bf518f-ezbrd \
bf526-ezbrd \
+ bf527-ad7160-eval \
bf527-ezkit \
bf527-ezkit-v2 \
bf533-ezkit \
@@ -1005,7 +1011,7 @@
for arg in $@
do
case "$arg" in
- arm|SA|ARM7|ARM9|ARM10|ARM11|ARM_CORTEX_A8|at91|ixp|pxa \
+ arm|SA|ARM7|ARM9|ARM10|ARM11|ARMV7|at91|ixp|pxa \
|avr32 \
|blackfin \
|coldfire \
diff --git a/Makefile b/Makefile
index 1d87f37..9cea069 100644
--- a/Makefile
+++ b/Makefile
@@ -221,6 +221,7 @@
LIBS += drivers/spi/libspi.a
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
+LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
endif
ifeq ($(CPU),mpc85xx)
LIBS += drivers/qe/qe.a
@@ -245,6 +246,13 @@
LIBS += api/libapi.a
LIBS += post/libpost.a
+ifeq ($(SOC),omap3)
+LIBS += $(CPUDIR)/omap-common/libomap-common.a
+endif
+ifeq ($(SOC),omap4)
+LIBS += $(CPUDIR)/omap-common/libomap-common.a
+endif
+
LIBS := $(addprefix $(obj),$(LIBS))
.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -2171,6 +2179,15 @@
fi;
@$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv
+vpac270_nor_config \
+vpac270_onenand_config : unconfig
+ @mkdir -p $(obj)include
+ @if [ "$(findstring onenand,$@)" ] ; then \
+ echo "#define CONFIG_ONENAND_U_BOOT" \
+ >>$(obj)include/config.h ; \
+ fi;
+ @$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270
+
#########################################################################
## ARM1136 Systems
#########################################################################
@@ -2436,7 +2453,6 @@
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \
- $(obj)arch/blackfin/lib/u-boot.lds \
$(obj)u-boot.lds \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
diff --git a/README b/README
index a9c98f2..c9fb284 100644
--- a/README
+++ b/README
@@ -1495,6 +1495,16 @@
#define I2C_DELAY udelay(2)
+ CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
+
+ If your arch supports the generic GPIO framework (asm/gpio.h),
+ then you may alternatively define the two GPIOs that are to be
+ used as SCL / SDA. Any of the previous I2C_xxx macros will
+ have GPIO-based defaults assigned to them as appropriate.
+
+ You should define these to the GPIO value as given directly to
+ the generic GPIO functions.
+
CONFIG_SYS_I2C_INIT_BOARD
When a board is reset during an i2c bus transfer
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 6fc3902..c63e864 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -378,10 +378,10 @@
}
#endif /* CONFIG_ARCH_MISC_INIT */
-#ifdef CONFIG_KIRKWOOD_EGIGA
+#ifdef CONFIG_MVGBE
int cpu_eth_init(bd_t *bis)
{
- kirkwood_egiga_initialize(bis);
+ mvgbe_initialize(bis);
return 0;
}
#endif
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
index 03c6d06..f3c1e21 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -268,3 +268,11 @@
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_MVGBE
+int cpu_eth_init(bd_t *bis)
+{
+ mvgbe_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm_cortexa8/Makefile b/arch/arm/cpu/armv7/Makefile
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/Makefile
rename to arch/arm/cpu/armv7/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/config.mk b/arch/arm/cpu/armv7/config.mk
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/config.mk
rename to arch/arm/cpu/armv7/config.mk
diff --git a/arch/arm/cpu/arm_cortexa8/cpu.c b/arch/arm/cpu/armv7/cpu.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/cpu.c
rename to arch/arm/cpu/armv7/cpu.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/Makefile b/arch/arm/cpu/armv7/mx51/Makefile
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/Makefile
rename to arch/arm/cpu/armv7/mx51/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/clock.c b/arch/arm/cpu/armv7/mx51/clock.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/clock.c
rename to arch/arm/cpu/armv7/mx51/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/iomux.c b/arch/arm/cpu/armv7/mx51/iomux.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/iomux.c
rename to arch/arm/cpu/armv7/mx51/iomux.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S b/arch/arm/cpu/armv7/mx51/lowlevel_init.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
rename to arch/arm/cpu/armv7/mx51/lowlevel_init.S
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/soc.c b/arch/arm/cpu/armv7/mx51/soc.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/soc.c
rename to arch/arm/cpu/armv7/mx51/soc.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/speed.c b/arch/arm/cpu/armv7/mx51/speed.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/speed.c
rename to arch/arm/cpu/armv7/mx51/speed.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/timer.c b/arch/arm/cpu/armv7/mx51/timer.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/timer.c
rename to arch/arm/cpu/armv7/mx51/timer.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds b/arch/arm/cpu/armv7/mx51/u-boot.lds
similarity index 97%
rename from arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
rename to arch/arm/cpu/armv7/mx51/u-boot.lds
index 2953b93..d66434c 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
+++ b/arch/arm/cpu/armv7/mx51/u-boot.lds
@@ -36,7 +36,7 @@
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm_cortexa8/start.o
+ arch/arm/cpu/armv7/start.o
*(.text)
}
diff --git a/board/gth/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
similarity index 84%
copy from board/gth/Makefile
copy to arch/arm/cpu/armv7/omap-common/Makefile
index 4b5c528..3a4a304 100644
--- a/board/gth/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -23,15 +23,17 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)libomap-common.a
-COBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
+SOBJS := reset.o
+COBJS := timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): $(obj).depend $(OBJS)
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
diff --git a/arch/arm/cpu/arm_cortexa8/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk
similarity index 100%
copy from arch/arm/cpu/arm_cortexa8/config.mk
copy to arch/arm/cpu/armv7/omap-common/config.mk
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/reset.S b/arch/arm/cpu/armv7/omap-common/reset.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/reset.S
rename to arch/arm/cpu/armv7/omap-common/reset.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
similarity index 95%
rename from arch/arm/cpu/arm_cortexa8/omap3/timer.c
rename to arch/arm/cpu/armv7/omap-common/timer.c
index 401bfe6..69e285f 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/timer.c
+++ b/arch/arm/cpu/armv7/omap-common/timer.c
@@ -84,6 +84,11 @@
/* delay x useconds */
void __udelay(unsigned long usec)
{
+#if defined(CONFIG_OMAP44XX)
+ /* TODO temporary hack until OMAP4 clock setup routines are present */
+ if (usec > 1000)
+ usec = usec/1000;
+#endif
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
unsigned long now, last = readl(&timer_base->tcrr);
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
similarity index 97%
rename from arch/arm/cpu/arm_cortexa8/omap3/Makefile
rename to arch/arm/cpu/armv7/omap3/Makefile
index 7d63c6b..79ae267 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -27,7 +27,6 @@
SOBJS := lowlevel_init.o
SOBJS += cache.o
-SOBJS += reset.o
COBJS += board.o
COBJS += clock.o
@@ -35,7 +34,6 @@
COBJS += mem.o
COBJS += syslib.o
COBJS += sys_info.o
-COBJS += timer.o
COBJS-$(CONFIG_EMIF4) += emif4.o
COBJS-$(CONFIG_SDRC) += sdrc.o
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/board.c
rename to arch/arm/cpu/armv7/omap3/board.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/cache.S
rename to arch/arm/cpu/armv7/omap3/cache.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/clock.c
rename to arch/arm/cpu/armv7/omap3/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/emif4.c
rename to arch/arm/cpu/armv7/omap3/emif4.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/gpio.c b/arch/arm/cpu/armv7/omap3/gpio.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/gpio.c
rename to arch/arm/cpu/armv7/omap3/gpio.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S
rename to arch/arm/cpu/armv7/omap3/lowlevel_init.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/mem.c
rename to arch/arm/cpu/armv7/omap3/mem.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
rename to arch/arm/cpu/armv7/omap3/sdrc.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
rename to arch/arm/cpu/armv7/omap3/sys_info.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/syslib.c b/arch/arm/cpu/armv7/omap3/syslib.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/syslib.c
rename to arch/arm/cpu/armv7/omap3/syslib.c
diff --git a/board/gth/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
similarity index 83%
copy from board/gth/Makefile
copy to arch/arm/cpu/armv7/omap4/Makefile
index 4b5c528..d926fbb 100644
--- a/board/gth/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -23,15 +23,20 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(SOC).a
-COBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
+SOBJS += lowlevel_init.o
+
+COBJS += board.o
+COBJS += mem.o
+COBJS += sys_info.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-$(LIB): $(obj).depend $(OBJS)
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
new file mode 100644
index 0000000..5bf7173
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -0,0 +1,90 @@
+/*
+ *
+ * Common functions for OMAP4 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with SRAM stack.
+ */
+void s_init(void)
+{
+ watchdog_init();
+}
+
+/*
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ */
+void wait_for_command_complete(struct watchdog *wd_base)
+{
+ int pending = 1;
+ do {
+ pending = readl(&wd_base->wwps);
+ } while (pending);
+}
+
+/*
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ */
+void watchdog_init(void)
+{
+ struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
+
+ writel(WD_UNLOCK1, &wd2_base->wspr);
+ wait_for_command_complete(wd2_base);
+ writel(WD_UNLOCK2, &wd2_base->wspr);
+}
+
+/*
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = 0x80000000;
+ gd->bd->bi_dram[0].size = 512 << 20;
+ return 0;
+}
+
+/*
+ * Print board information
+ */
+int checkboard(void)
+{
+ puts(sysinfo.board_string);
+ return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
new file mode 100644
index 0000000..9a181eb
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -0,0 +1,48 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/omap4.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, =LOW_LEVEL_SRAM_STACK
+
+ /*
+ * Save the old lr(passed in ip) and the current lr to stack
+ */
+ push {ip, lr}
+
+ /*
+ * go setup pll, mux, memory
+ */
+ bl s_init
+ pop {ip, pc}
+
diff --git a/arch/arm/cpu/armv7/omap4/mem.c b/arch/arm/cpu/armv7/omap4/mem.c
new file mode 100644
index 0000000..878f0e3
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/mem.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+struct gpmc *gpmc_cfg;
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+ gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+ /* global settings */
+ writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
+ writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
+
+ /*
+ * Disable the GPMC0 config set by ROM code
+ * It conflicts with our MPDB (both at 0x08000000)
+ */
+ writel(0, &gpmc_cfg->cs[0].config7);
+}
diff --git a/arch/arm/cpu/armv7/omap4/sys_info.c b/arch/arm/cpu/armv7/omap4/sys_info.c
new file mode 100644
index 0000000..3b73191
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/sys_info.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+ return 0;
+}
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+ return 0x20;
+}
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+
+ puts("CPU : OMAP4430\n");
+
+ return 0;
+}
+
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile
rename to arch/arm/cpu/armv7/s5pc1xx/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S
similarity index 98%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S
rename to arch/arm/cpu/armv7/s5pc1xx/cache.S
index 906118d..7734b32 100644
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S
+++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S
@@ -2,7 +2,7 @@
* Copyright (C) 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
- * based on arch/arm/cpu/arm_cortexa8/omap3/cache.S
+ * based on arch/arm/cpu/armv7/omap3/cache.S
*
* See file CREDITS for list of people who contributed to this
* project.
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c
rename to arch/arm/cpu/armv7/s5pc1xx/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c b/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c
rename to arch/arm/cpu/armv7/s5pc1xx/cpu_info.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S
rename to arch/arm/cpu/armv7/s5pc1xx/reset.S
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5pc1xx/sromc.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c
rename to arch/arm/cpu/armv7/s5pc1xx/sromc.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c b/arch/arm/cpu/armv7/s5pc1xx/timer.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c
rename to arch/arm/cpu/armv7/s5pc1xx/timer.c
diff --git a/arch/arm/cpu/arm_cortexa8/start.S b/arch/arm/cpu/armv7/start.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/start.S
rename to arch/arm/cpu/armv7/start.S
diff --git a/arch/arm/cpu/arm_cortexa8/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
similarity index 96%
rename from arch/arm/cpu/arm_cortexa8/u-boot.lds
rename to arch/arm/cpu/armv7/u-boot.lds
index 820e3a1..9e5b5a9 100644
--- a/arch/arm/cpu/arm_cortexa8/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -34,7 +34,7 @@
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm_cortexa8/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text)
*(.text)
}
diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
index d56c5f0..524a03b 100644
--- a/arch/arm/cpu/pxa/pxafb.c
+++ b/arch/arm/cpu/pxa/pxafb.c
@@ -112,6 +112,39 @@
vl_efw: 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
+/*----------------------------------------------------------------------*/
+#ifdef CONFIG_VOIPAC_LCD
+
+# define LCD_BPP LCD_COLOR8
+# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x043008f8
+# define REG_LCCR3 0x0340FF08
+
+vidinfo_t panel_info = {
+ vl_col: 640,
+ vl_row: 480,
+ vl_width: 157,
+ vl_height: 118,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_HIGH,
+ vl_hsp: CONFIG_SYS_HIGH,
+ vl_vsp: CONFIG_SYS_HIGH,
+ vl_dp: CONFIG_SYS_HIGH,
+ vl_bpix: LCD_BPP,
+ vl_lbw: 0,
+ vl_splt: 1,
+ vl_clor: 1,
+ vl_tft: 1,
+ vl_hpw: 32,
+ vl_blw: 144,
+ vl_elw: 32,
+ vl_vpw: 2,
+ vl_bfw: 13,
+ vl_efw: 30,
+};
+#endif /* CONFIG_VOIPAC_LCD */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SX14
@@ -147,6 +180,40 @@
#endif /* CONFIG_HITACHI_SX14 */
/*----------------------------------------------------------------------*/
+#ifdef CONFIG_LMS283GF05
+
+# define LCD_BPP LCD_COLOR8
+//# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x043008f8
+# define REG_LCCR3 0x03b00009
+
+vidinfo_t panel_info = {
+ vl_col: 240,
+ vl_row: 320,
+ vl_width: 240,
+ vl_height: 320,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_LOW,
+ vl_hsp: CONFIG_SYS_LOW,
+ vl_vsp: CONFIG_SYS_LOW,
+ vl_dp: CONFIG_SYS_HIGH,
+ vl_bpix: LCD_BPP,
+ vl_lbw: 0,
+ vl_splt: 1,
+ vl_clor: 1,
+ vl_tft: 1,
+ vl_hpw: 4,
+ vl_blw: 4,
+ vl_elw: 8,
+ vl_vpw: 4,
+ vl_bfw: 4,
+ vl_efw: 8,
+};
+#endif /* CONFIG_LMS283GF05 */
+
+/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
@@ -292,7 +359,9 @@
return 0;
}
-
+#ifdef CONFIG_CPU_MONAHANS
+static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
+#else
static void pxafb_setup_gpio (vidinfo_t *vid)
{
u_long lccr0;
@@ -349,6 +418,7 @@
printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
}
}
+#endif
static void pxafb_enable_controller (vidinfo_t *vid)
{
@@ -363,7 +433,11 @@
FDADR1 = vid->pxa.fdadr1;
LCCR0 |= LCCR0_ENB;
+#ifdef CONFIG_CPU_MONAHANS
+ CKENA |= CKENA_1_LCD;
+#else
CKEN |= CKEN16_LCD;
+#endif
debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index e07c8c2..8010b0e 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -34,6 +34,25 @@
.globl _start
_start: b reset
+#ifdef CONFIG_PRELOADER
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+
+_hang:
+ .word do_hang
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678 /* now 16*4=64 */
+#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -49,6 +68,7 @@
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
+#endif /* CONFIG_PRELOADER */
.balignl 16,0xdeadbeef
@@ -117,8 +137,10 @@
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+#ifndef CONFIG_PRELOADER
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
+#endif
ldr r2, _armboot_start
ldr r3, _bss_start
@@ -135,28 +157,37 @@
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
+#ifdef CONFIG_PRELOADER
+ sub sp, r0, #128 /* leave 32 words for abort-stack */
+#else
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif /* CONFIG_USE_IRQ */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+#endif
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
+#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
+#endif
ldr pc, _start_armboot
+#ifdef CONFIG_ONENAND_IPL
+_start_armboot: .word start_oneboot
+#else
_start_armboot: .word start_armboot
-
+#endif
/****************************************************************************/
/* */
@@ -296,7 +327,7 @@
*/
mov pc, lr
-
+#ifndef CONFIG_PRELOADER
/****************************************************************************/
/* */
/* Interrupt handling */
@@ -394,6 +425,7 @@
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
+#endif /* CONFIG_PRELOADER */
/****************************************************************************/
@@ -402,6 +434,12 @@
/* */
/****************************************************************************/
+#ifdef CONFIG_PRELOADER
+ .align 5
+do_hang:
+ ldr sp, _TEXT_BASE /* use 32 words abort stack */
+ bl hang /* hang and never return */
+#else /* !CONFIG_PRELOADER */
.align 5
undefined_instruction:
get_bad_stack
@@ -461,7 +499,7 @@
get_bad_stack
bad_save_user_regs
bl do_fiq
-
+#endif /* CONFIG_PRELOADER */
#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index 2470efb..9edb0be 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -60,6 +60,11 @@
#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
+/* Kirkwood GbE controller has two ports */
+#define MAX_MVGBE_DEVS 2
+#define MVGBE0_BASE KW_EGIGA0_BASE
+#define MVGBE1_BASE KW_EGIGA1_BASE
+
#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
#elif defined (CONFIG_KW88F6192)
diff --git a/arch/arm/include/asm/arch-mx51/asm-offsets.h b/arch/arm/include/asm/arch-mx51/asm-offsets.h
index fbba412..afd2728 100644
--- a/arch/arm/include/asm/arch-mx51/asm-offsets.h
+++ b/arch/arm/include/asm/arch-mx51/asm-offsets.h
@@ -1,5 +1,5 @@
/*
- * needed for arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
+ * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
*
* These should be auto-generated
*/
diff --git a/arch/arm/include/asm/arch-omap3/i2c.h b/arch/arm/include/asm/arch-omap3/i2c.h
index 490e03b..7a4a73a 100644
--- a/arch/arm/include/asm/arch-omap3/i2c.h
+++ b/arch/arm/include/asm/arch-omap3/i2c.h
@@ -20,9 +20,10 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef _I2C_H_
-#define _I2C_H_
+#ifndef _OMAP3_I2C_H_
+#define _OMAP3_I2C_H_
+#define I2C_BUS_MAX 3
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
@@ -58,146 +59,4 @@
unsigned short res15;
};
-#define I2C_BUS_MAX 3
-
-/* I2C masks */
-
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_GC_IE (1 << 5)
-#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
-#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
-#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
-#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Status Register (I2C_STAT): */
-
-#define I2C_STAT_SBD (1 << 15) /* Single byte data */
-#define I2C_STAT_BB (1 << 12) /* Bus busy */
-#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
-#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
-#define I2C_STAT_AAS (1 << 9) /* Address as slave */
-#define I2C_STAT_GC (1 << 5)
-#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
-#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
-#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
-#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Interrupt Code Register (I2C_INTCODE): */
-
-#define I2C_INTCODE_MASK 7
-#define I2C_INTCODE_NONE 0
-#define I2C_INTCODE_AL 1 /* Arbitration lost */
-#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
-#define I2C_INTCODE_ARDY 3 /* Register access ready */
-#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
-#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
-
-/* I2C Buffer Configuration Register (I2C_BUF): */
-
-#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
-#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
-
-/* I2C Configuration Register (I2C_CON): */
-
-#define I2C_CON_EN (1 << 15) /* I2C module enable */
-#define I2C_CON_BE (1 << 14) /* Big endian mode */
-#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
-#define I2C_CON_MST (1 << 10) /* Master/slave mode */
-#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
- /* (master mode only) */
-#define I2C_CON_XA (1 << 8) /* Expand address */
-#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
-#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
-
-/* I2C System Test Register (I2C_SYSTEST): */
-
-#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
-#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
-#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
-#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
-#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
-#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
-#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
-#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
-
-#define I2C_SCLL_SCLL 0
-#define I2C_SCLL_SCLL_M 0xFF
-#define I2C_SCLL_HSSCLL 8
-#define I2C_SCLH_HSSCLL_M 0xFF
-#define I2C_SCLH_SCLH 0
-#define I2C_SCLH_SCLH_M 0xFF
-#define I2C_SCLH_HSSCLH 8
-#define I2C_SCLH_HSSCLH_M 0xFF
-
-#define OMAP_I2C_STANDARD 100000
-#define OMAP_I2C_FAST_MODE 400000
-#define OMAP_I2C_HIGH_SPEED 3400000
-
-#define SYSTEM_CLOCK_12 12000000
-#define SYSTEM_CLOCK_13 13000000
-#define SYSTEM_CLOCK_192 19200000
-#define SYSTEM_CLOCK_96 96000000
-
-/* Use the reference value of 96MHz if not explicitly set by the board */
-#ifndef I2C_IP_CLK
-#define I2C_IP_CLK SYSTEM_CLOCK_96
-#endif
-
-/*
- * The reference minimum clock for high speed is 19.2MHz.
- * The linux 2.6.30 kernel uses this value.
- * The reference minimum clock for fast mode is 9.6MHz
- * The reference minimum clock for standard mode is 4MHz
- * In TRM, the value of 12MHz is used.
- */
-#ifndef I2C_INTERNAL_SAMPLING_CLK
-#define I2C_INTERNAL_SAMPLING_CLK 19200000
-#endif
-
-/*
- * The equation for the low and high time is
- * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
- * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
- *
- * If the duty cycle is 50%
- *
- * tlow = scll + scll_trim = sampling clock / (2 * speed)
- * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
- *
- * In TRM
- * scll_trim = 7
- * sclh_trim = 5
- *
- * The linux 2.6.30 kernel uses
- * scll_trim = 6
- * sclh_trim = 6
- *
- * These are the trim values for standard and fast speed
- */
-#ifndef I2C_FASTSPEED_SCLL_TRIM
-#define I2C_FASTSPEED_SCLL_TRIM 6
-#endif
-#ifndef I2C_FASTSPEED_SCLH_TRIM
-#define I2C_FASTSPEED_SCLH_TRIM 6
-#endif
-
-/* These are the trim values for high speed */
-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
-#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
-#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
-#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
-#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
-#endif
-
-#define I2C_PSC_MAX 0x0f
-#define I2C_PSC_MIN 0x00
-
-#endif /* _I2C_H_ */
+#endif /* _OMAP3_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index aa751c9..43dd705 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -29,13 +29,20 @@
#define T2_BASE 0x48002000
typedef struct t2 {
- unsigned char res1[0x274];
+ unsigned char res1[0x274]; /* 0x000 */
unsigned int devconf0; /* 0x274 */
- unsigned char res2[0x2A8];
+ unsigned char res2[0x060]; /* 0x278 */
+ unsigned int devconf1; /* 0x2D8 */
+ unsigned char res3[0x244]; /* 0x2DC */
unsigned int pbias_lite; /* 0x520 */
} t2_t;
#define MMCSDIO1ADPCLKISEL (1 << 24)
+#define MMCSDIO2ADPCLKISEL (1 << 6)
+
+#define EN_MMC1 (1 << 24)
+#define EN_MMC2 (1 << 25)
+#define EN_MMC3 (1 << 30)
#define PBIASLITEPWRDNZ0 (1 << 1)
#define PBIASSPEEDCTRL0 (1 << 2)
@@ -44,7 +51,9 @@
/*
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC_BASE 0x4809C000
+#define OMAP_HSMMC1_BASE 0x4809C000
+#define OMAP_HSMMC2_BASE 0x480B4000
+#define OMAP_HSMMC3_BASE 0x480AD000
typedef struct hsmmc {
unsigned char res1[0x10];
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
new file mode 100644
index 0000000..c056b95
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2006-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gpmc_cs {
+ u32 config1; /* 0x00 */
+ u32 config2; /* 0x04 */
+ u32 config3; /* 0x08 */
+ u32 config4; /* 0x0C */
+ u32 config5; /* 0x10 */
+ u32 config6; /* 0x14 */
+ u32 config7; /* 0x18 */
+ u32 nand_cmd; /* 0x1C */
+ u32 nand_adr; /* 0x20 */
+ u32 nand_dat; /* 0x24 */
+ u8 res[8]; /* blow up to 0x30 byte */
+};
+
+struct gpmc {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u8 res2[0x4];
+ u32 irqstatus; /* 0x18 */
+ u32 irqenable; /* 0x1C */
+ u8 res3[0x20];
+ u32 timeout_control; /* 0x40 */
+ u8 res4[0xC];
+ u32 config; /* 0x50 */
+ u32 status; /* 0x54 */
+ u8 res5[0x8]; /* 0x58 */
+ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
+ u8 res6[0x14]; /* 0x1E0 */
+ u32 ecc_config; /* 0x1F4 */
+ u32 ecc_control; /* 0x1F8 */
+ u32 ecc_size_config; /* 0x1FC */
+ u32 ecc1_result; /* 0x200 */
+ u32 ecc2_result; /* 0x204 */
+ u32 ecc3_result; /* 0x208 */
+ u32 ecc4_result; /* 0x20C */
+ u32 ecc5_result; /* 0x210 */
+ u32 ecc6_result; /* 0x214 */
+ u32 ecc7_result; /* 0x218 */
+ u32 ecc8_result; /* 0x21C */
+ u32 ecc9_result; /* 0x220 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
+struct gptimer {
+ u32 tidr; /* 0x00 r */
+ u8 res[0xc];
+ u32 tiocp_cfg; /* 0x10 rw */
+ u32 tistat; /* 0x14 r */
+ u32 tisr; /* 0x18 rw */
+ u32 tier; /* 0x1c rw */
+ u32 twer; /* 0x20 rw */
+ u32 tclr; /* 0x24 rw */
+ u32 tcrr; /* 0x28 rw */
+ u32 tldr; /* 0x2c rw */
+ u32 ttgr; /* 0x30 rw */
+ u32 twpc; /* 0x34 r */
+ u32 tmar; /* 0x38 rw */
+ u32 tcar1; /* 0x3c r */
+ u32 tcicr; /* 0x40 rw */
+ u32 tcar2; /* 0x44 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+ u8 res1[0x34];
+ u32 wwps; /* 0x34 r */
+ u8 res2[0x10];
+ u32 wspr; /* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+#define SYSCLKDIV_1 (0x1 << 6)
+#define SYSCLKDIV_2 (0x1 << 7)
+
+#define CLKSEL_GPT1 (0x1 << 0)
+
+#define EN_GPT1 (0x1 << 0)
+#define EN_32KSYNC (0x1 << 2)
+
+#define ST_WDT2 (0x1 << 5)
+
+#define RESETDONE (0x1 << 0)
+
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/* GPMC BASE */
+#define GPMC_BASE (OMAP44XX_GPMC_BASE)
+
+/* I2C base */
+#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
+#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
+#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000)
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h
new file mode 100644
index 0000000..a91b4c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/i2c.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP4_I2C_H_
+#define _OMAP4_I2C_H_
+
+#define I2C_BUS_MAX 3
+#define I2C_DEFAULT_BASE I2C_BASE1
+
+struct i2c {
+ unsigned short revnb_lo; /* 0x00 */
+ unsigned short res1;
+ unsigned short revnb_hi; /* 0x04 */
+ unsigned short res2[13];
+ unsigned short sysc; /* 0x20 */
+ unsigned short res3;
+ unsigned short irqstatus_raw; /* 0x24 */
+ unsigned short res4;
+ unsigned short stat; /* 0x28 */
+ unsigned short res5;
+ unsigned short ie; /* 0x2C */
+ unsigned short res6;
+ unsigned short irqenable_clr; /* 0x30 */
+ unsigned short res7;
+ unsigned short iv; /* 0x34 */
+ unsigned short res8[45];
+ unsigned short syss; /* 0x90 */
+ unsigned short res9;
+ unsigned short buf; /* 0x94 */
+ unsigned short res10;
+ unsigned short cnt; /* 0x98 */
+ unsigned short res11;
+ unsigned short data; /* 0x9C */
+ unsigned short res13;
+ unsigned short res14; /* 0xA0 */
+ unsigned short res15;
+ unsigned short con; /* 0xA4 */
+ unsigned short res16;
+ unsigned short oa; /* 0xA8 */
+ unsigned short res17;
+ unsigned short sa; /* 0xAC */
+ unsigned short res18;
+ unsigned short psc; /* 0xB0 */
+ unsigned short res19;
+ unsigned short scll; /* 0xB4 */
+ unsigned short res20;
+ unsigned short sclh; /* 0xB8 */
+ unsigned short res21;
+ unsigned short systest; /* 0xBC */
+ unsigned short res22;
+ unsigned short bufstat; /* 0xC0 */
+ unsigned short res23;
+};
+
+#endif /* _OMAP4_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
new file mode 100644
index 0000000..e5d8b53
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE 0x4809C100
+#define OMAP_HSMMC2_BASE 0x480B4100
+#define OMAP_HSMMC3_BASE 0x480AD100
+
+typedef struct hsmmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned char res2[0x14];
+ unsigned int con; /* 0x2C */
+ unsigned char res3[0xD4];
+ unsigned int blk; /* 0x104 */
+ unsigned int arg; /* 0x108 */
+ unsigned int cmd; /* 0x10C */
+ unsigned int rsp10; /* 0x110 */
+ unsigned int rsp32; /* 0x114 */
+ unsigned int rsp54; /* 0x118 */
+ unsigned int rsp76; /* 0x11C */
+ unsigned int data; /* 0x120 */
+ unsigned int pstate; /* 0x124 */
+ unsigned int hctl; /* 0x128 */
+ unsigned int sysctl; /* 0x12C */
+ unsigned int stat; /* 0x130 */
+ unsigned int ie; /* 0x134 */
+ unsigned char res4[0x8];
+ unsigned int capa; /* 0x140 */
+} hsmmc_t;
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET (0x1 << 1)
+#define RESETDONE (0x1 << 0)
+#define NOOPENDRAIN (0x0 << 0)
+#define OPENDRAIN (0x1 << 0)
+#define OD (0x1 << 0)
+#define INIT_NOINIT (0x0 << 1)
+#define INIT_INITSTREAM (0x1 << 1)
+#define HR_NOHOSTRESP (0x0 << 2)
+#define STR_BLOCK (0x0 << 3)
+#define MODE_FUNC (0x0 << 4)
+#define DW8_1_4BITMODE (0x0 << 5)
+#define MIT_CTO (0x0 << 6)
+#define CDP_ACTIVEHIGH (0x0 << 7)
+#define WPP_ACTIVEHIGH (0x0 << 8)
+#define RESERVED_MASK (0x3 << 9)
+#define CTPL_MMC_SD (0x0 << 11)
+#define BLEN_512BYTESLEN (0x200 << 0)
+#define NBLK_STPCNT (0x0 << 16)
+#define DE_DISABLE (0x0 << 0)
+#define BCE_DISABLE (0x0 << 1)
+#define ACEN_DISABLE (0x0 << 2)
+#define DDIR_OFFSET (4)
+#define DDIR_MASK (0x1 << 4)
+#define DDIR_WRITE (0x0 << 4)
+#define DDIR_READ (0x1 << 4)
+#define MSBS_SGLEBLK (0x0 << 5)
+#define RSP_TYPE_OFFSET (16)
+#define RSP_TYPE_MASK (0x3 << 16)
+#define RSP_TYPE_NORSP (0x0 << 16)
+#define RSP_TYPE_LGHT136 (0x1 << 16)
+#define RSP_TYPE_LGHT48 (0x2 << 16)
+#define RSP_TYPE_LGHT48B (0x3 << 16)
+#define CCCE_NOCHECK (0x0 << 19)
+#define CCCE_CHECK (0x1 << 19)
+#define CICE_NOCHECK (0x0 << 20)
+#define CICE_CHECK (0x1 << 20)
+#define DP_OFFSET (21)
+#define DP_MASK (0x1 << 21)
+#define DP_NO_DATA (0x0 << 21)
+#define DP_DATA (0x1 << 21)
+#define CMD_TYPE_NORMAL (0x0 << 22)
+#define INDEX_OFFSET (24)
+#define INDEX_MASK (0x3f << 24)
+#define INDEX(i) (i << 24)
+#define DATI_MASK (0x1 << 1)
+#define DATI_CMDDIS (0x1 << 1)
+#define DTW_1_BITMODE (0x0 << 1)
+#define DTW_4_BITMODE (0x1 << 1)
+#define SDBP_PWROFF (0x0 << 8)
+#define SDBP_PWRON (0x1 << 8)
+#define SDVS_1V8 (0x5 << 9)
+#define SDVS_3V0 (0x6 << 9)
+#define ICE_MASK (0x1 << 0)
+#define ICE_STOP (0x0 << 0)
+#define ICS_MASK (0x1 << 1)
+#define ICS_NOTREADY (0x0 << 1)
+#define ICE_OSCILLATE (0x1 << 0)
+#define CEN_MASK (0x1 << 2)
+#define CEN_DISABLE (0x0 << 2)
+#define CEN_ENABLE (0x1 << 2)
+#define CLKD_OFFSET (6)
+#define CLKD_MASK (0x3FF << 6)
+#define DTO_MASK (0xF << 16)
+#define DTO_15THDTO (0xE << 16)
+#define SOFTRESETALL (0x1 << 24)
+#define CC_MASK (0x1 << 0)
+#define TC_MASK (0x1 << 1)
+#define BWR_MASK (0x1 << 4)
+#define BRR_MASK (0x1 << 5)
+#define ERRI_MASK (0x1 << 15)
+#define IE_CC (0x01 << 0)
+#define IE_TC (0x01 << 1)
+#define IE_BWR (0x01 << 4)
+#define IE_BRR (0x01 << 5)
+#define IE_CTO (0x01 << 16)
+#define IE_CCRC (0x01 << 17)
+#define IE_CEB (0x01 << 18)
+#define IE_CIE (0x01 << 19)
+#define IE_DTO (0x01 << 20)
+#define IE_DCRC (0x01 << 21)
+#define IE_DEB (0x01 << 22)
+#define IE_CERR (0x01 << 28)
+#define IE_BADA (0x01 << 29)
+
+#define VS30_3V0SUP (1 << 25)
+#define VS18_1V8SUP (1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE 512
+#define MMC_CARD 0
+#define SD_CARD 1
+#define BYTE_MODE 0
+#define SECTOR_MODE 1
+#define CLK_INITSEQ 0
+#define CLK_400KHZ 1
+#define CLK_MISC 2
+
+typedef struct {
+ unsigned int card_type;
+ unsigned int version;
+ unsigned int mode;
+ unsigned int size;
+ unsigned int RCA;
+} mmc_card_data;
+
+#define mmc_reg_out(addr, mask, val)\
+ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
new file mode 100644
index 0000000..5243ea8
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Derived from OMAP3 work by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP4_H_
+#define _OMAP4_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP44XX_L4_CORE_BASE 0x4A000000
+#define OMAP44XX_L4_WKUP_BASE 0x4A300000
+#define OMAP44XX_L4_PER_BASE 0x48000000
+
+/* CONTROL */
+#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
+
+/* UART */
+#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
+
+/* General Purpose Timers */
+#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
+#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
+#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
+
+/* GPMC */
+#define OMAP44XX_GPMC_BASE 0x50000000
+
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+/* GP Timer */
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE 0x4A306000
+#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL PRM_DEVICE_BASE
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+ unsigned char res[0x10];
+ unsigned int s32k_cr; /* 0x10 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Non-secure SRAM Addresses
+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ * at 0x40304000(EMU base) so that our code works for both EMU and GP
+ */
+#define NON_SECURE_SRAM_START 0x40304000
+#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE 0x4030D000
+/* Temporary SRAM stack used while low level init is done */
+#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
+
+/*
+ * OMAP4 real hardware:
+ * TODO: Change this to the IDCODE in the hw regsiter
+ */
+#define CPU_OMAP4430_ES10 1
+#define CPU_OMAP4430_ES20 2
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
new file mode 100644
index 0000000..c6fab00
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap4.h>
+#include <asm/io.h>
+
+struct omap_sysinfo {
+ char *board_string;
+};
+
+void gpmc_init(void);
+void watchdog_init(void);
+u32 get_device_type(void);
+void invalidate_dcache(u32);
+
+extern const struct omap_sysinfo sysinfo;
+
+#endif
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
index 4008c84..d257b66 100644
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -56,6 +56,10 @@
#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
+/* Orion5x GbE controller has a single port */
+#define MAX_MVGBE_DEVS 1
+#define MVGBE0_BASE ORION5X_EGIGA_BASE
+
#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
/* include here SoC variants. 5181, 5281, 6183 should go here when
diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h
new file mode 100644
index 0000000..035a57e
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/macro.h
@@ -0,0 +1,324 @@
+/*
+ * arch/arm/include/asm/arch-pxa/macro.h
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_PXA_MACRO_H__
+#define __ASM_ARCH_PXA_MACRO_H__
+#ifdef __ASSEMBLY__
+
+#include <asm/macro.h>
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * This macro performs a 32bit write to a memory location and makes sure the
+ * write operation really happened by performing a read back.
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro write32rb addr, data
+ ldr r4, =\addr
+ ldr r5, =\data
+ str r5, [r4]
+ ldr r5, [r4]
+.endm
+
+/*
+ * This macro waits according to OSCR incrementation
+ *
+ * Clobbered regs: r4, r5, r6
+ */
+.macro pxa_wait_ticks ticks
+ ldr r4, =OSCR
+ mov r5, #0
+ str r5, [r4]
+ ldr r5, =\ticks
+1:
+ ldr r6, [r4]
+ cmp r5, r6
+ bgt 1b
+.endm
+
+/*
+ * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_gpio_setup
+ write32 GPSR0, CONFIG_SYS_GPSR0_VAL
+ write32 GPSR1, CONFIG_SYS_GPSR1_VAL
+ write32 GPSR2, CONFIG_SYS_GPSR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GPSR3, CONFIG_SYS_GPSR3_VAL
+#endif
+
+ write32 GPCR0, CONFIG_SYS_GPCR0_VAL
+ write32 GPCR1, CONFIG_SYS_GPCR1_VAL
+ write32 GPCR2, CONFIG_SYS_GPCR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GPCR3, CONFIG_SYS_GPCR3_VAL
+#endif
+
+ write32 GPDR0, CONFIG_SYS_GPDR0_VAL
+ write32 GPDR1, CONFIG_SYS_GPDR1_VAL
+ write32 GPDR2, CONFIG_SYS_GPDR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GPDR3, CONFIG_SYS_GPDR3_VAL
+#endif
+
+ write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
+ write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
+ write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
+ write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
+ write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
+ write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
+ write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
+#endif
+
+ write32 PSSR, CONFIG_SYS_PSSR_VAL
+.endm
+
+/*
+ * This macro sets up the Memory controller of the PXA2xx CPU
+ *
+ * Clobbered regs: r3, r4, r5
+ */
+.macro pxa_mem_setup
+ /* This comes handy when setting MDREFR */
+ ldr r3, =MEMC_BASE
+
+ /*
+ * 1) Initialize Asynchronous static memory controller
+ */
+
+ /* MSC0: nCS(0,1) */
+ write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
+ /* MSC1: nCS(2,3) */
+ write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
+ /* MSC2: nCS(4,5) */
+ write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
+
+ /*
+ * 2) Initialize Card Interface
+ */
+
+ /* MECR: Memory Expansion Card Register */
+ write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
+ /* MCMEM0: Card Interface slot 0 timing */
+ write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
+ /* MCMEM1: Card Interface slot 1 timing */
+ write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
+
+ /*
+ * 3) Configure Fly-By DMA register
+ */
+
+ write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
+
+ /*
+ * 4) Initialize Timing for Sync Memory (SDCLK0)
+ */
+
+ /*
+ * Before accessing MDREFR we need a valid DRI field, so we set
+ * this to power on defaults + DRI field.
+ */
+ ldr r5, [r3, #MDREFR_OFFSET]
+ bic r5, r5, #0x0ff
+ bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
+
+ ldr r4, =CONFIG_SYS_MDREFR_VAL
+ mov r6, r4
+ lsl r4, #20
+ lsr r4, #20 /* Get a valid DRI field */
+
+ orr r5, r5, r4 /* MDREFR user config with correct DRI */
+
+ orr r5, #MDREFR_K0RUN
+ orr r5, #MDREFR_SLFRSH
+ bic r5, #MDREFR_APD
+ bic r5, #MDREFR_E1PIN
+
+ str r5, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+
+ /*
+ * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
+ */
+
+ /* Initialize SXCNFG register. Assert the enable bits.
+ *
+ * Write SXMRS to cause an MRS command to all enabled banks of
+ * synchronous static memory. Note that SXLCR need not be written
+ * at this time.
+ */
+ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
+
+ /*
+ * 6) Initialize SDRAM
+ */
+
+ bic r6, #MDREFR_SLFRSH
+ str r6, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+
+ orr r6, #MDREFR_E1PIN
+ str r6, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+
+ /*
+ * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
+ * but not enable each SDRAM partition pair.
+ */
+
+ /* Fetch platform value of MDCNFG */
+ ldr r4, =CONFIG_SYS_MDCNFG_VAL
+ /* Disable all sdram banks */
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+ bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
+ /* Write initial value of MDCNFG, w/o enabling sdram banks */
+ str r4, [r3, #MDCNFG_OFFSET]
+ ldr r4, [r3, #MDCNFG_OFFSET]
+
+ /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
+ pxa_wait_ticks 0x300
+
+ /*
+ * 8) Trigger a number (usually 8) refresh cycles by attempting
+ * non-burst read or write accesses to disabled SDRAM, as commonly
+ * specified in the power up sequence documented in SDRAM data
+ * sheets. The address(es) used for this purpose must not be
+ * cacheable.
+ */
+
+ ldr r4, =CONFIG_SYS_DRAM_BASE
+.rept 9
+ str r5, [r4]
+.endr
+
+ /*
+ * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
+ */
+
+ ldr r5, =CONFIG_SYS_MDCNFG_VAL
+ ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
+ and r5, r5, r4
+ ldr r4, [r3, #MDCNFG_OFFSET]
+ orr r4, r4, r5
+ str r4, [r3, #MDCNFG_OFFSET]
+ ldr r4, [r3, #MDCNFG_OFFSET]
+
+ /*
+ * 10) Write MDMRS.
+ */
+
+ ldr r4, =CONFIG_SYS_MDMRS_VAL
+ str r4, [r3, #MDMRS_OFFSET]
+ ldr r4, [r3, #MDMRS_OFFSET]
+
+ /*
+ * 11) Enable APD
+ */
+
+ ldr r4, [r3, #MDREFR_OFFSET]
+ and r6, r6, #MDREFR_APD
+ orr r4, r4, r6
+ str r4, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+.endm
+
+/*
+ * This macro tests if the CPU woke up from sleep and eventually resumes
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_wakeup
+ ldr r4, =RCSR
+ ldr r5, [r4]
+ and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+ str r5, [r4]
+ teq r5, #RCSR_SMR
+
+ bne pxa_wakeup_exit
+
+ ldr r4, =PSSR
+ mov r5, #PSSR_PH
+ str r5, [r4]
+
+ ldr r4, =PSPR
+ ldr pc, [r4]
+pxa_wakeup_exit:
+.endm
+
+/*
+ * This macro disables all interupts on PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_intr_setup
+ write32 ICLR, 0
+ write32 ICMR, 0
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 ICLR2, 0
+ write32 ICMR2, 0
+#endif
+.endm
+
+/*
+ * This macro configures clock on PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_clock_setup
+ /* Disable the peripheral clocks, and set the core clock frequency */
+
+ /* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ write32 CKEN, CONFIG_SYS_CKEN
+
+ /* Write CCCR */
+ write32 CCCR, CONFIG_SYS_CCCR
+
+#ifdef CONFIG_RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ write32 OSCC, #OSCC_OON
+ ldr r4, =OSCC
+
+ /* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
+2:
+ ldr r5, [r4]
+ ands r5, r5, #1
+ beq 2b
+#endif
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_PXA_MACRO_H__ */
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index cd7b7f9..d442fb0 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -1132,10 +1132,18 @@
#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
-#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
+#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */
#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
+#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */
+#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */
+#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */
+
+#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */
+#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */
+#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */
+
/*
* Interrupt Controller
*/
diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile
index 211b8d5..b7f991d 100644
--- a/arch/blackfin/cpu/Makefile
+++ b/arch/blackfin/cpu/Makefile
@@ -17,7 +17,10 @@
CEXTRA := initcode.o
SEXTRA := start.o
SOBJS := interrupt.o cache.o
+COBJS-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount.o
+COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
COBJS-y += cpu.o
+COBJS-y += gpio.o
COBJS-y += interrupts.o
COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
COBJS-y += os_log.o
diff --git a/arch/blackfin/cpu/bootcount.c b/arch/blackfin/cpu/bootcount.c
new file mode 100644
index 0000000..6cf6dd5
--- /dev/null
+++ b/arch/blackfin/cpu/bootcount.c
@@ -0,0 +1,34 @@
+/*
+ * functions for handling bootcount support
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * Licensed under the 2-clause BSD.
+ */
+
+/* This version uses one 32bit storage and combines the magic/count */
+
+#include <common.h>
+
+/* We abuse the EVT0 MMR for bootcount storage by default */
+#ifndef CONFIG_SYS_BOOTCOUNT_ADDR
+# define CONFIG_SYS_BOOTCOUNT_ADDR EVT0
+#endif
+
+#define MAGIC_MASK 0xffff0000
+#define COUNT_MASK 0x0000ffff
+
+void bootcount_store(ulong cnt)
+{
+ ulong magic = (BOOTCOUNT_MAGIC & MAGIC_MASK) | (cnt & COUNT_MASK);
+ bfin_write32(CONFIG_SYS_BOOTCOUNT_ADDR, magic);
+}
+
+ulong bootcount_load(void)
+{
+ ulong magic = bfin_read32(CONFIG_SYS_BOOTCOUNT_ADDR);
+ if ((magic & MAGIC_MASK) == (BOOTCOUNT_MAGIC & MAGIC_MASK))
+ return magic & COUNT_MASK;
+ else
+ return 0;
+}
diff --git a/arch/blackfin/cpu/cmd_gpio.c b/arch/blackfin/cpu/cmd_gpio.c
new file mode 100644
index 0000000..9e505b6
--- /dev/null
+++ b/arch/blackfin/cpu/cmd_gpio.c
@@ -0,0 +1,120 @@
+/*
+ * Control GPIO pins on the fly
+ *
+ * Copyright (c) 2008-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+
+enum {
+ GPIO_INPUT,
+ GPIO_SET,
+ GPIO_CLEAR,
+ GPIO_TOGGLE,
+};
+
+int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc == 2 && !strcmp(argv[1], "status")) {
+ bfin_gpio_labels();
+ return 0;
+ }
+
+ if (argc != 3) {
+ show_usage:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ /* parse the behavior */
+ ulong sub_cmd;
+ switch (argv[1][0]) {
+ case 'i': sub_cmd = GPIO_INPUT; break;
+ case 's': sub_cmd = GPIO_SET; break;
+ case 'c': sub_cmd = GPIO_CLEAR; break;
+ case 't': sub_cmd = GPIO_TOGGLE; break;
+ default: goto show_usage;
+ }
+
+ /* parse the pin with format: [p][port]<#> */
+ const char *str_pin = argv[2];
+
+ /* grab the [p]<port> portion */
+ ulong port_base;
+ if (*str_pin == 'p') ++str_pin;
+ switch (*str_pin) {
+#ifdef GPIO_PA0
+ case 'a': port_base = GPIO_PA0; break;
+#endif
+#ifdef GPIO_PB0
+ case 'b': port_base = GPIO_PB0; break;
+#endif
+#ifdef GPIO_PC0
+ case 'c': port_base = GPIO_PC0; break;
+#endif
+#ifdef GPIO_PD0
+ case 'd': port_base = GPIO_PD0; break;
+#endif
+#ifdef GPIO_PE0
+ case 'e': port_base = GPIO_PE0; break;
+#endif
+#ifdef GPIO_PF0
+ case 'f': port_base = GPIO_PF0; break;
+#endif
+#ifdef GPIO_PG0
+ case 'g': port_base = GPIO_PG0; break;
+#endif
+#ifdef GPIO_PH0
+ case 'h': port_base = GPIO_PH0; break;
+#endif
+#ifdef GPIO_PI0
+ case 'i': port_base = GPIO_PI0; break;
+#endif
+#ifdef GPIO_PJ
+ case 'j': port_base = GPIO_PJ0; break;
+#endif
+ default: goto show_usage;
+ }
+
+ /* grab the <#> portion */
+ ulong pin = simple_strtoul(str_pin + 1, NULL, 10);
+ if (pin > 15)
+ goto show_usage;
+
+ /* grab the pin before we tweak it */
+ ulong gpio = port_base + pin;
+ gpio_request(gpio, "cmd_gpio");
+
+ /* finally, let's do it: set direction and exec command */
+ if (sub_cmd == GPIO_INPUT) {
+ gpio_direction_input(gpio);
+ printf("gpio: pin %lu on port %c set to input\n", pin, *str_pin);
+ return 0;
+ }
+
+ ulong value;
+ switch (sub_cmd) {
+ case GPIO_SET: value = 1; break;
+ case GPIO_CLEAR: value = 0; break;
+ case GPIO_TOGGLE: value = !gpio_get_value(gpio); break;
+ default: goto show_usage;
+ }
+ gpio_direction_output(gpio, value);
+ printf("gpio: pin %lu on port %c (gpio %lu) value is %lu\n",
+ pin, *str_pin, gpio, value);
+
+ gpio_free(gpio);
+
+ return 0;
+}
+
+U_BOOT_CMD(gpio, 3, 0, do_gpio,
+ "set/clear/toggle gpio output pins",
+ "<set|clear|toggle> <port><pin>\n"
+ " - set/clear/toggle the specified pin (e.g. PF10)");
diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
index 2c8fd86..18dbdf7 100644
--- a/arch/blackfin/cpu/cpu.c
+++ b/arch/blackfin/cpu/cpu.c
@@ -91,7 +91,9 @@
#else
bfin_write_SIC_IMASK(0);
#endif
- bfin_write_EVT2(evt_default); /* NMI */
+ /* Set up a dummy NMI handler if needed. */
+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
+ bfin_write_EVT2(evt_nmi); /* NMI */
bfin_write_EVT5(evt_default); /* hardware error */
bfin_write_EVT6(evt_default); /* core timer */
bfin_write_EVT7(evt_default);
diff --git a/arch/blackfin/cpu/cpu.h b/arch/blackfin/cpu/cpu.h
index 0a13c28..ba85e0b 100644
--- a/arch/blackfin/cpu/cpu.h
+++ b/arch/blackfin/cpu/cpu.h
@@ -29,10 +29,12 @@
void board_reset(void) __attribute__((__weak__));
void bfin_reset_or_hang(void) __attribute__((__noreturn__));
+void bfin_dump(struct pt_regs *reg);
void bfin_panic(struct pt_regs *reg);
void dump(struct pt_regs *regs);
asmlinkage void trap(void);
+asmlinkage void evt_nmi(void);
asmlinkage void evt_default(void);
#endif
diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c
new file mode 100644
index 0000000..488ca11
--- /dev/null
+++ b/arch/blackfin/cpu/gpio.c
@@ -0,0 +1,854 @@
+/*
+ * GPIO Abstraction Layer
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+
+#if ANOMALY_05000311 || ANOMALY_05000323
+enum {
+ AWA_data = SYSCR,
+ AWA_data_clear = SYSCR,
+ AWA_data_set = SYSCR,
+ AWA_toggle = SYSCR,
+ AWA_maska = UART_SCR,
+ AWA_maska_clear = UART_SCR,
+ AWA_maska_set = UART_SCR,
+ AWA_maska_toggle = UART_SCR,
+ AWA_maskb = UART_GCTL,
+ AWA_maskb_clear = UART_GCTL,
+ AWA_maskb_set = UART_GCTL,
+ AWA_maskb_toggle = UART_GCTL,
+ AWA_dir = SPORT1_STAT,
+ AWA_polar = SPORT1_STAT,
+ AWA_edge = SPORT1_STAT,
+ AWA_both = SPORT1_STAT,
+#if ANOMALY_05000311
+ AWA_inen = TIMER_ENABLE,
+#elif ANOMALY_05000323
+ AWA_inen = DMA1_1_CONFIG,
+#endif
+};
+ /* Anomaly Workaround */
+#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
+#else
+#define AWA_DUMMY_READ(...) do { } while (0)
+#endif
+
+static struct gpio_port_t * const gpio_array[] = {
+#if defined(BF533_FAMILY)
+ (struct gpio_port_t *) FIO_FLAG_D,
+#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) \
+ || defined(BF538_FAMILY)
+ (struct gpio_port_t *) PORTFIO,
+# if !defined(BF538_FAMILY)
+ (struct gpio_port_t *) PORTGIO,
+ (struct gpio_port_t *) PORTHIO,
+# endif
+#elif defined(BF561_FAMILY)
+ (struct gpio_port_t *) FIO0_FLAG_D,
+ (struct gpio_port_t *) FIO1_FLAG_D,
+ (struct gpio_port_t *) FIO2_FLAG_D,
+#elif defined(CONFIG_BF54x)
+ (struct gpio_port_t *)PORTA_FER,
+ (struct gpio_port_t *)PORTB_FER,
+ (struct gpio_port_t *)PORTC_FER,
+ (struct gpio_port_t *)PORTD_FER,
+ (struct gpio_port_t *)PORTE_FER,
+ (struct gpio_port_t *)PORTF_FER,
+ (struct gpio_port_t *)PORTG_FER,
+ (struct gpio_port_t *)PORTH_FER,
+ (struct gpio_port_t *)PORTI_FER,
+ (struct gpio_port_t *)PORTJ_FER,
+#else
+# error no gpio arrays defined
+#endif
+};
+
+#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
+static unsigned short * const port_fer[] = {
+ (unsigned short *) PORTF_FER,
+ (unsigned short *) PORTG_FER,
+ (unsigned short *) PORTH_FER,
+};
+
+# if !defined(BF537_FAMILY)
+static unsigned short * const port_mux[] = {
+ (unsigned short *) PORTF_MUX,
+ (unsigned short *) PORTG_MUX,
+ (unsigned short *) PORTH_MUX,
+};
+
+static const
+u8 pmux_offset[][16] = {
+# if defined(CONFIG_BF52x)
+ { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
+ { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
+# elif defined(CONFIG_BF51x)
+ { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
+ { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
+ { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
+# endif
+};
+# endif
+
+#elif defined(BF538_FAMILY)
+static unsigned short * const port_fer[] = {
+ (unsigned short *) PORTCIO_FER,
+ (unsigned short *) PORTDIO_FER,
+ (unsigned short *) PORTEIO_FER,
+};
+#endif
+
+#ifdef CONFIG_BFIN_GPIO_TRACK
+#define RESOURCE_LABEL_SIZE 16
+
+static struct str_ident {
+ char name[RESOURCE_LABEL_SIZE];
+} str_ident[MAX_RESOURCES];
+
+static void gpio_error(unsigned gpio)
+{
+ printf("bfin-gpio: GPIO %d wasn't requested!\n", gpio);
+}
+
+static void set_label(unsigned short ident, const char *label)
+{
+ if (label) {
+ strncpy(str_ident[ident].name, label,
+ RESOURCE_LABEL_SIZE);
+ str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
+ }
+}
+
+static char *get_label(unsigned short ident)
+{
+ return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
+}
+
+static int cmp_label(unsigned short ident, const char *label)
+{
+ if (label == NULL)
+ printf("bfin-gpio: please provide none-null label\n");
+
+ if (label)
+ return strcmp(str_ident[ident].name, label);
+ else
+ return -EINVAL;
+}
+
+#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)]
+#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
+#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i))
+#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i))
+#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
+#else
+#define is_reserved(m, i, e) (!(e))
+#define reserve(m, i)
+#define unreserve(m, i)
+#define DECLARE_RESERVED_MAP(m, c)
+#define gpio_error(gpio)
+#define set_label(...)
+#define get_label(...) ""
+#define cmp_label(...) 1
+#endif
+
+DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
+DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES));
+
+inline int check_gpio(unsigned gpio)
+{
+#if defined(CONFIG_BF54x)
+ if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
+ || gpio == GPIO_PH14 || gpio == GPIO_PH15
+ || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
+ return -EINVAL;
+#endif
+ if (gpio >= MAX_BLACKFIN_GPIOS)
+ return -EINVAL;
+ return 0;
+}
+
+static void port_setup(unsigned gpio, unsigned short usage)
+{
+#if defined(BF538_FAMILY)
+ /*
+ * BF538/9 Port C,D and E are special.
+ * Inverted PORT_FER polarity on CDE and no PORF_FER on F
+ * Regular PORT F GPIOs are handled here, CDE are exclusively
+ * managed by GPIOLIB
+ */
+
+ if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
+ return;
+
+ gpio -= MAX_BLACKFIN_GPIOS;
+
+ if (usage == GPIO_USAGE)
+ *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
+ else
+ *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
+ SSYNC();
+ return;
+#endif
+
+ if (check_gpio(gpio))
+ return;
+
+#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
+ if (usage == GPIO_USAGE)
+ *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
+ else
+ *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
+ SSYNC();
+#elif defined(CONFIG_BF54x)
+ if (usage == GPIO_USAGE)
+ gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
+ else
+ gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
+ SSYNC();
+#endif
+}
+
+#ifdef BF537_FAMILY
+static struct {
+ unsigned short res;
+ unsigned short offset;
+} port_mux_lut[] = {
+ {.res = P_PPI0_D13, .offset = 11},
+ {.res = P_PPI0_D14, .offset = 11},
+ {.res = P_PPI0_D15, .offset = 11},
+ {.res = P_SPORT1_TFS, .offset = 11},
+ {.res = P_SPORT1_TSCLK, .offset = 11},
+ {.res = P_SPORT1_DTPRI, .offset = 11},
+ {.res = P_PPI0_D10, .offset = 10},
+ {.res = P_PPI0_D11, .offset = 10},
+ {.res = P_PPI0_D12, .offset = 10},
+ {.res = P_SPORT1_RSCLK, .offset = 10},
+ {.res = P_SPORT1_RFS, .offset = 10},
+ {.res = P_SPORT1_DRPRI, .offset = 10},
+ {.res = P_PPI0_D8, .offset = 9},
+ {.res = P_PPI0_D9, .offset = 9},
+ {.res = P_SPORT1_DRSEC, .offset = 9},
+ {.res = P_SPORT1_DTSEC, .offset = 9},
+ {.res = P_TMR2, .offset = 8},
+ {.res = P_PPI0_FS3, .offset = 8},
+ {.res = P_TMR3, .offset = 7},
+ {.res = P_SPI0_SSEL4, .offset = 7},
+ {.res = P_TMR4, .offset = 6},
+ {.res = P_SPI0_SSEL5, .offset = 6},
+ {.res = P_TMR5, .offset = 5},
+ {.res = P_SPI0_SSEL6, .offset = 5},
+ {.res = P_UART1_RX, .offset = 4},
+ {.res = P_UART1_TX, .offset = 4},
+ {.res = P_TMR6, .offset = 4},
+ {.res = P_TMR7, .offset = 4},
+ {.res = P_UART0_RX, .offset = 3},
+ {.res = P_UART0_TX, .offset = 3},
+ {.res = P_DMAR0, .offset = 3},
+ {.res = P_DMAR1, .offset = 3},
+ {.res = P_SPORT0_DTSEC, .offset = 1},
+ {.res = P_SPORT0_DRSEC, .offset = 1},
+ {.res = P_CAN0_RX, .offset = 1},
+ {.res = P_CAN0_TX, .offset = 1},
+ {.res = P_SPI0_SSEL7, .offset = 1},
+ {.res = P_SPORT0_TFS, .offset = 0},
+ {.res = P_SPORT0_DTPRI, .offset = 0},
+ {.res = P_SPI0_SSEL2, .offset = 0},
+ {.res = P_SPI0_SSEL3, .offset = 0},
+};
+
+static void portmux_setup(unsigned short per)
+{
+ u16 y, offset, muxreg;
+ u16 function = P_FUNCT2MUX(per);
+
+ for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
+ if (port_mux_lut[y].res == per) {
+
+ /* SET PORTMUX REG */
+
+ offset = port_mux_lut[y].offset;
+ muxreg = bfin_read_PORT_MUX();
+
+ if (offset != 1)
+ muxreg &= ~(1 << offset);
+ else
+ muxreg &= ~(3 << 1);
+
+ muxreg |= (function << offset);
+ bfin_write_PORT_MUX(muxreg);
+ }
+ }
+}
+#elif defined(CONFIG_BF54x)
+inline void portmux_setup(unsigned short per)
+{
+ u32 pmux;
+ u16 ident = P_IDENT(per);
+ u16 function = P_FUNCT2MUX(per);
+
+ pmux = gpio_array[gpio_bank(ident)]->port_mux;
+
+ pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
+ pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
+
+ gpio_array[gpio_bank(ident)]->port_mux = pmux;
+}
+
+inline u16 get_portmux(unsigned short per)
+{
+ u32 pmux;
+ u16 ident = P_IDENT(per);
+
+ pmux = gpio_array[gpio_bank(ident)]->port_mux;
+
+ return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
+}
+#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
+inline void portmux_setup(unsigned short per)
+{
+ u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per);
+ u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
+
+ pmux = *port_mux[gpio_bank(ident)];
+ pmux &= ~(3 << offset);
+ pmux |= (function & 3) << offset;
+ *port_mux[gpio_bank(ident)] = pmux;
+ SSYNC();
+}
+#else
+# define portmux_setup(...) do { } while (0)
+#endif
+
+#ifndef CONFIG_BF54x
+/***********************************************************
+*
+* FUNCTIONS: Blackfin General Purpose Ports Access Functions
+*
+* INPUTS/OUTPUTS:
+* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
+*
+*
+* DESCRIPTION: These functions abstract direct register access
+* to Blackfin processor General Purpose
+* Ports Regsiters
+*
+* CAUTION: These functions do not belong to the GPIO Driver API
+*************************************************************
+* MODIFICATION HISTORY :
+**************************************************************/
+
+/* Set a specific bit */
+
+#define SET_GPIO(name) \
+void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
+{ \
+ unsigned long flags; \
+ local_irq_save(flags); \
+ if (arg) \
+ gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
+ else \
+ gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
+ AWA_DUMMY_READ(name); \
+ local_irq_restore(flags); \
+}
+
+SET_GPIO(dir) /* set_gpio_dir() */
+SET_GPIO(inen) /* set_gpio_inen() */
+SET_GPIO(polar) /* set_gpio_polar() */
+SET_GPIO(edge) /* set_gpio_edge() */
+SET_GPIO(both) /* set_gpio_both() */
+
+
+#define SET_GPIO_SC(name) \
+void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
+{ \
+ unsigned long flags; \
+ if (ANOMALY_05000311 || ANOMALY_05000323) \
+ local_irq_save(flags); \
+ if (arg) \
+ gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
+ else \
+ gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
+ if (ANOMALY_05000311 || ANOMALY_05000323) { \
+ AWA_DUMMY_READ(name); \
+ local_irq_restore(flags); \
+ } \
+}
+
+SET_GPIO_SC(maska)
+SET_GPIO_SC(maskb)
+SET_GPIO_SC(data)
+
+void set_gpio_toggle(unsigned gpio)
+{
+ unsigned long flags;
+ if (ANOMALY_05000311 || ANOMALY_05000323)
+ local_irq_save(flags);
+ gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
+ if (ANOMALY_05000311 || ANOMALY_05000323) {
+ AWA_DUMMY_READ(toggle);
+ local_irq_restore(flags);
+ }
+}
+
+/* Set current PORT date (16-bit word) */
+
+#define SET_GPIO_P(name) \
+void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
+{ \
+ unsigned long flags; \
+ if (ANOMALY_05000311 || ANOMALY_05000323) \
+ local_irq_save(flags); \
+ gpio_array[gpio_bank(gpio)]->name = arg; \
+ if (ANOMALY_05000311 || ANOMALY_05000323) { \
+ AWA_DUMMY_READ(name); \
+ local_irq_restore(flags); \
+ } \
+}
+
+SET_GPIO_P(data)
+SET_GPIO_P(dir)
+SET_GPIO_P(inen)
+SET_GPIO_P(polar)
+SET_GPIO_P(edge)
+SET_GPIO_P(both)
+SET_GPIO_P(maska)
+SET_GPIO_P(maskb)
+
+/* Get a specific bit */
+#define GET_GPIO(name) \
+unsigned short get_gpio_ ## name(unsigned gpio) \
+{ \
+ unsigned long flags; \
+ unsigned short ret; \
+ if (ANOMALY_05000311 || ANOMALY_05000323) \
+ local_irq_save(flags); \
+ ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
+ if (ANOMALY_05000311 || ANOMALY_05000323) { \
+ AWA_DUMMY_READ(name); \
+ local_irq_restore(flags); \
+ } \
+ return ret; \
+}
+
+GET_GPIO(data)
+GET_GPIO(dir)
+GET_GPIO(inen)
+GET_GPIO(polar)
+GET_GPIO(edge)
+GET_GPIO(both)
+GET_GPIO(maska)
+GET_GPIO(maskb)
+
+/* Get current PORT date (16-bit word) */
+
+#define GET_GPIO_P(name) \
+unsigned short get_gpiop_ ## name(unsigned gpio) \
+{ \
+ unsigned long flags; \
+ unsigned short ret; \
+ if (ANOMALY_05000311 || ANOMALY_05000323) \
+ local_irq_save(flags); \
+ ret = (gpio_array[gpio_bank(gpio)]->name); \
+ if (ANOMALY_05000311 || ANOMALY_05000323) { \
+ AWA_DUMMY_READ(name); \
+ local_irq_restore(flags); \
+ } \
+ return ret; \
+}
+
+GET_GPIO_P(data)
+GET_GPIO_P(dir)
+GET_GPIO_P(inen)
+GET_GPIO_P(polar)
+GET_GPIO_P(edge)
+GET_GPIO_P(both)
+GET_GPIO_P(maska)
+GET_GPIO_P(maskb)
+
+#else /* CONFIG_BF54x */
+
+unsigned short get_gpio_dir(unsigned gpio)
+{
+ return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
+}
+
+#endif /* CONFIG_BF54x */
+
+/***********************************************************
+*
+* FUNCTIONS: Blackfin Peripheral Resource Allocation
+* and PortMux Setup
+*
+* INPUTS/OUTPUTS:
+* per Peripheral Identifier
+* label String
+*
+* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
+*
+* CAUTION:
+*************************************************************
+* MODIFICATION HISTORY :
+**************************************************************/
+
+int peripheral_request(unsigned short per, const char *label)
+{
+ unsigned short ident = P_IDENT(per);
+
+ /*
+ * Don't cares are pins with only one dedicated function
+ */
+
+ if (per & P_DONTCARE)
+ return 0;
+
+ if (!(per & P_DEFINED))
+ return -ENODEV;
+
+ BUG_ON(ident >= MAX_RESOURCES);
+
+ /* If a pin can be muxed as either GPIO or peripheral, make
+ * sure it is not already a GPIO pin when we request it.
+ */
+ if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
+ printf("%s: Peripheral %d is already reserved as GPIO by %s !\n",
+ __func__, ident, get_label(ident));
+ return -EBUSY;
+ }
+
+ if (unlikely(is_reserved(peri, ident, 1))) {
+
+ /*
+ * Pin functions like AMC address strobes my
+ * be requested and used by several drivers
+ */
+
+#ifdef CONFIG_BF54x
+ if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
+#else
+ if (!(per & P_MAYSHARE)) {
+#endif
+ /*
+ * Allow that the identical pin function can
+ * be requested from the same driver twice
+ */
+
+ if (cmp_label(ident, label) == 0)
+ goto anyway;
+
+ printf("%s: Peripheral %d function %d is already reserved by %s !\n",
+ __func__, ident, P_FUNCT2MUX(per), get_label(ident));
+ return -EBUSY;
+ }
+ }
+
+ anyway:
+ reserve(peri, ident);
+
+ portmux_setup(per);
+ port_setup(ident, PERIPHERAL_USAGE);
+
+ set_label(ident, label);
+
+ return 0;
+}
+
+int peripheral_request_list(const unsigned short per[], const char *label)
+{
+ u16 cnt;
+ int ret;
+
+ for (cnt = 0; per[cnt] != 0; cnt++) {
+
+ ret = peripheral_request(per[cnt], label);
+
+ if (ret < 0) {
+ for ( ; cnt > 0; cnt--)
+ peripheral_free(per[cnt - 1]);
+
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+void peripheral_free(unsigned short per)
+{
+ unsigned short ident = P_IDENT(per);
+
+ if (per & P_DONTCARE)
+ return;
+
+ if (!(per & P_DEFINED))
+ return;
+
+ if (unlikely(!is_reserved(peri, ident, 0)))
+ return;
+
+ if (!(per & P_MAYSHARE))
+ port_setup(ident, GPIO_USAGE);
+
+ unreserve(peri, ident);
+
+ set_label(ident, "free");
+}
+
+void peripheral_free_list(const unsigned short per[])
+{
+ u16 cnt;
+ for (cnt = 0; per[cnt] != 0; cnt++)
+ peripheral_free(per[cnt]);
+}
+
+/***********************************************************
+*
+* FUNCTIONS: Blackfin GPIO Driver
+*
+* INPUTS/OUTPUTS:
+* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
+* label String
+*
+* DESCRIPTION: Blackfin GPIO Driver API
+*
+* CAUTION:
+*************************************************************
+* MODIFICATION HISTORY :
+**************************************************************/
+
+int bfin_gpio_request(unsigned gpio, const char *label)
+{
+ if (check_gpio(gpio) < 0)
+ return -EINVAL;
+
+ /*
+ * Allow that the identical GPIO can
+ * be requested from the same driver twice
+ * Do nothing and return -
+ */
+
+ if (cmp_label(gpio, label) == 0)
+ return 0;
+
+ if (unlikely(is_reserved(gpio, gpio, 1))) {
+ printf("bfin-gpio: GPIO %d is already reserved by %s !\n",
+ gpio, get_label(gpio));
+ return -EBUSY;
+ }
+ if (unlikely(is_reserved(peri, gpio, 1))) {
+ printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
+ gpio, get_label(gpio));
+ return -EBUSY;
+ }
+#ifndef CONFIG_BF54x
+ else { /* Reset POLAR setting when acquiring a gpio for the first time */
+ set_gpio_polar(gpio, 0);
+ }
+#endif
+
+ reserve(gpio, gpio);
+ set_label(gpio, label);
+
+ port_setup(gpio, GPIO_USAGE);
+
+ return 0;
+}
+
+void bfin_gpio_free(unsigned gpio)
+{
+ if (check_gpio(gpio) < 0)
+ return;
+
+ if (unlikely(!is_reserved(gpio, gpio, 0))) {
+ gpio_error(gpio);
+ return;
+ }
+
+ unreserve(gpio, gpio);
+
+ set_label(gpio, "free");
+}
+
+#ifdef BFIN_SPECIAL_GPIO_BANKS
+DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
+
+int bfin_special_gpio_request(unsigned gpio, const char *label)
+{
+ /*
+ * Allow that the identical GPIO can
+ * be requested from the same driver twice
+ * Do nothing and return -
+ */
+
+ if (cmp_label(gpio, label) == 0)
+ return 0;
+
+ if (unlikely(is_reserved(special_gpio, gpio, 1))) {
+ printf("bfin-gpio: GPIO %d is already reserved by %s !\n",
+ gpio, get_label(gpio));
+ return -EBUSY;
+ }
+ if (unlikely(is_reserved(peri, gpio, 1))) {
+ printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
+ gpio, get_label(gpio));
+
+ return -EBUSY;
+ }
+
+ reserve(special_gpio, gpio);
+ reserve(peri, gpio);
+
+ set_label(gpio, label);
+ port_setup(gpio, GPIO_USAGE);
+
+ return 0;
+}
+
+void bfin_special_gpio_free(unsigned gpio)
+{
+ if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
+ gpio_error(gpio);
+ return;
+ }
+
+ reserve(special_gpio, gpio);
+ reserve(peri, gpio);
+ set_label(gpio, "free");
+}
+#endif
+
+static inline void __bfin_gpio_direction_input(unsigned gpio)
+{
+#ifdef CONFIG_BF54x
+ gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
+#else
+ gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
+#endif
+ gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
+}
+
+int bfin_gpio_direction_input(unsigned gpio)
+{
+ unsigned long flags;
+
+ if (!is_reserved(gpio, gpio, 0)) {
+ gpio_error(gpio);
+ return -EINVAL;
+ }
+
+ local_irq_save(flags);
+ __bfin_gpio_direction_input(gpio);
+ AWA_DUMMY_READ(inen);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+void bfin_gpio_toggle_value(unsigned gpio)
+{
+#ifdef CONFIG_BF54x
+ gpio_set_value(gpio, !gpio_get_value(gpio));
+#else
+ gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
+#endif
+}
+
+void bfin_gpio_set_value(unsigned gpio, int arg)
+{
+ if (arg)
+ gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
+ else
+ gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
+}
+
+int bfin_gpio_direction_output(unsigned gpio, int value)
+{
+ unsigned long flags;
+
+ if (!is_reserved(gpio, gpio, 0)) {
+ gpio_error(gpio);
+ return -EINVAL;
+ }
+
+ local_irq_save(flags);
+
+ gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
+ gpio_set_value(gpio, value);
+#ifdef CONFIG_BF54x
+ gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
+#else
+ gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
+#endif
+
+ AWA_DUMMY_READ(dir);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+int bfin_gpio_get_value(unsigned gpio)
+{
+#ifdef CONFIG_BF54x
+ return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
+#else
+ unsigned long flags;
+
+ if (unlikely(get_gpio_edge(gpio))) {
+ int ret;
+ local_irq_save(flags);
+ set_gpio_edge(gpio, 0);
+ ret = get_gpio_data(gpio);
+ set_gpio_edge(gpio, 1);
+ local_irq_restore(flags);
+ return ret;
+ } else
+ return get_gpio_data(gpio);
+#endif
+}
+
+/* If we are booting from SPI and our board lacks a strong enough pull up,
+ * the core can reset and execute the bootrom faster than the resistor can
+ * pull the signal logically high. To work around this (common) error in
+ * board design, we explicitly set the pin back to GPIO mode, force /CS
+ * high, and wait for the electrons to do their thing.
+ *
+ * This function only makes sense to be called from reset code, but it
+ * lives here as we need to force all the GPIO states w/out going through
+ * BUG() checks and such.
+ */
+void bfin_reset_boot_spi_cs(unsigned short pin)
+{
+ unsigned short gpio = P_IDENT(pin);
+ port_setup(gpio, GPIO_USAGE);
+ gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
+ AWA_DUMMY_READ(data_set);
+ udelay(1);
+}
+
+#ifdef CONFIG_BFIN_GPIO_TRACK
+void bfin_gpio_labels(void)
+{
+ int c, gpio;
+
+ for (c = 0; c < MAX_RESOURCES; c++) {
+ gpio = is_reserved(gpio, c, 1);
+ if (!check_gpio(c) && gpio)
+ printf("GPIO_%d:\t%s\tGPIO %s\n", c,
+ get_label(c),
+ get_gpio_dir(c) ? "OUTPUT" : "INPUT");
+ else if (is_reserved(peri, c, 1))
+ printf("GPIO_%d:\t%s\tPeripheral\n", c, get_label(c));
+ else
+ continue;
+ }
+}
+#endif
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
index 5f80ad6..007f5ce 100644
--- a/arch/blackfin/cpu/initcode.c
+++ b/arch/blackfin/cpu/initcode.c
@@ -101,6 +101,28 @@
continue;
}
+__attribute__((always_inline)) static inline void
+program_nmi_handler(void)
+{
+ u32 tmp1, tmp2;
+
+ /* Older bootroms don't create a dummy NMI handler,
+ * so make one ourselves ASAP in case it fires.
+ */
+ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
+ return;
+
+ asm volatile (
+ "%0 = RETS;" /* Save current RETS */
+ "CALL 1f;" /* Figure out current PC */
+ "RTN;" /* The simple NMI handler */
+ "1:"
+ "%1 = RETS;" /* Load addr of NMI handler */
+ "RETS = %0;" /* Restore RETS */
+ "[%2] = %1;" /* Write NMI handler */
+ : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2)
+ );
+}
/* Max SCLK can be 133MHz ... dividing that by (2*4) gives
* us a freq of 16MHz for SPI which should generally be
@@ -640,6 +662,9 @@
{
ADI_BOOT_DATA bootstruct_scratch;
+ /* Setup NMI handler before anything else */
+ program_nmi_handler();
+
serial_init();
serial_putc('A');
@@ -675,7 +700,12 @@
#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
serial_putc('I');
- /* tell the bootrom where our entry point is */
+ /* Tell the bootrom where our entry point is so that it knows
+ * where to jump to when finishing processing the LDR. This
+ * allows us to avoid small jump blocks in the LDR, and also
+ * works around anomaly 05000389 (init address in external
+ * memory causes bootrom to trigger external addressing IVHW).
+ */
if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
#endif
diff --git a/arch/blackfin/cpu/interrupt.S b/arch/blackfin/cpu/interrupt.S
index 69bba3f..0e5e59e 100644
--- a/arch/blackfin/cpu/interrupt.S
+++ b/arch/blackfin/cpu/interrupt.S
@@ -150,3 +150,8 @@
RESTORE_ALL_SYS
rti;
ENDPROC(_evt_default)
+
+/* NMI handler */
+ENTRY(_evt_nmi)
+ rtn;
+ENDPROC(_evt_nmi)
diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h
index 5f9be86..f9e311f 100644
--- a/arch/blackfin/cpu/serial.h
+++ b/arch/blackfin/cpu/serial.h
@@ -26,6 +26,8 @@
#ifndef __ASSEMBLY__
+#include <asm/portmux.h>
+
#define LOB(x) ((x) & 0xFF)
#define HIB(x) (((x) >> 8) & 0xFF)
@@ -103,6 +105,23 @@
__attribute__((always_inline))
static inline void serial_do_portmux(void)
{
+ if (!BFIN_DEBUG_EARLY_SERIAL) {
+ const unsigned short pins[] = {
+#if CONFIG_UART_CONSOLE == 0
+ P_UART0_TX, P_UART0_RX,
+#elif CONFIG_UART_CONSOLE == 1
+ P_UART1_TX, P_UART1_RX,
+#elif CONFIG_UART_CONSOLE == 2
+ P_UART2_TX, P_UART2_RX,
+#elif CONFIG_UART_CONSOLE == 3
+ P_UART3_TX, P_UART3_RX,
+#endif
+ 0,
+ };
+ peripheral_request_list(pins, "bfin-uart");
+ return;
+ }
+
#if defined(__ADSPBF51x__)
# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \
diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c
index caaea94..09388aa 100644
--- a/arch/blackfin/cpu/traps.c
+++ b/arch/blackfin/cpu/traps.c
@@ -29,14 +29,26 @@
#include <asm/deferred.h>
#include "cpu.h"
+#ifdef CONFIG_DEBUG_DUMP
+# define ENABLE_DUMP 1
+#else
+# define ENABLE_DUMP 0
+#endif
+
#define trace_buffer_save(x) \
do { \
+ if (!ENABLE_DUMP) \
+ break; \
(x) = bfin_read_TBUFCTL(); \
bfin_write_TBUFCTL((x) & ~TBUFEN); \
} while (0)
#define trace_buffer_restore(x) \
- bfin_write_TBUFCTL((x))
+ do { \
+ if (!ENABLE_DUMP) \
+ break; \
+ bfin_write_TBUFCTL((x)); \
+ } while (0);
/* The purpose of this map is to provide a mapping of address<->cplb settings
* rather than an exact map of what is actually addressable on the part. This
@@ -82,8 +94,16 @@
{
uint32_t ret = 0;
uint32_t trapnr = (regs->seqstat & EXCAUSE);
+ unsigned long tflags;
bool data = false;
+ /*
+ * Keep the trace buffer so that a miss here points people
+ * to the right place (their code). Crashes here rarely
+ * happen. If they do, only the Blackfin maintainer cares.
+ */
+ trace_buffer_save(tflags);
+
switch (trapnr) {
/* 0x26 - Data CPLB Miss */
case VEC_CPLB_M:
@@ -97,7 +117,7 @@
*/
if (last_cplb_fault_retx != regs->retx) {
last_cplb_fault_retx = regs->retx;
- return ret;
+ break;
}
}
@@ -110,7 +130,6 @@
uint32_t new_cplb_addr = 0, new_cplb_data = 0;
static size_t last_evicted;
size_t i;
- unsigned long tflags;
#ifdef CONFIG_EXCEPTION_DEFER
/* This should never happen */
@@ -118,13 +137,6 @@
bfin_panic(regs);
#endif
- /*
- * Keep the trace buffer so that a miss here points people
- * to the right place (their code). Crashes here rarely
- * happen. If they do, only the Blackfin maintainer cares.
- */
- trace_buffer_save(tflags);
-
new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
@@ -180,7 +192,6 @@
for (i = 0; i < 16; ++i)
debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
- trace_buffer_restore(tflags);
break;
}
#ifdef CONFIG_CMD_KGDB
@@ -208,23 +219,21 @@
#ifdef CONFIG_CMD_KGDB
if (level == 3) {
/* We need to handle this at EVT5, so try again */
+ bfin_dump(regs);
ret = 1;
break;
}
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- return 0;
+ break;
#endif
bfin_panic(regs);
}
+
+ trace_buffer_restore(tflags);
+
return ret;
}
-#ifdef CONFIG_DEBUG_DUMP
-# define ENABLE_DUMP 1
-#else
-# define ENABLE_DUMP 0
-#endif
-
#ifndef CONFIG_KALLSYMS
const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
{
@@ -364,17 +373,14 @@
printf("\n");
}
-void dump_bfin_trace_buffer(void)
+static void _dump_bfin_trace_buffer(void)
{
char buf[150];
- unsigned long tflags;
int i = 0;
if (!ENABLE_DUMP)
return;
- trace_buffer_save(tflags);
-
printf("Hardware Trace:\n");
if (bfin_read_TBUFSTAT() & TBUFCNT) {
@@ -385,16 +391,21 @@
printf(" Source : %s\n", buf);
}
}
+}
+void dump_bfin_trace_buffer(void)
+{
+ unsigned long tflags;
+ trace_buffer_save(tflags);
+ _dump_bfin_trace_buffer();
trace_buffer_restore(tflags);
}
-void bfin_panic(struct pt_regs *regs)
+void bfin_dump(struct pt_regs *regs)
{
- if (ENABLE_DUMP) {
- unsigned long tflags;
- trace_buffer_save(tflags);
- }
+ unsigned long tflags;
+
+ trace_buffer_save(tflags);
puts(
"\n"
@@ -404,7 +415,16 @@
"\n"
);
dump(regs);
- dump_bfin_trace_buffer();
+ _dump_bfin_trace_buffer();
puts("\n");
+
+ trace_buffer_restore(tflags);
+}
+
+void bfin_panic(struct pt_regs *regs)
+{
+ unsigned long tflags;
+ trace_buffer_save(tflags);
+ bfin_dump(regs);
bfin_reset_or_hang();
}
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
index 3fd34b3..48f793a 100644
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -75,7 +75,15 @@
* regions can only be accessed via DMA, so if the address in question is in
* that region, make sure we attempt to DMA indirectly.
*/
-# define addr_bfin_on_chip_mem(addr) (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
+# ifdef __ADSPBF561__
+ /* Core B regions all need dma from Core A */
+# define addr_bfin_on_chip_mem(addr) \
+ ((((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) || \
+ (((unsigned long)(addr) & 0xFFC00000) == 0xFF400000))
+# else
+# define addr_bfin_on_chip_mem(addr) \
+ (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
+# endif
# include <asm/system.h>
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
new file mode 100644
index 0000000..b650ef0
--- /dev/null
+++ b/arch/blackfin/include/asm/gpio.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright 2006-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ARCH_BLACKFIN_GPIO_H__
+#define __ARCH_BLACKFIN_GPIO_H__
+
+#define gpio_bank(x) ((x) >> 4)
+#define gpio_bit(x) (1<<((x) & 0xF))
+#define gpio_sub_n(x) ((x) & 0xF)
+
+#define GPIO_BANKSIZE 16
+#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
+
+#define GPIO_0 0
+#define GPIO_1 1
+#define GPIO_2 2
+#define GPIO_3 3
+#define GPIO_4 4
+#define GPIO_5 5
+#define GPIO_6 6
+#define GPIO_7 7
+#define GPIO_8 8
+#define GPIO_9 9
+#define GPIO_10 10
+#define GPIO_11 11
+#define GPIO_12 12
+#define GPIO_13 13
+#define GPIO_14 14
+#define GPIO_15 15
+#define GPIO_16 16
+#define GPIO_17 17
+#define GPIO_18 18
+#define GPIO_19 19
+#define GPIO_20 20
+#define GPIO_21 21
+#define GPIO_22 22
+#define GPIO_23 23
+#define GPIO_24 24
+#define GPIO_25 25
+#define GPIO_26 26
+#define GPIO_27 27
+#define GPIO_28 28
+#define GPIO_29 29
+#define GPIO_30 30
+#define GPIO_31 31
+#define GPIO_32 32
+#define GPIO_33 33
+#define GPIO_34 34
+#define GPIO_35 35
+#define GPIO_36 36
+#define GPIO_37 37
+#define GPIO_38 38
+#define GPIO_39 39
+#define GPIO_40 40
+#define GPIO_41 41
+#define GPIO_42 42
+#define GPIO_43 43
+#define GPIO_44 44
+#define GPIO_45 45
+#define GPIO_46 46
+#define GPIO_47 47
+
+#define PERIPHERAL_USAGE 1
+#define GPIO_USAGE 0
+
+#ifndef __ASSEMBLY__
+
+#ifndef CONFIG_BF54x
+void set_gpio_dir(unsigned, unsigned short);
+void set_gpio_inen(unsigned, unsigned short);
+void set_gpio_polar(unsigned, unsigned short);
+void set_gpio_edge(unsigned, unsigned short);
+void set_gpio_both(unsigned, unsigned short);
+void set_gpio_data(unsigned, unsigned short);
+void set_gpio_maska(unsigned, unsigned short);
+void set_gpio_maskb(unsigned, unsigned short);
+void set_gpio_toggle(unsigned);
+void set_gpiop_dir(unsigned, unsigned short);
+void set_gpiop_inen(unsigned, unsigned short);
+void set_gpiop_polar(unsigned, unsigned short);
+void set_gpiop_edge(unsigned, unsigned short);
+void set_gpiop_both(unsigned, unsigned short);
+void set_gpiop_data(unsigned, unsigned short);
+void set_gpiop_maska(unsigned, unsigned short);
+void set_gpiop_maskb(unsigned, unsigned short);
+unsigned short get_gpio_dir(unsigned);
+unsigned short get_gpio_inen(unsigned);
+unsigned short get_gpio_polar(unsigned);
+unsigned short get_gpio_edge(unsigned);
+unsigned short get_gpio_both(unsigned);
+unsigned short get_gpio_maska(unsigned);
+unsigned short get_gpio_maskb(unsigned);
+unsigned short get_gpio_data(unsigned);
+unsigned short get_gpiop_dir(unsigned);
+unsigned short get_gpiop_inen(unsigned);
+unsigned short get_gpiop_polar(unsigned);
+unsigned short get_gpiop_edge(unsigned);
+unsigned short get_gpiop_both(unsigned);
+unsigned short get_gpiop_maska(unsigned);
+unsigned short get_gpiop_maskb(unsigned);
+unsigned short get_gpiop_data(unsigned);
+
+struct gpio_port_t {
+ unsigned short data;
+ unsigned short dummy1;
+ unsigned short data_clear;
+ unsigned short dummy2;
+ unsigned short data_set;
+ unsigned short dummy3;
+ unsigned short toggle;
+ unsigned short dummy4;
+ unsigned short maska;
+ unsigned short dummy5;
+ unsigned short maska_clear;
+ unsigned short dummy6;
+ unsigned short maska_set;
+ unsigned short dummy7;
+ unsigned short maska_toggle;
+ unsigned short dummy8;
+ unsigned short maskb;
+ unsigned short dummy9;
+ unsigned short maskb_clear;
+ unsigned short dummy10;
+ unsigned short maskb_set;
+ unsigned short dummy11;
+ unsigned short maskb_toggle;
+ unsigned short dummy12;
+ unsigned short dir;
+ unsigned short dummy13;
+ unsigned short polar;
+ unsigned short dummy14;
+ unsigned short edge;
+ unsigned short dummy15;
+ unsigned short both;
+ unsigned short dummy16;
+ unsigned short inen;
+};
+#endif
+
+#ifdef CONFIG_BFIN_GPIO_TRACK
+void bfin_gpio_labels(void);
+#else
+#define bfin_gpio_labels()
+#define bfin_gpio_request(gpio, label) bfin_gpio_request(gpio)
+#define bfin_special_gpio_request(gpio, label) bfin_special_gpio_request(gpio)
+#endif
+
+#ifdef BFIN_SPECIAL_GPIO_BANKS
+void bfin_special_gpio_free(unsigned gpio);
+int bfin_special_gpio_request(unsigned gpio, const char *label);
+#endif
+
+int bfin_gpio_request(unsigned gpio, const char *label);
+void bfin_gpio_free(unsigned gpio);
+int bfin_gpio_direction_input(unsigned gpio);
+int bfin_gpio_direction_output(unsigned gpio, int value);
+int bfin_gpio_get_value(unsigned gpio);
+void bfin_gpio_set_value(unsigned gpio, int value);
+void bfin_gpio_toggle_value(unsigned gpio);
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+ return bfin_gpio_request(gpio, label);
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+ return bfin_gpio_free(gpio);
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+ return bfin_gpio_direction_input(gpio);
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+ return bfin_gpio_direction_output(gpio, value);
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+ return bfin_gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+ return bfin_gpio_set_value(gpio, value);
+}
+
+static inline int gpio_is_valid(int number)
+{
+ return number >= 0 && number < MAX_BLACKFIN_GPIOS;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/anomaly.h b/arch/blackfin/include/asm/mach-bf527/anomaly.h
index 0fd7e31..9358afa 100644
--- a/arch/blackfin/include/asm/mach-bf527/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf527/anomaly.h
@@ -1,19 +1,28 @@
/*
- * File: include/asm-blackfin/mach-bf527/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
*
- * Copyright (C) 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
+ * Copyright 2004-2010 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List
+ * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
+ * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
+/* We do not support old silicon - sorry */
+#if __SILICON_REVISION__ < 0
+# error will not work on BF526/BF527 silicon version
+#endif
+
#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
# define ANOMALY_BF526 1
#else
@@ -25,10 +34,14 @@
# define ANOMALY_BF527 0
#endif
-/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
+#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
+#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
+
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
+#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -40,167 +53,226 @@
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
/* Host DMA Boot Modes Are Not Functional */
#define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
/* USB Calibration Value to use */
#define ANOMALY_05000346_value 0xE510
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
+#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (ANOMALY_BF526)
+#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
+#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Incorrect Default CSEL Value in PLL_DIV */
-#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
-#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
-#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
#define ANOMALY_05000405 (1)
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
#define ANOMALY_05000408 (1)
/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Incorrect Default Internal Voltage Regulator Setting */
-#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2))
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
/* DEB2_URGENT Bit Not Functional */
-#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
-#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
-#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
-#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
#define ANOMALY_05000421 (1)
/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
-#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Internal Voltage Regulator Not Trimmed */
-#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (1)
/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
-#define ANOMALY_05000432 (ANOMALY_BF526)
+#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
+/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
+#define ANOMALY_05000434 (1)
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
+#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (1)
+#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (1)
+#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
+#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* The WURESET Bit in the SYSCR Register is not Functional */
#define ANOMALY_05000445 (1)
+/* USB DMA Mode 1 Short Packet Data Corruption */
+#define ANOMALY_05000450 (1)
/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
#define ANOMALY_05000451 (1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (1)
+#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
#define ANOMALY_05000456 (1)
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
#define ANOMALY_05000457 (1)
+/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
+#define ANOMALY_05000460 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* USB Rx DMA hang */
+#define ANOMALY_05000465 (1)
+/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
+#define ANOMALY_05000466 (1)
+/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
+#define ANOMALY_05000467 (1)
+/* PLL Latches Incorrect Settings During Reset */
+#define ANOMALY_05000469 (1)
+/* Incorrect Default MSEL Value in PLL_CTL */
+#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* Possible Lockup Condition whem Modifying PLL from External Memory */
+#define ANOMALY_05000475 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
+#define ANOMALY_05000483 (1)
+/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
+#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000099 (0)
+#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
+#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
+#define ANOMALY_05000179 (0)
+#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
+#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
+#define ANOMALY_05000202 (0)
+#define ANOMALY_05000215 (0)
+#define ANOMALY_05000219 (0)
+#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000233 (0)
+#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0)
+#define ANOMALY_05000248 (0)
+#define ANOMALY_05000250 (0)
+#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
+#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
+#define ANOMALY_05000281 (0)
+#define ANOMALY_05000283 (0)
#define ANOMALY_05000285 (0)
+#define ANOMALY_05000287 (0)
+#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
+#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000400 (0)
+#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
+#define ANOMALY_05000474 (0)
#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/def_local.h b/arch/blackfin/include/asm/mach-bf527/def_local.h
index 81eca83..1ffa239 100644
--- a/arch/blackfin/include/asm/mach-bf527/def_local.h
+++ b/arch/blackfin/include/asm/mach-bf527/def_local.h
@@ -1,2 +1,6 @@
+#include "gpio.h"
#include "mem_map.h"
+#include "portmux.h"
#include "ports.h"
+
+#define CONFIG_BF52x 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf527/gpio.h b/arch/blackfin/include/asm/mach-bf527/gpio.h
new file mode 100644
index 0000000..f80c299
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/gpio.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 48
+
+#define GPIO_PF0 0
+#define GPIO_PF1 1
+#define GPIO_PF2 2
+#define GPIO_PF3 3
+#define GPIO_PF4 4
+#define GPIO_PF5 5
+#define GPIO_PF6 6
+#define GPIO_PF7 7
+#define GPIO_PF8 8
+#define GPIO_PF9 9
+#define GPIO_PF10 10
+#define GPIO_PF11 11
+#define GPIO_PF12 12
+#define GPIO_PF13 13
+#define GPIO_PF14 14
+#define GPIO_PF15 15
+#define GPIO_PG0 16
+#define GPIO_PG1 17
+#define GPIO_PG2 18
+#define GPIO_PG3 19
+#define GPIO_PG4 20
+#define GPIO_PG5 21
+#define GPIO_PG6 22
+#define GPIO_PG7 23
+#define GPIO_PG8 24
+#define GPIO_PG9 25
+#define GPIO_PG10 26
+#define GPIO_PG11 27
+#define GPIO_PG12 28
+#define GPIO_PG13 29
+#define GPIO_PG14 30
+#define GPIO_PG15 31
+#define GPIO_PH0 32
+#define GPIO_PH1 33
+#define GPIO_PH2 34
+#define GPIO_PH3 35
+#define GPIO_PH4 36
+#define GPIO_PH5 37
+#define GPIO_PH6 38
+#define GPIO_PH7 39
+#define GPIO_PH8 40
+#define GPIO_PH9 41
+#define GPIO_PH10 42
+#define GPIO_PH11 43
+#define GPIO_PH12 44
+#define GPIO_PH13 45
+#define GPIO_PH14 46
+#define GPIO_PH15 47
+
+#define PORT_F GPIO_PF0
+#define PORT_G GPIO_PG0
+#define PORT_H GPIO_PH0
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf527/portmux.h b/arch/blackfin/include/asm/mach-bf527/portmux.h
new file mode 100644
index 0000000..aa16558
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/portmux.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
+
+#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
+#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
+#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
+#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
+#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
+#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
+#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
+#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
+#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
+#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
+#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
+#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
+#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
+#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
+
+#if !defined(CONFIG_BF527_SPORT0_PORTG)
+#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#else
+#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
+#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
+#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
+#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
+#if !defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
+#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
+#else
+#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+#endif
+#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#endif
+
+#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
+#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
+#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
+#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
+#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+
+#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
+#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
+
+#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
+#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
+
+#if !defined(CONFIG_BF527_UART1_PORTG)
+#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
+#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
+#else
+#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
+#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
+#endif
+
+#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
+#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
+#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
+
+#define P_HWAIT (P_DONTCARE)
+
+#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
+#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
+
+#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
+#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
+#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
+#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
+#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
+#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
+#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
+#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
+#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
+#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
+#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
+
+#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
+#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
+#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
+
+#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
+#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
+#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
+#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
+
+#if defined(CONFIG_BF527_NAND_D_PORTF)
+#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
+#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
+#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
+#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
+#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
+#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
+#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
+#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
+#else /*if defined(CONFIG_BF527_NAND_D_PORTH)*/
+#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
+#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
+#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
+#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
+#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
+#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
+#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
+#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
+#endif
+
+#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
+#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
+#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
+#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
+#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
+#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
+#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
+#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
+
+#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
+#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
+#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
+#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
+#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
+#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
+#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
+#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
+#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
+#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
+#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
+#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
+#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
+#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
+#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
+#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
+
+#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
+#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
+#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
+#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
+#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
+#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
+#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
+#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
+#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
+#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
+#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
+#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
+#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
+#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
+#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
+#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
+#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
+#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
+
+#define P_TWI0_SCL (P_DONTCARE)
+#define P_TWI0_SDA (P_DONTCARE)
+#define P_PPI0_FS1 (P_DONTCARE)
+#define P_TMR0 (P_DONTCARE)
+#define P_TMRCLK (P_DONTCARE)
+#define P_PPI0_CLK (P_DONTCARE)
+
+#define P_MII0 {\
+ P_MII0_ETxD0, \
+ P_MII0_ETxD1, \
+ P_MII0_ETxD2, \
+ P_MII0_ETxD3, \
+ P_MII0_ETxEN, \
+ P_MII0_TxCLK, \
+ P_MII0_PHYINT, \
+ P_MII0_COL, \
+ P_MII0_ERxD0, \
+ P_MII0_ERxD1, \
+ P_MII0_ERxD2, \
+ P_MII0_ERxD3, \
+ P_MII0_ERxDV, \
+ P_MII0_ERxCLK, \
+ P_MII0_ERxER, \
+ P_MII0_CRS, \
+ P_MDC, \
+ P_MDIO, 0}
+
+#define P_RMII0 {\
+ P_MII0_ETxD0, \
+ P_MII0_ETxD1, \
+ P_MII0_ETxEN, \
+ P_MII0_ERxD0, \
+ P_MII0_ERxD1, \
+ P_MII0_ERxER, \
+ P_RMII0_REF_CLK, \
+ P_RMII0_MDINT, \
+ P_RMII0_CRS_DV, \
+ P_MDC, \
+ P_MDIO, 0}
+
+#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf533/anomaly.h b/arch/blackfin/include/asm/mach-bf533/anomaly.h
index c98747f..78f8721 100644
--- a/arch/blackfin/include/asm/mach-bf533/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf533/anomaly.h
@@ -1,9 +1,13 @@
/*
- * File: include/asm-blackfin/mach-bf533/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
*
- * Copyright (C) 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
+ * Copyright 2004-2010 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
@@ -34,7 +38,7 @@
# define ANOMALY_BF533 0
#endif
-/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
@@ -46,7 +50,7 @@
#define ANOMALY_05000122 (1)
/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
+/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1)
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
#define ANOMALY_05000167 (1)
@@ -56,13 +60,13 @@
#define ANOMALY_05000180 (1)
/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-/* False Protection Exceptions */
+/* False Protection Exceptions when Speculative Fetch Is Cancelled */
#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
/* Restarting SPORT in Specific Modes May Cause Data Corruption */
#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-/* Failing MMR Accesses When Stalled by Preceding Memory Read */
+/* Failing MMR Accesses when Preceding Memory Read Stalls */
#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
/* Current DMA Address Shows Wrong Value During Carry Fix */
#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
@@ -74,7 +78,7 @@
#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
+/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
/* Recovery from "Brown-Out" Condition */
#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
@@ -106,7 +110,7 @@
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
-/* Data CPLBs Should Prevent Spurious Hardware Errors */
+/* Data CPLBs Should Prevent False Hardware Errors */
#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
@@ -148,21 +152,21 @@
#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error Exception When ISR Context Is Not Restored */
+/* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
-/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
+/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
-/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
+/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
+/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
@@ -170,11 +174,11 @@
#define ANOMALY_05000310 (1)
/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
-/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
+/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
@@ -200,6 +204,18 @@
#define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_05000461 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* Possible Lockup Condition whem Modifying PLL from External Memory */
+#define ANOMALY_05000475 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
@@ -213,17 +229,17 @@
#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
/* Writing FIO_DIR can corrupt a programmable flag's data */
#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
-/* Timer Auto-Baud Mode requires the UART clock to be enabled */
+/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
/* Internal Clocking Modes on SPORT0 not supported */
#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
/* Internal voltage regulator does not wake up from an RTC wakeup */
#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
-/* The IFLUSH instruction must be preceded by a CSYNC instruction */
+/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
-/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */
+/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
-/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */
+/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
@@ -233,45 +249,45 @@
#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
-/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
+/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
-/* Incorrect value written to the cycle counters */
+/* Incorrect Value Written to the Cycle Counters */
#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
-/* Stores to L1 Data memory incorrect when a specific sequence is followed */
+/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
/* Programmable Flag (PF3) functionality not supported in all PPI modes */
#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
/* Data store can be lost when targeting a cache line fill */
#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
-/* Reserved bits in SYSCFG register not set at power on */
+/* Reserved Bits in SYSCFG Register Not Set at Power-On */
#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
/* Infinite Core Stall */
#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
-/* PPI_FSx may glitch when generated by the on chip Timers */
+/* PPI_FSx may glitch when generated by the on chip Timers. */
#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
-/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
+/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
-/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */
+/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-/* Erroneous exception when enabling cache */
+/* Erroneous Exception when Enabling Cache */
#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
/* SPI clock polarity and phase bits incorrect during booting */
#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL is not set on Reset */
+/* DMEM_CONTROL<12> Is Not Set on Reset */
#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
/* SPI boot will not complete if there is a zero fill block in the loader file */
#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
-/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */
+/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
/* Allowing the SPORT RX FIFO to fill will cause an overflow */
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
+/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
@@ -285,7 +301,7 @@
#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
+/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
/* Frame Delay in SPORT Multichannel Mode */
#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
@@ -293,13 +309,13 @@
#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
-/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* SPORT transmit data is not gated by external frame sync in certain conditions */
+/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* SDRAM auto-refresh and subsequent Power Ups */
+/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
-/* DATA CPLB page miss can result in lost write-through cache data writes */
+/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
/* DMA vs Core accesses to external memory */
#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
@@ -307,32 +323,47 @@
#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
/* Overlapping Sequencer and Memory Stalls */
#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
-/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
+/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
-/* Disabling the PPI resets the PPI configuration registers */
+/* Disabling the PPI Resets the PPI Configuration Registers */
#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
-/* PPI TX Mode with 2 External Frame Syncs */
+/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* In PPI Transmit Modes with External Frame Syncs POLC */
+/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
/* Internal Voltage Regulator may not start up */
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000120 (0)
+#define ANOMALY_05000149 (0)
#define ANOMALY_05000171 (0)
+#define ANOMALY_05000182 (0)
+#define ANOMALY_05000220 (0)
+#define ANOMALY_05000248 (0)
#define ANOMALY_05000266 (0)
+#define ANOMALY_05000274 (0)
+#define ANOMALY_05000287 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000362 (1)
+#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
+#define ANOMALY_05000389 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
+#define ANOMALY_05000456 (0)
+#define ANOMALY_05000450 (0)
+#define ANOMALY_05000465 (0)
+#define ANOMALY_05000467 (0)
+#define ANOMALY_05000474 (0)
+#define ANOMALY_05000485 (0)
#endif
diff --git a/arch/blackfin/include/asm/mach-bf533/def_local.h b/arch/blackfin/include/asm/mach-bf533/def_local.h
index 14c111f..c545b54 100644
--- a/arch/blackfin/include/asm/mach-bf533/def_local.h
+++ b/arch/blackfin/include/asm/mach-bf533/def_local.h
@@ -1 +1,5 @@
+#include "gpio.h"
+#include "portmux.h"
#include "ports.h"
+
+#define BF533_FAMILY 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf533/gpio.h b/arch/blackfin/include/asm/mach-bf533/gpio.h
new file mode 100644
index 0000000..e02416d
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/gpio.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 16
+
+#define GPIO_PF0 0
+#define GPIO_PF1 1
+#define GPIO_PF2 2
+#define GPIO_PF3 3
+#define GPIO_PF4 4
+#define GPIO_PF5 5
+#define GPIO_PF6 6
+#define GPIO_PF7 7
+#define GPIO_PF8 8
+#define GPIO_PF9 9
+#define GPIO_PF10 10
+#define GPIO_PF11 11
+#define GPIO_PF12 12
+#define GPIO_PF13 13
+#define GPIO_PF14 14
+#define GPIO_PF15 15
+
+#define PORT_F GPIO_PF0
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf533/portmux.h b/arch/blackfin/include/asm/mach-bf533/portmux.h
new file mode 100644
index 0000000..96f5d91
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/portmux.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
+
+#define P_PPI0_CLK (P_DONTCARE)
+#define P_PPI0_FS1 (P_DONTCARE)
+#define P_PPI0_FS2 (P_DONTCARE)
+#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
+#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
+#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
+#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
+#define P_PPI0_D0 (P_DONTCARE)
+#define P_PPI0_D1 (P_DONTCARE)
+#define P_PPI0_D2 (P_DONTCARE)
+#define P_PPI0_D3 (P_DONTCARE)
+#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
+#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
+#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
+#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
+
+#define P_SPORT1_TSCLK (P_DONTCARE)
+#define P_SPORT1_RSCLK (P_DONTCARE)
+#define P_SPORT0_TSCLK (P_DONTCARE)
+#define P_SPORT0_RSCLK (P_DONTCARE)
+#define P_UART0_RX (P_DONTCARE)
+#define P_UART0_TX (P_DONTCARE)
+#define P_SPORT1_DRSEC (P_DONTCARE)
+#define P_SPORT1_RFS (P_DONTCARE)
+#define P_SPORT1_DTPRI (P_DONTCARE)
+#define P_SPORT1_DTSEC (P_DONTCARE)
+#define P_SPORT1_TFS (P_DONTCARE)
+#define P_SPORT1_DRPRI (P_DONTCARE)
+#define P_SPORT0_DRSEC (P_DONTCARE)
+#define P_SPORT0_RFS (P_DONTCARE)
+#define P_SPORT0_DTPRI (P_DONTCARE)
+#define P_SPORT0_DTSEC (P_DONTCARE)
+#define P_SPORT0_TFS (P_DONTCARE)
+#define P_SPORT0_DRPRI (P_DONTCARE)
+
+#define P_SPI0_MOSI (P_DONTCARE)
+#define P_SPI0_MISO (P_DONTCARE)
+#define P_SPI0_SCK (P_DONTCARE)
+#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
+#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
+#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
+#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
+#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
+
+#define P_TMR2 (P_DONTCARE)
+#define P_TMR1 (P_DONTCARE)
+#define P_TMR0 (P_DONTCARE)
+#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
+
+#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf537/anomaly.h b/arch/blackfin/include/asm/mach-bf537/anomaly.h
index b7f1a3f..43df6af 100644
--- a/arch/blackfin/include/asm/mach-bf537/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf537/anomaly.h
@@ -1,9 +1,13 @@
/*
- * File: include/asm-blackfin/mach-bf537/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
*
- * Copyright (C) 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
+ * Copyright 2004-2010 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
@@ -34,13 +38,13 @@
# define ANOMALY_BF537 0
#endif
-/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
-/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000180 (1)
@@ -50,11 +54,11 @@
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
-/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
+/* Buffered CLKIN Output Is Disabled by Default */
#define ANOMALY_05000247 (1)
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
-/* EMAC Tx DMA error after an early frame abort */
+/* EMAC TX DMA Error After an Early Frame Abort */
#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
/* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
@@ -62,7 +66,7 @@
#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
-/* EMAC MDIO input latched on wrong MDC edge */
+/* EMAC MDIO Input Latched on Wrong MDC Edge */
#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
@@ -80,7 +84,7 @@
#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
-/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
+/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
@@ -92,15 +96,15 @@
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
-/* SPI Master boot mode does not work well with Atmel Data flash devices */
+/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
#define ANOMALY_05000280 (1)
-/* False Hardware Error Exception When ISR Context Is Not Restored */
+/* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
-/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
+/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
-/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
+/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
@@ -112,25 +116,25 @@
#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
-/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
+/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
+/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
-/* EMAC RMII mode: collisions occur in Full Duplex mode */
+/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
-/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
+/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
-/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
+/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
#define ANOMALY_05000322 (1)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
-/* New Feature: UART Remains Enabled after UART Boot */
+/* UART Gets Disabled after UART Boot */
#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (1)
@@ -143,7 +147,7 @@
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
@@ -154,29 +158,66 @@
#define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_05000461 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* Possible Lockup Condition whem Modifying PLL from External Memory */
+#define ANOMALY_05000475 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000099 (0)
+#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
+#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
+#define ANOMALY_05000179 (0)
+#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
+#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
+#define ANOMALY_05000202 (0)
+#define ANOMALY_05000215 (0)
+#define ANOMALY_05000219 (0)
+#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000233 (0)
+#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
+#define ANOMALY_05000248 (0)
#define ANOMALY_05000266 (0)
+#define ANOMALY_05000274 (0)
+#define ANOMALY_05000287 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
+#define ANOMALY_05000389 (0)
+#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
+#define ANOMALY_05000456 (0)
+#define ANOMALY_05000450 (0)
+#define ANOMALY_05000465 (0)
+#define ANOMALY_05000467 (0)
+#define ANOMALY_05000474 (0)
+#define ANOMALY_05000485 (0)
#endif
diff --git a/arch/blackfin/include/asm/mach-bf537/def_local.h b/arch/blackfin/include/asm/mach-bf537/def_local.h
index 14c111f..e210db9 100644
--- a/arch/blackfin/include/asm/mach-bf537/def_local.h
+++ b/arch/blackfin/include/asm/mach-bf537/def_local.h
@@ -1 +1,5 @@
+#include "gpio.h"
+#include "portmux.h"
#include "ports.h"
+
+#define BF537_FAMILY 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf537/gpio.h b/arch/blackfin/include/asm/mach-bf537/gpio.h
new file mode 100644
index 0000000..f80c299
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/gpio.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 48
+
+#define GPIO_PF0 0
+#define GPIO_PF1 1
+#define GPIO_PF2 2
+#define GPIO_PF3 3
+#define GPIO_PF4 4
+#define GPIO_PF5 5
+#define GPIO_PF6 6
+#define GPIO_PF7 7
+#define GPIO_PF8 8
+#define GPIO_PF9 9
+#define GPIO_PF10 10
+#define GPIO_PF11 11
+#define GPIO_PF12 12
+#define GPIO_PF13 13
+#define GPIO_PF14 14
+#define GPIO_PF15 15
+#define GPIO_PG0 16
+#define GPIO_PG1 17
+#define GPIO_PG2 18
+#define GPIO_PG3 19
+#define GPIO_PG4 20
+#define GPIO_PG5 21
+#define GPIO_PG6 22
+#define GPIO_PG7 23
+#define GPIO_PG8 24
+#define GPIO_PG9 25
+#define GPIO_PG10 26
+#define GPIO_PG11 27
+#define GPIO_PG12 28
+#define GPIO_PG13 29
+#define GPIO_PG14 30
+#define GPIO_PG15 31
+#define GPIO_PH0 32
+#define GPIO_PH1 33
+#define GPIO_PH2 34
+#define GPIO_PH3 35
+#define GPIO_PH4 36
+#define GPIO_PH5 37
+#define GPIO_PH6 38
+#define GPIO_PH7 39
+#define GPIO_PH8 40
+#define GPIO_PH9 41
+#define GPIO_PH10 42
+#define GPIO_PH11 43
+#define GPIO_PH12 44
+#define GPIO_PH13 45
+#define GPIO_PH14 46
+#define GPIO_PH15 47
+
+#define PORT_F GPIO_PF0
+#define PORT_G GPIO_PG0
+#define PORT_H GPIO_PH0
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf537/portmux.h b/arch/blackfin/include/asm/mach-bf537/portmux.h
new file mode 100644
index 0000000..71d9eae
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/portmux.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
+
+#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
+#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
+#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
+#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
+#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
+#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
+#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
+#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
+#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
+#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
+#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
+#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
+#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
+#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
+#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
+#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
+
+#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
+#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
+#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
+#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
+#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
+#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
+#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
+#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
+#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
+#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
+#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
+#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
+#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
+#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
+
+#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
+#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
+#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
+#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
+#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
+#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
+#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
+#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
+#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
+#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
+#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
+#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
+#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
+#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
+#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
+#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
+#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
+#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
+#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
+
+#define PORT_PJ0 (GPIO_PH15 + 1)
+#define PORT_PJ1 (GPIO_PH15 + 2)
+#define PORT_PJ2 (GPIO_PH15 + 3)
+#define PORT_PJ3 (GPIO_PH15 + 4)
+#define PORT_PJ4 (GPIO_PH15 + 5)
+#define PORT_PJ5 (GPIO_PH15 + 6)
+#define PORT_PJ6 (GPIO_PH15 + 7)
+#define PORT_PJ7 (GPIO_PH15 + 8)
+#define PORT_PJ8 (GPIO_PH15 + 9)
+#define PORT_PJ9 (GPIO_PH15 + 10)
+#define PORT_PJ10 (GPIO_PH15 + 11)
+#define PORT_PJ11 (GPIO_PH15 + 12)
+
+#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
+#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
+#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
+#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
+#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
+#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
+#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
+#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
+#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
+#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
+#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
+#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
+#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
+#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
+#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
+#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
+#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
+
+#define P_MII0 {\
+ P_MII0_ETxD0, \
+ P_MII0_ETxD1, \
+ P_MII0_ETxD2, \
+ P_MII0_ETxD3, \
+ P_MII0_ETxEN, \
+ P_MII0_TxCLK, \
+ P_MII0_PHYINT, \
+ P_MII0_COL, \
+ P_MII0_ERxD0, \
+ P_MII0_ERxD1, \
+ P_MII0_ERxD2, \
+ P_MII0_ERxD3, \
+ P_MII0_ERxDV, \
+ P_MII0_ERxCLK, \
+ P_MII0_ERxER, \
+ P_MII0_CRS, \
+ P_MDC, \
+ P_MDIO, 0}
+
+#define P_RMII0 {\
+ P_MII0_ETxD0, \
+ P_MII0_ETxD1, \
+ P_MII0_ETxEN, \
+ P_MII0_ERxD0, \
+ P_MII0_ERxD1, \
+ P_MII0_ERxER, \
+ P_RMII0_REF_CLK, \
+ P_RMII0_MDINT, \
+ P_RMII0_CRS_DV, \
+ P_MDC, \
+ P_MDIO, 0}
+
+#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf548/anomaly.h b/arch/blackfin/include/asm/mach-bf548/anomaly.h
index 192dd67..7bda09c 100644
--- a/arch/blackfin/include/asm/mach-bf548/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf548/anomaly.h
@@ -1,41 +1,54 @@
/*
- * File: include/asm-blackfin/mach-bf548/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
*
- * Copyright (C) 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
+ * Copyright 2004-2010 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
-/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+/* We do not support 0.0 or 0.1 silicon - sorry */
+/* XXX: let u-boot slide
+#if __SILICON_REVISION__ < 2
+# error will not work on BF548 silicon version 0.0, or 0.1
+#endif
+*/
+
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
+/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
+#define ANOMALY_05000220 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
-/* False Hardware Error Exception When ISR Context Is Not Restored */
+/* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
/* TWI Slave Boot Mode Is Not Functional */
#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
-/* External FIFO Boot Mode Is Not Functional */
+/* FIFO Boot Mode Not Functional */
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
@@ -157,6 +170,8 @@
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
+/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
+#define ANOMALY_05000434 (1)
/* OTP Write Accesses Not Supported */
#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
@@ -170,32 +185,93 @@
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
/* USB DMA Mode 1 Short Packet Data Corruption */
-#define ANOMALY_05000450 (1
+#define ANOMALY_05000450 (1)
+/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
+#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
+/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
+#define ANOMALY_05000456 (1)
+/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
+#define ANOMALY_05000457 (1)
+/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
+#define ANOMALY_05000460 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* USB DMA RX Data Corruption */
+#define ANOMALY_05000463 (1)
+/* USB TX DMA Hang */
+#define ANOMALY_05000464 (1)
+/* USB Rx DMA hang */
+#define ANOMALY_05000465 (1)
+/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
+#define ANOMALY_05000466 (1)
+/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
+#define ANOMALY_05000467 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
+#define ANOMALY_05000474 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
+#define ANOMALY_05000483 (1)
+/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
+#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000099 (0)
+#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
+#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
+#define ANOMALY_05000179 (0)
+#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
+#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
+#define ANOMALY_05000202 (0)
+#define ANOMALY_05000215 (0)
+#define ANOMALY_05000219 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000233 (0)
+#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0)
+#define ANOMALY_05000248 (0)
+#define ANOMALY_05000250 (0)
+#define ANOMALY_05000254 (0)
+#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
+#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
+#define ANOMALY_05000283 (0)
+#define ANOMALY_05000287 (0)
+#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
+#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000400 (0)
+#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000475 (0)
#endif
diff --git a/arch/blackfin/include/asm/mach-bf548/def_local.h b/arch/blackfin/include/asm/mach-bf548/def_local.h
index 81eca83..f1e69a7 100644
--- a/arch/blackfin/include/asm/mach-bf548/def_local.h
+++ b/arch/blackfin/include/asm/mach-bf548/def_local.h
@@ -1,2 +1,6 @@
+#include "gpio.h"
#include "mem_map.h"
+#include "portmux.h"
#include "ports.h"
+
+#define CONFIG_BF54x 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf548/gpio.h b/arch/blackfin/include/asm/mach-bf548/gpio.h
new file mode 100644
index 0000000..28037e3
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/gpio.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2007-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define GPIO_PA0 0
+#define GPIO_PA1 1
+#define GPIO_PA2 2
+#define GPIO_PA3 3
+#define GPIO_PA4 4
+#define GPIO_PA5 5
+#define GPIO_PA6 6
+#define GPIO_PA7 7
+#define GPIO_PA8 8
+#define GPIO_PA9 9
+#define GPIO_PA10 10
+#define GPIO_PA11 11
+#define GPIO_PA12 12
+#define GPIO_PA13 13
+#define GPIO_PA14 14
+#define GPIO_PA15 15
+#define GPIO_PB0 16
+#define GPIO_PB1 17
+#define GPIO_PB2 18
+#define GPIO_PB3 19
+#define GPIO_PB4 20
+#define GPIO_PB5 21
+#define GPIO_PB6 22
+#define GPIO_PB7 23
+#define GPIO_PB8 24
+#define GPIO_PB9 25
+#define GPIO_PB10 26
+#define GPIO_PB11 27
+#define GPIO_PB12 28
+#define GPIO_PB13 29
+#define GPIO_PB14 30
+#define GPIO_PB15 31 /* N/A */
+#define GPIO_PC0 32
+#define GPIO_PC1 33
+#define GPIO_PC2 34
+#define GPIO_PC3 35
+#define GPIO_PC4 36
+#define GPIO_PC5 37
+#define GPIO_PC6 38
+#define GPIO_PC7 39
+#define GPIO_PC8 40
+#define GPIO_PC9 41
+#define GPIO_PC10 42
+#define GPIO_PC11 43
+#define GPIO_PC12 44
+#define GPIO_PC13 45
+#define GPIO_PC14 46 /* N/A */
+#define GPIO_PC15 47 /* N/A */
+#define GPIO_PD0 48
+#define GPIO_PD1 49
+#define GPIO_PD2 50
+#define GPIO_PD3 51
+#define GPIO_PD4 52
+#define GPIO_PD5 53
+#define GPIO_PD6 54
+#define GPIO_PD7 55
+#define GPIO_PD8 56
+#define GPIO_PD9 57
+#define GPIO_PD10 58
+#define GPIO_PD11 59
+#define GPIO_PD12 60
+#define GPIO_PD13 61
+#define GPIO_PD14 62
+#define GPIO_PD15 63
+#define GPIO_PE0 64
+#define GPIO_PE1 65
+#define GPIO_PE2 66
+#define GPIO_PE3 67
+#define GPIO_PE4 68
+#define GPIO_PE5 69
+#define GPIO_PE6 70
+#define GPIO_PE7 71
+#define GPIO_PE8 72
+#define GPIO_PE9 73
+#define GPIO_PE10 74
+#define GPIO_PE11 75
+#define GPIO_PE12 76
+#define GPIO_PE13 77
+#define GPIO_PE14 78
+#define GPIO_PE15 79
+#define GPIO_PF0 80
+#define GPIO_PF1 81
+#define GPIO_PF2 82
+#define GPIO_PF3 83
+#define GPIO_PF4 84
+#define GPIO_PF5 85
+#define GPIO_PF6 86
+#define GPIO_PF7 87
+#define GPIO_PF8 88
+#define GPIO_PF9 89
+#define GPIO_PF10 90
+#define GPIO_PF11 91
+#define GPIO_PF12 92
+#define GPIO_PF13 93
+#define GPIO_PF14 94
+#define GPIO_PF15 95
+#define GPIO_PG0 96
+#define GPIO_PG1 97
+#define GPIO_PG2 98
+#define GPIO_PG3 99
+#define GPIO_PG4 100
+#define GPIO_PG5 101
+#define GPIO_PG6 102
+#define GPIO_PG7 103
+#define GPIO_PG8 104
+#define GPIO_PG9 105
+#define GPIO_PG10 106
+#define GPIO_PG11 107
+#define GPIO_PG12 108
+#define GPIO_PG13 109
+#define GPIO_PG14 110
+#define GPIO_PG15 111
+#define GPIO_PH0 112
+#define GPIO_PH1 113
+#define GPIO_PH2 114
+#define GPIO_PH3 115
+#define GPIO_PH4 116
+#define GPIO_PH5 117
+#define GPIO_PH6 118
+#define GPIO_PH7 119
+#define GPIO_PH8 120
+#define GPIO_PH9 121
+#define GPIO_PH10 122
+#define GPIO_PH11 123
+#define GPIO_PH12 124
+#define GPIO_PH13 125
+#define GPIO_PH14 126 /* N/A */
+#define GPIO_PH15 127 /* N/A */
+#define GPIO_PI0 128
+#define GPIO_PI1 129
+#define GPIO_PI2 130
+#define GPIO_PI3 131
+#define GPIO_PI4 132
+#define GPIO_PI5 133
+#define GPIO_PI6 134
+#define GPIO_PI7 135
+#define GPIO_PI8 136
+#define GPIO_PI9 137
+#define GPIO_PI10 138
+#define GPIO_PI11 139
+#define GPIO_PI12 140
+#define GPIO_PI13 141
+#define GPIO_PI14 142
+#define GPIO_PI15 143
+#define GPIO_PJ0 144
+#define GPIO_PJ1 145
+#define GPIO_PJ2 146
+#define GPIO_PJ3 147
+#define GPIO_PJ4 148
+#define GPIO_PJ5 149
+#define GPIO_PJ6 150
+#define GPIO_PJ7 151
+#define GPIO_PJ8 152
+#define GPIO_PJ9 153
+#define GPIO_PJ10 154
+#define GPIO_PJ11 155
+#define GPIO_PJ12 156
+#define GPIO_PJ13 157
+#define GPIO_PJ14 158 /* N/A */
+#define GPIO_PJ15 159 /* N/A */
+
+#define MAX_BLACKFIN_GPIOS 160
+
+#ifndef __ASSEMBLY__
+
+struct gpio_port_t {
+ unsigned short port_fer;
+ unsigned short dummy1;
+ unsigned short data;
+ unsigned short dummy2;
+ unsigned short data_set;
+ unsigned short dummy3;
+ unsigned short data_clear;
+ unsigned short dummy4;
+ unsigned short dir_set;
+ unsigned short dummy5;
+ unsigned short dir_clear;
+ unsigned short dummy6;
+ unsigned short inen;
+ unsigned short dummy7;
+ unsigned int port_mux;
+};
+
+struct gpio_port_s {
+ unsigned short fer;
+ unsigned short data;
+ unsigned short dir;
+ unsigned short inen;
+ unsigned int mux;
+};
+
+#endif
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf548/portmux.h b/arch/blackfin/include/asm/mach-bf548/portmux.h
new file mode 100644
index 0000000..e222462
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/portmux.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
+
+#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
+#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
+#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
+#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
+#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
+#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
+#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
+#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
+#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
+#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
+#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
+#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
+#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
+#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
+#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
+#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
+#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
+#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
+#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
+#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
+
+#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
+#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
+#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
+#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
+#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
+#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
+#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
+#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
+#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
+#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
+#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
+#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
+#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
+#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
+#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
+#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
+#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
+#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
+#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
+
+#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
+#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
+#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
+#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
+#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
+#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
+#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
+#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
+#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
+#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
+#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
+#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
+#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
+#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
+#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
+#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
+
+#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
+#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
+#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
+#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
+#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
+#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
+#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
+#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
+#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
+#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
+#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
+#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
+#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
+#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
+#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
+#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
+
+#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
+#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
+#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
+#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
+#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
+#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
+#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
+#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
+#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
+#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
+#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
+#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
+#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
+#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
+#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
+#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
+#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
+#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
+#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
+#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
+#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
+#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
+#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
+#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
+#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
+#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
+#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
+#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
+#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
+#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
+#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
+#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
+#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
+#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
+#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
+#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
+#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
+#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
+#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
+#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
+#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
+#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
+#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
+#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
+#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
+#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
+
+#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
+#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
+#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
+#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
+#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
+#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
+#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
+#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
+#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
+#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
+#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
+#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
+#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
+#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
+#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
+#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
+#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
+#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
+#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
+#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
+#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
+#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
+#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
+#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
+#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
+#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
+
+#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
+#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
+#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
+#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
+#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
+#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
+#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
+#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
+#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
+#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
+#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
+#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
+#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
+#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
+
+#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
+# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
+# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
+# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
+# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
+# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+#else
+# define P_ATAPI_D0A (P_DONTCARE)
+# define P_ATAPI_D1A (P_DONTCARE)
+# define P_ATAPI_D2A (P_DONTCARE)
+# define P_ATAPI_D3A (P_DONTCARE)
+# define P_ATAPI_D4A (P_DONTCARE)
+# define P_ATAPI_D5A (P_DONTCARE)
+# define P_ATAPI_D6A (P_DONTCARE)
+# define P_ATAPI_D7A (P_DONTCARE)
+# define P_ATAPI_D8A (P_DONTCARE)
+# define P_ATAPI_D9A (P_DONTCARE)
+# define P_ATAPI_D10A (P_DONTCARE)
+# define P_ATAPI_D11A (P_DONTCARE)
+# define P_ATAPI_D12A (P_DONTCARE)
+# define P_ATAPI_D13A (P_DONTCARE)
+# define P_ATAPI_D14A (P_DONTCARE)
+# define P_ATAPI_D15A (P_DONTCARE)
+#endif
+
+#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
+#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
+#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
+#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
+#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
+#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
+#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
+#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
+# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
+# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
+# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
+#else
+# define P_ATAPI_A0A (P_DONTCARE)
+# define P_ATAPI_A1A (P_DONTCARE)
+# define P_ATAPI_A2A (P_DONTCARE)
+#endif
+#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
+#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
+#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
+#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
+
+#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
+#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
+#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
+#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
+#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
+#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
+#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
+#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
+#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
+#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
+#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
+#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
+#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
+#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
+#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
+#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
+#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
+#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
+#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
+#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
+#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
+#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
+#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
+#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
+
+#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
+#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
+#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
+#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
+#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
+#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
+#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
+#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
+#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
+#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
+#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
+#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
+#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
+#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
+#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
+#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
+#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
+
+#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
+#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
+#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
+#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
+#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
+#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
+#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
+#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
+#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
+#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
+#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
+#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
+#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
+#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
+
+
+#define P_NAND_D0 (P_DONTCARE)
+#define P_NAND_D1 (P_DONTCARE)
+#define P_NAND_D2 (P_DONTCARE)
+#define P_NAND_D3 (P_DONTCARE)
+#define P_NAND_D4 (P_DONTCARE)
+#define P_NAND_D5 (P_DONTCARE)
+#define P_NAND_D6 (P_DONTCARE)
+#define P_NAND_D7 (P_DONTCARE)
+#define P_NAND_WE (P_DONTCARE)
+#define P_NAND_RE (P_DONTCARE)
+#define P_NAND_CLE (P_DONTCARE)
+#define P_NAND_ALE (P_DONTCARE)
+
+#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h
index e4aa20c..4c108c9 100644
--- a/arch/blackfin/include/asm/mach-bf561/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf561/anomaly.h
@@ -1,9 +1,13 @@
/*
- * File: include/asm-blackfin/mach-bf561/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
*
- * Copyright (C) 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
+ * Copyright 2004-2010 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
@@ -18,19 +22,19 @@
# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
#endif
-/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
+/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* Testset instructions restricted to 32-bit aligned memory locations */
+/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
#define ANOMALY_05000120 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
-/* Erroneous exception when enabling cache */
+/* Erroneous Exception when Enabling Cache */
#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* Signbits instruction not functional under certain conditions */
+/* SIGNBITS Instruction Not Functional under Certain Conditions */
#define ANOMALY_05000127 (1)
/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
@@ -40,7 +44,7 @@
#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
/* Allowing the SPORT RX FIFO to fill will cause an overflow */
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
+/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
@@ -52,7 +56,7 @@
#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* IMDMA S1/D1 channel may stall */
+/* IMDMA S1/D1 Channel May Stall */
#define ANOMALY_05000149 (1)
/* DMA engine may lose data due to incorrect handshaking */
#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
@@ -66,7 +70,7 @@
#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
@@ -76,17 +80,17 @@
#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
/* DMEM_CONTROL<12> is not set on Reset */
#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT transmit data is not gated by external frame sync in certain conditions */
+/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
+/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1)
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
#define ANOMALY_05000167 (1)
-/* SDRAM auto-refresh and subsequent Power Ups */
+/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
-/* DATA CPLB page miss can result in lost write-through cache data writes */
+/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
-/* Boot-ROM code modifies SICA_IWRx wakeup registers */
+/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
/* DSPID register values incorrect */
#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
@@ -96,29 +100,29 @@
#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
/* Overlapping Sequencer and Memory Stalls */
#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
-/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
+/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000180 (1)
-/* Disabling the PPI resets the PPI configuration registers */
+/* Disabling the PPI Resets the PPI Configuration Registers */
#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
-/* IMDMA does not operate to full speed for 600MHz and higher devices */
+/* Internal Memory DMA Does Not Operate at Full Speed */
#define ANOMALY_05000182 (1)
-/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
+/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
-/* PPI TX Mode with 2 External Frame Syncs */
+/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
-/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
+/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
/* IMDMA Corrupted Data after a Halt */
#define ANOMALY_05000187 (1)
/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
-/* False Protection Exceptions */
+/* False Protection Exceptions when Speculative Fetch Is Cancelled */
#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
-/* PPI not functional at core voltage < 1Volt */
+/* PPI Not Functional at Core Voltage < 1Volt */
#define ANOMALY_05000190 (1)
/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
@@ -126,7 +130,7 @@
#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
/* Restarting SPORT in Specific Modes May Cause Data Corruption */
#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
-/* Failing MMR Accesses When Stalled by Preceding Memory Read */
+/* Failing MMR Accesses when Preceding Memory Read Stalls */
#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
/* Current DMA Address Shows Wrong Value During Carry Fix */
#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
@@ -134,9 +138,9 @@
#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
/* Possible Infinite Stall with Specific Dual-DAG Situation */
#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
+/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
-/* Specific sequence that can cause DMA error or DMA stopping */
+/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
/* Recovery from "Brown-Out" Condition */
#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
@@ -148,8 +152,8 @@
#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
/* NMI Event at Boot Time Results in Unpredictable State */
#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
-/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
+/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
+#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
/* Incorrect Pulse-Width of UART Start Bit */
#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
/* Scratchpad Memory Bank Reads May Return Incorrect Data */
@@ -158,7 +162,7 @@
#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
/* UART STB Bit Incorrectly Affects Receiver Setting */
#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* SPORT data transmit lines are incorrectly driven in multichannel mode */
+/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
@@ -166,7 +170,7 @@
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
-/* TESTSET operation forces stall on the other core */
+/* TESTSET Operation Forces Stall on the Other Core */
#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
@@ -192,9 +196,9 @@
#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* IMDMA destination IRQ status must be read prior to using IMDMA */
+/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
-/* IMDMA may corrupt data under certain conditions */
+/* IMDMA May Corrupt Data under Certain Conditions */
#define ANOMALY_05000267 (1)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
#define ANOMALY_05000269 (1)
@@ -202,7 +206,7 @@
#define ANOMALY_05000270 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
-/* Data cache write back to external synchronous memory may be lost */
+/* Data Cache Write Back to External Synchronous Memory May Be Lost */
#define ANOMALY_05000274 (1)
/* PPI Timing and Sampling Information Updates */
#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
@@ -212,17 +216,21 @@
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error Exception When ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
-/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
+/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* Temporarily walk around for bug 5423 till this issue is confirmed by
+ * official anomaly document. It looks 05000281 still exists on bf561
+ * v0.5.
+ */
+#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
+/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
#define ANOMALY_05000283 (1)
-/* A read will receive incorrect data under certain conditions */
+/* Reads Will Receive Incorrect Data under Certain Conditions */
#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
+/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
#define ANOMALY_05000302 (1)
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
@@ -230,25 +238,25 @@
#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
+/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (1)
-/* PF2 Output Remains Asserted After SPI Master Boot */
+/* PF2 Output Remains Asserted after SPI Master Boot */
#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
-/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
+/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
#define ANOMALY_05000323 (1)
-/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
+/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
-/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
+/* 24-Bit SPI Boot Mode Is Not Functional */
#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
-/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
+/* Slave SPI Boot Mode Is Not Functional */
#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
-/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
+/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
-/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
+/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
@@ -262,6 +270,8 @@
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
@@ -276,19 +286,43 @@
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_05000461 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* Possible Lockup Condition whem Modifying PLL from External Memory */
+#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000119 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000183 (0)
+#define ANOMALY_05000233 (0)
+#define ANOMALY_05000234 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000353 (1)
+#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
+#define ANOMALY_05000389 (0)
+#define ANOMALY_05000400 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
+#define ANOMALY_05000456 (0)
+#define ANOMALY_05000450 (0)
+#define ANOMALY_05000465 (0)
+#define ANOMALY_05000467 (0)
+#define ANOMALY_05000474 (0)
+#define ANOMALY_05000485 (0)
#endif
diff --git a/arch/blackfin/include/asm/mach-bf561/def_local.h b/arch/blackfin/include/asm/mach-bf561/def_local.h
index 597dcec..08e37e5 100644
--- a/arch/blackfin/include/asm/mach-bf561/def_local.h
+++ b/arch/blackfin/include/asm/mach-bf561/def_local.h
@@ -9,4 +9,8 @@
#define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val)
#define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val)
+#include "gpio.h"
+#include "portmux.h"
#include "ports.h"
+
+#define BF561_FAMILY 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf561/gpio.h b/arch/blackfin/include/asm/mach-bf561/gpio.h
new file mode 100644
index 0000000..4f8aa5d
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf561/gpio.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 48
+
+#define GPIO_PF0 0
+#define GPIO_PF1 1
+#define GPIO_PF2 2
+#define GPIO_PF3 3
+#define GPIO_PF4 4
+#define GPIO_PF5 5
+#define GPIO_PF6 6
+#define GPIO_PF7 7
+#define GPIO_PF8 8
+#define GPIO_PF9 9
+#define GPIO_PF10 10
+#define GPIO_PF11 11
+#define GPIO_PF12 12
+#define GPIO_PF13 13
+#define GPIO_PF14 14
+#define GPIO_PF15 15
+#define GPIO_PF16 16
+#define GPIO_PF17 17
+#define GPIO_PF18 18
+#define GPIO_PF19 19
+#define GPIO_PF20 20
+#define GPIO_PF21 21
+#define GPIO_PF22 22
+#define GPIO_PF23 23
+#define GPIO_PF24 24
+#define GPIO_PF25 25
+#define GPIO_PF26 26
+#define GPIO_PF27 27
+#define GPIO_PF28 28
+#define GPIO_PF29 29
+#define GPIO_PF30 30
+#define GPIO_PF31 31
+#define GPIO_PF32 32
+#define GPIO_PF33 33
+#define GPIO_PF34 34
+#define GPIO_PF35 35
+#define GPIO_PF36 36
+#define GPIO_PF37 37
+#define GPIO_PF38 38
+#define GPIO_PF39 39
+#define GPIO_PF40 40
+#define GPIO_PF41 41
+#define GPIO_PF42 42
+#define GPIO_PF43 43
+#define GPIO_PF44 44
+#define GPIO_PF45 45
+#define GPIO_PF46 46
+#define GPIO_PF47 47
+
+#define PORT_FIO0 GPIO_0
+#define PORT_FIO1 GPIO_16
+#define PORT_FIO2 GPIO_32
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf561/portmux.h b/arch/blackfin/include/asm/mach-bf561/portmux.h
new file mode 100644
index 0000000..2339ffd
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf561/portmux.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
+
+#define P_PPI0_CLK (P_DONTCARE)
+#define P_PPI0_FS1 (P_DONTCARE)
+#define P_PPI0_FS2 (P_DONTCARE)
+#define P_PPI0_FS3 (P_DONTCARE)
+#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
+#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
+#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
+#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
+#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
+#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
+#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
+#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
+#define P_PPI0_D0 (P_DONTCARE)
+#define P_PPI0_D1 (P_DONTCARE)
+#define P_PPI0_D2 (P_DONTCARE)
+#define P_PPI0_D3 (P_DONTCARE)
+#define P_PPI0_D4 (P_DONTCARE)
+#define P_PPI0_D5 (P_DONTCARE)
+#define P_PPI0_D6 (P_DONTCARE)
+#define P_PPI0_D7 (P_DONTCARE)
+#define P_PPI1_CLK (P_DONTCARE)
+#define P_PPI1_FS1 (P_DONTCARE)
+#define P_PPI1_FS2 (P_DONTCARE)
+#define P_PPI1_FS3 (P_DONTCARE)
+#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
+#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
+#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
+#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
+#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
+#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
+#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
+#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
+#define P_PPI1_D0 (P_DONTCARE)
+#define P_PPI1_D1 (P_DONTCARE)
+#define P_PPI1_D2 (P_DONTCARE)
+#define P_PPI1_D3 (P_DONTCARE)
+#define P_PPI1_D4 (P_DONTCARE)
+#define P_PPI1_D5 (P_DONTCARE)
+#define P_PPI1_D6 (P_DONTCARE)
+#define P_PPI1_D7 (P_DONTCARE)
+#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
+#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
+#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
+#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
+#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
+#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
+#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
+#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
+#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
+#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
+#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
+#define P_SPORT1_DRPRI (P_DONTCARE)
+#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
+#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
+#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
+#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
+#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
+#define P_SPORT0_DRPRI (P_DONTCARE)
+#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
+#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
+#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
+#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
+#define P_TMR11 (P_DONTCARE)
+#define P_TMR10 (P_DONTCARE)
+#define P_TMR9 (P_DONTCARE)
+#define P_TMR8 (P_DONTCARE)
+#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
+#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
+#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
+#define P_SPI0_MOSI (P_DONTCARE)
+#define P_SPI0_MISO (P_DONTCARE)
+#define P_SPI0_SCK (P_DONTCARE)
+#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
+#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
+
+#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
new file mode 100644
index 0000000..b17207f
--- /dev/null
+++ b/arch/blackfin/include/asm/portmux.h
@@ -0,0 +1,1194 @@
+/*
+ * Common header file for Blackfin family of processors
+ *
+ * Copyright 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _PORTMUX_H_
+#define _PORTMUX_H_
+
+#define P_IDENT(x) ((x) & 0x1FF)
+#define P_FUNCT(x) (((x) & 0x3) << 9)
+#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3)
+#define P_DEFINED 0x8000
+#define P_UNDEF 0x4000
+#define P_MAYSHARE 0x2000
+#define P_DONTCARE 0x1000
+
+#ifndef CONFIG_BFIN_GPIO_TRACK
+#define peripheral_request(per, label) peripheral_request(per)
+#define peripheral_request_list(per, label) peripheral_request_list(per)
+#endif
+
+int peripheral_request(unsigned short per, const char *label);
+void peripheral_free(unsigned short per);
+int peripheral_request_list(const unsigned short per[], const char *label);
+void peripheral_free_list(const unsigned short per[]);
+
+#include <asm/blackfin.h>
+
+#ifndef P_SPORT2_TFS
+#define P_SPORT2_TFS P_UNDEF
+#endif
+
+#ifndef P_SPORT2_DTSEC
+#define P_SPORT2_DTSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT2_DTPRI
+#define P_SPORT2_DTPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT2_TSCLK
+#define P_SPORT2_TSCLK P_UNDEF
+#endif
+
+#ifndef P_SPORT2_RFS
+#define P_SPORT2_RFS P_UNDEF
+#endif
+
+#ifndef P_SPORT2_DRSEC
+#define P_SPORT2_DRSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT2_DRPRI
+#define P_SPORT2_DRPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT2_RSCLK
+#define P_SPORT2_RSCLK P_UNDEF
+#endif
+
+#ifndef P_SPORT3_TFS
+#define P_SPORT3_TFS P_UNDEF
+#endif
+
+#ifndef P_SPORT3_DTSEC
+#define P_SPORT3_DTSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT3_DTPRI
+#define P_SPORT3_DTPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT3_TSCLK
+#define P_SPORT3_TSCLK P_UNDEF
+#endif
+
+#ifndef P_SPORT3_RFS
+#define P_SPORT3_RFS P_UNDEF
+#endif
+
+#ifndef P_SPORT3_DRSEC
+#define P_SPORT3_DRSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT3_DRPRI
+#define P_SPORT3_DRPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT3_RSCLK
+#define P_SPORT3_RSCLK P_UNDEF
+#endif
+
+#ifndef P_TMR4
+#define P_TMR4 P_UNDEF
+#endif
+
+#ifndef P_TMR5
+#define P_TMR5 P_UNDEF
+#endif
+
+#ifndef P_TMR6
+#define P_TMR6 P_UNDEF
+#endif
+
+#ifndef P_TMR7
+#define P_TMR7 P_UNDEF
+#endif
+
+#ifndef P_TWI1_SCL
+#define P_TWI1_SCL P_UNDEF
+#endif
+
+#ifndef P_TWI1_SDA
+#define P_TWI1_SDA P_UNDEF
+#endif
+
+#ifndef P_UART3_RTS
+#define P_UART3_RTS P_UNDEF
+#endif
+
+#ifndef P_UART3_CTS
+#define P_UART3_CTS P_UNDEF
+#endif
+
+#ifndef P_UART2_TX
+#define P_UART2_TX P_UNDEF
+#endif
+
+#ifndef P_UART2_RX
+#define P_UART2_RX P_UNDEF
+#endif
+
+#ifndef P_UART3_TX
+#define P_UART3_TX P_UNDEF
+#endif
+
+#ifndef P_UART3_RX
+#define P_UART3_RX P_UNDEF
+#endif
+
+#ifndef P_SPI2_SS
+#define P_SPI2_SS P_UNDEF
+#endif
+
+#ifndef P_SPI2_SSEL1
+#define P_SPI2_SSEL1 P_UNDEF
+#endif
+
+#ifndef P_SPI2_SSEL2
+#define P_SPI2_SSEL2 P_UNDEF
+#endif
+
+#ifndef P_SPI2_SSEL3
+#define P_SPI2_SSEL3 P_UNDEF
+#endif
+
+#ifndef P_SPI2_SSEL4
+#define P_SPI2_SSEL4 P_UNDEF
+#endif
+
+#ifndef P_SPI2_SSEL5
+#define P_SPI2_SSEL5 P_UNDEF
+#endif
+
+#ifndef P_SPI2_SSEL6
+#define P_SPI2_SSEL6 P_UNDEF
+#endif
+
+#ifndef P_SPI2_SSEL7
+#define P_SPI2_SSEL7 P_UNDEF
+#endif
+
+#ifndef P_SPI2_SCK
+#define P_SPI2_SCK P_UNDEF
+#endif
+
+#ifndef P_SPI2_MOSI
+#define P_SPI2_MOSI P_UNDEF
+#endif
+
+#ifndef P_SPI2_MISO
+#define P_SPI2_MISO P_UNDEF
+#endif
+
+#ifndef P_TMR0
+#define P_TMR0 P_UNDEF
+#endif
+
+#ifndef P_TMR1
+#define P_TMR1 P_UNDEF
+#endif
+
+#ifndef P_TMR2
+#define P_TMR2 P_UNDEF
+#endif
+
+#ifndef P_TMR3
+#define P_TMR3 P_UNDEF
+#endif
+
+#ifndef P_SPORT0_TFS
+#define P_SPORT0_TFS P_UNDEF
+#endif
+
+#ifndef P_SPORT0_DTSEC
+#define P_SPORT0_DTSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT0_DTPRI
+#define P_SPORT0_DTPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT0_TSCLK
+#define P_SPORT0_TSCLK P_UNDEF
+#endif
+
+#ifndef P_SPORT0_RFS
+#define P_SPORT0_RFS P_UNDEF
+#endif
+
+#ifndef P_SPORT0_DRSEC
+#define P_SPORT0_DRSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT0_DRPRI
+#define P_SPORT0_DRPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT0_RSCLK
+#define P_SPORT0_RSCLK P_UNDEF
+#endif
+
+#ifndef P_SD_D0
+#define P_SD_D0 P_UNDEF
+#endif
+
+#ifndef P_SD_D1
+#define P_SD_D1 P_UNDEF
+#endif
+
+#ifndef P_SD_D2
+#define P_SD_D2 P_UNDEF
+#endif
+
+#ifndef P_SD_D3
+#define P_SD_D3 P_UNDEF
+#endif
+
+#ifndef P_SD_CLK
+#define P_SD_CLK P_UNDEF
+#endif
+
+#ifndef P_SD_CMD
+#define P_SD_CMD P_UNDEF
+#endif
+
+#ifndef P_MMCLK
+#define P_MMCLK P_UNDEF
+#endif
+
+#ifndef P_MBCLK
+#define P_MBCLK P_UNDEF
+#endif
+
+#ifndef P_PPI1_D0
+#define P_PPI1_D0 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D1
+#define P_PPI1_D1 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D2
+#define P_PPI1_D2 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D3
+#define P_PPI1_D3 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D4
+#define P_PPI1_D4 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D5
+#define P_PPI1_D5 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D6
+#define P_PPI1_D6 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D7
+#define P_PPI1_D7 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D8
+#define P_PPI1_D8 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D9
+#define P_PPI1_D9 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D10
+#define P_PPI1_D10 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D11
+#define P_PPI1_D11 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D12
+#define P_PPI1_D12 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D13
+#define P_PPI1_D13 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D14
+#define P_PPI1_D14 P_UNDEF
+#endif
+
+#ifndef P_PPI1_D15
+#define P_PPI1_D15 P_UNDEF
+#endif
+
+#ifndef P_HOST_D8
+#define P_HOST_D8 P_UNDEF
+#endif
+
+#ifndef P_HOST_D9
+#define P_HOST_D9 P_UNDEF
+#endif
+
+#ifndef P_HOST_D10
+#define P_HOST_D10 P_UNDEF
+#endif
+
+#ifndef P_HOST_D11
+#define P_HOST_D11 P_UNDEF
+#endif
+
+#ifndef P_HOST_D12
+#define P_HOST_D12 P_UNDEF
+#endif
+
+#ifndef P_HOST_D13
+#define P_HOST_D13 P_UNDEF
+#endif
+
+#ifndef P_HOST_D14
+#define P_HOST_D14 P_UNDEF
+#endif
+
+#ifndef P_HOST_D15
+#define P_HOST_D15 P_UNDEF
+#endif
+
+#ifndef P_HOST_D0
+#define P_HOST_D0 P_UNDEF
+#endif
+
+#ifndef P_HOST_D1
+#define P_HOST_D1 P_UNDEF
+#endif
+
+#ifndef P_HOST_D2
+#define P_HOST_D2 P_UNDEF
+#endif
+
+#ifndef P_HOST_D3
+#define P_HOST_D3 P_UNDEF
+#endif
+
+#ifndef P_HOST_D4
+#define P_HOST_D4 P_UNDEF
+#endif
+
+#ifndef P_HOST_D5
+#define P_HOST_D5 P_UNDEF
+#endif
+
+#ifndef P_HOST_D6
+#define P_HOST_D6 P_UNDEF
+#endif
+
+#ifndef P_HOST_D7
+#define P_HOST_D7 P_UNDEF
+#endif
+
+#ifndef P_SPORT1_TFS
+#define P_SPORT1_TFS P_UNDEF
+#endif
+
+#ifndef P_SPORT1_DTSEC
+#define P_SPORT1_DTSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT1_DTPRI
+#define P_SPORT1_DTPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT1_TSCLK
+#define P_SPORT1_TSCLK P_UNDEF
+#endif
+
+#ifndef P_SPORT1_RFS
+#define P_SPORT1_RFS P_UNDEF
+#endif
+
+#ifndef P_SPORT1_DRSEC
+#define P_SPORT1_DRSEC P_UNDEF
+#endif
+
+#ifndef P_SPORT1_DRPRI
+#define P_SPORT1_DRPRI P_UNDEF
+#endif
+
+#ifndef P_SPORT1_RSCLK
+#define P_SPORT1_RSCLK P_UNDEF
+#endif
+
+#ifndef P_PPI2_D0
+#define P_PPI2_D0 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D1
+#define P_PPI2_D1 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D2
+#define P_PPI2_D2 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D3
+#define P_PPI2_D3 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D4
+#define P_PPI2_D4 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D5
+#define P_PPI2_D5 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D6
+#define P_PPI2_D6 P_UNDEF
+#endif
+
+#ifndef P_PPI2_D7
+#define P_PPI2_D7 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D18
+#define P_PPI0_D18 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D19
+#define P_PPI0_D19 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D20
+#define P_PPI0_D20 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D21
+#define P_PPI0_D21 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D22
+#define P_PPI0_D22 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D23
+#define P_PPI0_D23 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW0
+#define P_KEY_ROW0 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW1
+#define P_KEY_ROW1 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW2
+#define P_KEY_ROW2 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW3
+#define P_KEY_ROW3 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL0
+#define P_KEY_COL0 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL1
+#define P_KEY_COL1 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL2
+#define P_KEY_COL2 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL3
+#define P_KEY_COL3 P_UNDEF
+#endif
+
+#ifndef P_SPI0_SCK
+#define P_SPI0_SCK P_UNDEF
+#endif
+
+#ifndef P_SPI0_MISO
+#define P_SPI0_MISO P_UNDEF
+#endif
+
+#ifndef P_SPI0_MOSI
+#define P_SPI0_MOSI P_UNDEF
+#endif
+
+#ifndef P_SPI0_SS
+#define P_SPI0_SS P_UNDEF
+#endif
+
+#ifndef P_SPI0_SSEL1
+#define P_SPI0_SSEL1 P_UNDEF
+#endif
+
+#ifndef P_SPI0_SSEL2
+#define P_SPI0_SSEL2 P_UNDEF
+#endif
+
+#ifndef P_SPI0_SSEL3
+#define P_SPI0_SSEL3 P_UNDEF
+#endif
+
+#ifndef P_SPI0_SSEL4
+#define P_SPI0_SSEL4 P_UNDEF
+#endif
+
+#ifndef P_SPI0_SSEL5
+#define P_SPI0_SSEL5 P_UNDEF
+#endif
+
+#ifndef P_SPI0_SSEL6
+#define P_SPI0_SSEL6 P_UNDEF
+#endif
+
+#ifndef P_SPI0_SSEL7
+#define P_SPI0_SSEL7 P_UNDEF
+#endif
+
+#ifndef P_UART0_TX
+#define P_UART0_TX P_UNDEF
+#endif
+
+#ifndef P_UART0_RX
+#define P_UART0_RX P_UNDEF
+#endif
+
+#ifndef P_UART1_RTS
+#define P_UART1_RTS P_UNDEF
+#endif
+
+#ifndef P_UART1_CTS
+#define P_UART1_CTS P_UNDEF
+#endif
+
+#ifndef P_PPI1_CLK
+#define P_PPI1_CLK P_UNDEF
+#endif
+
+#ifndef P_PPI1_FS1
+#define P_PPI1_FS1 P_UNDEF
+#endif
+
+#ifndef P_PPI1_FS2
+#define P_PPI1_FS2 P_UNDEF
+#endif
+
+#ifndef P_TWI0_SCL
+#define P_TWI0_SCL P_UNDEF
+#endif
+
+#ifndef P_TWI0_SDA
+#define P_TWI0_SDA P_UNDEF
+#endif
+
+#ifndef P_KEY_COL7
+#define P_KEY_COL7 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW6
+#define P_KEY_ROW6 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL6
+#define P_KEY_COL6 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW5
+#define P_KEY_ROW5 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL5
+#define P_KEY_COL5 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW4
+#define P_KEY_ROW4 P_UNDEF
+#endif
+
+#ifndef P_KEY_COL4
+#define P_KEY_COL4 P_UNDEF
+#endif
+
+#ifndef P_KEY_ROW7
+#define P_KEY_ROW7 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D0
+#define P_PPI0_D0 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D1
+#define P_PPI0_D1 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D2
+#define P_PPI0_D2 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D3
+#define P_PPI0_D3 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D4
+#define P_PPI0_D4 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D5
+#define P_PPI0_D5 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D6
+#define P_PPI0_D6 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D7
+#define P_PPI0_D7 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D8
+#define P_PPI0_D8 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D9
+#define P_PPI0_D9 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D10
+#define P_PPI0_D10 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D11
+#define P_PPI0_D11 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D12
+#define P_PPI0_D12 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D13
+#define P_PPI0_D13 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D14
+#define P_PPI0_D14 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D15
+#define P_PPI0_D15 P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D0A
+#define P_ATAPI_D0A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D1A
+#define P_ATAPI_D1A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D2A
+#define P_ATAPI_D2A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D3A
+#define P_ATAPI_D3A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D4A
+#define P_ATAPI_D4A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D5A
+#define P_ATAPI_D5A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D6A
+#define P_ATAPI_D6A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D7A
+#define P_ATAPI_D7A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D8A
+#define P_ATAPI_D8A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D9A
+#define P_ATAPI_D9A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D10A
+#define P_ATAPI_D10A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D11A
+#define P_ATAPI_D11A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D12A
+#define P_ATAPI_D12A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D13A
+#define P_ATAPI_D13A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D14A
+#define P_ATAPI_D14A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_D15A
+#define P_ATAPI_D15A P_UNDEF
+#endif
+
+#ifndef P_PPI0_CLK
+#define P_PPI0_CLK P_UNDEF
+#endif
+
+#ifndef P_PPI0_FS1
+#define P_PPI0_FS1 P_UNDEF
+#endif
+
+#ifndef P_PPI0_FS2
+#define P_PPI0_FS2 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D16
+#define P_PPI0_D16 P_UNDEF
+#endif
+
+#ifndef P_PPI0_D17
+#define P_PPI0_D17 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SSEL1
+#define P_SPI1_SSEL1 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SSEL2
+#define P_SPI1_SSEL2 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SSEL3
+#define P_SPI1_SSEL3 P_UNDEF
+#endif
+
+
+#ifndef P_SPI1_SSEL4
+#define P_SPI1_SSEL4 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SSEL5
+#define P_SPI1_SSEL5 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SSEL6
+#define P_SPI1_SSEL6 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SSEL7
+#define P_SPI1_SSEL7 P_UNDEF
+#endif
+
+#ifndef P_SPI1_SCK
+#define P_SPI1_SCK P_UNDEF
+#endif
+
+#ifndef P_SPI1_MISO
+#define P_SPI1_MISO P_UNDEF
+#endif
+
+#ifndef P_SPI1_MOSI
+#define P_SPI1_MOSI P_UNDEF
+#endif
+
+#ifndef P_SPI1_SS
+#define P_SPI1_SS P_UNDEF
+#endif
+
+#ifndef P_CAN0_TX
+#define P_CAN0_TX P_UNDEF
+#endif
+
+#ifndef P_CAN0_RX
+#define P_CAN0_RX P_UNDEF
+#endif
+
+#ifndef P_CAN1_TX
+#define P_CAN1_TX P_UNDEF
+#endif
+
+#ifndef P_CAN1_RX
+#define P_CAN1_RX P_UNDEF
+#endif
+
+#ifndef P_ATAPI_A0A
+#define P_ATAPI_A0A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_A1A
+#define P_ATAPI_A1A P_UNDEF
+#endif
+
+#ifndef P_ATAPI_A2A
+#define P_ATAPI_A2A P_UNDEF
+#endif
+
+#ifndef P_HOST_CE
+#define P_HOST_CE P_UNDEF
+#endif
+
+#ifndef P_HOST_RD
+#define P_HOST_RD P_UNDEF
+#endif
+
+#ifndef P_HOST_WR
+#define P_HOST_WR P_UNDEF
+#endif
+
+#ifndef P_MTXONB
+#define P_MTXONB P_UNDEF
+#endif
+
+#ifndef P_PPI2_FS2
+#define P_PPI2_FS2 P_UNDEF
+#endif
+
+#ifndef P_PPI2_FS1
+#define P_PPI2_FS1 P_UNDEF
+#endif
+
+#ifndef P_PPI2_CLK
+#define P_PPI2_CLK P_UNDEF
+#endif
+
+#ifndef P_CNT_CZM
+#define P_CNT_CZM P_UNDEF
+#endif
+
+#ifndef P_UART1_TX
+#define P_UART1_TX P_UNDEF
+#endif
+
+#ifndef P_UART1_RX
+#define P_UART1_RX P_UNDEF
+#endif
+
+#ifndef P_ATAPI_RESET
+#define P_ATAPI_RESET P_UNDEF
+#endif
+
+#ifndef P_HOST_ADDR
+#define P_HOST_ADDR P_UNDEF
+#endif
+
+#ifndef P_HOST_ACK
+#define P_HOST_ACK P_UNDEF
+#endif
+
+#ifndef P_MTX
+#define P_MTX P_UNDEF
+#endif
+
+#ifndef P_MRX
+#define P_MRX P_UNDEF
+#endif
+
+#ifndef P_MRXONB
+#define P_MRXONB P_UNDEF
+#endif
+
+#ifndef P_A4
+#define P_A4 P_UNDEF
+#endif
+
+#ifndef P_A5
+#define P_A5 P_UNDEF
+#endif
+
+#ifndef P_A6
+#define P_A6 P_UNDEF
+#endif
+
+#ifndef P_A7
+#define P_A7 P_UNDEF
+#endif
+
+#ifndef P_A8
+#define P_A8 P_UNDEF
+#endif
+
+#ifndef P_A9
+#define P_A9 P_UNDEF
+#endif
+
+#ifndef P_PPI1_FS3
+#define P_PPI1_FS3 P_UNDEF
+#endif
+
+#ifndef P_PPI2_FS3
+#define P_PPI2_FS3 P_UNDEF
+#endif
+
+#ifndef P_TMR8
+#define P_TMR8 P_UNDEF
+#endif
+
+#ifndef P_TMR9
+#define P_TMR9 P_UNDEF
+#endif
+
+#ifndef P_TMR10
+#define P_TMR10 P_UNDEF
+#endif
+#ifndef P_TMR11
+#define P_TMR11 P_UNDEF
+#endif
+
+#ifndef P_DMAR0
+#define P_DMAR0 P_UNDEF
+#endif
+
+#ifndef P_DMAR1
+#define P_DMAR1 P_UNDEF
+#endif
+
+#ifndef P_PPI0_FS3
+#define P_PPI0_FS3 P_UNDEF
+#endif
+
+#ifndef P_CNT_CDG
+#define P_CNT_CDG P_UNDEF
+#endif
+
+#ifndef P_CNT_CUD
+#define P_CNT_CUD P_UNDEF
+#endif
+
+#ifndef P_A10
+#define P_A10 P_UNDEF
+#endif
+
+#ifndef P_A11
+#define P_A11 P_UNDEF
+#endif
+
+#ifndef P_A12
+#define P_A12 P_UNDEF
+#endif
+
+#ifndef P_A13
+#define P_A13 P_UNDEF
+#endif
+
+#ifndef P_A14
+#define P_A14 P_UNDEF
+#endif
+
+#ifndef P_A15
+#define P_A15 P_UNDEF
+#endif
+
+#ifndef P_A16
+#define P_A16 P_UNDEF
+#endif
+
+#ifndef P_A17
+#define P_A17 P_UNDEF
+#endif
+
+#ifndef P_A18
+#define P_A18 P_UNDEF
+#endif
+
+#ifndef P_A19
+#define P_A19 P_UNDEF
+#endif
+
+#ifndef P_A20
+#define P_A20 P_UNDEF
+#endif
+
+#ifndef P_A21
+#define P_A21 P_UNDEF
+#endif
+
+#ifndef P_A22
+#define P_A22 P_UNDEF
+#endif
+
+#ifndef P_A23
+#define P_A23 P_UNDEF
+#endif
+
+#ifndef P_A24
+#define P_A24 P_UNDEF
+#endif
+
+#ifndef P_A25
+#define P_A25 P_UNDEF
+#endif
+
+#ifndef P_NOR_CLK
+#define P_NOR_CLK P_UNDEF
+#endif
+
+#ifndef P_TMRCLK
+#define P_TMRCLK P_UNDEF
+#endif
+
+#ifndef P_AMC_ARDY_NOR_WAIT
+#define P_AMC_ARDY_NOR_WAIT P_UNDEF
+#endif
+
+#ifndef P_NAND_CE
+#define P_NAND_CE P_UNDEF
+#endif
+
+#ifndef P_NAND_RB
+#define P_NAND_RB P_UNDEF
+#endif
+
+#ifndef P_ATAPI_DIOR
+#define P_ATAPI_DIOR P_UNDEF
+#endif
+
+#ifndef P_ATAPI_DIOW
+#define P_ATAPI_DIOW P_UNDEF
+#endif
+
+#ifndef P_ATAPI_CS0
+#define P_ATAPI_CS0 P_UNDEF
+#endif
+
+#ifndef P_ATAPI_CS1
+#define P_ATAPI_CS1 P_UNDEF
+#endif
+
+#ifndef P_ATAPI_DMACK
+#define P_ATAPI_DMACK P_UNDEF
+#endif
+
+#ifndef P_ATAPI_DMARQ
+#define P_ATAPI_DMARQ P_UNDEF
+#endif
+
+#ifndef P_ATAPI_INTRQ
+#define P_ATAPI_INTRQ P_UNDEF
+#endif
+
+#ifndef P_ATAPI_IORDY
+#define P_ATAPI_IORDY P_UNDEF
+#endif
+
+#ifndef P_AMC_BR
+#define P_AMC_BR P_UNDEF
+#endif
+
+#ifndef P_AMC_BG
+#define P_AMC_BG P_UNDEF
+#endif
+
+#ifndef P_AMC_BGH
+#define P_AMC_BGH P_UNDEF
+#endif
+
+/* EMAC */
+
+#ifndef P_MII0_ETxD0
+#define P_MII0_ETxD0 P_UNDEF
+#endif
+
+#ifndef P_MII0_ETxD1
+#define P_MII0_ETxD1 P_UNDEF
+#endif
+
+#ifndef P_MII0_ETxD2
+#define P_MII0_ETxD2 P_UNDEF
+#endif
+
+#ifndef P_MII0_ETxD3
+#define P_MII0_ETxD3 P_UNDEF
+#endif
+
+#ifndef P_MII0_ETxEN
+#define P_MII0_ETxEN P_UNDEF
+#endif
+
+#ifndef P_MII0_TxCLK
+#define P_MII0_TxCLK P_UNDEF
+#endif
+
+#ifndef P_MII0_PHYINT
+#define P_MII0_PHYINT P_UNDEF
+#endif
+
+#ifndef P_MII0_COL
+#define P_MII0_COL P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxD0
+#define P_MII0_ERxD0 P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxD1
+#define P_MII0_ERxD1 P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxD2
+#define P_MII0_ERxD2 P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxD3
+#define P_MII0_ERxD3 P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxDV
+#define P_MII0_ERxDV P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxCLK
+#define P_MII0_ERxCLK P_UNDEF
+#endif
+
+#ifndef P_MII0_ERxER
+#define P_MII0_ERxER P_UNDEF
+#endif
+
+#ifndef P_MII0_CRS
+#define P_MII0_CRS P_UNDEF
+#endif
+
+#ifndef P_RMII0_REF_CLK
+#define P_RMII0_REF_CLK P_UNDEF
+#endif
+
+#ifndef P_RMII0_MDINT
+#define P_RMII0_MDINT P_UNDEF
+#endif
+
+#ifndef P_RMII0_CRS_DV
+#define P_RMII0_CRS_DV P_UNDEF
+#endif
+
+#ifndef P_MDC
+#define P_MDC P_UNDEF
+#endif
+
+#ifndef P_MDIO
+#define P_MDIO P_UNDEF
+#endif
+
+#endif /* _PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
index 6bc7208..952438e 100644
--- a/arch/blackfin/include/asm/system.h
+++ b/arch/blackfin/include/asm/system.h
@@ -118,4 +118,6 @@
return tmp;
}
+void bfin_reset_boot_spi_cs(unsigned short pin);
+
#endif /* _BLACKFIN_SYSTEM_H */
diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk
index 793cc43..aba96b3 100644
--- a/arch/nios2/config.mk
+++ b/arch/nios2/config.mk
@@ -30,3 +30,6 @@
PLATFORM_CPPFLAGS += -G0
LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+LDFLAGS += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
diff --git a/arch/nios2/include/asm/gpio.h b/arch/nios2/include/asm/gpio.h
index 76c425e..cff1dd9 100644
--- a/arch/nios2/include/asm/gpio.h
+++ b/arch/nios2/include/asm/gpio.h
@@ -21,6 +21,11 @@
#ifdef CONFIG_SYS_GPIO_BASE
#include <asm/io.h>
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
static inline int gpio_direction_input(unsigned gpio)
{
writel(1, CONFIG_SYS_GPIO_BASE + (gpio << 2));
@@ -43,6 +48,7 @@
writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2));
}
#else
+extern int gpio_request(unsigned gpio, const char *label);
extern int gpio_direction_input(unsigned gpio);
extern int gpio_direction_output(unsigned gpio, int value);
extern int gpio_get_value(unsigned gpio);
diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c
index e4093a8..e25a113 100644
--- a/arch/nios2/lib/bootm.c
+++ b/arch/nios2/lib/bootm.c
@@ -34,6 +34,18 @@
char *commandline = getenv("bootargs");
ulong initrd_start = images->rd_start;
ulong initrd_end = images->rd_end;
+ char *of_flat_tree = NULL;
+#if defined(CONFIG_OF_LIBFDT)
+ ulong of_size = 0;
+
+ /* find flattened device tree */
+ if (boot_get_fdt(flag, argc, argv, images, &of_flat_tree, &of_size))
+ return 1;
+#endif
+ if (!of_flat_tree)
+ of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
+ if (of_flat_tree)
+ initrd_end = (ulong)of_flat_tree;
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
return 1;
@@ -45,6 +57,15 @@
debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline);
debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end);
+ /* kernel parameters passing
+ * r4 : NIOS magic
+ * r5 : initrd start
+ * r6 : initrd end or fdt
+ * r7 : kernel command line
+ * fdt is passed to kernel via r6, the same as initrd_end. fdt will be
+ * verified with fdt magic. when both initrd and fdt are used at the
+ * same time, fdt must follow immediately after initrd.
+ */
kernel(NIOS_MAGIC, initrd_start, initrd_end, commandline);
/* does not return */
diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c
index f638c00..9ef5609 100644
--- a/arch/powerpc/cpu/mpc512x/diu.c
+++ b/arch/powerpc/cpu/mpc512x/diu.c
@@ -111,10 +111,8 @@
{
unsigned int addr;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
if (!strncmp(argv[1], "init", 4)) {
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
diff --git a/arch/powerpc/cpu/mpc8260/bedbug_603e.c b/arch/powerpc/cpu/mpc8260/bedbug_603e.c
index 2488612..89193a3 100644
--- a/arch/powerpc/cpu/mpc8260/bedbug_603e.c
+++ b/arch/powerpc/cpu/mpc8260/bedbug_603e.c
@@ -71,10 +71,7 @@
/* -------------------------------------------------- */
if (argc < 2)
- {
- cmd_usage(cmdtp);
- return;
- }
+ return cmd_usage(cmdtp);
/* Turn off a breakpoint */
@@ -118,10 +115,7 @@
if(!(( isdigit( argv[ 1 ][ 0 ] )) ||
(( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) ||
(( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' ))))
- {
- cmd_usage(cmdtp);
- return;
- }
+ return cmd_usage(cmdtp);
addr = simple_strtoul( argv[ 1 ], NULL, 16 );
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index b664c64..6635109 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -55,6 +55,7 @@
char name[15];
u32 partid;
} cpu_type_list [] = {
+ CPU_TYPE_ENTRY(8308),
CPU_TYPE_ENTRY(8311),
CPU_TYPE_ENTRY(8313),
CPU_TYPE_ENTRY(8314),
@@ -125,72 +126,6 @@
return 0;
}
-
-/*
- * Program a UPM with the code supplied in the table.
- *
- * The 'dummy' variable is used to increment the MAD. 'dummy' is
- * supposed to be a pointer to the memory of the device being
- * programmed by the UPM. The data in the MDR is written into
- * memory and the MAD is incremented every time there's a write
- * to 'dummy'. Unfortunately, the current prototype for this
- * function doesn't allow for passing the address of this
- * device, and changing the prototype will break a number lots
- * of other code, so we need to use a round-about way of finding
- * the value for 'dummy'.
- *
- * The value can be extracted from the base address bits of the
- * Base Register (BR) associated with the specific UPM. To find
- * that BR, we need to scan all 8 BRs until we find the one that
- * has its MSEL bits matching the UPM we want. Once we know the
- * right BR, we can extract the base address bits from it.
- *
- * The MxMR and the BR and OR of the chosen bank should all be
- * configured before calling this function.
- *
- * Parameters:
- * upm: 0=UPMA, 1=UPMB, 2=UPMC
- * table: Pointer to an array of values to program
- * size: Number of elements in the array. Must be 64 or less.
- */
-void upmconfig (uint upm, uint *table, uint size)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbus = &immap->lbus;
- volatile uchar *dummy = NULL;
- const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
- volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
- uint i;
-
- /* Scan all the banks to determine the base address of the device */
- for (i = 0; i < 8; i++) {
- if ((lbus->bank[i].br & BR_MSEL) == msel) {
- dummy = (uchar *) (lbus->bank[i].br & BR_BA);
- break;
- }
- }
-
- if (!dummy) {
- printf("Error: %s() could not find matching BR\n", __FUNCTION__);
- hang();
- }
-
- /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
- *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
-
- for (i = 0; i < size; i++) {
- lbus->mdr = table[i];
- __asm__ __volatile__ ("sync");
- *dummy = 0; /* Write the value to memory and increment MAD */
- __asm__ __volatile__ ("sync");
- while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
- }
-
- /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
- *mxmr &= 0xCFFFFFC0;
-}
-
-
int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index f3b67ae..83cba93 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -236,8 +236,8 @@
/* LCRR - Clock Ratio Register (10.3.1.16)
* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
*/
- clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
- __raw_readl(&im->lbus.lcrr);
+ clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
+ __raw_readl(&im->im_lbc.lcrr);
isync();
/* Enable Time Base & Decrementer ( so we will have udelay() )*/
@@ -267,80 +267,41 @@
/* Config QE ioports */
config_qe_ioports();
#endif
+ /* Set up preliminary BR/OR regs */
+ init_early_memctl_regs();
- /*
- * Memory Controller:
- */
-
- /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
- * addresses - these have to be modified later when FLASH size
- * has been determined
- */
-
-#if defined(CONFIG_SYS_BR0_PRELIM) \
- && defined(CONFIG_SYS_OR0_PRELIM) \
- && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
- && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
- im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
- im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
+ /* Local Access window setup */
+#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
#else
-#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
+#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#endif
-#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
- im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
- im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
- im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
- im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
- im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
- im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
- im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
- im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
- im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
- im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
- im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
- im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
- im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c
index 8dadd64..f8eab96 100644
--- a/arch/powerpc/cpu/mpc83xx/ecc.c
+++ b/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -118,10 +118,8 @@
writeback[0] = 0x01234567UL;
writeback[1] = 0x89abcdefUL;
- if (argc > 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc > 4)
+ return cmd_usage(cmdtp);
if (argc == 2) {
if (strcmp(argv[1], "status") == 0) {
@@ -350,8 +348,7 @@
return 0;
}
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(ecc, 4, 0, do_ecc,
diff --git a/arch/powerpc/cpu/mpc83xx/nand_init.c b/arch/powerpc/cpu/mpc83xx/nand_init.c
index 38e141a..d1648b7 100644
--- a/arch/powerpc/cpu/mpc83xx/nand_init.c
+++ b/arch/powerpc/cpu/mpc83xx/nand_init.c
@@ -88,8 +88,8 @@
&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
- im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM;
- im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM;
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
#else
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index b5076a9..93e9f1c 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -100,7 +100,8 @@
u32 lcrr;
u32 csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
@@ -132,7 +133,8 @@
u32 qe_clk;
u32 brg_clk;
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC837x)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
@@ -164,7 +166,8 @@
sccr = im->clk.sccr;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
@@ -202,7 +205,8 @@
}
#endif
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
+ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
@@ -319,7 +323,7 @@
i2c1_clk = csb_clk;
#elif defined(CONFIG_MPC832x)
i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC831x)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
i2c1_clk = sdhc_clk;
@@ -328,7 +332,8 @@
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC837x)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
pciexp1_clk = 0;
@@ -388,7 +393,7 @@
lbiu_clk = csb_clk *
(1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
- lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
+ lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
switch (lcrr) {
case 2:
case 4:
@@ -444,7 +449,8 @@
#endif
gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
gd->tsec1_clk = tsec1_clk;
gd->tsec2_clk = tsec2_clk;
gd->usbdr_clk = usbdr_clk;
@@ -525,7 +531,8 @@
#if defined(CONFIG_FSL_ESDHC)
printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
#endif
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index f064fee..fe851f1 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -32,6 +32,7 @@
SOBJS-$(CONFIG_MP) += release.o
SOBJS = $(SOBJS-y)
+COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o
COBJS-$(CONFIG_CPM2) += commproc.o
# supports ddr1
@@ -57,12 +58,15 @@
COBJS-$(CONFIG_P1022) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_MP) += mp.o
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
+COBJS-$(CONFIG_P1022) += p1022_serdes.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
new file mode 100644
index 0000000..d7835c8
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/compiler.h>
+#include <asm/processor.h>
+
+static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ __maybe_unused u32 svr = get_svr();
+
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+ if (IS_SVR_REV(svr, 1, 0)) {
+ switch (SVR_SOC_VER(svr)) {
+ case SVR_P1013:
+ case SVR_P1013_E:
+ case SVR_P1022:
+ case SVR_P1022_E:
+ puts("Work-around for Erratum SATA A001 enabled\n");
+ }
+ }
+#endif
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ errata, 1, 0, do_errata,
+ "Report errata workarounds",
+ ""
+);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 6f81fdf..f15d43c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -32,6 +32,8 @@
#include <fsl_esdhc.h>
#include <asm/cache.h>
#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -93,18 +95,26 @@
minor = PVR_MIN(pvr);
printf("Core: ");
- switch (fam) {
- case PVR_FAM(PVR_85xx):
- puts("E500");
- break;
- default:
- puts("Unknown");
- break;
+ if (PVR_FAM(PVR_85xx)) {
+ switch(PVR_MEM(pvr)) {
+ case 0x1:
+ case 0x2:
+ puts("E500");
+ break;
+ case 0x3:
+ puts("E500MC");
+ break;
+ case 0x4:
+ puts("E5500");
+ break;
+ default:
+ puts("Unknown");
+ break;
+ }
+ } else {
+ puts("Unknown");
}
- if (PVR_MEM(pvr) == 0x03)
- puts("MC");
-
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
@@ -169,7 +179,7 @@
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
- printf(" FMAN%d: %s MHz\n", i,
+ printf(" FMAN%d: %s MHz\n", i + 1,
strmhz(buf1, sysinfo.freqFMan[i]));
}
#endif
@@ -250,71 +260,6 @@
#endif /* CONFIG_WATCHDOG */
/*
- * Configures a UPM. The function requires the respective MxMR to be set
- * before calling this function. "size" is the number or entries, not a sizeof.
- */
-void upmconfig (uint upm, uint * table, uint size)
-{
- int i, mdr, mad, old_mad = 0;
- volatile u32 *mxmr;
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
- volatile u32 *brp,*orp;
- volatile u8* dummy = NULL;
- int upmmask;
-
- switch (upm) {
- case UPMA:
- mxmr = &lbc->mamr;
- upmmask = BR_MS_UPMA;
- break;
- case UPMB:
- mxmr = &lbc->mbmr;
- upmmask = BR_MS_UPMB;
- break;
- case UPMC:
- mxmr = &lbc->mcmr;
- upmmask = BR_MS_UPMC;
- break;
- default:
- printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
- hang();
- }
-
- /* Find the address for the dummy write transaction */
- for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
- i++, brp += 2, orp += 2) {
-
- /* Look for a valid BR with selected UPM */
- if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
- dummy = (volatile u8*)(in_be32(brp) & BR_BA);
- break;
- }
- }
-
- if (i == 8) {
- printf("Error: %s() could not find matching BR\n", __FUNCTION__);
- hang();
- }
-
- for (i = 0; i < size; i++) {
- /* 1 */
- out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
- /* 2 */
- out_be32(&lbc->mdr, table[i]);
- /* 3 */
- mdr = in_be32(&lbc->mdr);
- /* 4 */
- *(volatile u8 *)dummy = 0;
- /* 5 */
- do {
- mad = in_be32(mxmr) & MxMR_MAD_MSK;
- } while (mad <= old_mad && !(!mad && i == (size-1)));
- old_mad = mad;
- }
- out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
-}
-
-/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
@@ -326,3 +271,14 @@
return 0;
#endif
}
+
+/*
+ * Print out the state of various machine registers.
+ * Currently prints out LAWs, BR0/OR0, and TLBs
+ */
+void mpc85xx_reginfo(void)
+{
+ print_tlbcam();
+ print_laws();
+ print_lbc_regs();
+}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 99431dc..5d5b4c2 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -39,10 +39,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_MPC8536
-extern void fsl_serdes_init(void);
-#endif
-
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -154,7 +150,6 @@
void cpu_init_f (void)
{
- volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
@@ -177,60 +172,7 @@
config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
#endif
- /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
- * addresses - these have to be modified later when FLASH size
- * has been determined
- */
-#if defined(CONFIG_SYS_OR0_REMAP)
- out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
-#endif
-#if defined(CONFIG_SYS_OR1_REMAP)
- out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
-#endif
-
- /* now restrict to preliminary range */
- /* if cs1 is already set via debugger, leave cs0/cs1 alone */
- if (! memctl->br1 & 1) {
-#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
- out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
- out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
-#endif
-
-#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
- out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
- out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
-#endif
- }
-
-#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
- out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
- out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
-#endif
-
-#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
- out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
-#endif
-
-#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
- out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
- out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
-#endif
-
-#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
- out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
- out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
-#endif
-
-#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
- out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
- out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
-#endif
-
-#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
- out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
- out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
-#endif
+ init_early_memctl_regs();
#if defined(CONFIG_CPM2)
m8560_cpm_reset();
@@ -239,9 +181,6 @@
/* Config QE ioports */
config_qe_ioports();
#endif
-#if defined(CONFIG_MPC8536)
- fsl_serdes_init();
-#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
@@ -263,7 +202,7 @@
int cpu_init_r(void)
{
#ifdef CONFIG_SYS_LBC_LCRR
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
puts ("L2: ");
@@ -386,6 +325,11 @@
qe_reset();
#endif
+#if defined(CONFIG_SYS_HAS_SERDES)
+ /* needs to be in ram since code uses global static vars */
+ fsl_serdes_init();
+#endif
+
#if defined(CONFIG_MP)
setup_mp();
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 184cca4..8fb27ab 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -25,7 +25,7 @@
void cpu_init_f(void)
{
- ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
/*
* LCRR - Clock Ratio Register - set up local bus timing
@@ -34,8 +34,8 @@
out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
- out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
- out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
+ set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
#else
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 1d11ab4..932466e 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -298,17 +298,17 @@
}
#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
-static void ft_fixup_clks(void *blob, const char *alias, unsigned long freq)
+static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
+ unsigned long freq)
{
- const char *path = fdt_get_alias(blob, alias);
-
- int off = fdt_path_offset(blob, path);
+ phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
+ int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
if (off >= 0) {
off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
if (off > 0)
printf("WARNING enable to set clock-frequency "
- "for %s: %s\n", alias, fdt_strerror(off));
+ "for %s: %s\n", compat, fdt_strerror(off));
}
}
@@ -317,14 +317,17 @@
sys_info_t sysinfo;
get_sys_info(&sysinfo);
- ft_fixup_clks(blob, "fman0", sysinfo.freqFMan[0]);
+ ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
+ sysinfo.freqFMan[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
- ft_fixup_clks(blob, "fman1", sysinfo.freqFMan[1]);
+ ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
+ sysinfo.freqFMan[1]);
#endif
#ifdef CONFIG_SYS_DPAA_PME
- ft_fixup_clks(blob, "pme", sysinfo.freqPME);
+ do_fixup_by_compat_u32(blob, "fsl,pme",
+ "clock-frequency", sysinfo.freqPME, 1);
#endif
}
#else
@@ -400,12 +403,17 @@
"clock-frequency", bd->bi_brgfreq, 1);
#endif
+#ifdef CONFIG_FSL_CORENET
+ do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
+ "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+#endif
+
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#ifdef CONFIG_MP
ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
-#endif
ft_fixup_num_cores(blob);
+#endif
ft_fixup_cache(blob);
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index ddbc221..e05257c 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -77,6 +77,13 @@
return 0;
}
+
+int is_core_disabled(int nr) {
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 coredisrl = in_be32(&gur->coredisrl);
+
+ return (coredisrl & (1 << nr));
+}
#else
int cpu_disable(int nr)
{
@@ -96,6 +103,22 @@
return 0;
}
+
+int is_core_disabled(int nr) {
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr = in_be32(&gur->devdisr);
+
+ switch (nr) {
+ case 0:
+ return (devdisr & MPC85xx_DEVDISR_CPU0);
+ case 1:
+ return (devdisr & MPC85xx_DEVDISR_CPU1);
+ default:
+ printf("Invalid cpu number for disable %d\n", nr);
+ }
+
+ return 0;
+}
#endif
static u8 boot_entry_map[4] = {
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
index 7e72f5f..6dadeb8 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
@@ -66,10 +66,11 @@
#define FSL_SRDSCR3_LANEE_SGMII 0x00000000
#define FSL_SRDSCR3_LANEE_SATA 0x00150005
-
#define SRDS1_MAX_LANES 8
#define SRDS2_MAX_LANES 2
+static u32 serdes1_prtcl_map, serdes2_prtcl_map;
+
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
@@ -86,39 +87,12 @@
int is_serdes_configured(enum srds_prtcl device)
{
- int i;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int ret = (1 << device) & serdes1_prtcl_map;
- u32 srds2_cfg = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >>
- GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
+ if (ret)
+ return ret;
- debug("%s: dev = %d\n", __FUNCTION__, device);
- debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
- debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_cfg);
-
- if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
- return 0;
- }
-
- if (srds2_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
- printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_cfg);
- return 0;
- }
-
- for (i = 0; i < SRDS1_MAX_LANES; i++) {
- if (serdes1_cfg_tbl[srds1_cfg][i] == device)
- return 1;
- }
- for (i = 0; i < SRDS2_MAX_LANES; i++) {
- if (serdes2_cfg_tbl[srds2_cfg][i] == device)
- return 1;
- }
-
- return 0;
+ return (1 << device) & serdes2_prtcl_map;
}
void fsl_serdes_init(void)
@@ -126,13 +100,20 @@
void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
- u32 srds2_io_sel;
+ u32 srds1_io_sel, srds2_io_sel;
u32 tmp;
+ int lane;
+
+ srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
/* parse the SRDS2_IO_SEL of PORDEVSR */
srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
>> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
+ debug("PORDEVSR[SRDS1_IO_SEL] = %x\n", srds1_io_sel);
+ debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_io_sel);
+
switch (srds2_io_sel) {
case 1: /* Lane A - SATA1, Lane E - SATA2 */
/* CR 0 */
@@ -246,4 +227,23 @@
default:
break;
}
+
+ if (srds1_io_sel > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
+ return;
+ }
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+
+ if (srds2_io_sel > ARRAY_SIZE(serdes2_cfg_tbl)) {
+ printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
+ return;
+ }
+
+ for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane];
+ serdes2_prtcl_map |= (1 << lane_prtcl);
+ }
}
diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
new file mode 100644
index 0000000..e4c9c22
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 4
+#define SRDS2_MAX_LANES 2
+
+static u32 serdes1_prtcl_map, serdes2_prtcl_map;
+
+static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0x00] = {NONE, NONE, NONE, NONE},
+ [0x01] = {NONE, NONE, NONE, NONE},
+ [0x02] = {NONE, NONE, NONE, NONE},
+ [0x03] = {NONE, NONE, NONE, NONE},
+ [0x04] = {NONE, NONE, NONE, NONE},
+ [0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
+ [0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
+ [0x09] = {PCIE1, NONE, NONE, NONE},
+ [0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
+ [0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
+ [0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
+ [0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
+ [0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
+ [0x15] = {PCIE1, PCIE3, PCIE2, PCIE2},
+ [0x16] = {PCIE1, PCIE3, PCIE2, PCIE2},
+ [0x17] = {PCIE1, PCIE3, PCIE2, PCIE2},
+ [0x18] = {PCIE1, PCIE1, PCIE2, PCIE2},
+ [0x19] = {PCIE1, PCIE1, PCIE2, PCIE2},
+ [0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2},
+ [0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2},
+ [0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1},
+ [0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2},
+ [0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2},
+ [0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2},
+};
+
+static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
+ [0x00] = {PCIE3, PCIE3},
+ [0x01] = {PCIE2, PCIE3},
+ [0x02] = {SATA1, SATA2},
+ [0x03] = {SGMII_TSEC1, SGMII_TSEC2},
+ [0x04] = {NONE, NONE},
+ [0x06] = {SATA1, SATA2},
+ [0x07] = {NONE, NONE},
+ [0x09] = {PCIE3, PCIE2},
+ [0x0a] = {SATA1, SATA2},
+ [0x0b] = {NONE, NONE},
+ [0x0d] = {PCIE3, PCIE2},
+ [0x0e] = {SATA1, SATA2},
+ [0x0f] = {NONE, NONE},
+ [0x15] = {SGMII_TSEC1, SGMII_TSEC2},
+ [0x16] = {SATA1, SATA2},
+ [0x17] = {NONE, NONE},
+ [0x18] = {PCIE3, PCIE3},
+ [0x19] = {SGMII_TSEC1, SGMII_TSEC2},
+ [0x1a] = {SATA1, SATA2},
+ [0x1b] = {NONE, NONE},
+ [0x1c] = {PCIE3, PCIE3},
+ [0x1d] = {SGMII_TSEC1, SGMII_TSEC2},
+ [0x1e] = {SATA1, SATA2},
+ [0x1f] = {NONE, NONE},
+};
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ int ret = (1 << device) & serdes1_prtcl_map;
+
+ if (ret)
+ return ret;
+
+ return (1 << device) & serdes2_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+
+ if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
+ serdes2_prtcl_map |= (1 << lane_prtcl);
+ }
+}
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 8132115..dd4c6b3 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -172,10 +172,7 @@
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
- {
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
- lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
- }
+ lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index b3037ac..f2833a5 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -55,7 +55,45 @@
return ;
}
+void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
+ phys_addr_t *rpn)
+{
+ u32 _mas1;
+
+ mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
+ asm volatile("tlbre;isync");
+ _mas1 = mfspr(MAS1);
+
+ *valid = (_mas1 & MAS1_VALID);
+ *tsize = (_mas1 >> 8) & 0xf;
+ *epn = mfspr(MAS2) & MAS2_EPN;
+ *rpn = mfspr(MAS3) & MAS3_RPN;
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+ *rpn |= ((u64)mfspr(MAS7)) << 32;
+#endif
+}
+
#ifndef CONFIG_NAND_SPL
+void print_tlbcam(void)
+{
+ int i;
+ unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
+
+ /* walk all the entries */
+ printf("TLBCAM entries\n");
+ for (i = 0; i < num_cam; i++) {
+ unsigned long epn;
+ u32 tsize, valid;
+ phys_addr_t rpn;
+
+ read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
+ printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
+ i, (valid == 0) ? 0 : 1, (unsigned int)epn,
+ (unsigned long long)rpn);
+ print_size(TSIZE_TO_BYTES(tsize), "\n");
+ }
+}
+
static inline void use_tlb_cam(u8 idx)
{
int i = idx / 32;
@@ -82,15 +120,9 @@
/* walk all the entries */
for (i = 0; i < num_cam; i++) {
- u32 _mas1;
-
mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
-
asm volatile("tlbre;isync");
- _mas1 = mfspr(MAS1);
-
- /* if the entry isn't valid skip it */
- if ((_mas1 & MAS1_VALID))
+ if (mfspr(MAS1) & MAS1_VALID)
use_tlb_cam(i);
}
}
@@ -134,7 +166,7 @@
#ifdef CONFIG_ADDR_MAP
if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
- addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
+ addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
#endif
}
@@ -201,26 +233,12 @@
/* walk all the entries */
for (i = 0; i < num_cam; i++) {
unsigned long epn;
- u32 tsize, _mas1;
+ u32 tsize, valid;
phys_addr_t rpn;
- mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
-
- asm volatile("tlbre;isync");
- _mas1 = mfspr(MAS1);
-
- /* if the entry isn't valid skip it */
- if (!(_mas1 & MAS1_VALID))
- continue;
-
- tsize = (_mas1 >> 8) & 0xf;
- epn = mfspr(MAS2) & MAS2_EPN;
- rpn = mfspr(MAS3) & MAS3_RPN;
-#ifdef CONFIG_ENABLE_36BIT_PHYS
- rpn |= ((phys_addr_t)mfspr(MAS7)) << 32;
-#endif
-
- addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i);
+ read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
+ if (valid & MAS1_VALID)
+ addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
}
return ;
diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
index 9064e78..4e90fd2 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu.c
@@ -180,22 +180,9 @@
*/
void mpc86xx_reginfo(void)
{
- immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- ccsr_lbc_t *lbc = &immap->im_lbc;
-
print_bats();
print_laws();
-
- printf ("Local Bus Controller Registers\n"
- "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
- printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
- printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
- printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
- printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
- printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
- printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
- printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
-
+ print_lbc_regs();
}
/*
diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c
index b4f047d..82c216b 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c
@@ -46,9 +46,6 @@
void cpu_init_f(void)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_lbc_t *memctl = &immap->im_lbc;
-
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -61,58 +58,8 @@
setup_bats();
- /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
- * addresses - these have to be modified later when FLASH size
- * has been determined
- */
+ init_early_memctl_regs();
-#if defined(CONFIG_SYS_OR0_REMAP)
- memctl->or0 = CONFIG_SYS_OR0_REMAP;
-#endif
-#if defined(CONFIG_SYS_OR1_REMAP)
- memctl->or1 = CONFIG_SYS_OR1_REMAP;
-#endif
-
- /* now restrict to preliminary range */
-#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
- memctl->br0 = CONFIG_SYS_BR0_PRELIM;
- memctl->or0 = CONFIG_SYS_OR0_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
- memctl->or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->br1 = CONFIG_SYS_BR1_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
- memctl->or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->br2 = CONFIG_SYS_BR2_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- memctl->or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->br3 = CONFIG_SYS_BR3_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
- memctl->or4 = CONFIG_SYS_OR4_PRELIM;
- memctl->br4 = CONFIG_SYS_BR4_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
- memctl->or5 = CONFIG_SYS_OR5_PRELIM;
- memctl->br5 = CONFIG_SYS_BR5_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
- memctl->or6 = CONFIG_SYS_OR6_PRELIM;
- memctl->br6 = CONFIG_SYS_BR6_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
- memctl->or7 = CONFIG_SYS_OR7_PRELIM;
- memctl->br7 = CONFIG_SYS_BR7_PRELIM;
-#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
index 51f3f4c..ff89ee5 100644
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ b/arch/powerpc/cpu/mpc86xx/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -55,6 +55,7 @@
off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
if (off < 0)
printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
-#endif
+
ft_fixup_num_cores(blob);
+#endif
}
diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c
index 24eb30a..30c99eb 100644
--- a/arch/powerpc/cpu/mpc86xx/mp.c
+++ b/arch/powerpc/cpu/mpc86xx/mp.c
@@ -66,6 +66,23 @@
return 0;
}
+int is_core_disabled(int nr) {
+ immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
+ ccsr_gur_t *gur = &immap->im_gur;
+ u32 devdisr = in_be32(&gur->devdisr);
+
+ switch (nr) {
+ case 0:
+ return (devdisr & MPC86xx_DEVDISR_CPU0);
+ case 1:
+ return (devdisr & MPC86xx_DEVDISR_CPU1);
+ default:
+ printf("Invalid cpu number for disable %d\n", nr);
+ }
+
+ return 0;
+}
+
int cpu_release(int nr, int argc, char * const argv[])
{
/* dummy function so common/cmd_mp.c will build
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index 64a3479..a2d0a8a 100644
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -97,10 +97,7 @@
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
- {
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
- lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
- }
+ lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);
diff --git a/arch/powerpc/cpu/mpc8xx/bedbug_860.c b/arch/powerpc/cpu/mpc8xx/bedbug_860.c
index 9deda6c..83db035 100644
--- a/arch/powerpc/cpu/mpc8xx/bedbug_860.c
+++ b/arch/powerpc/cpu/mpc8xx/bedbug_860.c
@@ -70,10 +70,7 @@
/* -------------------------------------------------- */
if (argc < 2)
- {
- cmd_usage(cmdtp);
- return;
- }
+ return cmd_usage(cmdtp);
/* Turn off a breakpoint */
@@ -121,10 +118,7 @@
/* Set a breakpoint at the address */
if( !isdigit( argv[ 1 ][ 0 ]))
- {
- cmd_usage(cmdtp);
- return;
- }
+ return cmd_usage(cmdtp);
addr = simple_strtoul( argv[ 1 ], NULL, 16 ) & 0xfffffffc;
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index eb0091b..e97ae68 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -149,8 +149,7 @@
* I owe him a free beer. - wd]
*/
-#if defined(CONFIG_GTH) || \
- defined(CONFIG_HERMES) || \
+#if defined(CONFIG_HERMES) || \
defined(CONFIG_ICU862) || \
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index 481f9e5..ea51222 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2009 Freescale Semiconductor, Inc.
+# Copyright 2009-2010 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
@@ -10,9 +10,13 @@
LIB = $(obj)lib8xxx.a
+ifneq ($(CPU),mpc83xx)
COBJS-y += cpu.o
-COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_PCI) += pci_cfg.o
+endif
+
+COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 22f3423..dc3da16 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -80,10 +80,16 @@
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2020, P2020_E, 2),
+ CPU_TYPE_ENTRY(P3041, P3041, 4),
+ CPU_TYPE_ENTRY(P3041, P3041_E, 4),
CPU_TYPE_ENTRY(P4040, P4040, 4),
CPU_TYPE_ENTRY(P4040, P4040_E, 4),
CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P4080, P4080_E, 8),
+ CPU_TYPE_ENTRY(P5010, P5010, 1),
+ CPU_TYPE_ENTRY(P5010, P5010_E, 1),
+ CPU_TYPE_ENTRY(P5020, P5020, 2),
+ CPU_TYPE_ENTRY(P5020, P5020_E, 2),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index ccefaf5..88c47d1 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -26,6 +26,27 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <asm/mp.h>
+
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
+static int ft_del_cpuhandle(void *blob, int cpuhandle)
+{
+ int off, ret = -FDT_ERR_NOTFOUND;
+
+ /* if we find a match, we'll delete at it which point the offsets are
+ * invalid so we start over from the beginning
+ */
+ off = fdt_node_offset_by_prop_value(blob, -1, "cpu-handle",
+ &cpuhandle, 4);
+ while (off != -FDT_ERR_NOTFOUND) {
+ fdt_delprop(blob, off, "cpu-handle");
+ ret = 1;
+ off = fdt_node_offset_by_prop_value(blob, -1, "cpu-handle",
+ &cpuhandle, 4);
+ }
+
+ return ret;
+}
void ft_fixup_num_cores(void *blob) {
int off, num_cores, del_cores;
@@ -37,13 +58,18 @@
while (off != -FDT_ERR_NOTFOUND) {
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
- /* if we find a cpu node outside of what we expect delete it
- * and reset the offset back to the start since we can't
- * trust the offsets anymore
- */
- if (*reg > num_cores-1) {
- fdt_del_node(blob, off);
- del_cores++;
+ if ((*reg > num_cores-1) || (is_core_disabled(*reg))) {
+ int ph = fdt_get_phandle(blob, off);
+
+ /* Delete the cpu node once there are no cpu handles */
+ if (-FDT_ERR_NOTFOUND == ft_del_cpuhandle(blob, ph)) {
+ fdt_del_node(blob, off);
+ del_cores++;
+ }
+ /* either we deleted some cpu handles or the cpu node
+ * so we reset the offset back to the start since we
+ * can't trust the offsets anymore
+ */
off = -1;
}
off = fdt_node_offset_by_prop_value(blob, off,
@@ -53,3 +79,139 @@
debug ("deleted %d extra core entry entries from device tree\n",
del_cores);
}
+#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+{
+ char *mode;
+ char *type;
+ const char *compat = "fsl-usb2-dr";
+ const char *prop_mode = "dr_mode";
+ const char *prop_type = "phy_type";
+ int node_offset;
+ int err;
+
+ mode = getenv("usb_dr_mode");
+ type = getenv("usb_phy_type");
+ if (!mode && !type)
+ return;
+
+ node_offset = fdt_node_offset_by_compatible(blob, 0, compat);
+ if (node_offset < 0) {
+ printf("WARNING: could not find compatible node %s: %s.\n",
+ compat, fdt_strerror(node_offset));
+ return;
+ }
+
+ if (mode) {
+ err = fdt_setprop(blob, node_offset, prop_mode, mode,
+ strlen(mode) + 1);
+ if (err < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop_mode, compat, fdt_strerror(err));
+ }
+
+ if (type) {
+ err = fdt_setprop(blob, node_offset, prop_type, type,
+ strlen(type) + 1);
+ if (err < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop_type, compat, fdt_strerror(err));
+ }
+}
+#endif /* CONFIG_HAS_FSL_DR_USB */
+
+/*
+ * update crypto node properties to a specified revision of the SEC
+ * called with sec_rev == 0 if not on an E processor
+ */
+#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
+void fdt_fixup_crypto_node(void *blob, int sec_rev)
+{
+ const struct sec_rev_prop {
+ u32 sec_rev;
+ u32 num_channels;
+ u32 channel_fifo_len;
+ u32 exec_units_mask;
+ u32 descriptor_types_mask;
+ } sec_rev_prop_list [] = {
+ { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
+ { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
+ { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
+ { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
+ { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
+ { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
+ { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
+ };
+ char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
+ sizeof("fsl,secX.Y")];
+ int crypto_node, sec_idx, err;
+ char *p;
+ u32 val;
+
+ /* locate crypto node based on lowest common compatible */
+ crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
+ if (crypto_node == -FDT_ERR_NOTFOUND)
+ return;
+
+ /* delete it if not on an E-processor */
+ if (crypto_node > 0 && !sec_rev) {
+ fdt_del_node(blob, crypto_node);
+ return;
+ }
+
+ /* else we got called for possible uprev */
+ for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
+ if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
+ break;
+
+ if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
+ puts("warning: unknown SEC revision number\n");
+ return;
+ }
+
+ val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
+ err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
+ if (err < 0)
+ printf("WARNING: could not set crypto property: %s\n",
+ fdt_strerror(err));
+
+ val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
+ err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4);
+ if (err < 0)
+ printf("WARNING: could not set crypto property: %s\n",
+ fdt_strerror(err));
+
+ val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
+ err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
+ if (err < 0)
+ printf("WARNING: could not set crypto property: %s\n",
+ fdt_strerror(err));
+
+ val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
+ err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
+ if (err < 0)
+ printf("WARNING: could not set crypto property: %s\n",
+ fdt_strerror(err));
+
+ val = 0;
+ while (sec_idx >= 0) {
+ p = compat_strlist + val;
+ val += sprintf(p, "fsl,sec%d.%d",
+ (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
+ sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
+ sec_idx--;
+ }
+ err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val);
+ if (err < 0)
+ printf("WARNING: could not set crypto property: %s\n",
+ fdt_strerror(err));
+}
+#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */
+void fdt_fixup_crypto_node(void *blob, int sec_rev)
+{
+ if (!sec_rev)
+ fdt_del_node_and_alias(blob, "crypto");
+}
+#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
new file mode 100644
index 0000000..fcef40c
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_lbc.h>
+
+void print_lbc_regs(void)
+{
+ int i;
+
+ printf("\nLocal Bus Controller Registers\n");
+ for (i = 0; i < 8; i++) {
+ printf("BR%d\t0x%08X\tOR%d\t0x%08X\n",
+ i, get_lbc_br(i), i, get_lbc_or(i));
+ }
+}
+
+void init_early_memctl_regs(void)
+{
+ uint init_br1 = 1;
+
+#ifdef CONFIG_MPC85xx
+ /* if cs1 is already set via debugger, leave cs0/cs1 alone */
+ if (get_lbc_br(1) & BR_V)
+ init_br1 = 0;
+#endif
+
+ /*
+ * Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
+ * preliminary addresses - these have to be modified later
+ * when FLASH size has been determined
+ */
+#if defined(CONFIG_SYS_OR0_REMAP)
+ set_lbc_or(0, CONFIG_SYS_OR0_REMAP);
+#endif
+#if defined(CONFIG_SYS_OR1_REMAP)
+ set_lbc_or(1, CONFIG_SYS_OR1_REMAP);
+#endif
+ /* now restrict to preliminary range */
+ if (init_br1) {
+ set_lbc_br(0, CONFIG_SYS_BR0_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_OR0_PRELIM);
+
+#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
+ set_lbc_or(1, CONFIG_SYS_OR1_PRELIM);
+ set_lbc_br(1, CONFIG_SYS_BR1_PRELIM);
+#endif
+ }
+
+#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
+ set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
+ set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
+ set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
+ set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
+ set_lbc_or(5, CONFIG_SYS_OR5_PRELIM);
+ set_lbc_br(5, CONFIG_SYS_BR5_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
+ set_lbc_or(6, CONFIG_SYS_OR6_PRELIM);
+ set_lbc_br(6, CONFIG_SYS_BR6_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
+ set_lbc_or(7, CONFIG_SYS_OR7_PRELIM);
+ set_lbc_br(7, CONFIG_SYS_BR7_PRELIM);
+#endif
+}
+
+/*
+ * Configures a UPM. The function requires the respective MxMR to be set
+ * before calling this function. "size" is the number or entries, not a sizeof.
+ */
+void upmconfig(uint upm, uint *table, uint size)
+{
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ int i, mdr, mad, old_mad = 0;
+ u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK);
+ u32 msel = BR_UPMx_TO_MSEL(upm);
+ u32 *mxmr = &lbc->mamr + upm;
+ volatile u8 *dummy = NULL;
+
+ if (upm < UPMA || upm > UPMC) {
+ printf("Error: %s() Bad UPM index %d\n", __func__, upm);
+ hang();
+ }
+
+ /*
+ * Find the address for the dummy write - scan all of the BRs until we
+ * find one matching the UPM and extract the base address bits from it.
+ */
+ for (i = 0; i < 8; i++) {
+ if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | msel)) {
+ dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
+ break;
+ }
+ }
+
+ if (!dummy) {
+ printf("Error: %s() No matching BR\n", __func__);
+ hang();
+ }
+
+ /* Program UPM using steps outlined by the reference manual */
+ for (i = 0; i < size; i++) {
+ out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i);
+ out_be32(&lbc->mdr, table[i]);
+ mdr = in_be32(&lbc->mdr);
+ *dummy = 0;
+ do {
+ mad = in_be32(mxmr) & MxMR_MAD_MSK;
+ } while (mad <= old_mad && !(!mad && i == (size-1)));
+ old_mad = mad;
+ }
+
+ /* Return to normal operation */
+ out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_NORM);
+}
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 0f69ef9..2fee995 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -767,6 +767,13 @@
debug("\n\n");
+#if defined(CONFIG_DDR_RFDC_FIXED)
+ mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
+ size = 512;
+ rffd_average = CONFIG_DDR_RFDC_FIXED & SDRAM_RFDC_RFFD_MASK;
+ mfsdram(SDRAM_RDCC, rdcc); /* record this value */
+ cal->rdcc = rdcc;
+#else /* CONFIG_DDR_RFDC_FIXED */
in_window = 0;
rdcc = 0;
@@ -830,6 +837,7 @@
rffd_average = SDRAM_RFDC_RFFD_MAX;
mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
+#endif /* CONFIG_DDR_RFDC_FIXED */
rffd = rffd_average;
in_window = 0;
@@ -1211,10 +1219,14 @@
debug("*** best_result: read value SDRAM_RQDC 0x%08x\n",
rqdc_reg);
+#if defined(CONFIG_DDR_RFDC_FIXED)
+ mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
+#else /* CONFIG_DDR_RFDC_FIXED */
mfsdram(SDRAM_RFDC, rfdc_reg);
rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
mtsdram(SDRAM_RFDC, rfdc_reg |
SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd));
+#endif /* CONFIG_DDR_RFDC_FIXED */
mfsdram(SDRAM_RFDC, rfdc_reg);
debug("*** best_result: read value SDRAM_RFDC 0x%08x\n",
diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile
index 88d53fb..c9c1a33 100644
--- a/arch/powerpc/cpu/ppc4xx/Makefile
+++ b/arch/powerpc/cpu/ppc4xx/Makefile
@@ -51,6 +51,9 @@
COBJS += denali_data_eye.o
COBJS += denali_spd_ddr2.o
COBJS += ecc.o
+ifdef CONFIG_CMD_ECCTEST
+COBJS += cmd_ecctest.o
+endif
COBJS += fdt.o
COBJS += interrupts.o
COBJS += iop480_uart.o
diff --git a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
new file mode 100644
index 0000000..b4eac40
--- /dev/null
+++ b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
+ defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
+
+#if defined(CONFIG_405EX)
+/*
+ * Currently only 405EX uses 16bit data bus width as an alternative
+ * option to 32bit data width (SDRAM0_MCOPT1_WDTH)
+ */
+#define SDRAM_DATA_ALT_WIDTH 2
+#else
+#define SDRAM_DATA_ALT_WIDTH 8
+#endif
+
+#if defined(CONFIG_SYS_OCM_BASE)
+#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_OCM_BASE
+#endif
+
+#if defined(CONFIG_SYS_ISRAM_BASE)
+#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_ISRAM_BASE
+#endif
+
+#if !defined(CONFIG_FUNC_ISRAM_ADDR)
+#error "No internal SRAM/OCM provided!"
+#endif
+
+#define force_inline inline __attribute__ ((always_inline))
+
+static inline void machine_check_disable(void)
+{
+ mtmsr(mfmsr() & ~MSR_ME);
+}
+
+static inline void machine_check_enable(void)
+{
+ mtmsr(mfmsr() | MSR_ME);
+}
+
+/*
+ * These helper functions need to be inlined, since they
+ * are called from the functions running from internal SRAM.
+ * SDRAM operation is forbidden at that time, so calling
+ * functions in SDRAM has to be avoided.
+ */
+static force_inline void wait_ddr_idle(void)
+{
+ u32 val;
+
+ do {
+ mfsdram(SDRAM_MCSTAT, val);
+ } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
+}
+
+static force_inline void recalibrate_ddr(void)
+{
+ u32 val;
+
+ /*
+ * Rewrite RQDC & RFDC to calibrate again. If this is not
+ * done, the SDRAM controller is working correctly after
+ * changing the MCOPT1_MCHK bits.
+ */
+ mfsdram(SDRAM_RQDC, val);
+ mtsdram(SDRAM_RQDC, val);
+ mfsdram(SDRAM_RFDC, val);
+ mtsdram(SDRAM_RFDC, val);
+}
+
+static force_inline void set_mcopt1_mchk(u32 bits)
+{
+ u32 val;
+
+ wait_ddr_idle();
+ mfsdram(SDRAM_MCOPT1, val);
+ mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | bits);
+ recalibrate_ddr();
+}
+
+/*
+ * The next 2 functions are copied to internal SRAM/OCM and run
+ * there. No function calls allowed here. No SDRAM acitivity should
+ * be done here.
+ */
+static void inject_ecc_error(void *ptr, int par)
+{
+ u32 val;
+
+ /*
+ * Taken from PPC460EX/EXr/GT users manual (Rev 1.21)
+ * 22.2.17.13 ECC Diagnostics
+ *
+ * Items 1 ... 5 are already done by now, running from RAM
+ * with ECC enabled
+ */
+
+ out_be32(ptr, 0x00000000);
+ val = in_be32(ptr);
+
+ /* 6. Set memory controller to no error checking */
+ set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON);
+
+ /* 7. Modify one or two bits for error simulation */
+ if (par == 1)
+ out_be32(ptr, in_be32(ptr) ^ 0x00000001);
+ else
+ out_be32(ptr, in_be32(ptr) ^ 0x00000003);
+
+ /* 8. Wait for SDRAM idle */
+ val = in_be32(ptr);
+ set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
+
+ /* Wait for SDRAM idle */
+ wait_ddr_idle();
+
+ /* Continue with 9. in calling function... */
+}
+
+static void rewrite_ecc_parity(void *ptr, int par)
+{
+ u32 current_address = (u32)ptr;
+ u32 end_address;
+ u32 address_increment;
+ u32 mcopt1;
+ u32 val;
+
+ /*
+ * Fill ECC parity byte again. Otherwise further accesses to
+ * the failure address will result in exceptions.
+ */
+
+ /* Wait for SDRAM idle */
+ val = in_be32(0x00000000);
+ set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN);
+
+ /* ECC bit set method for non-cached memory */
+ mfsdram(SDRAM_MCOPT1, mcopt1);
+ if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
+ address_increment = 4;
+ else
+ address_increment = SDRAM_DATA_ALT_WIDTH;
+ end_address = current_address + CONFIG_SYS_CACHELINE_SIZE;
+
+ while (current_address < end_address) {
+ *((unsigned long *)current_address) = 0;
+ current_address += address_increment;
+ }
+
+ set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
+
+ /* Wait for SDRAM idle */
+ wait_ddr_idle();
+}
+
+static int do_ecctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 old_val;
+ u32 val;
+ u32 *ptr;
+ void (*sram_func)(u32 *, int);
+ int error;
+
+ if (argc < 3) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ ptr = (u32 *)simple_strtoul(argv[1], NULL, 16);
+ error = simple_strtoul(argv[2], NULL, 16);
+ if ((error < 1) || (error > 2)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ printf("Using address %p for %d bit ECC error injection\n",
+ ptr, error);
+
+ /*
+ * Save value to restore it later on
+ */
+ old_val = in_be32(ptr);
+
+ /*
+ * Copy ECC injection function into internal SRAM/OCM
+ */
+ sram_func = (void *)CONFIG_FUNC_ISRAM_ADDR;
+ memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, inject_ecc_error, 0x10000);
+
+ /*
+ * Disable interrupts and exceptions before calling this
+ * function in internal SRAM/OCM
+ */
+ disable_interrupts();
+ machine_check_disable();
+ eieio();
+
+ /*
+ * Jump to ECC simulation function in internal SRAM/OCM
+ */
+ (*sram_func)(ptr, error);
+
+ /* 10. Read the corresponding address */
+ val = in_be32(ptr);
+
+ /*
+ * Read and print ECC status register/info:
+ * The faulting address is only known upon uncorrectable ECC
+ * errors.
+ */
+ mfsdram(SDRAM_ECCES, val);
+ if (val & SDRAM_ECCES_CE)
+ printf("ECC: Correctable error\n");
+ if (val & SDRAM_ECCES_UE) {
+ printf("ECC: Uncorrectable error at 0x%02x%08x\n",
+ mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
+ }
+
+ /*
+ * Clear pending interrupts/exceptions
+ */
+ mtsdram(SDRAM_ECCES, 0xffffffff);
+ mtdcr(SDRAM_ERRSTATLL, 0xff000000);
+ set_mcsr(get_mcsr());
+
+ /* Now enable interrupts and exceptions again */
+ eieio();
+ machine_check_enable();
+ enable_interrupts();
+
+ /*
+ * The ECC parity byte need to be re-written for the
+ * corresponding address. Otherwise future accesses to it
+ * will result in exceptions.
+ *
+ * Jump to ECC parity generation function
+ */
+ memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, rewrite_ecc_parity, 0x10000);
+ (*sram_func)(ptr, 0);
+
+ /*
+ * Restore value in corresponding address
+ */
+ out_be32(ptr, old_val);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ecctest, 3, 0, do_ecctest,
+ "Test ECC by single and double error bit injection",
+ "address 1/2"
+);
+
+#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
+#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c
index f105605..49f28d9 100644
--- a/arch/powerpc/cpu/ppc4xx/ecc.c
+++ b/arch/powerpc/cpu/ppc4xx/ecc.c
@@ -130,7 +130,26 @@
/* clear ECC error repoting registers */
mtsdram(SDRAM_ECCES, 0xffffffff);
- mtdcr(0x4c, 0xffffffff);
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
+ /*
+ * IBM DDR(1) core (440GX):
+ * Clear Mx bits in SDRAM0_BESR0/1
+ */
+ mtsdram(SDRAM0_BESR0, 0xffffffff);
+ mtsdram(SDRAM0_BESR1, 0xffffffff);
+#elif defined(CONFIG_440)
+ /*
+ * 440/460 DDR2 core:
+ * Clear EMID (Error PLB Master ID) in MQ0_ESL
+ */
+ mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
+#else
+ /*
+ * 405EX(r) DDR2 core:
+ * Clear M0ID (Error PLB Master ID) in SDRAM_BESR
+ */
+ mtsdram(SDRAM_BESR, 0xf0000000);
+#endif
mtsdram(SDRAM_MCOPT1,
(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
diff --git a/arch/powerpc/cpu/ppc4xx/traps.c b/arch/powerpc/cpu/ppc4xx/traps.c
index 1616772..b5562ad 100644
--- a/arch/powerpc/cpu/ppc4xx/traps.c
+++ b/arch/powerpc/cpu/ppc4xx/traps.c
@@ -209,6 +209,22 @@
/* Clear MCSR */
mtspr(SPRN_MCSR, val);
}
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+ /*
+ * Read and print ECC status register/info:
+ * The faulting address is only known upon uncorrectable ECC
+ * errors.
+ */
+ mfsdram(SDRAM_ECCES, val);
+ if (val & SDRAM_ECCES_CE)
+ printf("ECC: Correctable error\n");
+ if (val & SDRAM_ECCES_UE) {
+ printf("ECC: Uncorrectable error at 0x%02x%08x\n",
+ mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
+ }
+#endif /* CONFIG_DDR_ECC ... */
+
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
mfsdram(DDR0_00, val) ;
printf("DDR0: DDR0_00 %lx\n", val);
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index fc3facb..f70699d 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -44,8 +44,12 @@
defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_PPC_P3041)
+#define CONFIG_MAX_CPUS 4
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
+#elif defined(CONFIG_PPC_P5020)
+#define CONFIG_MAX_CPUS 2
#else
#define CONFIG_MAX_CPUS 1
#endif
@@ -66,6 +70,15 @@
#define CONFIG_TSECV2
#endif
+/*
+ * SEC (crypto unit) major compatible version determination
+ */
+#if defined(CONFIG_FSL_CORENET)
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
+#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#endif
+
/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
#define CONFIG_SYS_NUM_TLBCAMS 64
@@ -76,4 +89,10 @@
/* Relocation to SDRAM works on all PPC boards */
#define CONFIG_RELOC_FIXUP_WORKS
+/* Since so many PPC SOCs have a semi-common LBC, define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+ defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC
+#endif
+
#endif /* _ASM_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 34c56a2..12ba1a6 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -47,6 +47,7 @@
};
#define law_size_bits(sz) (__ilog2_u64(sz) - 1)
+#define lawar_size(x) (1ULL << ((x & 0x3f) + 1))
#ifdef CONFIG_FSL_CORENET
enum law_trgt_if {
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 03ae6a7..82d24ab 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -14,6 +14,7 @@
#define __ASM_PPC_FSL_LBC_H
#include <config.h>
+#include <common.h>
/* BR - Base Registers
*/
@@ -61,6 +62,8 @@
#define BR_V 0x00000001
#define BR_V_SHIFT 0
+#define BR_UPMx_TO_MSEL(x) ((x + 4) << BR_MSEL_SHIFT)
+
#define UPMA 0
#define UPMB 1
#define UPMC 2
@@ -453,49 +456,70 @@
#define LTESR_CC 0x00000001
#ifndef __ASSEMBLY__
-/*
- * Local Bus Controller Registers.
- */
-typedef struct lbus_bank {
- u32 br; /* Base Register */
- u32 or; /* Option Register */
-} lbus_bank_t;
+#include <asm/io.h>
-typedef struct fsl_lbus {
- lbus_bank_t bank[8];
- u8 res0[0x28];
- u32 mar; /* UPM Address Register */
- u8 res1[0x4];
- u32 mamr; /* UPMA Mode Register */
- u32 mbmr; /* UPMB Mode Register */
- u32 mcmr; /* UPMC Mode Register */
- u8 res2[0x8];
- u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
- u32 mdr; /* UPM Data Register */
- u8 res3[0x4];
- u32 lsor; /* Special Operation Initiation Register */
- u32 lsdmr; /* SDRAM Mode Register */
- u8 res4[0x8];
- u32 lurt; /* UPM Refresh Timer */
- u32 lsrt; /* SDRAM Refresh Timer */
- u8 res5[0x8];
- u32 ltesr; /* Transfer Error Status Register */
- u32 ltedr; /* Transfer Error Disable Register */
- u32 lteir; /* Transfer Error Interrupt Register */
- u32 lteatr; /* Transfer Error Attributes Register */
- u32 ltear; /* Transfer Error Address Register */
- u8 res6[0xC];
- u32 lbcr; /* Configuration Register */
- u32 lcrr; /* Clock Ratio Register */
- u8 res7[0x8];
- u32 fmr; /* Flash Mode Register */
- u32 fir; /* Flash Instruction Register */
- u32 fcr; /* Flash Command Register */
- u32 fbar; /* Flash Block Addr Register */
- u32 fpar; /* Flash Page Addr Register */
- u32 fbcr; /* Flash Byte Count Register */
- u8 res8[0xF08];
-} fsl_lbus_t;
+extern void print_lbc_regs(void);
+extern void init_early_memctl_regs(void);
+extern void upmconfig(uint upm, uint *table, uint size);
+
+#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
+#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
+#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
+#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
+#define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
+
+typedef struct lbc_bank {
+ u32 br;
+ u32 or;
+} lbc_bank_t;
+
+/* Local Bus Controller Registers */
+typedef struct fsl_lbc {
+ lbc_bank_t bank[8];
+ u8 res1[40];
+ u32 mar; /* LBC UPM Addr */
+ u8 res2[4];
+ u32 mamr; /* LBC UPMA Mode */
+ u32 mbmr; /* LBC UPMB Mode */
+ u32 mcmr; /* LBC UPMC Mode */
+ u8 res3[8];
+ u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
+ u32 mdr; /* LBC UPM Data */
+#ifdef CONFIG_FSL_ELBC
+ u8 res4[4];
+ u32 lsor;
+ u8 res5[12];
+ u32 lurt; /* LBC UPM Refresh Timer */
+ u8 res6[4];
+#else
+ u8 res4[8];
+ u32 lsdmr; /* LBC SDRAM Mode */
+ u8 res5[8];
+ u32 lurt; /* LBC UPM Refresh Timer */
+ u32 lsrt; /* LBC SDRAM Refresh Timer */
+#endif
+ u8 res7[8];
+ u32 ltesr; /* LBC Transfer Error Status */
+ u32 ltedr; /* LBC Transfer Error Disable */
+ u32 lteir; /* LBC Transfer Error IRQ */
+ u32 lteatr; /* LBC Transfer Error Attrs */
+ u32 ltear; /* LBC Transfer Error Addr */
+ u8 res8[12];
+ u32 lbcr; /* LBC Configuration */
+ u32 lcrr; /* LBC Clock Ratio */
+#ifdef CONFIG_NAND_FSL_ELBC
+ u8 res9[0x8];
+ u32 fmr; /* Flash Mode Register */
+ u32 fir; /* Flash Instruction Register */
+ u32 fcr; /* Flash Command Register */
+ u32 fbar; /* Flash Block Addr Register */
+ u32 fpar; /* Flash Page Addr Register */
+ u32 fbcr; /* Flash Byte Count Register */
+ u8 res10[0xF08];
+#else
+ u8 res9[0xF28];
+#endif
+} fsl_lbc_t;
+
#endif /* __ASSEMBLY__ */
-
#endif /* __ASM_PPC_FSL_LBC_H */
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index db61e7e..dc5c579 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -29,8 +29,8 @@
int fsl_is_pci_agent(struct pci_controller *hose);
void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
void fsl_pci_config_unlock(struct pci_controller *hose);
-void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
+void ft_fsl_pci_setup(void *blob, const char *pci_compat,
+ struct pci_controller *hose, unsigned long ctrl_addr);
/*
* Common PCI/PCIE Register structure for mpc85xx and mpc86xx
@@ -162,14 +162,15 @@
} ccsr_fsl_pci_t;
struct fsl_pci_info {
- unsigned long regs;
- pci_addr_t mem_bus;
- phys_size_t mem_phys;
- pci_size_t mem_size;
- pci_addr_t io_bus;
- phys_size_t io_phys;
- pci_size_t io_size;
- int pci_num;
+ unsigned long regs;
+ pci_addr_t mem_bus;
+ phys_size_t mem_phys;
+ pci_size_t mem_size;
+ pci_addr_t io_bus;
+ phys_size_t io_phys;
+ pci_size_t io_size;
+ enum law_trgt_if law;
+ int pci_num;
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
@@ -184,6 +185,7 @@
x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
+ x.law = LAW_TRGT_IF_PCI_##num; \
x.pci_num = num; \
}
@@ -196,7 +198,86 @@
x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+ x.law = LAW_TRGT_IF_PCIE_##num; \
x.pci_num = num; \
}
+#define __FT_FSL_PCI_SETUP(blob, compat, num) \
+ ft_fsl_pci_setup(blob, compat, &pci##num##_hose, \
+ CONFIG_SYS_PCI##num##_ADDR)
+
+#define __FT_FSL_PCI_DEL(blob, compat, num) \
+ ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCI##num##_ADDR)
+
+#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
+ ft_fsl_pci_setup(blob, compat, &pcie##num##_hose, \
+ CONFIG_SYS_PCIE##num##_ADDR)
+
+#define __FT_FSL_PCIE_DEL(blob, compat, num) \
+ ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCIE##num##_ADDR)
+
+#ifdef CONFIG_PCI1
+#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
+#else
+#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 1)
+#endif
+
+#ifdef CONFIG_PCI2
+#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
+#else
+#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 2)
+#endif
+
+#ifdef CONFIG_PCIE1
+#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
+#else
+#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 1)
+#endif
+
+#ifdef CONFIG_PCIE2
+#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
+#else
+#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 2)
+#endif
+
+#ifdef CONFIG_PCIE3
+#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
+#else
+#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 3)
+#endif
+
+#ifdef CONFIG_PCIE4
+#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
+#else
+#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 4)
+#endif
+
+#if defined(CONFIG_FSL_CORENET)
+#define FSL_PCIE_COMPAT "fsl,p4080-pcie"
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP; \
+ FT_FSL_PCIE4_SETUP;
+#elif defined(CONFIG_MPC85xx)
+#define FSL_PCI_COMPAT "fsl,mpc8540-pci"
+#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCI1_SETUP; \
+ FT_FSL_PCI2_SETUP; \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP;
+#elif defined(CONFIG_MPC86xx)
+#define FSL_PCI_COMPAT "fsl,mpc8610-pci"
+#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCI1_SETUP; \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP;
+#else
+#error FT_FSL_PCI_SETUP not defined
+#endif
+
+
#endif
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index d4839f4..c7877b9 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -44,5 +44,6 @@
};
int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
#endif /* __FSL_SERDES_H */
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index d3dd44e..c854ce9 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -60,7 +60,8 @@
#if defined(CONFIG_MPC83xx)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
@@ -76,7 +77,8 @@
u32 lbiu_clk;
u32 lclk_clk;
u32 pci_clk;
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC837x)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 6b42a73..cc0293a 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -73,7 +73,11 @@
u32 obir; /* Output Buffer Impedance Register */
u8 res8[0xC];
u32 pecr1; /* PCI Express control register 1 */
+#ifdef CONFIG_MPC8308
+ u32 sdhccr; /* eSDHC Control Registers for MPC8308 */
+#else
u32 pecr2; /* PCI Express control register 2 */
+#endif
u8 res9[0xB8];
} sysconf83xx_t;
@@ -589,7 +593,14 @@
* SerDes
*/
typedef struct serdes83xx {
- u8 fixme[0x100];
+ u32 srdscr0;
+ u32 srdscr1;
+ u32 srdscr2;
+ u32 srdscr3;
+ u32 srdscr4;
+ u8 res0[0xc];
+ u32 srdsrstctl;
+ u8 res1[0xdc];
} serdes83xx_t;
/*
@@ -635,7 +646,7 @@
u8 res2[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res3[0x900];
- fsl_lbus_t lbus; /* Local Bus Controller Registers */
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res4[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@@ -675,7 +686,7 @@
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
- fsl_lbus_t lbus; /* Local Bus Controller Registers */
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@@ -691,7 +702,7 @@
u8 res7[0xC0000];
} immap_t;
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@@ -710,7 +721,7 @@
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
- fsl_lbus_t lbus; /* Local Bus Controller Registers */
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@@ -755,7 +766,7 @@
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
- fsl_lbus_t lbus; /* Local Bus Controller Registers */
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@@ -805,7 +816,7 @@
u8 res4[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res5[0x900];
- fsl_lbus_t lbus; /* Local Bus Controller Registers */
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res6[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
@@ -844,7 +855,7 @@
u8 res3[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res4[0x900];
- fsl_lbus_t lbus; /* Local Bus Controller Registers */
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res5[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
@@ -868,6 +879,7 @@
#endif
#define CONFIG_SYS_MPC83xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
+#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 5b205d1..b1d219b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -266,50 +266,6 @@
} ccsr_duart_t;
#endif
-/* Local Bus Controller Registers */
-typedef struct ccsr_lbc {
- u32 br0; /* LBC Base 0 */
- u32 or0; /* LBC Options 0 */
- u32 br1; /* LBC Base 1 */
- u32 or1; /* LBC Options 1 */
- u32 br2; /* LBC Base 2 */
- u32 or2; /* LBC Options 2 */
- u32 br3; /* LBC Base 3 */
- u32 or3; /* LBC Options 3 */
- u32 br4; /* LBC Base 4 */
- u32 or4; /* LBC Options 4 */
- u32 br5; /* LBC Base 5 */
- u32 or5; /* LBC Options 5 */
- u32 br6; /* LBC Base 6 */
- u32 or6; /* LBC Options 6 */
- u32 br7; /* LBC Base 7 */
- u32 or7; /* LBC Options 7 */
- u8 res1[40];
- u32 mar; /* LBC UPM Addr */
- u8 res2[4];
- u32 mamr; /* LBC UPMA Mode */
- u32 mbmr; /* LBC UPMB Mode */
- u32 mcmr; /* LBC UPMC Mode */
- u8 res3[8];
- u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
- u32 mdr; /* LBC UPM Data */
- u8 res4[8];
- u32 lsdmr; /* LBC SDRAM Mode */
- u8 res5[8];
- u32 lurt; /* LBC UPM Refresh Timer */
- u32 lsrt; /* LBC SDRAM Refresh Timer */
- u8 res6[8];
- u32 ltesr; /* LBC Transfer Error Status */
- u32 ltedr; /* LBC Transfer Error Disable */
- u32 lteir; /* LBC Transfer Error IRQ */
- u32 lteatr; /* LBC Transfer Error Attrs */
- u32 ltear; /* LBC Transfer Error Addr */
- u8 res7[12];
- u32 lbcr; /* LBC Configuration */
- u32 lcrr; /* LBC Clock Ratio */
- u8 res8[3880];
-} ccsr_lbc_t;
-
/* eSPI Registers */
typedef struct ccsr_espi {
u32 mode; /* eSPI mode */
@@ -2045,6 +2001,41 @@
FSL_SRDS_B3_LANE_D = 23,
};
+/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+typedef struct ccsr_sec {
+ u8 res1[0xfa0];
+ u32 crnr_ms; /* CHA Revision Number Register, MS */
+ u32 crnr_ls; /* CHA Revision Number Register, LS */
+ u32 ctpr_ms; /* Compile Time Parameters Register, MS */
+#define SEC_CTPR_MS_AXI_LIODN 0x08000000
+#define SEC_CTPR_MS_QI 0x02000000
+ u32 ctpr_ls; /* Compile Time Parameters Register, LS */
+ u8 res2[0x10];
+ u32 far_ms; /* Fault Address Register, MS */
+ u32 far_ls; /* Fault Address Register, LS */
+ u32 falr; /* Fault Address LIODN Register */
+ u32 fadr; /* Fault Address Detail Register */
+ u8 res3[0x4];
+ u32 csta; /* CAAM Status Register */
+ u8 res4[0x8];
+ u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
+#define SEC_RVID_MA 0x0f000000
+ u32 ccbvid; /* CHA Cluster Block Version ID Register */
+ u32 chavid_ms; /* CHA Version ID Register, MS */
+ u32 chavid_ls; /* CHA Version ID Register, LS */
+ u32 chanum_ms; /* CHA Number Register, MS */
+#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000
+#define SEC_CHANUM_MS_JQNUM_SHIFT 28
+#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
+#define SEC_CHANUM_MS_DECONUM_SHIFT 24
+ u32 chanum_ls; /* CHA Number Register, LS */
+ u32 caamvid_ms; /* CAAM Version ID Register, MS */
+ u32 caamvid_ls; /* CAAM Version ID Register, LS */
+ u8 res5[0xf000];
+} ccsr_sec_t;
+#endif
+
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
@@ -2059,6 +2050,7 @@
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
#define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */
@@ -2068,8 +2060,17 @@
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
+#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
+#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
+#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
+#else
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
+#endif
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
@@ -2111,7 +2112,7 @@
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC85xx_LBC_ADDR \
+#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
@@ -2143,6 +2144,19 @@
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CONFIG_SYS_MPC85xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
+#define CONFIG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+
+#define CONFIG_SYS_PCI1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
+#define CONFIG_SYS_PCI2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
+#define CONFIG_SYS_PCIE1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
+#define CONFIG_SYS_PCIE2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
+#define CONFIG_SYS_PCIE3_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index fd7acdb..4bebb68 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -12,6 +12,7 @@
#include <asm/types.h>
#include <asm/fsl_dma.h>
+#include <asm/fsl_lbc.h>
#include <asm/fsl_i2c.h>
/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
@@ -190,51 +191,6 @@
char res5[2543];
} ccsr_duart_t;
-
-/* Local Bus Controller Registers(0x5000-0x6000) */
-typedef struct ccsr_lbc {
- uint br0; /* 0x5000 - LBC Base Register 0 */
- uint or0; /* 0x5004 - LBC Options Register 0 */
- uint br1; /* 0x5008 - LBC Base Register 1 */
- uint or1; /* 0x500c - LBC Options Register 1 */
- uint br2; /* 0x5010 - LBC Base Register 2 */
- uint or2; /* 0x5014 - LBC Options Register 2 */
- uint br3; /* 0x5018 - LBC Base Register 3 */
- uint or3; /* 0x501c - LBC Options Register 3 */
- uint br4; /* 0x5020 - LBC Base Register 4 */
- uint or4; /* 0x5024 - LBC Options Register 4 */
- uint br5; /* 0x5028 - LBC Base Register 5 */
- uint or5; /* 0x502c - LBC Options Register 5 */
- uint br6; /* 0x5030 - LBC Base Register 6 */
- uint or6; /* 0x5034 - LBC Options Register 6 */
- uint br7; /* 0x5038 - LBC Base Register 7 */
- uint or7; /* 0x503c - LBC Options Register 7 */
- char res1[40];
- uint mar; /* 0x5068 - LBC UPM Address Register */
- char res2[4];
- uint mamr; /* 0x5070 - LBC UPMA Mode Register */
- uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
- uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
- char res3[8];
- uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
- uint mdr; /* 0x5088 - LBC UPM Data Register */
- char res4[8];
- uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
- char res5[8];
- uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
- uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
- char res6[8];
- uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
- uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
- uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
- uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
- uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
- char res7[12];
- uint lbcr; /* 0x50d0 - LBC Configuration Register */
- uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
- char res8[3880];
-} ccsr_lbc_t;
-
/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
typedef struct ccsr_pex {
uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
@@ -1270,7 +1226,7 @@
ccsr_ddr_t im_ddr1;
ccsr_i2c_t im_i2c;
ccsr_duart_t im_duart;
- ccsr_lbc_t im_lbc;
+ fsl_lbc_t im_lbc;
ccsr_ddr_t im_ddr2;
char res1[4096];
ccsr_pex_t im_pex1;
@@ -1301,8 +1257,26 @@
#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000)
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
+#ifdef CONFIG_MPC8610
+#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000
+#else
+#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000
+#endif
+#define CONFIG_SYS_MPC86xx_PCIE2_OFFSET 0x9000
+
+#define CONFIG_SYS_PCI1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET)
+#define CONFIG_SYS_PCI2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET)
+#define CONFIG_SYS_PCIE1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET)
+#define CONFIG_SYS_PCIE2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET)
+
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
+#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 5166507..c01c85f 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -402,6 +402,7 @@
#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
#define MAS1_TS 0x00001000
#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
+#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10)))
#define MAS2_EPN 0xFFFFF000
#define MAS2_X0 0x00000040
@@ -485,6 +486,7 @@
extern int find_tlb_idx(void *addr, u8 tlbsel);
extern void init_used_tlb_cams(void);
extern int find_free_tlbcam(void);
+extern void print_tlbcam(void);
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h
index 5388c95..3ffa30b 100644
--- a/arch/powerpc/include/asm/mp.h
+++ b/arch/powerpc/include/asm/mp.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -26,5 +26,6 @@
void setup_mp(void);
void cpu_mp_lmb_reserve(struct lmb *lmb);
u32 determine_mp_bootpg(void);
+int is_core_disabled(int nr);
#endif
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 41737d3..b0082af 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -27,9 +27,10 @@
#include <asm/types.h>
-#if defined(CONFIG_MPC834x) || \
+#if defined(CONFIG_MPC8308) || \
defined(CONFIG_MPC8313) || \
defined(CONFIG_MPC8315) || \
+ defined(CONFIG_MPC834x) || \
defined(CONFIG_MPC837x)
typedef struct spi8xxx {
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index d9506e2..4ec1ef8 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -63,6 +63,8 @@
#define SDRAM_CFG0 0x20 /* memory controller options 0 */
#define SDRAM_CFG1 0x21 /* memory controller options 1 */
+#define SDRAM0_BESR0 0x0000 /* bus error status reg 0 */
+#define SDRAM0_BESR1 0x0008 /* bus error status reg 1 */
#define SDRAM0_BEAR 0x0010 /* bus error address reg */
#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */
@@ -363,6 +365,7 @@
/*
* Memory controller registers
*/
+#ifdef CONFIG_405EX
#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
#define SDRAM_BEARL 0x02 /* PLB bus error address low */
@@ -371,11 +374,10 @@
#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */
#define SDRAM_PLBOPT 0x08 /* PLB slave options */
#define SDRAM_PUABA 0x09 /* PLB upper address base */
-#ifndef CONFIG_405EX
-#define SDRAM_MCSTAT 0x14 /* memory controller status */
-#else
#define SDRAM_MCSTAT 0x1F /* memory controller status */
-#endif
+#else /* CONFIG_405EX */
+#define SDRAM_MCSTAT 0x14 /* memory controller status */
+#endif /* CONFIG_405EX */
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 9ec319a..89f283a 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -534,9 +534,11 @@
#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
+#define BUCSR_STAC_EN 0x01000000 /* Segment target addr cache enable */
+#define BUCSR_LS_EN 0x00400000 /* Link stack enable */
#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */
#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
-#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN)
+#define BUCSR_ENABLE (BUCSR_STAC_EN|BUCSR_LS_EN|BUCSR_BBFI|BUCSR_BPEN)
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
#define SPRN_PID1 0x279 /* Process ID Register 1 */
@@ -1050,10 +1052,16 @@
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
#define SVR_P2020_E 0x80EA00
+#define SVR_P3041 0x821103
+#define SVR_P3041_E 0x821903
#define SVR_P4040 0x820100
#define SVR_P4040_E 0x820900
#define SVR_P4080 0x820000
#define SVR_P4080_E 0x820800
+#define SVR_P5010 0x822100
+#define SVR_P5010_E 0x822900
+#define SVR_P5020 0x822000
+#define SVR_P5020_E 0x822800
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
index 54c0ffe..bb388ed 100644
--- a/board/LaCie/edminiv2/edminiv2.c
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <miiphy.h>
#include <asm/arch/orion5x.h>
+#include "edminiv2.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -90,3 +91,38 @@
return 0;
}
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h
new file mode 100644
index 0000000..88e62b2
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EDMINIV2_BASE_H
+#define __EDMINIV2_BASE_H
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __EDMINIV2_BASE_H */
diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c
index 4652672..3c37557 100644
--- a/board/afeb9260/afeb9260.c
+++ b/board/afeb9260/afeb9260.c
@@ -167,13 +167,6 @@
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
-#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init(gd->bd);
-#endif
}
#endif
diff --git a/board/altera/ep1c20/ep1c20.c b/board/altera/ep1c20/ep1c20.c
deleted file mode 100644
index 82900f7..0000000
--- a/board/altera/ep1c20/ep1c20.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- puts ("BOARD : Altera EP-1C20\n");
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/altera/ep1s10/Makefile b/board/altera/ep1s10/Makefile
deleted file mode 100644
index acad2aa..0000000
--- a/board/altera/ep1s10/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).a
-
-COMOBJS := ../common/AMDLV065D.o ../common/epled.o
-
-COBJS := $(BOARD).o $(COMOBJS)
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/altera/ep1s10/config.mk b/board/altera/ep1s10/config.mk
deleted file mode 100644
index dab2740..0000000
--- a/board/altera/ep1s10/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
-# Scott McNutt <smcnutt@psyent.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0x01fc0000
-
-PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/altera/ep1s10/ep1s10.c b/board/altera/ep1s10/ep1s10.c
deleted file mode 100644
index cf886da..0000000
--- a/board/altera/ep1s10/ep1s10.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- puts ("BOARD : Altera EP-1S10\n");
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/altera/ep1s40/Makefile b/board/altera/ep1s40/Makefile
deleted file mode 100644
index acad2aa..0000000
--- a/board/altera/ep1s40/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).a
-
-COMOBJS := ../common/AMDLV065D.o ../common/epled.o
-
-COBJS := $(BOARD).o $(COMOBJS)
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/altera/ep1s40/config.mk b/board/altera/ep1s40/config.mk
deleted file mode 100644
index dab2740..0000000
--- a/board/altera/ep1s40/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
-# Scott McNutt <smcnutt@psyent.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0x01fc0000
-
-PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h
index 761f605..a11add5 100644
--- a/board/altera/nios2-generic/custom_fpga.h
+++ b/board/altera/nios2-generic/custom_fpga.h
@@ -35,6 +35,16 @@
#define CONFIG_SMC91111
#define CONFIG_SMC_USE_32_BIT
+/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */
+#define EPCS_CONTROLLER_REG_BASE 0x82100200
+#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE }
+#define CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
diff --git a/board/altera/nios2-generic/gpio.c b/board/altera/nios2-generic/gpio.c
index 6c9c6c2..d449684 100644
--- a/board/altera/nios2-generic/gpio.c
+++ b/board/altera/nios2-generic/gpio.c
@@ -15,6 +15,11 @@
static u32 pio_data_reg;
static u32 pio_dir_reg;
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
int gpio_direction_input(unsigned gpio)
{
u32 mask = 1 << gpio;
diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c
index 86f86e2..6936e51 100644
--- a/board/amcc/acadia/cmd_acadia.c
+++ b/board/amcc/acadia/cmd_acadia.c
@@ -44,10 +44,8 @@
u8 *buf;
int cpu_freq;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
cpu_freq = simple_strtol(argv[1], NULL, 10);
if (cpu_freq != 267) {
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 23874d2..158f7bb 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -34,7 +34,17 @@
DECLARE_GLOBAL_DATA_PTR;
-#define CONFIG_SYS_BCSR3_PCIE 0x10
+ struct board_bcsr {
+ u8 board_id;
+ u8 cpld_rev;
+ u8 led_user;
+ u8 board_status;
+ u8 reset_ctrl;
+ u8 flash_ctrl;
+ u8 eth_ctrl;
+ u8 usb_ctrl;
+ u8 irq_ctrl;
+};
#define BOARD_CANYONLANDS_PCIE 1
#define BOARD_CANYONLANDS_SATA 2
@@ -112,6 +122,9 @@
{
#if !defined(CONFIG_ARCHES)
u32 sdr0_cust0;
+ struct board_bcsr *bcsr_data =
+ (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+
#endif
/*
@@ -172,14 +185,10 @@
#if !defined(CONFIG_ARCHES)
/* Enable ethernet and take out of reset */
- out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
+ out_8(&bcsr_data->eth_ctrl, 0) ;
/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
- out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
-
- /* Enable USB host & USB-OTG */
- out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
-
+ out_8(&bcsr_data->flash_ctrl, 0) ;
mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
/* Setup PLB4-AHB bridge based on the system address map */
@@ -201,6 +210,41 @@
return 0;
}
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int usb_board_init(void)
+{
+ struct board_bcsr *bcsr_data =
+ (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+ u8 val;
+
+ /* Enable USB host & USB-OTG */
+ val = in_8(&bcsr_data->usb_ctrl);
+ val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+ out_8(&bcsr_data->usb_ctrl, val);
+
+ return 0;
+}
+
+int usb_board_stop(void)
+{
+ struct board_bcsr *bcsr_data =
+ (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+ u8 val;
+
+ /* Disable USB host & USB-OTG */
+ val = in_8(&bcsr_data->usb_ctrl);
+ val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+ out_8(&bcsr_data->usb_ctrl, val);
+
+ return 0;
+}
+
+int usb_board_init_fail(void)
+{
+ return usb_board_stop();
+}
+#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
+
#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
@@ -244,11 +288,13 @@
#if !defined(CONFIG_ARCHES)
int checkboard(void)
{
+ struct board_bcsr *bcsr_data =
+ (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
char *s = getenv("serial#");
if (pvr_460ex()) {
printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
- if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
+ if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
gd->board_type = BOARD_CANYONLANDS_PCIE;
else
gd->board_type = BOARD_CANYONLANDS_SATA;
@@ -268,7 +314,7 @@
break;
}
- printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
+ printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
if (s != NULL) {
puts(", serial# ");
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index c0368c0..c09d730 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -223,8 +223,7 @@
l2cache_status() ? "ON" : "OFF");
return 0;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return 0;
diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c
index 3c0dc5f..7f75ad7 100644
--- a/board/amcc/makalu/cmd_pll.c
+++ b/board/amcc/makalu/cmd_pll.c
@@ -182,14 +182,14 @@
{
char c = '\0';
pll_freq_t pll_freq;
- if (argc < 2) {
- cmd_usage(cmdtp);
- goto ret;
- }
- for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++)
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) {
if (!strcmp(pll_name[pll_freq], argv[1]))
break;
+ }
switch (pll_freq) {
case PLL_ebc20:
@@ -223,8 +223,7 @@
default:
printf("Invalid options\n\n");
- cmd_usage(cmdtp);
- goto ret;
+ return cmd_usage(cmdtp);
}
printf("PLL set to %s, "
diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c
index 595dee3..9b2afda 100644
--- a/board/amcc/taihu/lcd.c
+++ b/board/amcc/taihu/lcd.c
@@ -139,10 +139,9 @@
static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
lcd_puts(argv[1]);
return 0;
@@ -150,10 +149,9 @@
static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
lcd_putc((char)argv[1][0]);
return 0;
@@ -165,10 +163,8 @@
ulong dir;
char cur_addr;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
count = simple_strtoul(argv[1], NULL, 16);
if (count > 31) {
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
index 1682cf7..dd2aba5 100644
--- a/board/amcc/taihu/taihu.c
+++ b/board/amcc/taihu/taihu.c
@@ -101,16 +101,12 @@
{
int led_no;
- if (argc != 3) {
- cmd_usage(cmd_tp);
- return -1;
- }
+ if (argc != 3)
+ return cmd_usage(cmd_tp);
led_no = simple_strtoul(argv[1], NULL, 16);
- if (led_no != 1 && led_no != 2) {
- cmd_usage(cmd_tp);
- return -1;
- }
+ if (led_no != 1 && led_no != 2)
+ return cmd_usage(cmd_tp);
if (strcmp(argv[2],"off") == 0x0) {
if (led_no == 1)
@@ -123,8 +119,7 @@
else
gpio_write_bit(31, 0);
} else {
- cmd_usage(cmd_tp);
- return -1;
+ return cmd_usage(cmd_tp);
}
return 0;
diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c
index 6a049df..7f7730a 100644
--- a/board/amcc/taishan/lcd.c
+++ b/board/amcc/taishan/lcd.c
@@ -166,19 +166,17 @@
}
static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
lcd_puts(argv[1]);
return 0;
}
static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
lcd_putc((char)argv[1][0]);
return 0;
}
@@ -188,10 +186,8 @@
ulong dir;
char cur_addr;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
count = simple_strtoul(argv[1], NULL, 16);
if (count > 31) {
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
index cde13e4..e9cd333 100644
--- a/board/amcc/yucca/cmd_yucca.c
+++ b/board/amcc/yucca/cmd_yucca.c
@@ -58,10 +58,8 @@
char plbClock[4];
char pcixClock[4];
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
if (strcmp(argv[2], "prom0") == 0)
chip = IIC0_BOOTPROM_ADDR;
diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c
index 258d1ea..2ab8bc2 100644
--- a/board/atmel/at91cap9adk/at91cap9adk.c
+++ b/board/atmel/at91cap9adk/at91cap9adk.c
@@ -339,13 +339,6 @@
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
-#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init(gd->bd);
-#endif
}
#endif
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index ed47360..64c6d17 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -179,13 +179,6 @@
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
-#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init(gd->bd);
-#endif
}
#endif
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 5cd7aa7..91efc07 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -284,13 +284,6 @@
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
-#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init(gd->bd);
-#endif
}
#endif
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 8fa0449..f92b20f 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -291,13 +291,6 @@
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
-#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init(gd->bd);
-#endif
}
#endif
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c
index c11a5c3..671f9e9 100644
--- a/board/atum8548/atum8548.c
+++ b/board/atum8548/atum8548.c
@@ -47,7 +47,7 @@
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
if ((uint)&gur->porpllsr != 0xe00e0000) {
@@ -292,14 +292,6 @@
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCI2
- ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
}
#endif
diff --git a/board/barco/barco.c b/board/barco/barco.c
index b8d968b..6ce3480 100644
--- a/board/barco/barco.c
+++ b/board/barco/barco.c
@@ -290,12 +290,6 @@
int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
-#if 0
- if (argc > 1) {
- cmd_usage(cmdtp);
- return 1;
- }
-#endif
barcobcd_boot ();
return 0;
diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c
index 85b350f..ff1ac4c 100644
--- a/board/bf518f-ezbrd/bf518f-ezbrd.c
+++ b/board/bf518f-ezbrd/bf518f-ezbrd.c
@@ -14,6 +14,7 @@
#include <spi.h>
#include <asm/blackfin.h>
#include <asm/net.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/otp.h>
#include <asm/sdh.h>
@@ -61,6 +62,7 @@
#define KSZ_WRITE 0x02
#define KSZ_READ 0x03
+#define KSZ_REG_CHID 0x00 /* Register 0: Chip ID0 */
#define KSZ_REG_STPID 0x01 /* Register 1: Chip ID1 / Start Switch */
#define KSZ_REG_GC9 0x0b /* Register 11: Global Control 9 */
#define KSZ_REG_P3C0 0x30 /* Register 48: Port 3 Control 0 */
@@ -78,15 +80,17 @@
return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din);
}
+static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg)
+{
+ int ret;
+ unsigned char din[3];
+ ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
+ return ret ? ret : din[2];
+}
+
static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
{
- int ret = 0;
- unsigned char din[3];
-
- ret |= ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
- ret |= ksz8893m_reg_set(slave, reg, din[2] & mask);
-
- return ret;
+ return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask);
}
static int ksz8893m_reset(struct spi_slave *slave)
@@ -107,16 +111,16 @@
int board_eth_init(bd_t *bis)
{
- static bool switch_is_alive = false;
+ static bool switch_is_alive = false, phy_is_ksz = true;
int ret;
if (!switch_is_alive) {
struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3);
if (slave) {
if (!spi_claim_bus(slave)) {
- ret = ksz8893m_reset(slave);
- if (!ret)
- switch_is_alive = true;
+ phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88);
+ ret = phy_is_ksz ? ksz8893m_reset(slave) : 0;
+ switch_is_alive = (ret == 0);
spi_release_bus(slave);
}
spi_free_slave(slave);
@@ -143,18 +147,11 @@
int board_early_init_f(void)
{
-#if !defined(CONFIG_SYS_NO_FLASH)
- /* setup BF518-EZBRD GPIO pin PG11 to AMS2. */
- bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2);
- bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG11);
-
-# if !defined(CONFIG_BFIN_SPI)
- /* setup BF518-EZBRD GPIO pin PG15 to AMS3. */
- bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_3);
- bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG15);
-# endif
-#endif
- return 0;
+ /* connect async banks by default */
+ const unsigned short pins[] = {
+ P_AMS2, P_AMS3, 0,
+ };
+ return peripheral_request_list(pins, "async");
}
#ifdef CONFIG_BFIN_SDH
diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile
index a9ff760..f2bd2c2 100644
--- a/board/bf526-ezbrd/Makefile
+++ b/board/bf526-ezbrd/Makefile
@@ -30,7 +30,6 @@
LIB = $(obj)lib$(BOARD).a
COBJS-y := $(BOARD).o
-COBJS-$(CONFIG_STATUS_LED) += status-led.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/bf526-ezbrd/status-led.c b/board/bf526-ezbrd/status-led.c
deleted file mode 100644
index 6327022..0000000
--- a/board/bf526-ezbrd/status-led.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * U-boot - status leds
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <status_led.h>
-
-static void set_led_f(int pf, int state)
-{
- switch (state) {
- case STATUS_LED_OFF: bfin_write_PORTFIO_CLEAR(pf); break;
- case STATUS_LED_BLINKING: bfin_write_PORTFIO_TOGGLE(pf); break;
- case STATUS_LED_ON: bfin_write_PORTFIO_SET(pf); break;
- }
-}
-static void set_led_g(int pf, int state)
-{
- switch (state) {
- case STATUS_LED_OFF: bfin_write_PORTGIO_CLEAR(pf); break;
- case STATUS_LED_BLINKING: bfin_write_PORTGIO_TOGGLE(pf); break;
- case STATUS_LED_ON: bfin_write_PORTGIO_SET(pf); break;
- }
-}
-
-static void set_leds(led_id_t mask, int state)
-{
- if (mask & 0x1) set_led_f(PF8, state);
- if (mask & 0x2) set_led_g(PG11, state);
- if (mask & 0x4) set_led_g(PG12, state);
-}
-
-void __led_init(led_id_t mask, int state)
-{
- bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~(PF8));
- bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~(PG11 | PG12));
- bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() & ~(PF8));
- bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() & ~(PG11 | PG12));
- bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (PF8));
- bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (PG11 | PG12));
-}
-
-void __led_set(led_id_t mask, int state)
-{
- set_leds(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
- set_leds(mask, STATUS_LED_BLINKING);
-}
diff --git a/board/altera/ep1c20/Makefile b/board/bf527-ad7160-eval/Makefile
similarity index 77%
copy from board/altera/ep1c20/Makefile
copy to board/bf527-ad7160-eval/Makefile
index acad2aa..f2bd2c2 100644
--- a/board/altera/ep1c20/Makefile
+++ b/board/bf527-ad7160-eval/Makefile
@@ -1,5 +1,9 @@
#
-# (C) Copyright 2001-2006
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -22,22 +26,17 @@
#
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
LIB = $(obj)lib$(BOARD).a
-COMOBJS := ../common/AMDLV065D.o ../common/epled.o
+COBJS-y := $(BOARD).o
-COBJS := $(BOARD).o $(COMOBJS)
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c
new file mode 100644
index 0000000..b06d5ab
--- /dev/null
+++ b/board/bf527-ad7160-eval/bf527-ad7160-eval.c
@@ -0,0 +1,25 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/pll.h>
+
+int checkboard(void)
+{
+ printf("Board: ADI BF527 AD7160-EVAL board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ /* CLKIN Buffer Output Enable */
+ *pVR_CTL |= CLKBUFOE;
+ return 0;
+}
diff --git a/board/gth/config.mk b/board/bf527-ad7160-eval/config.mk
similarity index 73%
rename from board/gth/config.mk
rename to board/bf527-ad7160-eval/config.mk
index 3c80156..f85bef5 100644
--- a/board/gth/config.mk
+++ b/board/bf527-ad7160-eval/config.mk
@@ -1,5 +1,7 @@
#
-# (C) Copyright 2000, 2001
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -21,20 +23,11 @@
# MA 02111-1307 USA
#
-#
-ifeq ($(TBASE),0)
-TEXT_BASE = 0
-else
-ifeq ($(TBASE),1)
-TEXT_BASE = 0x80010070
-else
-ifeq ($(TBASE),2)
-TEXT_BASE = 0x80030070
-else
-## Only to make ordinary make work
-TEXT_BASE = 0x90000000
-endif
-endif
-endif
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
-OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
+CFLAGS_lib_generic += -O2
+CFLAGS_lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c
index a911880..211cf24 100644
--- a/board/bf527-ezkit/bf527-ezkit.c
+++ b/board/bf527-ezkit/bf527-ezkit.c
@@ -12,6 +12,7 @@
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
@@ -75,9 +76,7 @@
/*
* BF527 EZ-KITs require PG13 to be high for HOST mode
*/
- bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~PG13);
- bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | PG13);
- bfin_write_PORTGIO_SET(PG13);
- SSYNC();
+ gpio_request(GPIO_PG13, "musb-vbus");
+ gpio_direction_output(GPIO_PG13, 1);
}
#endif
diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c
index 8f6ea23..891070b 100644
--- a/board/bf527-ezkit/video.c
+++ b/board/bf527-ezkit/video.c
@@ -11,6 +11,7 @@
#include <config.h>
#include <malloc.h>
#include <asm/blackfin.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <spi.h>
#include <linux/types.h>
@@ -171,13 +172,11 @@
void Init_Ports(void)
{
- *pPORTF_MUX &= ~PORT_x_MUX_0_MASK;
- *pPORTF_MUX |= PORT_x_MUX_0_FUNC_1;
- *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7;
-
- *pPORTG_MUX &= ~PORT_x_MUX_1_MASK;
- *pPORTG_MUX |= PORT_x_MUX_1_FUNC_1;
- *pPORTG_FER |= PG5;
+ const unsigned short pins[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+ P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
+ };
+ peripheral_request_list(pins, "lcd");
}
void Init_PPI(void)
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index 4abad08..935aad2 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -27,8 +27,7 @@
#include <common.h>
#include <netdev.h>
-#include <asm/io.h>
-#include "bf533-stamp.h"
+#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -46,15 +45,10 @@
*/
void swap_to(int device_id)
{
- bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0);
- SSYNC();
- bfin_write_FIO_FLAG_C(PF1);
- if (device_id == ETHERNET)
- bfin_write_FIO_FLAG_S(PF0);
- else if (device_id == FLASH)
- bfin_write_FIO_FLAG_C(PF0);
- else
- printf("Unknown device to switch\n");
+ gpio_request(GPIO_PF0, "eth_flash_swap");
+ gpio_request(GPIO_PF1, "eth_flash_swap");
+ gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
+ gpio_direction_output(GPIO_PF1, 0);
SSYNC();
}
@@ -75,24 +69,23 @@
#define STATUS_LED_OFF 0
#define STATUS_LED_ON 1
+static int gpio_setup;
+
static void stamp_led_set(int LED1, int LED2, int LED3)
{
- bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4));
- bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4));
-
- if (LED1 == STATUS_LED_OFF)
- *pFIO_FLAG_S = PF2;
- else
- *pFIO_FLAG_C = PF2;
- if (LED2 == STATUS_LED_OFF)
- *pFIO_FLAG_S = PF3;
- else
- *pFIO_FLAG_C = PF3;
- if (LED3 == STATUS_LED_OFF)
- *pFIO_FLAG_S = PF4;
- else
- *pFIO_FLAG_C = PF4;
- SSYNC();
+ if (!gpio_setup) {
+ gpio_request(GPIO_PF2, "boot_progress");
+ gpio_request(GPIO_PF3, "boot_progress");
+ gpio_request(GPIO_PF4, "boot_progress");
+ gpio_direction_output(GPIO_PF2, LED1);
+ gpio_direction_output(GPIO_PF3, LED2);
+ gpio_direction_output(GPIO_PF4, LED3);
+ gpio_setup = 1;
+ } else {
+ gpio_set_value(GPIO_PF2, LED1);
+ gpio_set_value(GPIO_PF3, LED2);
+ gpio_set_value(GPIO_PF4, LED3);
+ }
}
void show_boot_progress(int status)
@@ -134,43 +127,6 @@
}
#endif
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-
-static void set_led(int pf, int state)
-{
- switch (state) {
- case STATUS_LED_OFF: bfin_write_FIO_FLAG_S(pf); break;
- case STATUS_LED_BLINKING: bfin_write_FIO_FLAG_T(pf); break;
- case STATUS_LED_ON: bfin_write_FIO_FLAG_C(pf); break;
- }
-}
-
-static void set_leds(led_id_t mask, int state)
-{
- if (mask & 0x1) set_led(PF2, state);
- if (mask & 0x2) set_led(PF3, state);
- if (mask & 0x4) set_led(PF4, state);
-}
-
-void __led_init(led_id_t mask, int state)
-{
- bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4));
- bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4));
-}
-
-void __led_set(led_id_t mask, int state)
-{
- set_leds(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
- set_leds(mask, STATUS_LED_BLINKING);
-}
-
-#endif
-
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{
diff --git a/board/bf533-stamp/bf533-stamp.h b/board/bf533-stamp/bf533-stamp.h
deleted file mode 100644
index ebd39c7..0000000
--- a/board/bf533-stamp/bf533-stamp.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * U-boot - stamp.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __STAMP_H__
-#define __STAMP_H__
-
-extern void init_Flags(void);
-
-extern volatile unsigned long *ambctl0;
-extern volatile unsigned long *ambctl1;
-extern volatile unsigned long *amgctl;
-
-/* Definitions used in Compact Flash Boot support */
-#define FIO_EDGE_CF_BITS 0x0000
-#define FIO_POLAR_CF_BITS 0x0000
-#define FIO_EDGE_BITS 0x1E0
-#define FIO_POLAR_BITS 0x160
-
-/* Compact flash status bits in status register */
-#define CF_STAT_BITS 0x00000060
-
-/* CF Flags used to switch between expansion and external
- * memory banks
- */
-#define CF_PF0 0x0001
-#define CF_PF1 0x0002
-#define CF_PF1_PF0 0x0003
-
-#endif
diff --git a/board/bf533-stamp/ide-cf.c b/board/bf533-stamp/ide-cf.c
index 23e786b..3e4080e 100644
--- a/board/bf533-stamp/ide-cf.c
+++ b/board/bf533-stamp/ide-cf.c
@@ -11,7 +11,6 @@
#include <common.h>
#include <config.h>
#include <asm/blackfin.h>
-#include "bf533-stamp.h"
void cf_outb(unsigned char val, volatile unsigned char *addr)
{
@@ -66,6 +65,15 @@
swap_to(FLASH);
}
+/* Definitions used in Compact Flash Boot support */
+#define FIO_EDGE_CF_BITS 0x0000
+#define FIO_POLAR_CF_BITS 0x0000
+#define FIO_EDGE_BITS 0x1E0
+#define FIO_POLAR_BITS 0x160
+
+/* Compact flash status bits in status register */
+#define CF_STAT_BITS 0x00000060
+
void cf_ide_init(void)
{
int i, cf_stat;
diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
index f728e2c..4f8985b 100644
--- a/board/bf537-stamp/Makefile
+++ b/board/bf537-stamp/Makefile
@@ -29,9 +29,8 @@
LIB = $(obj)lib$(BOARD).a
-COBJS-y := $(BOARD).o cmd_bf537led.o
+COBJS-y := $(BOARD).o
COBJS-$(CONFIG_BFIN_IDE) += ide-cf.o
-COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
COBJS-$(CONFIG_POST) += post.o post-memory.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c
index 3911be6..ec888d4 100644
--- a/board/bf537-stamp/bf537-stamp.c
+++ b/board/bf537-stamp/bf537-stamp.c
@@ -46,11 +46,8 @@
void board_reset(void)
{
/* workaround for weak pull ups on ssel */
- if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
- bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
- bfin_write_PORTFIO_SET(PF10);
- udelay(1);
- }
+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+ bfin_reset_boot_spi_cs(GPIO_PF10);
}
#ifdef CONFIG_BFIN_MAC
diff --git a/board/bf537-stamp/cmd_bf537led.c b/board/bf537-stamp/cmd_bf537led.c
deleted file mode 100644
index 7d8f3ea..0000000
--- a/board/bf537-stamp/cmd_bf537led.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * U-boot - cmd_bf537led.c
- *
- * Copyright (C) 2006 Aaron Gage, Ocean Optics Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/string.h>
-#ifdef CONFIG_BF537_STAMP_LEDCMD
-
-/* Define the command usage in a reusable way */
-#define USAGE_LONG \
- "led <number> <action>\n" \
- " <number> - Index (0-5) of LED to change, or \"all\"\n" \
- " <action> - Must be one of:\n" \
- " on off toggle"
-
-/* Number of LEDs supported by the board */
-#define NUMBER_LEDS 6
-/* The BF537 stamp has 6 LEDs. This mask indicates that all should be lit. */
-#define LED_ALL_MASK 0x003F
-
-void show_cmd_usage(void);
-void set_led_state(int index, int state);
-void configure_GPIO_to_output(int index);
-
-/* Map of LEDs according to their GPIO ports. This can be rearranged or
- * otherwise changed to account for different GPIO configurations.
- */
-int led_ports[] = { PF6, PF7, PF8, PF9, PF10, PF11 };
-
-#define ACTION_TOGGLE -1
-#define ACTION_OFF 0
-#define ACTION_ON 1
-
-#define LED_STATE_OFF 0
-#define LED_STATE_ON 1
-
-/* This is a trivial atoi implementation since we don't have one available */
-int atoi(char *string)
-{
- int length;
- int retval = 0;
- int i;
- int sign = 1;
-
- length = strlen(string);
- for (i = 0; i < length; i++) {
- if (0 == i && string[0] == '-') {
- sign = -1;
- continue;
- }
- if (string[i] > '9' || string[i] < '0') {
- break;
- }
- retval *= 10;
- retval += string[i] - '0';
- }
- retval *= sign;
- return retval;
-}
-
-int do_bf537led(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- int led_mask = 0;
- int led_current_state = 0;
- int action = ACTION_OFF;
- int temp;
-
- if (3 != argc) {
- /* Not enough arguments, so just show usage information */
- show_cmd_usage();
- return 1;
- }
-
- if (strcmp(argv[1], "all") == 0) {
- led_mask = LED_ALL_MASK;
- } else {
- temp = atoi(argv[1]);
- if (temp < 0 || temp >= NUMBER_LEDS) {
- printf("Invalid LED number [%s]\n", argv[1]);
- show_cmd_usage();
- return 2;
- }
- led_mask |= (1 << temp);
- }
-
- if (strcmp(argv[2], "off") == 0) {
- action = ACTION_OFF;
- } else if (strcmp(argv[2], "on") == 0) {
- action = ACTION_ON;
- } else if (strcmp(argv[2], "toggle") == 0) {
- action = ACTION_TOGGLE;
- } else {
- printf("Invalid action [%s]\n", argv[2]);
- show_cmd_usage();
- return 3;
- }
-
- for (temp = 0; temp < NUMBER_LEDS; temp++) {
- if ((led_mask & (1 << temp)) > 0) {
- /*
- * It is possible that the user has wired one of PF6-PF11 to
- * something other than an LED, so this will only change a pin
- * to output if the user has indicated a state change. This may
- * happen a lot, but this way is safer than just setting all pins
- * to output.
- */
- configure_GPIO_to_output(temp);
-
- led_current_state =
- ((*pPORTFIO & led_ports[temp]) >
- 0) ? LED_STATE_ON : LED_STATE_OFF;
- /*
- printf("LED state for index %d (%x) is %d\n", temp, led_ports[temp],
- led_current_state);
- printf("*pPORTFIO is %x\n", *pPORTFIO);
- */
- if (ACTION_ON == action
- || (ACTION_TOGGLE == action
- && 0 == led_current_state)) {
- printf("Turning LED %d on\n", temp);
- set_led_state(temp, LED_STATE_ON);
- } else {
- printf("Turning LED %d off\n", temp);
- set_led_state(temp, LED_STATE_OFF);
- }
- }
- }
-
- return 0;
-}
-
-/*
- * The GPIO pins that go to the LEDs on the BF537 stamp must be configured
- * as output. This function simply configures them that way. This could
- * be done to all of the GPIO lines at once, but if a user is using a
- * custom board, this will try to be nice and only change the GPIO lines
- * that the user specifically names.
- */
-void configure_GPIO_to_output(int index)
-{
- int port;
-
- port = led_ports[index];
-
- /* Clear the Port F Function Enable Register */
- *pPORTF_FER &= ~port;
- /* Set the Port F I/O direction register */
- *pPORTFIO_DIR |= port;
- /* Clear the Port F I/O Input Enable Register */
- *pPORTFIO_INEN &= ~port;
-}
-
-/* Enforce the given state on the GPIO line for the indicated LED */
-void set_led_state(int index, int state)
-{
- int port;
-
- port = led_ports[index];
-
- if (LED_STATE_OFF == state) {
- /* Clear the bit to turn off the LED */
- *pPORTFIO &= ~port;
- } else {
- /* Set the bit to turn on the LED */
- *pPORTFIO |= port;
- }
-}
-
-/* Display usage information */
-void show_cmd_usage()
-{
- printf("Usage:\n%s\n", USAGE_LONG);
-}
-
-/* Register information for u-boot to find this command */
-U_BOOT_CMD(led, 3, 1, do_bf537led,
- "Control BF537 stamp LEDs", USAGE_LONG);
-
-#endif
diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c
deleted file mode 100644
index 7b753ad..0000000
--- a/board/bf537-stamp/spi_flash.c
+++ /dev/null
@@ -1,996 +0,0 @@
-/*
- * SPI flash driver
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* Configuration options:
- * CONFIG_SPI_BAUD - value to load into SPI_BAUD (divisor of SCLK to get SPI CLK)
- * CONFIG_SPI_FLASH_SLOW_READ - force usage of the slower read
- * WARNING: make sure your SCLK + SPI_BAUD is slow enough
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/spi.h>
-#include <asm/mach-common/bits/dma.h>
-
-/* Forcibly phase out these */
-#ifdef CONFIG_SPI_FLASH_NUM_SECTORS
-# error do not set CONFIG_SPI_FLASH_NUM_SECTORS
-#endif
-#ifdef CONFIG_SPI_FLASH_SECTOR_SIZE
-# error do not set CONFIG_SPI_FLASH_SECTOR_SIZE
-#endif
-
-#if defined(CONFIG_SPI)
-
-struct flash_info {
- char *name;
- uint16_t id;
- uint16_t ext_id;
- unsigned sector_size;
- unsigned num_sectors;
-};
-
-/* SPI Speeds: 50 MHz / 33 MHz */
-static struct flash_info flash_spansion_serial_flash[] = {
- { "S25FL016", 0x0215, 0, 64 * 1024, 32 },
- { "S25FL032", 0x0216, 0, 64 * 1024, 64 },
- { "S25FL064", 0x0217, 0, 64 * 1024, 128 },
- { "S25FL128-00", 0x2018, 0x0301, 64 * 1024, 256 }, /* Package marking FL128PIF */
- { "S25FL128-01", 0x2018, 0x0300, 128 * 1024, 64 }, /* Package marking FL128PIFL */
- { NULL, 0, 0, 0, 0 }
-};
-
-/* SPI Speeds: 50 MHz / 20 MHz */
-static struct flash_info flash_st_serial_flash[] = {
- { "m25p05", 0x2010, 0, 32 * 1024, 2 },
- { "m25p10", 0x2011, 0, 32 * 1024, 4 },
- { "m25p20", 0x2012, 0, 64 * 1024, 4 },
- { "m25p40", 0x2013, 0, 64 * 1024, 8 },
- { "m25p80", 0x20FF, 0, 64 * 1024, 16 },
- { "m25p16", 0x2015, 0, 64 * 1024, 32 },
- { "m25p32", 0x2016, 0, 64 * 1024, 64 },
- { "m25p64", 0x2017, 0, 64 * 1024, 128 },
- { "m25p128", 0x2018, 0, 256 * 1024, 64 },
- { NULL, 0, 0, 0, 0 }
-};
-
-/* SPI Speeds: 20 MHz / 40 MHz */
-static struct flash_info flash_sst_serial_flash[] = {
- { "SST25WF512", 0x2501, 0, 4 * 1024, 128 },
- { "SST25WF010", 0x2502, 0, 4 * 1024, 256 },
- { "SST25WF020", 0x2503, 0, 4 * 1024, 512 },
- { "SST25WF040", 0x2504, 0, 4 * 1024, 1024 },
- { NULL, 0, 0, 0, 0 }
-};
-
-/* SPI Speeds: 66 MHz / 33 MHz */
-static struct flash_info flash_atmel_dataflash[] = {
- { "AT45DB011x", 0x0c, 0, 264, 512 },
- { "AT45DB021x", 0x14, 0, 264, 1025 },
- { "AT45DB041x", 0x1c, 0, 264, 2048 },
- { "AT45DB081x", 0x24, 0, 264, 4096 },
- { "AT45DB161x", 0x2c, 0, 528, 4096 },
- { "AT45DB321x", 0x34, 0, 528, 8192 },
- { "AT45DB642x", 0x3c, 0, 1056, 8192 },
- { NULL, 0, 0, 0, 0 }
-};
-
-/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */
-static struct flash_info flash_winbond_serial_flash[] = {
- { "W25X10", 0x3011, 0, 16 * 256, 32 },
- { "W25X20", 0x3012, 0, 16 * 256, 64 },
- { "W25X40", 0x3013, 0, 16 * 256, 128 },
- { "W25X80", 0x3014, 0, 16 * 256, 256 },
- { "W25P80", 0x2014, 0, 256 * 256, 16 },
- { "W25P16", 0x2015, 0, 256 * 256, 32 },
- { NULL, 0, 0, 0, 0 }
-};
-
-struct flash_ops {
- uint8_t read, write, erase, status;
-};
-
-#ifdef CONFIG_SPI_FLASH_SLOW_READ
-# define OP_READ 0x03
-#else
-# define OP_READ 0x0B
-#endif
-static struct flash_ops flash_st_ops = {
- .read = OP_READ,
- .write = 0x02,
- .erase = 0xD8,
- .status = 0x05,
-};
-
-static struct flash_ops flash_sst_ops = {
- .read = OP_READ,
- .write = 0x02,
- .erase = 0x20,
- .status = 0x05,
-};
-
-static struct flash_ops flash_atmel_ops = {
- .read = OP_READ,
- .write = 0x82,
- .erase = 0x81,
- .status = 0xD7,
-};
-
-static struct flash_ops flash_winbond_ops = {
- .read = OP_READ,
- .write = 0x02,
- .erase = 0x20,
- .status = 0x05,
-};
-
-struct manufacturer_info {
- const char *name;
- uint8_t id;
- struct flash_info *flashes;
- struct flash_ops *ops;
-};
-
-static struct {
- struct manufacturer_info *manufacturer;
- struct flash_info *flash;
- struct flash_ops *ops;
- uint8_t manufacturer_id, device_id1, device_id2, device_extid1, device_extid2;
- unsigned int write_length;
- unsigned long sector_size, num_sectors;
-} flash;
-
-enum {
- JED_MANU_SPANSION = 0x01,
- JED_MANU_ST = 0x20,
- JED_MANU_SST = 0xBF,
- JED_MANU_ATMEL = 0x1F,
- JED_MANU_WINBOND = 0xEF,
-};
-
-static struct manufacturer_info flash_manufacturers[] = {
- {
- .name = "Spansion",
- .id = JED_MANU_SPANSION,
- .flashes = flash_spansion_serial_flash,
- .ops = &flash_st_ops,
- },
- {
- .name = "ST",
- .id = JED_MANU_ST,
- .flashes = flash_st_serial_flash,
- .ops = &flash_st_ops,
- },
- {
- .name = "SST",
- .id = JED_MANU_SST,
- .flashes = flash_sst_serial_flash,
- .ops = &flash_sst_ops,
- },
- {
- .name = "Atmel",
- .id = JED_MANU_ATMEL,
- .flashes = flash_atmel_dataflash,
- .ops = &flash_atmel_ops,
- },
- {
- .name = "Winbond",
- .id = JED_MANU_WINBOND,
- .flashes = flash_winbond_serial_flash,
- .ops = &flash_winbond_ops,
- },
-};
-
-#define TIMEOUT 5000 /* timeout of 5 seconds */
-
-/* If part has multiple SPI flashes, assume SPI0 as that is
- * the one we can boot off of ...
- */
-#ifndef pSPI_CTL
-# define pSPI_CTL pSPI0_CTL
-# define pSPI_BAUD pSPI0_BAUD
-# define pSPI_FLG pSPI0_FLG
-# define pSPI_RDBR pSPI0_RDBR
-# define pSPI_STAT pSPI0_STAT
-# define pSPI_TDBR pSPI0_TDBR
-#endif
-
-/* Default to the SPI SSEL that we boot off of:
- * BF54x, BF537, (everything new?): SSEL1
- * BF51x, BF533, BF561: SSEL2
- */
-#ifndef CONFIG_SPI_FLASH_SSEL
-# define CONFIG_SPI_FLASH_SSEL BFIN_BOOT_SPI_SSEL
-#endif
-#define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL)
-
-static void SPI_INIT(void)
-{
- /* [#3541] This delay appears to be necessary, but not sure
- * exactly why as the history behind it is non-existant.
- */
- *pSPI_CTL = 0;
- udelay(CONFIG_CCLK_HZ / 25000000);
-
- /* enable SPI pins: SSEL, MOSI, MISO, SCK */
-#ifdef __ADSPBF54x__
- *pPORTE_FER |= (PE0 | PE1 | PE2 | PE4);
-#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
- *pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
-#elif defined(__ADSPBF52x__)
- bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_3);
- bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG1 | PG2 | PG3 | PG4);
-#elif defined(__ADSPBF51x__)
- bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_1);
- bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG12 | PG13 | PG14 | PG15);
-#endif
-
- /* initate communication upon write of TDBR */
- *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE);
- *pSPI_BAUD = CONFIG_SPI_BAUD;
-}
-
-static void SPI_DEINIT(void)
-{
- *pSPI_CTL = 0;
- *pSPI_BAUD = 0;
- SSYNC();
-}
-
-static void SPI_ON(void)
-{
- /* toggle SSEL to reset the device so it'll take a new command */
- *pSPI_FLG = 0xFF00 | SSEL_MASK;
- SSYNC();
-
- *pSPI_FLG = ((0xFF & ~SSEL_MASK) << 8) | SSEL_MASK;
- SSYNC();
-}
-
-static void SPI_OFF(void)
-{
- /* put SPI settings back to reset state */
- *pSPI_FLG = 0xFF00;
- SSYNC();
-}
-
-static uint8_t spi_write_read_byte(uint8_t transmit)
-{
- *pSPI_TDBR = transmit;
- SSYNC();
-
- while ((*pSPI_STAT & TXS))
- if (ctrlc())
- break;
- while (!(*pSPI_STAT & SPIF))
- if (ctrlc())
- break;
- while (!(*pSPI_STAT & RXS))
- if (ctrlc())
- break;
-
- /* Read dummy to empty the receive register */
- return *pSPI_RDBR;
-}
-
-static uint8_t read_status_register(void)
-{
- uint8_t status_register;
-
- /* send instruction to read status register */
- SPI_ON();
- spi_write_read_byte(flash.ops->status);
- /* send dummy to receive the status register */
- status_register = spi_write_read_byte(0);
- SPI_OFF();
-
- return status_register;
-}
-
-static int wait_for_ready_status(void)
-{
- ulong start = get_timer(0);
-
- while (get_timer(0) - start < TIMEOUT) {
- switch (flash.manufacturer_id) {
- case JED_MANU_SPANSION:
- case JED_MANU_ST:
- case JED_MANU_SST:
- case JED_MANU_WINBOND:
- if (!(read_status_register() & 0x01))
- return 0;
- break;
-
- case JED_MANU_ATMEL:
- if (read_status_register() & 0x80)
- return 0;
- break;
- }
-
- if (ctrlc()) {
- puts("\nAbort\n");
- return -1;
- }
- }
-
- puts("Timeout\n");
- return -1;
-}
-
-static int enable_writing(void)
-{
- ulong start;
-
- if (flash.manufacturer_id == JED_MANU_ATMEL)
- return 0;
-
- /* A write enable instruction must previously have been executed */
- SPI_ON();
- spi_write_read_byte(0x06);
- SPI_OFF();
-
- /* The status register will be polled to check the write enable latch "WREN" */
- start = get_timer(0);
- while (get_timer(0) - start < TIMEOUT) {
- if (read_status_register() & 0x02)
- return 0;
-
- if (ctrlc()) {
- puts("\nAbort\n");
- return -1;
- }
- }
-
- puts("Timeout\n");
- return -1;
-}
-
-static void write_status_register(uint8_t val)
-{
- if (flash.manufacturer_id != JED_MANU_SST)
- hang();
-
- if (enable_writing())
- return;
-
- /* send instruction to write status register */
- SPI_ON();
- spi_write_read_byte(0x01);
- /* and clear it! */
- spi_write_read_byte(val);
- SPI_OFF();
-}
-
-/* Request and read the manufacturer and device id of parts which
- * are compatible with the JEDEC standard (JEP106) and use that to
- * setup other operating conditions.
- */
-static int spi_detect_part(void)
-{
- uint16_t dev_id, dev_extid;
- size_t i;
-
- static char called_init;
- if (called_init)
- return 0;
-
-#ifdef CONFIG_SPI_FLASH_M25P80
- flash.manufacturer_id = JED_MANU_ST;
- flash.device_id1 = 0x20;
- flash.device_id2 = 0xFF;
-#else
- SPI_ON();
-
- /* Send the request for the part identification */
- spi_write_read_byte(0x9F);
-
- /* Now read in the manufacturer id bytes */
- do {
- flash.manufacturer_id = spi_write_read_byte(0);
- if (flash.manufacturer_id == 0x7F)
- puts("Warning: unhandled manufacturer continuation byte!\n");
- } while (flash.manufacturer_id == 0x7F);
-
- /* Now read in the first device id byte */
- flash.device_id1 = spi_write_read_byte(0);
-
- /* Now read in the second device id byte */
- flash.device_id2 = spi_write_read_byte(0);
-
- /* Read extended device ids */
- flash.device_extid1 = spi_write_read_byte(0);
- flash.device_extid2 = spi_write_read_byte(0);
-
- SPI_OFF();
-#endif
-
- dev_id = (flash.device_id1 << 8) | flash.device_id2;
- dev_extid = (flash.device_extid1 << 8) | flash.device_extid2;
-
- for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) {
- if (flash.manufacturer_id == flash_manufacturers[i].id)
- break;
- }
- if (i == ARRAY_SIZE(flash_manufacturers))
- goto unknown;
-
- flash.manufacturer = &flash_manufacturers[i];
- flash.ops = flash_manufacturers[i].ops;
-
- switch (flash.manufacturer_id) {
- case JED_MANU_SPANSION:
- case JED_MANU_ST:
- case JED_MANU_SST:
- case JED_MANU_WINBOND:
- for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
- if (dev_id == flash.manufacturer->flashes[i].id &&
- (flash.manufacturer->flashes[i].ext_id == 0 ||
- flash.manufacturer->flashes[i].ext_id == dev_extid))
- break;
- }
- if (!flash.manufacturer->flashes[i].name)
- goto unknown;
-
- flash.flash = &flash.manufacturer->flashes[i];
- flash.sector_size = flash.flash->sector_size;
- flash.num_sectors = flash.flash->num_sectors;
-
- if (flash.manufacturer_id == JED_MANU_SST)
- flash.write_length = 1; /* pwnt :( */
- else
- flash.write_length = 256;
- break;
-
- case JED_MANU_ATMEL: {
- uint8_t status = read_status_register();
-
- for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
- if ((status & 0x3c) == flash.manufacturer->flashes[i].id)
- break;
- }
- if (!flash.manufacturer->flashes[i].name)
- goto unknown;
-
- flash.flash = &flash.manufacturer->flashes[i];
- flash.sector_size = flash.flash->sector_size;
- flash.num_sectors = flash.flash->num_sectors;
-
- /* see if flash is in "power of 2" mode */
- if (status & 0x1)
- flash.sector_size &= ~(1 << (ffs(flash.sector_size) - 1));
-
- flash.write_length = flash.sector_size;
- break;
- }
- }
-
- /* the SST parts power up with software protection enabled by default */
- if (flash.manufacturer_id == JED_MANU_SST)
- write_status_register(0);
-
- called_init = 1;
- return 0;
-
- unknown:
- printf("Unknown SPI device: 0x%02X 0x%02X 0x%02X\n",
- flash.manufacturer_id, flash.device_id1, flash.device_id2);
- return 1;
-}
-
-/*
- * Function: spi_init_f
- * Description: Init SPI-Controller (ROM part)
- * return: ---
- */
-void spi_init_f(void)
-{
-}
-
-/*
- * Function: spi_init_r
- * Description: Init SPI-Controller (RAM part) -
- * The malloc engine is ready and we can move our buffers to
- * normal RAM
- * return: ---
- */
-void spi_init_r(void)
-{
-#if defined(CONFIG_POST) && (CONFIG_POST & CONFIG_SYS_POST_SPI)
- /* Our testing strategy here is pretty basic:
- * - fill src memory with an 8-bit pattern
- * - write the src memory to the SPI flash
- * - read the SPI flash into the dst memory
- * - compare src and dst memory regions
- * - repeat a few times
- * The variations we test for:
- * - change the 8-bit pattern a bit
- * - change the read/write block size so we know:
- * - writes smaller/equal/larger than the buffer work
- * - writes smaller/equal/larger than the sector work
- * - change the SPI offsets so we know:
- * - writing partial sectors works
- */
- uint8_t *mem_src, *mem_dst;
- size_t i, c, l, o;
- size_t test_count, errors;
- uint8_t pattern;
-
- SPI_INIT();
-
- if (spi_detect_part())
- goto out;
- eeprom_info();
-
- ulong lengths[] = {
- flash.write_length,
- flash.write_length * 2,
- flash.write_length / 2,
- flash.sector_size,
- flash.sector_size * 2,
- flash.sector_size / 2
- };
- ulong offsets[] = {
- 0,
- flash.write_length,
- flash.write_length * 2,
- flash.write_length / 2,
- flash.write_length / 4,
- flash.sector_size,
- flash.sector_size * 2,
- flash.sector_size / 2,
- flash.sector_size / 4,
- };
-
- /* the exact addresses are arbitrary ... they just need to not overlap */
- mem_src = (void *)(0);
- mem_dst = (void *)(max(flash.write_length, flash.sector_size) * 2);
-
- test_count = 0;
- errors = 0;
- pattern = 0x00;
-
- for (i = 0; i < 16; ++i) { /* 16 = 8 bits * 2 iterations */
- for (l = 0; l < ARRAY_SIZE(lengths); ++l) {
- for (o = 0; o < ARRAY_SIZE(offsets); ++o) {
- ulong len = lengths[l];
- ulong off = offsets[o];
-
- printf("Testing pattern 0x%02X of length %5lu and offset %5lu: ", pattern, len, off);
-
- /* setup the source memory region */
- memset(mem_src, pattern, len);
-
- test_count += 4;
- for (c = 0; c < 4; ++c) { /* 4 is just a random repeat count */
- if (ctrlc()) {
- puts("\nAbort\n");
- goto out;
- }
-
- /* make sure background fill pattern != pattern */
- memset(mem_dst, pattern ^ 0xFF, len);
-
- /* write out the source memory and then read it back and compare */
- eeprom_write(0, off, mem_src, len);
- eeprom_read(0, off, mem_dst, len);
-
- if (memcmp(mem_src, mem_dst, len)) {
- for (c = 0; c < len; ++c)
- if (mem_src[c] != mem_dst[c])
- break;
- printf(" FAIL @ offset %u, skipping repeats ", c);
- ++errors;
- break;
- }
-
- /* XXX: should shrink write region here to test with
- * leading/trailing canaries so we know surrounding
- * bytes don't get screwed.
- */
- }
- puts("\n");
- }
- }
-
- /* invert the pattern every other run and shift out bits slowly */
- pattern ^= 0xFF;
- if (i % 2)
- pattern = (pattern | 0x01) << 1;
- }
-
- if (errors)
- printf("SPI FAIL: Out of %i tests, there were %i errors ;(\n", test_count, errors);
- else
- printf("SPI PASS: %i tests worked!\n", test_count);
-
- out:
- SPI_DEINIT();
-
-#endif
-}
-
-static void transmit_address(uint32_t addr)
-{
- /* Send the highest byte of the 24 bit address at first */
- spi_write_read_byte(addr >> 16);
- /* Send the middle byte of the 24 bit address at second */
- spi_write_read_byte(addr >> 8);
- /* Send the lowest byte of the 24 bit address finally */
- spi_write_read_byte(addr);
-}
-
-/*
- * Read a value from flash for verify purpose
- * Inputs: unsigned long ulStart - holds the SPI start address
- * int pnData - pointer to store value read from flash
- * long lCount - number of elements to read
- */
-#ifdef CONFIG_SPI_READFLASH_NODMA
-static int read_flash(unsigned long address, long count, uchar *buffer)
-{
- size_t i, j;
-
- /* Send the read command to SPI device */
- SPI_ON();
- spi_write_read_byte(flash.ops->read);
- transmit_address(address);
-
-#ifndef CONFIG_SPI_FLASH_SLOW_READ
- /* Send dummy byte when doing SPI fast reads */
- spi_write_read_byte(0);
-#endif
-
- /* After the SPI device address has been placed on the MOSI pin the data can be */
- /* received on the MISO pin. */
- j = flash.sector_size << 1;
- for (i = 1; i <= count; ++i) {
- *buffer++ = spi_write_read_byte(0);
- if (!j--) {
- puts(".");
- j = flash.sector_size;
- }
- }
-
- SPI_OFF();
-
- return 0;
-}
-#else
-
-#ifdef __ADSPBF54x__
-#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA4_IRQ_STATUS
-#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA4_IRQ_STATUS
-#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA4_CURR_DESC_PTR
-#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA4_CONFIG
-#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \
- defined(__ADSPBF538__) || defined(__ADSPBF539__)
-#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA5_IRQ_STATUS
-#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA5_IRQ_STATUS
-#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA5_CURR_DESC_PTR
-#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA5_CONFIG
-#elif defined(__ADSPBF561__)
-#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA16_IRQ_STATUS
-#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA16_IRQ_STATUS
-#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA16_CURR_DESC_PTR
-#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA16_CONFIG
-#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
- defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
-#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA7_IRQ_STATUS
-#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA7_IRQ_STATUS
-#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA7_CURR_DESC_PTR
-#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA7_CONFIG
-#else
-#error "Please provide SPI DMA channel defines"
-#endif
-
-struct dmadesc_array {
- unsigned long start_addr;
- unsigned short cfg;
- unsigned short x_count;
- short x_modify;
- unsigned short y_count;
- short y_modify;
-} __attribute__((packed));
-
-/*
- * Read a value from flash for verify purpose
- * Inputs: unsigned long ulStart - holds the SPI start address
- * int pnData - pointer to store value read from flash
- * long lCount - number of elements to read
- */
-
-static int read_flash(unsigned long address, long count, uchar *buffer)
-{
- unsigned int ndsize;
- struct dmadesc_array dma[2];
- /* Send the read command to SPI device */
-
- if (!count)
- return 0;
-
- dma[0].start_addr = (unsigned long)buffer;
- dma[0].x_modify = 1;
- if (count <= 65536) {
- blackfin_dcache_flush_invalidate_range(buffer, buffer + count);
- ndsize = NDSIZE_5;
- dma[0].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN;
- dma[0].x_count = count;
- } else {
- blackfin_dcache_flush_invalidate_range(buffer, buffer + 65536 - 1);
- ndsize = NDSIZE_7;
- dma[0].cfg = NDSIZE_5 | WNR | WDSIZE_8 | FLOW_ARRAY | DMAEN | DMA2D;
- dma[0].x_count = 0; /* 2^16 */
- dma[0].y_count = count >> 16; /* count / 2^16 */
- dma[0].y_modify = 1;
- dma[1].start_addr = (unsigned long)(buffer + (count & ~0xFFFF));
- dma[1].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN;
- dma[1].x_count = count & 0xFFFF; /* count % 2^16 */
- dma[1].x_modify = 1;
- }
-
- bfin_write_DMA_SPI_CONFIG(0);
- bfin_write_DMA_SPI_IRQ_STATUS(DMA_DONE | DMA_ERR);
- bfin_write_DMA_SPI_CURR_DESC_PTR(dma);
-
- SPI_ON();
-
- spi_write_read_byte(flash.ops->read);
- transmit_address(address);
-
-#ifndef CONFIG_SPI_FLASH_SLOW_READ
- /* Send dummy byte when doing SPI fast reads */
- spi_write_read_byte(0);
-#endif
-
- bfin_write_DMA_SPI_CONFIG(ndsize | FLOW_ARRAY | DMAEN);
- *pSPI_CTL = (MSTR | CPHA | CPOL | RDBR_DMA | SPE | SZ);
- SSYNC();
-
- /*
- * We already invalidated the first 64k,
- * now while we just wait invalidate the remaining part.
- * Its not likely that the DMA is going to overtake
- */
- if (count > 65536)
- blackfin_dcache_flush_invalidate_range(buffer + 65536,
- buffer + count);
-
- while (!(bfin_read_DMA_SPI_IRQ_STATUS() & DMA_DONE))
- if (ctrlc())
- break;
-
- SPI_OFF();
-
- *pSPI_CTL = 0;
-
- bfin_write_DMA_SPI_CONFIG(0);
-
- *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE);
-
- return 0;
-}
-#endif
-
-static long address_to_sector(unsigned long address)
-{
- if (address > (flash.num_sectors * flash.sector_size) - 1)
- return -1;
- return address / flash.sector_size;
-}
-
-static int erase_sector(int address)
-{
- /* sector gets checked in higher function, so assume it's valid
- * here and figure out the offset of the sector in flash
- */
- if (enable_writing())
- return -1;
-
- /*
- * Send the erase block command to the flash followed by the 24 address
- * to point to the start of a sector
- */
- SPI_ON();
- spi_write_read_byte(flash.ops->erase);
- transmit_address(address);
- SPI_OFF();
-
- return wait_for_ready_status();
-}
-
-/* Write [count] bytes out of [buffer] into the given SPI [address] */
-static long write_flash(unsigned long address, long count, uchar *buffer)
-{
- long i, write_buffer_size;
-
- if (enable_writing())
- return -1;
-
- /* Send write command followed by the 24 bit address */
- SPI_ON();
- spi_write_read_byte(flash.ops->write);
- transmit_address(address);
-
- /* Shoot out a single write buffer */
- write_buffer_size = min(count, flash.write_length);
- for (i = 0; i < write_buffer_size; ++i)
- spi_write_read_byte(buffer[i]);
-
- SPI_OFF();
-
- /* Wait for the flash to do its thing */
- if (wait_for_ready_status()) {
- puts("SPI Program Time out! ");
- return -1;
- }
-
- return i;
-}
-
-/* Write [count] bytes out of [buffer] into the given SPI [address] */
-static int write_sector(unsigned long address, long count, uchar *buffer)
-{
- long write_cnt;
-
- while (count != 0) {
- write_cnt = write_flash(address, count, buffer);
- if (write_cnt == -1)
- return -1;
-
- /* Now that we've sent some bytes out to the flash, update
- * our counters a bit
- */
- count -= write_cnt;
- address += write_cnt;
- buffer += write_cnt;
- }
-
- /* return the appropriate error code */
- return 0;
-}
-
-/*
- * Function: spi_write
- */
-ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
-{
- unsigned long offset;
- int start_sector, end_sector;
- int start_byte, end_byte;
- uchar *temp = NULL;
- int num, ret = 0;
-
- SPI_INIT();
-
- if (spi_detect_part())
- goto out;
-
- offset = addr[0] << 16 | addr[1] << 8 | addr[2];
-
- /* Get the start block number */
- start_sector = address_to_sector(offset);
- if (start_sector == -1) {
- puts("Invalid sector! ");
- goto out;
- }
- end_sector = address_to_sector(offset + len - 1);
- if (end_sector == -1) {
- puts("Invalid sector! ");
- goto out;
- }
-
- /* Since flashes operate in sector units but the eeprom command
- * operates as a continuous stream of bytes, we need to emulate
- * the eeprom behavior. So here we read in the sector, overlay
- * any bytes we're actually modifying, erase the sector, and
- * then write back out the new sector.
- */
- temp = malloc(flash.sector_size);
- if (!temp) {
- puts("Malloc for sector failed! ");
- goto out;
- }
-
- for (num = start_sector; num <= end_sector; num++) {
- unsigned long address = num * flash.sector_size;
-
- /* XXX: should add an optimization when spanning sectors:
- * No point in reading in a sector if we're going to be
- * clobbering the whole thing. Need to also add a test
- * case to make sure the optimization is correct.
- */
- if (read_flash(address, flash.sector_size, temp)) {
- puts("Read sector failed! ");
- len = 0;
- break;
- }
-
- start_byte = max(address, offset);
- end_byte = address + flash.sector_size - 1;
- if (end_byte > (offset + len))
- end_byte = (offset + len - 1);
-
- memcpy(temp + start_byte - address,
- buffer + start_byte - offset,
- end_byte - start_byte + 1);
-
- if (erase_sector(address)) {
- puts("Erase sector failed! ");
- goto out;
- }
-
- if (write_sector(address, flash.sector_size, temp)) {
- puts("Write sector failed! ");
- goto out;
- }
-
- puts(".");
- }
-
- ret = len;
-
- out:
- free(temp);
-
- SPI_DEINIT();
-
- return ret;
-}
-
-/*
- * Function: spi_read
- */
-ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
-{
- unsigned long offset;
-
- SPI_INIT();
-
- if (spi_detect_part())
- len = 0;
- else {
- offset = addr[0] << 16 | addr[1] << 8 | addr[2];
- read_flash(offset, len, buffer);
- }
-
- SPI_DEINIT();
-
- return len;
-}
-
-/*
- * Spit out some useful information about the SPI eeprom
- */
-int eeprom_info(void)
-{
- int ret = 0;
-
- SPI_INIT();
-
- if (spi_detect_part())
- ret = 1;
- else
- printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n"
- "Parameters: num sectors = %lu, sector size = %lu, write size = %i\n"
- "Flash Size: %lu mbit (%lu mbyte)\n"
- "Status: 0x%02X\n",
- flash.flash->name, flash.manufacturer_id, flash.manufacturer->name,
- flash.device_id1, flash.device_id2, flash.num_sectors,
- flash.sector_size, flash.write_length,
- (flash.num_sectors * flash.sector_size) >> 17,
- (flash.num_sectors * flash.sector_size) >> 20,
- read_status_register());
-
- SPI_DEINIT();
-
- return ret;
-}
-
-#endif
diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c
index 65fb81a..cb9ee86 100644
--- a/board/bf548-ezkit/bf548-ezkit.c
+++ b/board/bf548-ezkit/bf548-ezkit.c
@@ -7,10 +7,12 @@
*/
#include <common.h>
-#include <netdev.h>
#include <config.h>
#include <command.h>
+#include <netdev.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
#include <asm/sdh.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -24,53 +26,13 @@
int board_early_init_f(void)
{
- /* Port H: PH8 - PH13 == A4 - A9
- * address lines of the parallel asynchronous memory interface
- */
-
- /************************************************
- * configure GPIO *
- * set port H function enable register *
- * configure PH8-PH13 as peripheral (not GPIO) *
- *************************************************/
- bfin_write_PORTH_FER(0x3F03);
-
- /************************************************
- * set port H MUX to configure PH8-PH13 *
- * 1st Function (MUX = 00) (bits 16-27 == 0) *
- * Set to address signals A4-A9 *
- *************************************************/
- bfin_write_PORTH_MUX(0);
-
- /************************************************
- * set port H direction register *
- * enable PH8-PH13 as outputs *
- *************************************************/
- bfin_write_PORTH_DIR_SET(0x3F00);
-
- /* Port I: PI0 - PH14 == A10 - A24
- * address lines of the parallel asynchronous memory interface
- */
-
- /************************************************
- * set port I function enable register *
- * configure PI0-PI14 as peripheral (not GPIO) *
- *************************************************/
- bfin_write_PORTI_FER(0x7fff);
-
- /**************************************************
- * set PORT I MUX to configure PI14-PI0 as *
- * 1st Function (MUX=00) - address signals A10-A24 *
- ***************************************************/
- bfin_write_PORTI_MUX(0);
-
- /****************************************
- * set PORT I direction register *
- * enable PI0 - PI14 as outputs *
- *****************************************/
- bfin_write_PORTI_DIR_SET(0x7fff);
-
- return 0;
+ /* Set async addr lines as peripheral */
+ const unsigned short pins[] = {
+ P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+ P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
+ P_A21, P_A22, P_A23, P_A24, 0
+ };
+ return peripheral_request_list(pins, "async");
}
#ifdef CONFIG_SMC911X
@@ -96,9 +58,7 @@
* be low for device mode and high for host mode. We set it high
* here because we are in host mode.
*/
- bfin_write_PORTE_FER(bfin_read_PORTE_FER() & ~PE7);
- bfin_write_PORTE_DIR_SET(PE7);
- bfin_write_PORTE_SET(PE7);
- SSYNC();
+ gpio_request(GPIO_PE7, "musb-vbus");
+ gpio_direction_output(GPIO_PE7, 1);
}
#endif
diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c
index 10b08e2..af3d58b 100644
--- a/board/bf548-ezkit/video.c
+++ b/board/bf548-ezkit/video.c
@@ -11,6 +11,8 @@
#include <config.h>
#include <malloc.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <i2c.h>
#include <linux/types.h>
@@ -173,22 +175,21 @@
void Init_Ports(void)
{
- *pPORTF_MUX = 0x00000000;
- *pPORTF_FER |= 0xFFFF; /* PPI0..15 */
-
- *pPORTG_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK);
- *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */
-
+ const unsigned short pins[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+ P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
+ P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
+ P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
#if !defined(CONFIG_VIDEO_RGB666)
- *pPORTD_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK);
- *pPORTD_MUX |= (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4);
- *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */
+ P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
+ P_PPI0_D23,
#endif
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
+ };
+ peripheral_request_list(pins, "lcd");
- *pPORTE_FER &= ~PE3; /* DISP */
- *pPORTE_DIR_SET = PE3;
- *pPORTE_SET = PE3;
-
+ gpio_request(GPIO_PE3, "lcd-disp");
+ gpio_direction_output(GPIO_PE3, 1);
}
void EnableDMA(void)
diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c
index 6355c10..06d004a 100644
--- a/board/blackstamp/blackstamp.c
+++ b/board/blackstamp/blackstamp.c
@@ -13,7 +13,7 @@
#include <common.h>
#include <netdev.h>
-#include <asm/io.h>
+#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -27,14 +27,8 @@
#ifdef SHARED_RESOURCES
void swap_to(int device_id)
{
- bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0);
- SSYNC();
- if (device_id == ETHERNET)
- bfin_write_FIO_FLAG_S(PF0);
- else if (device_id == FLASH)
- bfin_write_FIO_FLAG_C(PF0);
- else
- printf("Unknown device to switch\n");
+ gpio_request(GPIO_PF0, "eth_flash_swap");
+ gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
SSYNC();
}
#endif
diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c
index da34b40..9df45c0 100644
--- a/board/calao/sbc35_a9g20/sbc35_a9g20.c
+++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c
@@ -177,13 +177,6 @@
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
-#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init(gd->bd);
-#endif
}
#endif
diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile
index c2cd244..bad018a 100644
--- a/board/cm-bf527/Makefile
+++ b/board/cm-bf527/Makefile
@@ -29,7 +29,7 @@
LIB = $(obj)lib$(BOARD).a
-COBJS-y := $(BOARD).o gpio.o gpio_cfi_flash.o
+COBJS-y := $(BOARD).o gpio_cfi_flash.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/cm-bf527/gpio.c b/board/cm-bf527/gpio.c
deleted file mode 100644
index 7e0babe..0000000
--- a/board/cm-bf527/gpio.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Control GPIO pins on the fly
- *
- * Copyright (c) 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-
-#include <asm/blackfin.h>
-
-int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc != 3) {
- show_usage:
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
-
- /* parse the behavior */
- ulong port_cmd = 0;
- switch (argv[1][0]) {
- case 'i': break;
- case 's': port_cmd = (PORTFIO_SET - PORTFIO); break;
- case 'c': port_cmd = (PORTFIO_CLEAR - PORTFIO); break;
- case 't': port_cmd = (PORTFIO_TOGGLE - PORTFIO); break;
- default: goto show_usage;
- }
-
- /* parse the pin with format: [p]<fgh><#> */
- const char *str_pin = argv[2];
-
- /* grab the [p]<fgh> portion */
- ulong port_base;
- if (*str_pin == 'p') ++str_pin;
- switch (*str_pin) {
- case 'f': port_base = PORTFIO; break;
- case 'g': port_base = PORTGIO; break;
- case 'h': port_base = PORTHIO; break;
- default: goto show_usage;
- }
-
- /* grab the <#> portion */
- ulong pin = simple_strtoul(str_pin+1, NULL, 10);
- ulong pin_mask = (1 << pin);
- if (pin > 15)
- goto show_usage;
-
- /* finally, let's do it: set direction and exec command */
- switch (*str_pin) {
- case 'f': bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~pin_mask); break;
- case 'g': bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~pin_mask); break;
- case 'h': bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~pin_mask); break;
- }
-
- ulong port_dir = port_base + (PORTFIO_DIR - PORTFIO);
- if (argv[1][0] == 'i')
- bfin_write16(port_dir, bfin_read16(port_dir) & ~pin_mask);
- else {
- bfin_write16(port_dir, bfin_read16(port_dir) | pin_mask);
- bfin_write16(port_base + port_cmd, pin_mask);
- }
-
- printf("gpio: pin %li on port %c has been %c\n", pin, *str_pin, argv[1][0]);
-
- return 0;
-}
-
-U_BOOT_CMD(gpio, 3, 0, do_gpio,
- "gpio - set/clear/toggle gpio output pins\n",
- "<s|c|t> <port><pin>\n"
- " - set/clear/toggle the specified pin\n");
diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c
index 7167680..f8ccc07 100644
--- a/board/cm-bf527/gpio_cfi_flash.c
+++ b/board/cm-bf527/gpio_cfi_flash.c
@@ -8,12 +8,13 @@
#include <common.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include "gpio_cfi_flash.h"
-#define GPIO_PIN_1 PH9
+#define GPIO_PIN_1 GPIO_PH9
#define GPIO_MASK_1 (1 << 21)
-#define GPIO_PIN_2 PG11
+#define GPIO_PIN_2 GPIO_PG11
#define GPIO_MASK_2 (1 << 22)
#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2)
@@ -21,16 +22,10 @@
{
unsigned long addr = (unsigned long)vaddr;
- if (addr & GPIO_MASK_1)
- bfin_write_PORTHIO_SET(GPIO_PIN_1);
- else
- bfin_write_PORTHIO_CLEAR(GPIO_PIN_1);
+ gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
#ifdef GPIO_MASK_2
- if (addr & GPIO_MASK_2)
- bfin_write_PORTGIO_SET(GPIO_PIN_2);
- else
- bfin_write_PORTGIO_CLEAR(GPIO_PIN_2);
+ gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
#endif
SSYNC();
@@ -57,7 +52,9 @@
void gpio_cfi_flash_init(void)
{
- bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1);
- bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | GPIO_PIN_2);
+ gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
+#ifdef GPIO_MASK_2
+ gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+#endif
gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
}
diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile
index 3812ba1..bad018a 100644
--- a/board/cm-bf537e/Makefile
+++ b/board/cm-bf537e/Makefile
@@ -29,7 +29,7 @@
LIB = $(obj)lib$(BOARD).a
-COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o
+COBJS-y := $(BOARD).o gpio_cfi_flash.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/cm-bf537e/flash.c b/board/cm-bf537e/flash.c
deleted file mode 100644
index a4c1ec0..0000000
--- a/board/cm-bf537e/flash.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * flash.c - helper commands for working with GPIO-assisted flash
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong faddr = CONFIG_SYS_FLASH_BASE;
- ushort data;
- ulong dflg;
-
- if (argc > 1) {
- dflg = simple_strtoul(argv[1], NULL, 16);
- faddr |= (dflg << 21);
- gpio_cfi_flash_swizzle((void *)faddr);
- } else {
- data = bfin_read_PORTFIO();
- printf("Port F data %04x (PF4:%i)\n", data, !!(data & PF4));
- }
-
- return 0;
-}
-
-U_BOOT_CMD(pf, 3, 0, do_pf,
- "set/clear PF4 GPIO flash bank switch\n",
- "<pf4> - set PF4 GPIO pin state\n");
diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c
index a9e69cf..79ee844 100644
--- a/board/cm-bf537e/gpio_cfi_flash.c
+++ b/board/cm-bf537e/gpio_cfi_flash.c
@@ -8,10 +8,11 @@
#include <common.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include "gpio_cfi_flash.h"
-#define GPIO_PIN_1 PF4
+#define GPIO_PIN_1 GPIO_PF4
#define GPIO_MASK_1 (1 << 21)
#define GPIO_MASK (GPIO_MASK_1)
@@ -19,16 +20,10 @@
{
unsigned long addr = (unsigned long)vaddr;
- if (addr & GPIO_MASK_1)
- bfin_write_PORTFIO_SET(GPIO_PIN_1);
- else
- bfin_write_PORTFIO_CLEAR(GPIO_PIN_1);
+ gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
#ifdef GPIO_MASK_2
- if (addr & GPIO_MASK_2)
- bfin_write_PORTGIO_SET(GPIO_PIN_2);
- else
- bfin_write_PORTGIO_CLEAR(GPIO_PIN_2);
+ gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
#endif
SSYNC();
@@ -55,6 +50,9 @@
void gpio_cfi_flash_init(void)
{
- bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1);
+ gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
+#ifdef GPIO_MASK_2
+ gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+#endif
gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
}
diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile
index 3812ba1..bad018a 100644
--- a/board/cm-bf537u/Makefile
+++ b/board/cm-bf537u/Makefile
@@ -29,7 +29,7 @@
LIB = $(obj)lib$(BOARD).a
-COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o
+COBJS-y := $(BOARD).o gpio_cfi_flash.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/cm-bf537u/flash.c b/board/cm-bf537u/flash.c
deleted file mode 100644
index 52abe79..0000000
--- a/board/cm-bf537u/flash.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * flash.c - helper commands for working with GPIO-assisted flash
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-int do_ph(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong faddr = CONFIG_SYS_FLASH_BASE;
- ushort data;
- ulong dflg;
-
- if (argc > 1) {
- dflg = simple_strtoul(argv[1], NULL, 16);
- faddr |= (dflg << 21);
- gpio_cfi_flash_swizzle((void *)faddr);
- } else {
- data = bfin_read_PORTHIO();
- printf("Port H data %04x (PH0:%i)\n", data, !!(data & PH0));
- }
-
- return 0;
-}
-
-U_BOOT_CMD(ph, 3, 0, do_ph,
- "set/clear PH0 GPIO flash bank switch\n",
- "<ph0> - set PH0 GPIO pin state\n");
diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c
index 68633ec..416c689 100644
--- a/board/cm-bf537u/gpio_cfi_flash.c
+++ b/board/cm-bf537u/gpio_cfi_flash.c
@@ -8,10 +8,11 @@
#include <common.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include "gpio_cfi_flash.h"
-#define GPIO_PIN_1 PH0
+#define GPIO_PIN_1 GPIO_PH0
#define GPIO_MASK_1 (1 << 21)
#define GPIO_MASK (GPIO_MASK_1)
@@ -19,16 +20,10 @@
{
unsigned long addr = (unsigned long)vaddr;
- if (addr & GPIO_MASK_1)
- bfin_write_PORTHIO_SET(GPIO_PIN_1);
- else
- bfin_write_PORTHIO_CLEAR(GPIO_PIN_1);
+ gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
#ifdef GPIO_MASK_2
- if (addr & GPIO_MASK_2)
- bfin_write_PORTGIO_SET(GPIO_PIN_2);
- else
- bfin_write_PORTGIO_CLEAR(GPIO_PIN_2);
+ gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
#endif
SSYNC();
@@ -55,6 +50,9 @@
void gpio_cfi_flash_init(void)
{
- bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1);
+ gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
+#ifdef GPIO_MASK_2
+ gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+#endif
gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
}
diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c
index 3627586..90ce4c3 100644
--- a/board/cm-bf548/cm-bf548.c
+++ b/board/cm-bf548/cm-bf548.c
@@ -11,6 +11,7 @@
#include <command.h>
#include <netdev.h>
#include <asm/blackfin.h>
+#include <asm/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -23,53 +24,13 @@
int board_early_init_f(void)
{
- /* Port H: PH8 - PH13 == A4 - A9
- * address lines of the parallel asynchronous memory interface
- */
-
- /************************************************
- * configure GPIO *
- * set port H function enable register *
- * configure PH8-PH13 as peripheral (not GPIO) *
- *************************************************/
- bfin_write_PORTH_FER(0x3F03);
-
- /************************************************
- * set port H MUX to configure PH8-PH13 *
- * 1st Function (MUX = 00) (bits 16-27 == 0) *
- * Set to address signals A4-A9 *
- *************************************************/
- bfin_write_PORTH_MUX(0);
-
- /************************************************
- * set port H direction register *
- * enable PH8-PH13 as outputs *
- *************************************************/
- bfin_write_PORTH_DIR_SET(0x3F00);
-
- /* Port I: PI0 - PH14 == A10 - A24
- * address lines of the parallel asynchronous memory interface
- */
-
- /************************************************
- * set port I function enable register *
- * configure PI0-PI14 as peripheral (not GPIO) *
- *************************************************/
- bfin_write_PORTI_FER(0x7fff);
-
- /**************************************************
- * set PORT I MUX to configure PI14-PI0 as *
- * 1st Function (MUX=00) - address signals A10-A24 *
- ***************************************************/
- bfin_write_PORTI_MUX(0);
-
- /****************************************
- * set PORT I direction register *
- * enable PI0 - PI14 as outputs *
- *****************************************/
- bfin_write_PORTI_DIR_SET(0x7fff);
-
- return 0;
+ /* Set async addr lines as peripheral */
+ const unsigned short pins[] = {
+ P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+ P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
+ P_A21, P_A22, P_A23, P_A24, 0
+ };
+ return peripheral_request_list(pins, "async");
}
int board_eth_init(bd_t *bis)
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
index 4097f09..d43f5a1 100644
--- a/board/cm-bf548/video.c
+++ b/board/cm-bf548/video.c
@@ -11,6 +11,8 @@
#include <config.h>
#include <malloc.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <i2c.h>
#include <linux/types.h>
@@ -174,28 +176,21 @@
void Init_Ports(void)
{
- *pPORTF_MUX = 0x00000000;
- *pPORTF_FER |= 0xFFFF; /* PPI0..15 */
-
- *pPORTG_MUX &=
- ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK |
- PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK);
- *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */
-
+ const unsigned short pins[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+ P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
+ P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
+ P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
#if !defined(CONFIG_VIDEO_RGB666)
- *pPORTD_MUX &=
- ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK |
- PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK);
- *pPORTD_MUX |=
- (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 |
- PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4);
- *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */
+ P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
+ P_PPI0_D23,
#endif
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
+ };
+ peripheral_request_list(pins, "lcd");
- *pPORTE_FER &= ~PE3; /* DISP */
- *pPORTE_DIR_SET = PE3;
- *pPORTE_SET = PE3;
-
+ gpio_request(GPIO_PE3, "lcd-disp");
+ gpio_direction_output(GPIO_PE3, 1);
}
void EnableDMA(void)
diff --git a/board/gth/Makefile b/board/colibri_pxa270/Makefile
similarity index 64%
copy from board/gth/Makefile
copy to board/colibri_pxa270/Makefile
index 4b5c528..44d73cc 100644
--- a/board/gth/Makefile
+++ b/board/colibri_pxa270/Makefile
@@ -1,9 +1,7 @@
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Toradex Colibri PXA270 Support
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -23,22 +21,25 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
+OBJS := colibri_pxa270.o
+SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
#########################################################################
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-sinclude $(obj).depend
+-include .depend
#########################################################################
diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c
new file mode 100644
index 0000000..d3822f0
--- /dev/null
+++ b/board/colibri_pxa270/colibri_pxa270.c
@@ -0,0 +1,118 @@
+/*
+ * Toradex Colibri PXA270 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+struct serial_device *default_serial_console (void)
+{
+ return &serial_ffuart_device;
+}
+
+int board_init (void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_USB
+int usb_board_init(void)
+{
+ UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+
+ UHCHR |= UHCHR_FSBIR;
+
+ while (UHCHR & UHCHR_FSBIR);
+
+ UHCHR &= ~UHCHR_SSE;
+ UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+
+ /* Clear any OTG Pin Hold */
+ if (PSSR & PSSR_OTGPH)
+ PSSR |= PSSR_OTGPH;
+
+ UHCRHDA &= ~(0x200);
+ UHCRHDA |= 0x100;
+
+ /* Set port power control mask bits, only 3 ports. */
+ UHCRHDB |= (0x7<<17);
+
+ /* enable port 2 */
+ UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+
+ return 0;
+}
+
+void usb_board_init_fail(void)
+{
+ return;
+}
+
+void usb_board_stop(void)
+{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+ CKEN &= ~CKEN10_USBHOST;
+
+ return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/board/colibri_pxa270/config.mk b/board/colibri_pxa270/config.mk
new file mode 100644
index 0000000..1d650ac
--- /dev/null
+++ b/board/colibri_pxa270/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1000000
diff --git a/board/colibri_pxa270/lowlevel_init.S b/board/colibri_pxa270/lowlevel_init.S
new file mode 100644
index 0000000..a43dac2
--- /dev/null
+++ b/board/colibri_pxa270/lowlevel_init.S
@@ -0,0 +1,36 @@
+/*
+ * Toradex Colibri PXA270 Lowlevel Hardware Initialization
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ pxa_gpio_setup
+ pxa_wait_ticks 0x8000
+ pxa_mem_setup
+ pxa_wakeup
+ pxa_intr_setup
+ pxa_clock_setup
+
+ mov pc, lr
diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c
index 57506d6..6baa860 100644
--- a/board/davinci/da8xxevm/da830evm.c
+++ b/board/davinci/da8xxevm/da830evm.c
@@ -45,63 +45,63 @@
DECLARE_GLOBAL_DATA_PTR;
-#define pinmux &davinci_syscfg_regs->pinmux
+#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* SPI0 pin muxer settings */
static const struct pinmux_config spi0_pins[] = {
- { pinmux[7], 1, 3 },
- { pinmux[7], 1, 4 },
- { pinmux[7], 1, 5 },
- { pinmux[7], 1, 6 },
- { pinmux[7], 1, 7 }
+ { pinmux(7), 1, 3 },
+ { pinmux(7), 1, 4 },
+ { pinmux(7), 1, 5 },
+ { pinmux(7), 1, 6 },
+ { pinmux(7), 1, 7 }
};
/* EMIF-A bus pins for 8-bit NAND support on CS3 */
static const struct pinmux_config emifa_nand_pins[] = {
- { pinmux[13], 1, 6 },
- { pinmux[13], 1, 7 },
- { pinmux[14], 1, 0 },
- { pinmux[14], 1, 1 },
- { pinmux[14], 1, 2 },
- { pinmux[14], 1, 3 },
- { pinmux[14], 1, 4 },
- { pinmux[14], 1, 5 },
- { pinmux[15], 1, 7 },
- { pinmux[16], 1, 0 },
- { pinmux[18], 1, 1 },
- { pinmux[18], 1, 4 },
- { pinmux[18], 1, 5 },
+ { pinmux(13), 1, 6 },
+ { pinmux(13), 1, 7 },
+ { pinmux(14), 1, 0 },
+ { pinmux(14), 1, 1 },
+ { pinmux(14), 1, 2 },
+ { pinmux(14), 1, 3 },
+ { pinmux(14), 1, 4 },
+ { pinmux(14), 1, 5 },
+ { pinmux(15), 1, 7 },
+ { pinmux(16), 1, 0 },
+ { pinmux(18), 1, 1 },
+ { pinmux(18), 1, 4 },
+ { pinmux(18), 1, 5 },
};
/* EMAC PHY interface pins */
static const struct pinmux_config emac_pins[] = {
- { pinmux[9], 0, 5 },
- { pinmux[10], 2, 1 },
- { pinmux[10], 2, 2 },
- { pinmux[10], 2, 3 },
- { pinmux[10], 2, 4 },
- { pinmux[10], 2, 5 },
- { pinmux[10], 2, 6 },
- { pinmux[10], 2, 7 },
- { pinmux[11], 2, 0 },
- { pinmux[11], 2, 1 },
+ { pinmux(9), 0, 5 },
+ { pinmux(10), 2, 1 },
+ { pinmux(10), 2, 2 },
+ { pinmux(10), 2, 3 },
+ { pinmux(10), 2, 4 },
+ { pinmux(10), 2, 5 },
+ { pinmux(10), 2, 6 },
+ { pinmux(10), 2, 7 },
+ { pinmux(11), 2, 0 },
+ { pinmux(11), 2, 1 },
};
/* UART pin muxer settings */
static const struct pinmux_config uart_pins[] = {
- { pinmux[8], 2, 7 },
- { pinmux[9], 2, 0 }
+ { pinmux(8), 2, 7 },
+ { pinmux(9), 2, 0 }
};
/* I2C pin muxer settings */
static const struct pinmux_config i2c_pins[] = {
- { pinmux[8], 2, 3 },
- { pinmux[8], 2, 4 }
+ { pinmux(8), 2, 3 },
+ { pinmux(8), 2, 4 }
};
/* USB0_DRVVBUS pin muxer settings */
static const struct pinmux_config usb_pins[] = {
- { pinmux[9], 1, 1 }
+ { pinmux(9), 1, 1 }
};
static const struct pinmux_resource pinmuxes[] = {
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 959b2c6..eeb456c 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -30,28 +30,28 @@
DECLARE_GLOBAL_DATA_PTR;
-#define pinmux (&davinci_syscfg_regs->pinmux)
+#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* SPI0 pin muxer settings */
static const struct pinmux_config spi1_pins[] = {
- { pinmux[5], 1, 1 },
- { pinmux[5], 1, 2 },
- { pinmux[5], 1, 4 },
- { pinmux[5], 1, 5 }
+ { pinmux(5), 1, 1 },
+ { pinmux(5), 1, 2 },
+ { pinmux(5), 1, 4 },
+ { pinmux(5), 1, 5 }
};
/* UART pin muxer settings */
static const struct pinmux_config uart_pins[] = {
- { pinmux[0], 4, 6 },
- { pinmux[0], 4, 7 },
- { pinmux[4], 2, 4 },
- { pinmux[4], 2, 5 }
+ { pinmux(0), 4, 6 },
+ { pinmux(0), 4, 7 },
+ { pinmux(4), 2, 4 },
+ { pinmux(4), 2, 5 }
};
/* I2C pin muxer settings */
static const struct pinmux_config i2c_pins[] = {
- { pinmux[4], 2, 2 },
- { pinmux[4], 2, 3 }
+ { pinmux(4), 2, 2 },
+ { pinmux(4), 2, 3 }
};
static const struct pinmux_resource pinmuxes[] = {
diff --git a/board/digsy_mtc/cmd_mtc.c b/board/digsy_mtc/cmd_mtc.c
index 621980d..ba0c367 100644
--- a/board/digsy_mtc/cmd_mtc.c
+++ b/board/digsy_mtc/cmd_mtc.c
@@ -75,10 +75,8 @@
int err;
int i;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return -1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
memset(&pcmd, 0, sizeof(pcmd));
memset(&prx, 0, sizeof(prx));
@@ -149,10 +147,8 @@
int err;
uchar channel_mask = 0;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return -1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
if (strncmp(argv[1], "on", 2) == 0)
channel_mask |= 1;
@@ -178,10 +174,8 @@
int err;
uchar channel_num = 0;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return -1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
channel_num = simple_strtol(argv[1], NULL, 10);
if ((channel_num != 1) && (channel_num != 2)) {
@@ -332,8 +326,7 @@
return c->cmd(c, flag, argc, argv);
} else {
/* Unrecognized command */
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return err;
diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
index 9109b64..3dfbf3b 100644
--- a/board/esd/common/lcd.c
+++ b/board/esd/common/lcd.c
@@ -345,10 +345,8 @@
#ifdef CONFIG_VIDEO_SM501
char *str;
#endif
- if (argc != 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 2)
+ return cmd_usage(cmdtp);
addr = simple_strtoul(argv[1], NULL, 16);
diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c
index aa74376..4946538 100644
--- a/board/esd/dasa_sim/cmd_dasa_sim.c
+++ b/board/esd/dasa_sim/cmd_dasa_sim.c
@@ -221,9 +221,7 @@
return 0;
}
- cmd_usage(cmdtp);
- return 1;
-
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
index b0ebad7..96698e7 100644
--- a/board/esd/vme8349/vme8349.c
+++ b/board/esd/vme8349/vme8349.c
@@ -105,7 +105,7 @@
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
+ clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
return 0;
}
diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c
index af8a4a2..61b6c33 100644
--- a/board/eukrea/cpu9260/cpu9260.c
+++ b/board/eukrea/cpu9260/cpu9260.c
@@ -200,13 +200,6 @@
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
-#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init(gd->bd);
-#endif
}
#endif
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index df289aa..2d48d7e 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -42,6 +42,10 @@
COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
+COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o
+COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
+COBJS-$(CONFIG_P1022DS) += ics307_clk.o
+COBJS-$(CONFIG_P2020DS) += ics307_clk.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c
new file mode 100644
index 0000000..89d8810
--- /dev/null
+++ b/board/freescale/common/ics307_clk.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "ics307_clk.h"
+
+#ifdef CONFIG_FSL_NGPIXIS
+#include "ngpixis.h"
+#else
+#include "pixis.h"
+#endif
+
+/* decode S[0-2] to Output Divider (OD) */
+static u8 ics307_s_to_od[] = {
+ 10, 2, 8, 4, 5, 7, 3, 6
+};
+
+/*
+ * Calculate frequency being generated by ICS307-02 clock chip based upon
+ * the control bytes being programmed into it.
+ */
+static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
+{
+ const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+ unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
+ unsigned long rdw = cw2 & 0x7F;
+ unsigned long od = ics307_s_to_od[cw0 & 0x7];
+ unsigned long freq;
+
+ /*
+ * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
+ *
+ * cw0: C1 C0 TTL F1 F0 S2 S1 S0
+ * cw1: V8 V7 V6 V5 V4 V3 V2 V1
+ * cw2: V0 R6 R5 R4 R3 R2 R1 R0
+ *
+ * R6:R0 = Reference Divider Word (RDW)
+ * V8:V0 = VCO Divider Word (VDW)
+ * S2:S0 = Output Divider Select (OD)
+ * F1:F0 = Function of CLK2 Output
+ * TTL = duty cycle
+ * C1:C0 = internal load capacitance for cyrstal
+ *
+ */
+
+ freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
+
+ debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
+ freq);
+ return freq;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return ics307_clk_freq(
+ in_8(&pixis->sclk[0]),
+ in_8(&pixis->sclk[1]),
+ in_8(&pixis->sclk[2]));
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return ics307_clk_freq(
+ in_8(&pixis->dclk[0]),
+ in_8(&pixis->dclk[1]),
+ in_8(&pixis->dclk[2]));
+}
diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h
new file mode 100644
index 0000000..db3dbc4
--- /dev/null
+++ b/board/freescale/common/ics307_clk.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ICS_CLK_H_
+#define __ICS_CLK_H_ 1
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(void);
+extern unsigned long get_board_ddr_clk(void);
+#endif
+
+#endif /* __ICS_CLK_H_ */
diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h
index 3c59ea8..089408b 100644
--- a/board/freescale/common/ngpixis.h
+++ b/board/freescale/common/ngpixis.h
@@ -45,7 +45,7 @@
u8 sw;
u8 en;
} s[8];
-} ngpixis_t __attribute__ ((aligned(1)));
+} __attribute__ ((packed)) ngpixis_t;
/* Pointer to the PIXIS register set */
#define pixis ((ngpixis_t *)PIXIS_BASE)
diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h
new file mode 100644
index 0000000..7f86de7
--- /dev/null
+++ b/board/freescale/common/pixis.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __PIXIS_H_
+#define __PIXIS_H_ 1
+
+/* PIXIS register set. */
+#if defined(CONFIG_MPC8536DS)
+typedef struct pixis {
+ u8 id;
+ u8 ver;
+ u8 pver;
+ u8 csr;
+ u8 rst;
+ u8 rst2;
+ u8 aux1;
+ u8 spd;
+ u8 aux2;
+ u8 csr2;
+ u8 watch;
+ u8 led;
+ u8 pwr;
+ u8 res[3];
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 vcfgen1;
+ u8 vcore0;
+ u8 res1;
+ u8 vboot;
+ u8 vspeed[3];
+ u8 sclk[3];
+ u8 dclk[3];
+ u8 i2cdacr;
+ u8 vcoreacc[4];
+ u8 vcorecnt[3];
+ u8 vcoremax[2];
+ u8 vplatacc[4];
+ u8 vplatcnt[3];
+ u8 vplatmax[2];
+ u8 vtempacc[4];
+ u8 vtempcnt[3];
+ u8 vtempmax[2];
+ u8 res2[4];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8544DS)
+typedef struct pixis {
+ u8 id;
+ u8 ver;
+ u8 pver;
+ u8 csr;
+ u8 rst;
+ u8 pwr;
+ u8 aux1;
+ u8 spd;
+ u8 res[8];
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 vcfgen1;
+ u8 vcore0;
+ u8 res1;
+ u8 vboot;
+ u8 vspeed[2];
+ u8 vclkh;
+ u8 vclkl;
+ u8 watch;
+ u8 led;
+ u8 vspeed2;
+ u8 res2[34];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8572DS)
+typedef struct pixis {
+ u8 id;
+ u8 ver;
+ u8 pver;
+ u8 csr;
+ u8 rst;
+ u8 pwr1;
+ u8 aux1;
+ u8 spd;
+ u8 aux2;
+ u8 res[7];
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 vcfgen1;
+ u8 vcore0;
+ u8 res1;
+ u8 vboot;
+ u8 vspeed[3];
+ u8 res2[2];
+ u8 sclk[3];
+ u8 dclk[3];
+ u8 res3[2];
+ u8 watch;
+ u8 led;
+ u8 res4[25];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8610HPCD)
+typedef struct pixis {
+ u8 id;
+ u8 ver; /* also called arch */
+ u8 pver;
+ u8 csr;
+ u8 rst;
+ u8 pwr;
+ u8 aux;
+ u8 spd;
+ u8 brdcfg0;
+ u8 brdcfg1;
+ u8 res[4];
+ u8 led;
+ u8 serno;
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 vcfgen1;
+ u8 vcore0;
+ u8 res1;
+ u8 vboot;
+ u8 vspeed[2];
+ u8 res2;
+ u8 sclk[3];
+ u8 res3;
+ u8 watch;
+ u8 res4[33];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8641HPCN)
+typedef struct pixis {
+ u8 id;
+ u8 ver;
+ u8 pver;
+ u8 csr;
+ u8 rst;
+ u8 pwr;
+ u8 aux;
+ u8 spd;
+ u8 res[8];
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 vcfgen1;
+ u8 vcore0;
+ u8 res1;
+ u8 vboot;
+ u8 vspeed[2];
+ u8 vclkh;
+ u8 vclkl;
+ u8 watch;
+ u8 res3[36];
+} __attribute__ ((packed)) pixis_t;
+#else
+#error Need to define pixis_t for this board
+#endif
+
+/* Pointer to the PIXIS register set */
+#define pixis ((pixis_t *)PIXIS_BASE)
+
+#endif /* __PIXIS_H_ */
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 5a8f4f5..3929ad0 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -351,8 +351,7 @@
prog_eeprom();
break;
default:
- cmd_usage(cmdtp);
- break;
+ return cmd_usage(cmdtp);
}
return 0;
@@ -388,8 +387,7 @@
break;
case 'h': /* help */
default:
- cmd_usage(cmdtp);
- break;
+ return cmd_usage(cmdtp);
}
return 0;
diff --git a/board/altera/ep1c20/Makefile b/board/freescale/mpc8308rdb/Makefile
similarity index 88%
rename from board/altera/ep1c20/Makefile
rename to board/freescale/mpc8308rdb/Makefile
index acad2aa..e9bfa2b 100644
--- a/board/altera/ep1c20/Makefile
+++ b/board/freescale/mpc8308rdb/Makefile
@@ -1,6 +1,8 @@
#
-# (C) Copyright 2001-2006
+# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -22,15 +24,10 @@
#
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
LIB = $(obj)lib$(BOARD).a
-COMOBJS := ../common/AMDLV065D.o ../common/epled.o
-
-COBJS := $(BOARD).o $(COMOBJS)
+COBJS := $(BOARD).o sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mpc8308rdb/config.mk b/board/freescale/mpc8308rdb/config.mk
new file mode 100644
index 0000000..f768264
--- /dev/null
+++ b/board/freescale/mpc8308rdb/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xFE000000
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
new file mode 100644
index 0000000..a864189
--- /dev/null
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+ gd->flags |= GD_FLG_SILENT;
+
+ return 0;
+}
+
+static u8 read_board_info(void)
+{
+ u8 val8;
+ i2c_set_bus_num(0);
+
+ if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+ return val8;
+ else
+ return 0;
+}
+
+int checkboard(void)
+{
+ static const char * const rev_str[] = {
+ "1.0",
+ "<reserved>",
+ "<reserved>",
+ "<reserved>",
+ "<unknown>",
+ };
+ u8 info;
+ int i;
+
+ info = read_board_info();
+ i = (!info) ? 4 : info & 0x03;
+
+ printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
+
+ return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+void pci_init_board(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+ clk83xx_t *clk = (clk83xx_t *)&immr->clk;
+ law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+ clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM ,
+ SCCR_PCIEXP1CM_1);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(1, pcie_reg, 0);
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+#ifdef CONFIG_VSC7385_IMAGE
+ if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+ CONFIG_VSC7385_IMAGE_SIZE)) {
+ puts("Failure uploading VSC7385 microcode.\n");
+ return 1;
+ }
+#endif
+
+ return 0;
+}
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_dr_usb(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, num_if = 0;
+
+ /* Initialize TSECs first */
+ if ((rv = cpu_eth_init(bis)) >= 0)
+ num_if += rv;
+ else
+ printf("ERROR: failed to initialize TSECs.\n");
+
+ if ((rv = pci_eth_init(bis)) >= 0)
+ num_if += rv;
+ else
+ printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+ return num_if;
+}
diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
new file mode 100644
index 0000000..939c1b8
--- /dev/null
+++ b/board/freescale/mpc8308rdb/sdram.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * Authors: Nick.Spence@freescale.com
+ * Wilson.Lo@freescale.com
+ * scottwood@freescale.com
+ *
+ * This files is mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void resume_from_sleep(void)
+{
+ u32 magic = *(u32 *)0;
+
+ typedef void (*func_t)(void);
+ func_t resume = *(func_t *)4;
+
+ if (magic == 0xf5153ae5)
+ resume();
+
+ gd->flags &= ~GD_FLG_SILENT;
+ puts("\nResume from sleep failed: bad magic word\n");
+}
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+
+ out_be32(&im->sysconf.ddrlaw[0].bar,
+ CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+ out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+ /*
+ * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+ * or the DDR2 controller may fail to initialize correctly.
+ */
+ udelay(50000);
+
+ out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+ /* Currently we use only one CS, so disable the other bank. */
+ out_be32(&im->ddr.cs_config[1], 0);
+
+ out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+ out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+ if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
+ out_be32(&im->ddr.sdram_cfg,
+ CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
+ } else {
+ out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+ }
+
+ out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+ out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+ out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ sync();
+
+ /* enable DDR controller */
+ setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+ sync();
+
+ return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize;
+
+ if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM */
+ msize = fixed_sdram();
+
+ if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+ resume_from_sleep();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 0c4fd68..7aede13 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -110,7 +110,7 @@
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbc = &im->lbus;
+ volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 61d1249..365ac37 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -192,7 +192,7 @@
void sdram_init(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbc = &immap->lbus;
+ volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
/*
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 7da39f1..5647579 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -221,15 +221,14 @@
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
};
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbus = &immap->lbus;
- lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
- lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
+ set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+ set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
*/
- lbus->mamr = 0x08404440;
+ immap->im_lbc.mamr = 0x08404440;
upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 4f55732..59ada9c 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -280,7 +280,7 @@
static int sdram_init(unsigned int base)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbc = &immap->lbus;
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
int rem = base % sdram_size;
uint *sdram_addr;
@@ -293,8 +293,8 @@
/*
* Setup SDRAM Base and Option Registers
*/
- immap->lbus.bank[2].br = base | CONFIG_SYS_BR2;
- immap->lbus.bank[2].or = CONFIG_SYS_OR2;
+ set_lbc_br(2, base | CONFIG_SYS_BR2);
+ set_lbc_or(2, CONFIG_SYS_OR2);
immap->sysconf.lblaw[2].bar = base;
immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c
index 9ffffb4..92d56a3 100644
--- a/board/freescale/mpc8360erdk/nand.c
+++ b/board/freescale/mpc8360erdk/nand.c
@@ -82,9 +82,9 @@
int board_nand_init(struct nand_chip *nand)
{
- fun.upm.mxmr = &im->lbus.mamr;
- fun.upm.mdr = &im->lbus.mdr;
- fun.upm.mar = &im->lbus.mar;
+ fun.upm.mxmr = &im->im_lbc.mamr;
+ fun.upm.mdr = &im->im_lbc.mdr;
+ fun.upm.mar = &im->im_lbc.mar;
upm_setup(&fun.upm);
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 1968106..c8e0856 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -350,154 +350,6 @@
return 0;
}
-#ifdef CONFIG_GET_CLK_FROM_ICS307
-/* decode S[0-2] to Output Divider (OD) */
-static unsigned char
-ics307_S_to_OD[] = {
- 10, 2, 8, 4, 5, 7, 3, 6
-};
-
-/* Calculate frequency being generated by ICS307-02 clock chip based upon
- * the control bytes being programmed into it. */
-/* XXX: This function should probably go into a common library */
-static unsigned long
-ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
-{
- const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
- unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
- unsigned long RDW = cw2 & 0x7F;
- unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
- unsigned long freq;
-
- /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
-
- /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
- * cw1: V8 V7 V6 V5 V4 V3 V2 V1
- * cw2: V0 R6 R5 R4 R3 R2 R1 R0
- *
- * R6:R0 = Reference Divider Word (RDW)
- * V8:V0 = VCO Divider Word (VDW)
- * S2:S0 = Output Divider Select (OD)
- * F1:F0 = Function of CLK2 Output
- * TTL = duty cycle
- * C1:C0 = internal load capacitance for cyrstal
- */
-
- /* Adding 1 to get a "nicely" rounded number, but this needs
- * more tweaking to get a "properly" rounded number. */
-
- freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
-
- debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
- freq);
- return freq;
-}
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- return ics307_clk_freq (
- in_8(pixis_base + PIXIS_VSYSCLK0),
- in_8(pixis_base + PIXIS_VSYSCLK1),
- in_8(pixis_base + PIXIS_VSYSCLK2)
- );
-}
-
-unsigned long
-get_board_ddr_clk(ulong dummy)
-{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- return ics307_clk_freq (
- in_8(pixis_base + PIXIS_VDDRCLK0),
- in_8(pixis_base + PIXIS_VDDRCLK1),
- in_8(pixis_base + PIXIS_VDDRCLK2)
- );
-}
-#else
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
- u8 i;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- i = in_8(pixis_base + PIXIS_SPD);
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33333333;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66666666;
- break;
- case 4:
- val = 83333333;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 133333333;
- break;
- case 7:
- val = 166666666;
- break;
- }
-
- return val;
-}
-
-unsigned long
-get_board_ddr_clk(ulong dummy)
-{
- u8 i;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- i = in_8(pixis_base + PIXIS_SPD);
- i &= 0x38;
- i >>= 3;
-
- switch (i) {
- case 0:
- val = 33333333;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66666666;
- break;
- case 4:
- val = 83333333;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 133333333;
- break;
- case 7:
- val = 166666666;
- break;
- }
- return val;
-}
-#endif
-
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
@@ -544,26 +396,8 @@
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#else
- ft_fsl_pci_setup(blob, "pci0", NULL);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#else
- ft_fsl_pci_setup(blob, "pci1", NULL);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#else
- ft_fsl_pci_setup(blob, "pci2", NULL);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
-#else
- ft_fsl_pci_setup(blob, "pci3", NULL);
-#endif
+ FT_FSL_PCI_SETUP;
+
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 9e3f677..f9ff827 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -117,7 +117,7 @@
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@@ -176,7 +176,7 @@
void
sdram_init(void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts(" SDRAM: ");
@@ -185,8 +185,8 @@
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CONFIG_SYS_OR2_PRELIM;
- lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index c30d966..0580fe7 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -291,7 +291,7 @@
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@@ -340,7 +340,7 @@
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@@ -352,16 +352,11 @@
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CONFIG_SYS_OR2_PRELIM;
- asm("msync");
-
- lbc->br2 = CONFIG_SYS_BR2_PRELIM;
- asm("msync");
-
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
-
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 0be2d89..da3a2b6 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -40,7 +40,7 @@
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
@@ -360,19 +360,8 @@
{
ft_cpu_setup(blob, bd);
+ FT_FSL_PCI_SETUP;
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE3
- ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
-#endif
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index aa3f32b..23e552b 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004, 2007, 200 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
@@ -118,7 +118,7 @@
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@@ -154,7 +154,7 @@
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@@ -166,16 +166,11 @@
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CONFIG_SYS_OR2_PRELIM;
- asm("msync");
-
- lbc->br2 = CONFIG_SYS_BR2_PRELIM;
- asm("msync");
-
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
-
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");
@@ -393,11 +388,6 @@
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_pci_setup(void *blob, bd_t *bd)
{
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
}
#endif
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index ecddd0d..b7e0e0c 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -291,7 +291,7 @@
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@@ -340,7 +340,7 @@
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@@ -352,12 +352,8 @@
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CONFIG_SYS_OR2_PRELIM;
- asm("msync");
-
- lbc->br2 = CONFIG_SYS_BR2_PRELIM;
- asm("msync");
-
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 2bca0f2..489f90b 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -322,7 +322,7 @@
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@@ -381,7 +381,7 @@
void
sdram_init(void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts(" SDRAM: ");
@@ -390,8 +390,8 @@
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CONFIG_SYS_OR2_PRELIM;
- lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 4ec13a9..bd859e4 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
@@ -181,7 +181,7 @@
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@@ -214,7 +214,7 @@
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint lsdmr_common;
@@ -225,16 +225,13 @@
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or2 = CONFIG_SYS_OR2_PRELIM;
- asm("msync");
-
- lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
asm("msync");
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
-
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");
@@ -429,11 +426,6 @@
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
}
#endif
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 1eddeef..01b7dcb 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor.
+ * Copyright 2009-2010 Freescale Semiconductor.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
@@ -308,7 +308,7 @@
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@@ -635,9 +635,8 @@
#endif
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
+
fdt_board_fixup_esdhc(blob, bd);
fdt_board_fixup_qe_uart(blob, bd);
fdt_board_fixup_qe_usb(blob, bd);
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 6029a51..6b96dfc 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -284,149 +284,6 @@
return 0;
}
-#ifdef CONFIG_GET_CLK_FROM_ICS307
-/* decode S[0-2] to Output Divider (OD) */
-static unsigned char ics307_S_to_OD[] = {
- 10, 2, 8, 4, 5, 7, 3, 6
-};
-
-/* Calculate frequency being generated by ICS307-02 clock chip based upon
- * the control bytes being programmed into it. */
-/* XXX: This function should probably go into a common library */
-static unsigned long
-ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
-{
- const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
- unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
- unsigned long RDW = cw2 & 0x7F;
- unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
- unsigned long freq;
-
- /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
-
- /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
- * cw1: V8 V7 V6 V5 V4 V3 V2 V1
- * cw2: V0 R6 R5 R4 R3 R2 R1 R0
- *
- * R6:R0 = Reference Divider Word (RDW)
- * V8:V0 = VCO Divider Word (VDW)
- * S2:S0 = Output Divider Select (OD)
- * F1:F0 = Function of CLK2 Output
- * TTL = duty cycle
- * C1:C0 = internal load capacitance for cyrstal
- */
-
- /* Adding 1 to get a "nicely" rounded number, but this needs
- * more tweaking to get a "properly" rounded number. */
-
- freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
-
- debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
- freq);
- return freq;
-}
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- return ics307_clk_freq (
- in_8(pixis_base + PIXIS_VSYSCLK0),
- in_8(pixis_base + PIXIS_VSYSCLK1),
- in_8(pixis_base + PIXIS_VSYSCLK2)
- );
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- return ics307_clk_freq (
- in_8(pixis_base + PIXIS_VDDRCLK0),
- in_8(pixis_base + PIXIS_VDDRCLK1),
- in_8(pixis_base + PIXIS_VDDRCLK2)
- );
-}
-#else
-unsigned long get_board_sys_clk(ulong dummy)
-{
- u8 i;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- i = in_8(pixis_base + PIXIS_SPD);
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33333333;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66666666;
- break;
- case 4:
- val = 83333333;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 133333333;
- break;
- case 7:
- val = 166666666;
- break;
- }
-
- return val;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
- u8 i;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- i = in_8(pixis_base + PIXIS_SPD);
- i &= 0x38;
- i >>= 3;
-
- switch (i) {
- case 0:
- val = 33333333;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66666666;
- break;
- case 4:
- val = 83333333;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 133333333;
- break;
- case 7:
- val = 166666666;
- break;
- }
- return val;
-}
-#endif
-
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
@@ -488,15 +345,8 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_PCIE3
- ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
+
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 2ef7b23..6578f58 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007,2009 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -309,15 +309,7 @@
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
-#endif
+ FT_FSL_PCI_SETUP;
}
#endif
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index 0b7f787..781a7c8 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -115,10 +115,8 @@
{
unsigned int addr;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
if (!strncmp(argv[1],"init",4)) {
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index bd357b8..8c8ce95 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -32,14 +32,14 @@
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M
* else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
* 0x8000_0000 0x9fff_ffff RapidIO 512M
* endif
* (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
- * 0xffc0_0000 0xffc0_ffff PCI1 IO 64K
- * 0xffc1_0000 0xffc1_ffff PCI2 IO 64K
+ * 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K
+ * 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K
* 0xffe0_0000 0xffef_ffff CCSRBAR 1M
* 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K
* 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M
@@ -54,10 +54,10 @@
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
#endif
#ifdef CONFIG_PCI
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
#elif defined(CONFIG_RIO)
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
#endif
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index b352c33..d86ca12 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2006, 2007 Freescale Semiconductor.
+ * Copyright 2006, 2007, 2010 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -129,21 +129,21 @@
#if defined(CONFIG_PCI)
-static struct pci_controller pci1_hose;
+static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCI */
-#ifdef CONFIG_PCI2
-static struct pci_controller pci2_hose;
-#endif /* CONFIG_PCI2 */
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif /* CONFIG_PCIE2 */
int first_free_busno = 0;
void pci_init_board(void)
{
-#ifdef CONFIG_PCI1
+#ifdef CONFIG_PCIE1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
+ struct pci_controller *hose = &pcie1_hose;
struct pci_region *r = hose->regions;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
@@ -169,16 +169,16 @@
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
+ CONFIG_SYS_PCIE1_IO_BUS,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
@@ -195,8 +195,8 @@
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
- + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
+ in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
+ + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
} else {
puts("PCI-EXPRESS 1: Disabled\n");
@@ -204,26 +204,26 @@
}
#else
puts("PCI-EXPRESS1: Disabled\n");
-#endif /* CONFIG_PCI1 */
+#endif /* CONFIG_PCIE1 */
-#ifdef CONFIG_PCI2
+#ifdef CONFIG_PCIE2
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
- struct pci_controller *hose = &pci2_hose;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
+ struct pci_controller *hose = &pcie2_hose;
struct pci_region *r = hose->regions;
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI2_MEM_BUS,
- CONFIG_SYS_PCI2_MEM_PHYS,
- CONFIG_SYS_PCI2_MEM_SIZE,
+ CONFIG_SYS_PCIE2_MEM_BUS,
+ CONFIG_SYS_PCIE2_MEM_PHYS,
+ CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI2_IO_BUS,
- CONFIG_SYS_PCI2_IO_PHYS,
- CONFIG_SYS_PCI2_IO_SIZE,
+ CONFIG_SYS_PCIE2_IO_BUS,
+ CONFIG_SYS_PCIE2_IO_PHYS,
+ CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
@@ -238,7 +238,7 @@
}
#else
puts("PCI-EXPRESS 2: Disabled\n");
-#endif /* CONFIG_PCI2 */
+#endif /* CONFIG_PCIE2 */
}
@@ -253,12 +253,7 @@
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCI2
- ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
-#endif
+ FT_FSL_PCI_SETUP;
/*
* Warn if it looks like the device tree doesn't match u-boot.
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
new file mode 100644
index 0000000..8ede2d6
--- /dev/null
+++ b/board/freescale/p1022ds/Makefile
@@ -0,0 +1,39 @@
+#
+# Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1022ds/config.mk b/board/freescale/p1022ds/config.mk
new file mode 100644
index 0000000..4581d20
--- /dev/null
+++ b/board/freescale/p1022ds/config.mk
@@ -0,0 +1,14 @@
+#
+# Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xeff80000
+endif
+
+RESET_VECTOR_ADDRESS = 0xeffffffc
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
new file mode 100644
index 0000000..7ecfb3e
--- /dev/null
+++ b/board/freescale/p1022ds/ddr.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
+{
+ int ret;
+
+ /*
+ * The P1022 has only one DDR controller, and the board has only one
+ * DIMM slot.
+ */
+ ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd,
+ sizeof(ddr3_spd_eeprom_t));
+ if (ret) {
+ debug("DDR: failed to read SPD from address %u\n",
+ SPD_EEPROM_ADDRESS1);
+ memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t));
+ }
+}
+
+typedef struct {
+ u32 datarate_mhz_low;
+ u32 datarate_mhz_high;
+ u32 n_ranks;
+ u32 clk_adjust; /* Range: 0-8 */
+ u32 cpo; /* Range: 2-31 */
+ u32 write_data_delay; /* Range: 0-6 */
+ u32 force_2T;
+} board_specific_parameters_t;
+
+static const board_specific_parameters_t bsp[] = {
+/*
+ * lo| hi| num| clk| cpo|wrdata|2T
+ * mhz| mhz|ranks|adjst| | delay|
+ */
+ { 0, 333, 1, 5, 31, 3, 0},
+ {334, 400, 1, 5, 31, 3, 0},
+ {401, 549, 1, 5, 31, 3, 0},
+ {550, 680, 1, 5, 31, 5, 0},
+ {681, 850, 1, 5, 31, 5, 0},
+ { 0, 333, 2, 5, 31, 3, 0},
+ {334, 400, 2, 5, 31, 3, 0},
+ {401, 549, 2, 5, 31, 3, 0},
+ {550, 680, 2, 5, 31, 5, 0},
+ {681, 850, 2, 5, 31, 5, 0},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ unsigned long ddr_freq;
+ unsigned int i;
+
+ /* set odt_rd_cfg and odt_wr_cfg. */
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 1;
+ }
+
+ /*
+ * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ for (i = 0; i < ARRAY_SIZE(bsp); i++) {
+ if (ddr_freq >= bsp[i].datarate_mhz_low &&
+ ddr_freq <= bsp[i].datarate_mhz_high &&
+ pdimm->n_ranks == bsp[i].n_ranks) {
+ popts->clk_adjust = bsp[i].clk_adjust;
+ popts->cpo_override = bsp[i].cpo;
+ popts->write_data_delay = bsp[i].write_data_delay;
+ popts->twoT_en = bsp[i].force_2T;
+ break;
+ }
+ }
+
+ popts->half_strength_driver_enable = 1;
+
+ /* Per AN4039, enable ZQ calibration. */
+ popts->zq_en = 1;
+
+ /*
+ * For wake-up on ARP, we need auto self refresh enabled
+ */
+ popts->auto_self_refresh_en = 1;
+ popts->sr_it = 0xb;
+}
diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c
new file mode 100644
index 0000000..b23b8f9
--- /dev/null
+++ b/board/freescale/p1022ds/law.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
new file mode 100644
index 0000000..5cdee9f
--- /dev/null
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <asm/mp.h>
+#include <netdev.h>
+#include <i2c.h>
+
+#include "../common/ngpixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, 0x1000);
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+ /* Set the pin muxing to enable ETSEC2. */
+ clrbits_be32(&gur->pmuxcr2, 0x001F8000);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u8 sw;
+
+ puts("Board: P1022DS ");
+
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+ sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+
+ switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
+ case 0:
+ printf ("vBank: %u\n", ((sw & 0x30) >> 4));
+ break;
+ case 1:
+ printf ("NAND\n");
+ break;
+ case 2:
+ case 3:
+ puts ("Promjet\n");
+ break;
+ }
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+ puts("Initializing....\n");
+
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+#define CONFIG_TFP410_I2C_ADDR 0x38
+
+int misc_init_r(void)
+{
+ u8 temp;
+
+ /* Enable the TFP410 Encoder */
+
+ temp = 0xBF;
+ if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
+ return -1;
+
+ /* Verify if enabled */
+ temp = 0;
+ if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
+ return -1;
+
+ debug("DVI Encoder Read: 0x%02x\n", temp);
+
+ temp = 0x10;
+ if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
+ return -1;
+
+ /* Verify if enabled */
+ temp = 0;
+ if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
+ return -1;
+
+ debug("DVI Encoder Read: 0x%02x\n",temp);
+
+ return 0;
+}
+
+/*
+ * A list of PCI and SATA slots
+ */
+enum slot_id {
+ SLOT_PCIE1 = 1,
+ SLOT_PCIE2,
+ SLOT_PCIE3,
+ SLOT_PCIE4,
+ SLOT_PCIE5,
+ SLOT_SATA1,
+ SLOT_SATA2
+};
+
+/*
+ * This array maps the slot identifiers to their names on the P1022DS board.
+ */
+static const char *slot_names[] = {
+ [SLOT_PCIE1] = "Slot 1",
+ [SLOT_PCIE2] = "Slot 2",
+ [SLOT_PCIE3] = "Slot 3",
+ [SLOT_PCIE4] = "Slot 4",
+ [SLOT_PCIE5] = "Mini-PCIe",
+ [SLOT_SATA1] = "SATA 1",
+ [SLOT_SATA2] = "SATA 2",
+};
+
+/*
+ * This array maps a given SERDES configuration and SERDES device to the PCI or
+ * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
+ */
+static u8 serdes_dev_slot[][SATA2 + 1] = {
+ [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
+ [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
+ [PCIE2] = SLOT_PCIE5 },
+ [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
+ [PCIE2] = SLOT_PCIE3,
+ [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
+ [PCIE2] = SLOT_PCIE3 },
+ [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
+ [PCIE2] = SLOT_PCIE3,
+ [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x1c] = { [PCIE1] = SLOT_PCIE1,
+ [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
+ [0x1f] = { [PCIE1] = SLOT_PCIE1 },
+};
+
+
+/*
+ * Returns the name of the slot to which the PCIe or SATA controller is
+ * connected
+ */
+const char *serdes_slot_name(enum srds_prtcl device)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ enum slot_id slot = serdes_dev_slot[srds_cfg][device];
+ const char *name = slot_names[slot];
+
+ if (name)
+ return name;
+ else
+ return "Nothing";
+}
+
+static void configure_pcie(struct fsl_pci_info *info,
+ struct pci_controller *hose,
+ const char *connected)
+{
+ static int bus_number = 0;
+ int is_endpoint;
+
+ set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
+ set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
+ is_endpoint = fsl_setup_hose(hose, info->regs);
+ printf(" PCIE%u connected to %s as %s (base addr %lx)\n",
+ info->pci_num, connected,
+ is_endpoint ? "Endpoint" : "Root Complex", info->regs);
+ bus_number = fsl_pci_init_port(info, hose, bus_number);
+}
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct fsl_pci_info pci_info;
+ u32 devdisr = in_be32(&gur->devdisr);
+
+#ifdef CONFIG_PCIE1
+ if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+ SET_STD_PCIE_INFO(pci_info, 1);
+ configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
+ } else {
+ printf(" PCIE1: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+ if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
+ SET_STD_PCIE_INFO(pci_info, 2);
+ configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
+ } else {
+ printf(" PCIE2: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE3
+ if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
+ SET_STD_PCIE_INFO(pci_info, 3);
+ configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
+ } else {
+ printf(" PCIE3: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
+#endif
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ return 0;
+}
+
+/*
+ * Initialize on-board and/or PCI Ethernet devices
+ *
+ * Returns:
+ * <0, error
+ * 0, no ethernet devices found
+ * >0, number of ethernet devices initialized
+ */
+int board_eth_init(bd_t *bis)
+{
+ struct tsec_info_struct tsec_info[2];
+ unsigned int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+
+ return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+}
+#endif
+
+#ifdef CONFIG_MP
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
new file mode 100644
index 0000000..e620112
--- /dev/null
+++ b/board/freescale/p1022ds/tlb.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_4K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index aa2f64c..97d4f83 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -100,16 +100,5 @@
void ft_pci_board_setup(void *blob)
{
-/* According to h/w manual, PCIE2 is at lower address(0x9000)
- * than PCIE1(0xa000).
- * Hence PCIE2 is made to occupy the pci1 position in dts to
- * keep the addresses sorted there.
- * Generally the case with all FSL SOCs.
- */
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
}
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index f0ff209..3fd1b34 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -313,155 +313,6 @@
return 0;
}
-#ifdef CONFIG_GET_CLK_FROM_ICS307
-/* decode S[0-2] to Output Divider (OD) */
-static unsigned char ics307_S_to_OD[] = {
- 10, 2, 8, 4, 5, 7, 3, 6
-};
-
-/* Calculate frequency being generated by ICS307-02 clock chip based upon
- * the control bytes being programmed into it. */
-/* XXX: This function should probably go into a common library */
-static unsigned long
-ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
-{
- const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
- unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
- unsigned long RDW = cw2 & 0x7F;
- unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
- unsigned long freq;
-
- /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
-
- /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
- * cw1: V8 V7 V6 V5 V4 V3 V2 V1
- * cw2: V0 R6 R5 R4 R3 R2 R1 R0
- *
- * R6:R0 = Reference Divider Word (RDW)
- * V8:V0 = VCO Divider Word (VDW)
- * S2:S0 = Output Divider Select (OD)
- * F1:F0 = Function of CLK2 Output
- * TTL = duty cycle
- * C1:C0 = internal load capacitance for cyrstal
- */
-
- /* Adding 1 to get a "nicely" rounded number, but this needs
- * more tweaking to get a "properly" rounded number. */
-
- freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
-
- debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
- freq);
- return freq;
-}
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- return gd->bus_clk;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
- return gd->mem_clk;
-}
-
-unsigned long calculate_board_sys_clk(ulong dummy)
-{
- ulong val;
-
- val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
- in_8(&pixis->sclk[2]));
- debug("sysclk val = %lu\n", val);
- return val;
-}
-
-unsigned long calculate_board_ddr_clk(ulong dummy)
-{
- ulong val;
-
- val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
- in_8(&pixis->dclk[2]));
- debug("ddrclk val = %lu\n", val);
- return val;
-}
-#else
-unsigned long get_board_sys_clk(ulong dummy)
-{
- u8 i;
- ulong val = 0;
-
- i = in_8(&pixis->spd);
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33333333;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66666666;
- break;
- case 4:
- val = 83333333;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 133333333;
- break;
- case 7:
- val = 166666666;
- break;
- }
-
- return val;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
- u8 i;
- ulong val = 0;
-
- i = in_8(&pixis->spd);
- i &= 0x38;
- i >>= 3;
-
- switch (i) {
- case 0:
- val = 33333333;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66666666;
- break;
- case 4:
- val = 83333333;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 133333333;
- break;
- case 7:
- val = 166666666;
- break;
- }
- return val;
-}
-#endif
-
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
@@ -515,15 +366,8 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_PCIE3
- ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
+
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
diff --git a/board/gth/README b/board/gth/README
deleted file mode 100644
index 241c70b..0000000
--- a/board/gth/README
+++ /dev/null
@@ -1,18 +0,0 @@
-Written by Thomas.Lange@corelatus.com 010805
-
-To make a system for gth that actually works ;-)
-the variable TBASE needs to be set to 0,1 or 2
-depending on location where image is supposed to
-be started from.
-E.g. make TBASE=1
-
-0: Start from RAM, base 0
-
-1: Start from flash_base + 0x10070
-
-2: Start from flash_base + 0x30070
-
-When using 1 or 2, the image is supposed to be launched
-from miniboot that boots the first U-Boot image found in
-flash.
-For miniboot code, description, see www.opensource.se
diff --git a/board/gth/ee_access.c b/board/gth/ee_access.c
deleted file mode 100644
index 2a33a0e..0000000
--- a/board/gth/ee_access.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/* Module for handling DALLAS DS2438, smart battery monitor
- Chip can store up to 40 bytes of user data in EEPROM,
- perform temp, voltage and current measurements.
- Chip also contains a unique serial number.
-
- Always read/write LSb first
-
- For documentaion, see data sheet for DS2438, 2438.pdf
-
- By Thomas.Lange@corelatus.com 001025 */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-#include <../board/gth/ee_dev.h>
-
-/* We dont have kernel functions */
-#define printk printf
-#define KERN_DEBUG
-#define KERN_ERR
-#define EIO 1
-
-static int Debug = 0;
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-/*
- * lookup table ripped from DS app note 17, understanding and using
- * cyclic redundancy checks...
- */
-
-static u8 crc_lookup[256] = {
- 0, 94, 188, 226, 97, 63, 221, 131,
- 194, 156, 126, 32, 163, 253, 31, 65,
- 157, 195, 33, 127, 252, 162, 64, 30,
- 95, 1, 227, 189, 62, 96, 130, 220,
- 35, 125, 159, 193, 66, 28, 254, 160,
- 225, 191, 93, 3, 128, 222, 60, 98,
- 190, 224, 2, 92, 223, 129, 99, 61,
- 124, 34, 192, 158, 29, 67, 161, 255,
- 70, 24, 250, 164, 39, 121, 155, 197,
- 132, 218, 56, 102, 229, 187, 89, 7,
- 219, 133, 103, 57, 186, 228, 6, 88,
- 25, 71, 165, 251, 120, 38, 196, 154,
- 101, 59, 217, 135, 4, 90, 184, 230,
- 167, 249, 27, 69, 198, 152, 122, 36,
- 248, 166, 68, 26, 153, 199, 37, 123,
- 58, 100, 134, 216, 91, 5, 231, 185,
- 140, 210, 48, 110, 237, 179, 81, 15,
- 78, 16, 242, 172, 47, 113, 147, 205,
- 17, 79, 173, 243, 112, 46, 204, 146,
- 211, 141, 111, 49, 178, 236, 14, 80,
- 175, 241, 19, 77, 206, 144, 114, 44,
- 109, 51, 209, 143, 12, 82, 176, 238,
- 50, 108, 142, 208, 83, 13, 239, 177,
- 240, 174, 76, 18, 145, 207, 45, 115,
- 202, 148, 118, 40, 171, 245, 23, 73,
- 8, 86, 180, 234, 105, 55, 213, 139,
- 87, 9, 235, 181, 54, 104, 138, 212,
- 149, 203, 41, 119, 244, 170, 72, 22,
- 233, 183, 85, 11, 136, 214, 52, 106,
- 43, 117, 151, 201, 74, 20, 246, 168,
- 116, 42, 200, 150, 21, 75, 169, 247,
- 182, 232, 10, 84, 215, 137, 107, 53
-};
-
-static u8 make_new_crc( u8 Old_crc, u8 New_value ){
- /* Compute a new checksum with new byte, using previous checksum as input
- See DS app note 17, understanding and using cyclic redundancy checks...
- Also see DS2438, page 11 */
- return( crc_lookup[Old_crc ^ New_value ]);
-}
-
-int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
- /* Check if the checksum for this buffer is correct */
- u8 Curr_crc=0;
- int i;
- u8 *Curr_byte = Buffer;
-
- for(i=0;i<Len;i++){
- Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
- Curr_byte++;
- }
- E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
-
- if(Curr_crc == Crc){
- /* Good */
- return(TRUE);
- }
- printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n",
- Curr_crc, Crc);
- return(FALSE);
-}
-
-static void
-set_idle(void){
- /* Send idle and keep start time
- Continous 1 is idle */
- WRITE_PORT(1);
-}
-
-static int
-do_reset(void){
- /* Release reset and verify that chip responds with presence pulse */
- int Retries = 0;
- while(Retries<5){
- udelay(RESET_LOW_TIME);
-
- /* Send reset */
- WRITE_PORT(0);
- udelay(RESET_LOW_TIME);
-
- /* Release reset */
- WRITE_PORT(1);
-
- /* Wait for EEPROM to drive output */
- udelay(PRESENCE_TIMEOUT);
- if(!READ_PORT){
- /* Ok, EEPROM is driving a 0 */
- E_DEBUG("Presence detected\n");
- if(Retries){
- E_DEBUG("Retries %d\n",Retries);
- }
- /* Make sure chip releases pin */
- udelay(PRESENCE_LOW_TIME);
- return 0;
- }
- Retries++;
- }
-
- printk(KERN_ERR"EEPROM did not respond when releasing reset\n");
-
- /* Make sure chip releases pin */
- udelay(PRESENCE_LOW_TIME);
-
- /* Set to idle again */
- set_idle();
-
- return(-EIO);
-}
-
-static u8
-read_byte(void){
- /* Read a single byte from EEPROM
- Read LSb first */
- int i;
- int Value;
- u8 Result=0;
-#ifndef CONFIG_SYS_IMMR
- u32 Flags;
-#endif
-
- E_DEBUG("Reading byte\n");
-
- for(i=0;i<8;i++){
- /* Small delay between pulses */
- udelay(1);
-
-#ifndef CONFIG_SYS_IMMR
- /* Disable irq */
- save_flags(Flags);
- cli();
-#endif
-
- /* Pull down pin short time to start read
- See page 26 in data sheet */
-
- WRITE_PORT(0);
- udelay(READ_LOW);
- WRITE_PORT(1);
-
- /* Wait for chip to drive pin */
- udelay(READ_TIMEOUT);
-
- Value = READ_PORT;
- if(Value)
- Value=1;
-
-#ifndef CONFIG_SYS_IMMR
- /* Enable irq */
- restore_flags(Flags);
-#endif
-
- /* Wait for chip to release pin */
- udelay(TOTAL_READ_LOW-READ_TIMEOUT);
-
- /* LSb first */
- Result|=Value<<i;
- }
-
- E_DEBUG("Read byte 0x%x\n",Result);
-
- return(Result);
-}
-
-static void
-write_byte(u8 Byte){
- /* Write a single byte to EEPROM
- Write LSb first */
- int i;
- int Value;
-#ifndef CONFIG_SYS_IMMR
- u32 Flags;
-#endif
-
- E_DEBUG("Writing byte 0x%x\n",Byte);
-
- for(i=0;i<8;i++){
- /* Small delay between pulses */
- udelay(1);
- Value = Byte&1;
-
-#ifndef CONFIG_SYS_IMMR
- /* Disable irq */
- save_flags(Flags);
- cli();
-#endif
-
- /* Pull down pin short time for a 1, long time for a 0
- See page 26 in data sheet */
-
- WRITE_PORT(0);
- if(Value){
- /* Write a 1 */
- udelay(WRITE_1_LOW);
- }
- else{
- /* Write a 0 */
- udelay(WRITE_0_LOW);
- }
-
- WRITE_PORT(1);
-
-#ifndef CONFIG_SYS_IMMR
- /* Enable irq */
- restore_flags(Flags);
-#endif
-
- if(Value)
- /* Wait for chip to read the 1 */
- udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
- Byte>>=1;
- }
-}
-
-int ee_do_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
- /* Execute this command string, including
- giving reset and setting to idle after command
- if Rx_len is set, we read out data from EEPROM */
- int i;
-
- E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
-
- if(do_reset()){
- /* Failed! */
- return(-EIO);
- }
-
- if(Send_skip)
- /* Always send SKIP_ROM first to tell chip we are sending a command,
- except when we read out rom data for chip */
- write_byte(SKIP_ROM);
-
- /* Always have Tx data */
- for(i=0;i<Tx_len;i++){
- write_byte(Tx[i]);
- }
-
- if(Rx_len){
- for(i=0;i<Rx_len;i++){
- Rx[i]=read_byte();
- }
- }
-
- set_idle();
-
- E_DEBUG("Command done\n");
-
- return(0);
-}
-
-int ee_init_data(void){
- int i;
- u8 Tx[10];
- int tmp;
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-
- while(0){
- tmp = 1-tmp;
- if(tmp)
- immap->im_ioport.iop_padat &= ~PA_FRONT_LED;
- else
- immap->im_ioport.iop_padat |= PA_FRONT_LED;
- udelay(1);
- }
-
- /* Set port to open drain to be able to read data from
- port without setting it to input */
- PORT_B_PAR &= ~PB_EEPROM;
- PORT_B_ODR |= PB_EEPROM;
- SET_PORT_B_OUTPUT(PB_EEPROM);
-
- /* Set idle mode */
- set_idle();
-
- /* Copy all User EEPROM data to scratchpad */
- for(i=0;i<USER_PAGES;i++){
- Tx[0]=RECALL_MEMORY;
- Tx[1]=EE_USER_PAGE_0+i;
- if(ee_do_command(Tx,2,NULL,0,TRUE)) return(-EIO);
- }
-
- /* Make sure chip doesnt store measurements in NVRAM */
- Tx[0]=WRITE_SCRATCHPAD;
- Tx[1]=0; /* Page */
- Tx[2]=9;
- if(ee_do_command(Tx,3,NULL,0,TRUE)) return(-EIO);
-
- Tx[0]=COPY_SCRATCHPAD;
- if(ee_do_command(Tx,2,NULL,0,TRUE)) return(-EIO);
-
- /* FIXME check status bit instead
- Could take 10 ms to store in EEPROM */
- for(i=0;i<10;i++){
- udelay(1000);
- }
-
- return(0);
-}
diff --git a/board/gth/ee_access.h b/board/gth/ee_access.h
deleted file mode 100644
index e847f2c..0000000
--- a/board/gth/ee_access.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* By Thomas.Lange@Corelatus.com 001025
-
- Definitions for EEPROM/VOLT METER DS2438 */
-
-#ifndef INCeeaccessh
-#define INCeeaccessh
-
-int ee_do_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
-int ee_init_data(void);
-int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-
-#endif /* INCeeaccessh */
diff --git a/board/gth/ee_dev.h b/board/gth/ee_dev.h
deleted file mode 100644
index 3004b46..0000000
--- a/board/gth/ee_dev.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* By Thomas.Lange@Corelatus.com 001025
- $Revision: 1.6 $
-
- Definitions for EEPROM/VOLT METER DS2438
- Copyright (C) 2000-2001 Corelatus AB */
-
-#ifndef INCeedevh
-#define INCeedevh
-
-#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
-
-#define PORT_B_PAR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar
-#define PORT_B_ODR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr
-#define PORT_B_DIR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir
-#define PORT_B_DAT ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat
-
-#define SET_PORT_B_INPUT(Mask) PORT_B_DIR &= ~(Mask)
-#define SET_PORT_B_OUTPUT(Mask) PORT_B_DIR |= Mask
-
-#define WRITE_PORT_B(Mask,Value) { \
- if (Value) PORT_B_DAT |= Mask; \
- else PORT_B_DAT &= ~(Mask); \
- }
-#define WRITE_PORT(Value) WRITE_PORT_B(PB_EEPROM,Value)
-
-#define READ_PORT (PORT_B_DAT&PB_EEPROM)
-
-/* 64 bytes chip */
-#define EE_CHIP_SIZE 64
-
-/* We use this resistor for measuring the current drain on 3.3V */
-#define CURRENT_RESISTOR 0.022
-
-/* microsecs
- Pull line down at least this long for reset pulse */
-#define RESET_LOW_TIME 490
-
-/* Read presence pulse after we release reset pulse */
-#define PRESENCE_TIMEOUT 100
-#define PRESENCE_LOW_TIME 200
-
-#define WRITE_0_LOW 80
-#define WRITE_1_LOW 2
-#define TOTAL_WRITE_LOW 80
-
-#define READ_LOW 2
-#define READ_TIMEOUT 10
-#define TOTAL_READ_LOW 80
-
-/*** Rom function commands ***/
-#define READ_ROM 0x33
-#define MATCH_ROM 0x55
-#define SKIP_ROM 0xCC
-#define SEARCH_ROM 0xF0
-
-
-/*** Memory_command_function ***/
-#define WRITE_SCRATCHPAD 0x4E
-#define READ_SCRATCHPAD 0xBE
-#define COPY_SCRATCHPAD 0x48
-#define RECALL_MEMORY 0xB8
-#define CONVERT_TEMP 0x44
-#define CONVERT_VOLTAGE 0xB4
-
-/* Chip is divided in 8 pages, 8 bytes each */
-
-#define EE_PAGE_SIZE 8
-
-/* All chip data we want are in page 0 */
-
-/* Bytes in page 0 */
-#define EE_P0_STATUS 0
-#define EE_P0_TEMP_LSB 1
-#define EE_P0_TEMP_MSB 2
-#define EE_P0_VOLT_LSB 3
-#define EE_P0_VOLT_MSB 4
-#define EE_P0_CURRENT_LSB 5
-#define EE_P0_CURRENT_MSB 6
-
-
-/* 40 byte user data is located at page 3-7 */
-#define EE_USER_PAGE_0 3
-#define USER_PAGES 5
-
-#endif /* INCeedevh */
diff --git a/board/gth/flash.c b/board/gth/flash.c
deleted file mode 100644
index 169270b..0000000
--- a/board/gth/flash.c
+++ /dev/null
@@ -1,649 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET 0x01
-#define FLAG_PROTECT_CLEAR 0x02
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
- int i;
-
- /*printf("faking");*/
-
- return(0x1fffff);
-
- /* Init: no FLASHes known */
- for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN)
- {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
-#if 0
- if (FLASH_BASE1_PRELIM != 0x0) {
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,size_b0, size_b0<<20);
-
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
- } else {
-#endif
- size_b1 = 0;
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
- memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- if (size_b1)
- {
- /* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
- &flash_info[1]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[1]);
-#endif
- }
- else
- {
-/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- FIXME memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
- return (size_b0 + size_b1);
-}
-
-
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start adress table */
- if (info->flash_id & FLASH_BTYPE)
- {
- /* set sector offsets for bottom boot block type */
- for (i = 0; i < info->sector_count; i++)
- {
- info->start[i] = base + (i * 0x00040000);
- }
- }
- else
- {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- for (; i >= 0; i--)
- {
- info->start[i] = base + i * 0x00040000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
-
-#if 0
- case FLASH_AM040B:
- printf ("AM29F040B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM040T:
- printf ("AM29F040T (4 Mbit, top boot sect)\n");
- break;
-#endif
- case FLASH_AM400B:
- printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i=0; i<info->sector_count; ++i)
- {
- if ((i % 5) == 0)
- {
- printf ("\n ");
- }
-
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
-
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
-#if 0
- ulong base = (ulong)addr;
-#endif
- ulong value;
-
- /* Write auto select command: read Manufacturer ID */
-#if 0
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-#else
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0x90909090;
-#endif
-
- value = addr[0];
-
- switch (value)
- {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- value = addr[1]; /* device ID */
-
- switch (value)
- {
-#if 0
- case AMD_ID_F040B:
- info->flash_id += FLASH_AM040B;
- info->sector_count = 8;
- info->size = 0x00200000;
- break; /* => 2 MB */
-#endif
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
-#if 0
- /* set up sector start adress table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-#else
- flash_get_offsets ((ulong)addr, &flash_info[0]);
-#endif
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++)
- {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN)
- {
- addr = (volatile unsigned long *)info->start[0];
-#if 0
- *addr = 0x00F000F0; /* reset bank */
-#else
- *addr = 0xF0F0F0F0; /* reset bank */
-#endif
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
-#if 0
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-#else
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0x80808080;
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
-#endif
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
-#if 0
- addr[0] = 0x00300030;
-#else
- addr[0] = 0x30303030;
-#endif
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
-#if 0
- while ((addr[0] & 0x00800080) != 0x00800080)
-#else
- while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
-#endif
- {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
-#if 0
- addr[0] = 0x00F000F0; /* reset bank */
-#else
- addr[0] = 0xF0F0F0F0; /* reset bank */
-#endif
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
-#if 0
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-#else
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0xA0A0A0A0;
-#endif
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
-#if 0
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
-#else
- while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
-#endif
- {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/gth/gth.c b/board/gth/gth.c
deleted file mode 100644
index 4399db2..0000000
--- a/board/gth/gth.c
+++ /dev/null
@@ -1,595 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Adapted from FADS and other board config files to GTH by thomas@corelatus.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <watchdog.h>
-#include <mpc8xx.h>
-#include "ee_access.h"
-#include "ee_dev.h"
-
-#ifdef CONFIG_BDM
-#undef printf
-#define printf(a,...) /* nothing */
-#endif
-
-
-int checkboard (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- int Id = 0;
- int Rev = 0;
- u32 Pbdat;
-
- puts ("Board: ");
-
- /* Turn on leds and setup for reading rev and id */
-
-#define PB_OUTS (PB_BLUE_LED|PB_ID_GND)
-#define PB_INS (PB_ID_0|PB_ID_1|PB_ID_2|PB_ID_3|PB_REV_1|PB_REV_0)
-
- immap->im_cpm.cp_pbpar &= ~(PB_OUTS | PB_INS);
-
- immap->im_cpm.cp_pbdir &= ~PB_INS;
-
- immap->im_cpm.cp_pbdir |= PB_OUTS;
- immap->im_cpm.cp_pbodr |= PB_OUTS;
- immap->im_cpm.cp_pbdat &= ~PB_OUTS;
-
- /* Hold 100 Mbit in reset until fpga is loaded */
- immap->im_ioport.iop_pcpar &= ~PC_ENET100_RESET;
- immap->im_ioport.iop_pcdir |= PC_ENET100_RESET;
- immap->im_ioport.iop_pcso &= ~PC_ENET100_RESET;
- immap->im_ioport.iop_pcdat &= ~PC_ENET100_RESET;
-
- /* Turn on front led to show that we are alive */
- immap->im_ioport.iop_papar &= ~PA_FRONT_LED;
- immap->im_ioport.iop_padir |= PA_FRONT_LED;
- immap->im_ioport.iop_paodr |= PA_FRONT_LED;
- immap->im_ioport.iop_padat &= ~PA_FRONT_LED;
-
- Pbdat = immap->im_cpm.cp_pbdat;
-
- if (!(Pbdat & PB_ID_0))
- Id += 1;
- if (!(Pbdat & PB_ID_1))
- Id += 2;
- if (!(Pbdat & PB_ID_2))
- Id += 4;
- if (!(Pbdat & PB_ID_3))
- Id += 8;
-
- if (Pbdat & PB_REV_0)
- Rev += 1;
- if (Pbdat & PB_REV_1)
- Rev += 2;
-
- /* Turn ID off since we dont need it anymore */
- immap->im_cpm.cp_pbdat |= PB_ID_GND;
-
- printf ("GTH board, rev %d, id=0x%01x\n", Rev, Id);
- return 0;
-}
-
-#define _NOT_USED_ 0xffffffff
-const uint sdram_table[] = {
- /* Single read, offset 0 */
- 0x0f3dfc04, 0x0eefbc04, 0x01bf7c04, 0x0feafc00,
- 0x1fb5fc45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* Burst read, Offset 0x8, 4 reads */
- 0x0f3dfc04, 0x0eefbc04, 0x00bf7c04, 0x00ffec00,
- 0x00fffc00, 0x01eafc00, 0x1fb5fc00, 0xfffffc45,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* Not used part of burst read is used for MRS, Offset 0x14 */
- 0xefeabc34, 0x1fb57c34, 0xfffffc05, _NOT_USED_,
- /* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */
-
- /* Single write, Offset 0x18 */
- 0x0f3dfc04, 0x0eebbc00, 0x01a27c04, 0x1fb5fc45,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* Burst write, Offset 0x20. 4 writes */
- 0x0f3dfc04, 0x0eebbc00, 0x00b77c00, 0x00fffc00,
- 0x00fffc00, 0x01eafc04, 0x1fb5fc45, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* Not used part of burst write is used for precharge, Offset 0x2C */
- 0x0ff5fc04, 0xfffffc05, _NOT_USED_, _NOT_USED_,
- /* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */
-
- /* Period timer service. Offset 0x30. Refresh. Wait at least 70 ns after refresh command */
- 0x1ffd7c04, 0xfffffc04, 0xfffffc04, 0xfffffc05,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* Exception, Offset 0x3C */
- 0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_
-};
-
-const uint fpga_table[] = {
- /* Single read, offset 0 */
- 0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
- 0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
-
- /* Burst read, Offset 0x8 */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* Single write, Offset 0x18 */
- 0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
- 0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
-
- /* Burst write, Offset 0x20. */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* Period timer service. Offset 0x30. */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* Exception, Offset 0x3C */
- 0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_
-};
-
-int _initsdram (uint base, uint * noMbytes)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *mc = &immap->im_memctl;
- volatile u32 *memptr;
-
- mc->memc_mptpr = MPTPR_PTP_DIV16; /* (16-17) */
-
- /* SDRAM in UPMA
-
- GPL_0 is connected instead of A19 to SDRAM.
- According to table 16-17, AMx should be 001, i.e. type 1
- and GPL_0 should hold address A10 when multiplexing */
-
- mc->memc_mamr = (0x2E << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_AMA_TYPE_1 | MAMR_G0CLA_A10 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X; /* (16-13) */
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /* Perform init of sdram ( Datasheet Page 9 )
- Precharge */
- mc->memc_mcr = 0x8000212C; /* run upm a at 0x2C (16-15) */
-
- /* Run 2 refresh cycles */
- mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */
- mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */
-
- /* Set Mode register */
- mc->memc_mar = 0x00000088; /* set mode register (address) to 0x022 (16-17) */
- /* Lower 2 bits are not connected to chip */
- mc->memc_mcr = 0x80002114; /* run upm a at 0x14 (16-15) */
-
- /* CS1, base 0x0000000 - 64 Mbyte, use UPM A */
- mc->memc_or1 = 0xfc000000 | OR_CSNT_SAM;
- mc->memc_br1 = BR_MS_UPMA | BR_V; /* SDRAM base always 0 */
-
- /* Test if we really have 64 MB SDRAM */
- memptr = (u32 *) 0;
- *memptr = 0;
-
- memptr = (u32 *) 0x2000000; /* First u32 in upper 32 MB */
- *memptr = 0x12345678;
-
- memptr = (u32 *) 0;
- if (*memptr == 0x12345678) {
- /* Wrapped, only have 32 MB */
- mc->memc_or1 = 0xfe000000 | OR_CSNT_SAM;
- *noMbytes = 32;
- } else {
- /* 64 MB */
- *noMbytes = 64;
- }
-
- /* Setup FPGA in UPMB */
- upmconfig (UPMB, (uint *) fpga_table,
- sizeof (fpga_table) / sizeof (uint));
-
- /* Enable UPWAITB */
- mc->memc_mbmr = MBMR_GPL_B4DIS; /* (16-13) */
-
- /* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */
- mc->memc_or2 = 0xffc00000 | OR_BI;
- mc->memc_br2 = FPGA_2_BASE | BR_MS_UPMB | BR_V;
-
- /* CS3, base FPGA_3_BASE - 4 MByte, use UPM B 16 bit */
- mc->memc_or3 = 0xffc00000 | OR_BI;
- mc->memc_br3 = FPGA_3_BASE | BR_MS_UPMB | BR_V | BR_PS_16;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void _sdramdisable (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_br1 = 0x00000000;
-
- /* maybe we should turn off upmb here or something */
-}
-
-/* ------------------------------------------------------------------------- */
-
-int initsdram (uint base, uint * noMbytes)
-{
- *noMbytes = 32;
-
-#ifdef CONFIG_START_IN_RAM
- /* SDRAM is already setup. Dont touch it */
- return 0;
-#else
-
- if (!_initsdram (base, noMbytes)) {
-
- return 0;
- } else {
- _sdramdisable ();
-
- return -1;
- }
-#endif
-}
-
-phys_size_t initdram (int board_type)
-{
- u32 *i;
- u32 j;
- u32 k;
-
- /* GTH only have SDRAM */
- uint sdramsz;
-
- if (!initsdram (0x00000000, &sdramsz)) {
- printf ("(%u MB SDRAM) ", sdramsz);
- } else {
- /********************************
- *SDRAM ERROR, HALT PROCESSOR
- *********************************/
- printf ("SDRAM ERROR\n");
- while (1);
- }
-
-#ifndef CONFIG_START_IN_RAM
-
-#define U32_S ((sdramsz<<18)-1)
-
-#if 1
- /* Do a simple memory test */
- for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) {
- *i = j + (j << 17);
- *(i + 1) = ~(j + (j << 18));
- }
-
- WATCHDOG_RESET ();
-
- printf (".");
-
- for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) {
- k = *i;
- if (k != (j + (j << 17))) {
- printf ("Mem test error, i=0x%x, 0x%x\n, 0x%x", (u32) i, j, k);
- while (1);
- }
- k = *(i + 1);
- if (k != ~(j + (j << 18))) {
- printf ("Mem test error(+1), i=0x%x, 0x%x\n, 0x%x",
- (u32) i + 1, j, k);
- while (1);
- }
- }
-#endif
-
- WATCHDOG_RESET ();
-
- /* Clear memory */
- for (i = (u32 *) 0; (u32) i < U32_S; i++) {
- *i = 0;
- }
-#endif /* !start in ram */
-
- WATCHDOG_RESET ();
-
- return (sdramsz << 20);
-}
-
-#define POWER_OFFSET 0xF0000
-#define SW_WATCHDOG_REASON 13
-
-#define BOOTDATA_OFFSET 0xF8000
-#define MAX_ATTEMPTS 5
-
-#define FAILSAFE_BOOT 1
-#define SYSTEM_BOOT 2
-
-#define WRITE_FLASH16(a, d) \
-do \
-{ \
- *((volatile u16 *) (a)) = (d);\
- } while(0)
-
-static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
-{
- u16 data;
- volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
-
- if ((System != FAILSAFE_BOOT) & (System != SYSTEM_BOOT)) {
- printf ("Invalid system data %u, setting failsafe\n", System);
- System = FAILSAFE_BOOT;
- }
-
- if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
- printf ("Invalid boot count %u, setting 1\n", Count);
- Count = 1;
- }
-
- if (System == FAILSAFE_BOOT) {
- printf ("Setting failsafe boot in flash\n");
- } else {
- printf ("Setting system boot in flash\n");
- }
- printf ("Boot attempt %d\n", Count);
-
- data = (System << 8) | Count;
- /* AMD 16 bit */
- WRITE_FLASH16 (&flash[0x555], 0xAAAA);
- WRITE_FLASH16 (&flash[0x2AA], 0x5555);
- WRITE_FLASH16 (&flash[0x555], 0xA0A0);
-
- WRITE_FLASH16 (addr, data);
-}
-
-static void maybe_update_restart_reason (volatile u32 * addr32)
-{
- /* Update addr if sw wd restart */
- volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
- volatile u16 *addr_16 = (u16 *) addr32;
- u32 rsr;
-
- /* Dont reset register now */
- rsr = ((volatile immap_t *) CONFIG_SYS_IMMR)->im_clkrst.car_rsr;
-
- rsr >>= 24;
-
- if (rsr & 0x10) {
- /* Was really a sw wd restart, update reason */
-
- printf ("Last restart by software watchdog\n");
-
- /* AMD 16 bit */
- WRITE_FLASH16 (&flash[0x555], 0xAAAA);
- WRITE_FLASH16 (&flash[0x2AA], 0x5555);
- WRITE_FLASH16 (&flash[0x555], 0xA0A0);
-
- WRITE_FLASH16 (addr_16, 0);
-
- udelay (1000);
-
- WATCHDOG_RESET ();
-
- /* AMD 16 bit */
- WRITE_FLASH16 (&flash[0x555], 0xAAAA);
- WRITE_FLASH16 (&flash[0x2AA], 0x5555);
- WRITE_FLASH16 (&flash[0x555], 0xA0A0);
-
- WRITE_FLASH16 (addr_16 + 1, SW_WATCHDOG_REASON);
-
- }
-}
-
-static void check_restart_reason (void)
-{
- /* Update restart reason if sw watchdog was
- triggered */
-
- int i;
- volatile u32 *raddr;
-
- raddr = (u32 *) (CONFIG_SYS_FLASH_BASE + POWER_OFFSET);
-
- if (*raddr == 0xFFFFFFFF) {
- /* Nothing written */
- maybe_update_restart_reason (raddr);
- } else {
- /* Search for latest written reason */
- i = 0;
- while ((*(raddr + 2) != 0xFFFFFFFF) & (i < 2000)) {
- raddr += 2;
- i++;
- }
- if (i >= 2000) {
- /* Whoa, dont write any more */
- printf ("*** No free restart reason found ***\n");
- } else {
- /* Check if written */
- if (*raddr == 0) {
- /* Erased by kernel, no new reason written */
- maybe_update_restart_reason (raddr + 2);
- }
- }
- }
-}
-
-static void check_boot_tries (void)
-{
- /* Count the number of boot attemps
- switch system if too many */
-
- int i;
- volatile u16 *addr;
- volatile u16 data;
- int failsafe = 1;
- u8 system;
- u8 count;
-
- addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET);
-
- if (*addr == 0xFFFF) {
- printf ("*** No bootdata exists. ***\n");
- write_bootdata (addr, FAILSAFE_BOOT, 1);
- } else {
- /* Search for latest written bootdata */
- i = 0;
- while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
- addr++;
- i++;
- }
- if (i >= 8000) {
- /* Whoa, dont write any more */
- printf ("*** No bootdata found. Not updating flash***\n");
- } else {
- /* See how many times we have tried to boot real system */
- data = *addr;
- system = data >> 8;
- count = data & 0xFF;
- if ((system != SYSTEM_BOOT) & (system != FAILSAFE_BOOT)) {
- printf ("*** Wrong system %d\n", system);
- system = FAILSAFE_BOOT;
- count = 1;
- } else {
- switch (count) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- /* Try same system again if needed */
- count++;
- break;
-
- case 5:
- /* Switch system and reset tries */
- count = 1;
- system = 3 - system;
- printf ("***Too many boot attempts, switching system***\n");
- break;
- default:
- /* Switch system, start over and hope it works */
- printf ("***Unexpected data on addr 0x%x, %u***\n",
- (u32) addr, data);
- count = 1;
- system = 3 - system;
- }
- }
- write_bootdata (addr + 1, system, count);
- if (system == SYSTEM_BOOT) {
- failsafe = 0;
- }
- }
- }
- if (failsafe) {
- printf ("Booting failsafe system\n");
- setenv ("bootargs", "panic=1 root=/dev/hda7");
- setenv ("bootcmd", "disk 100000 0:5;bootm 100000");
- } else {
- printf ("Using normal system\n");
- setenv ("bootargs", "panic=1 root=/dev/hda4");
- setenv ("bootcmd", "disk 100000 0:2;bootm 100000");
- }
-}
-
-int misc_init_r (void)
-{
- u8 Rx[80];
- u8 Tx[5];
- int page;
- int read = 0;
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- /* Kill fpga */
- immap->im_ioport.iop_papar &= ~(PA_FL_CONFIG | PA_FL_CE);
- immap->im_ioport.iop_padir |= (PA_FL_CONFIG | PA_FL_CE);
- immap->im_ioport.iop_paodr &= ~(PA_FL_CONFIG | PA_FL_CE);
-
- /* Enable fpga, active low */
- immap->im_ioport.iop_padat &= ~PA_FL_CE;
-
- /* Start configuration */
- immap->im_ioport.iop_padat &= ~PA_FL_CONFIG;
- udelay (2);
-
- immap->im_ioport.iop_padat |= (PA_FL_CONFIG | PA_FL_CE);
-
- /* Check if we need to boot failsafe system */
- check_boot_tries ();
-
- /* Check if we need to update restart reason */
- check_restart_reason ();
-
- if (ee_init_data ()) {
- printf ("EEPROM init failed\n");
- return (0);
- }
-
- /* Read the pages where ethernet address is stored */
-
- for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
- /* Copy from nvram to scratchpad */
- Tx[0] = RECALL_MEMORY;
- Tx[1] = page;
- if (ee_do_command (Tx, 2, NULL, 0, TRUE)) {
- printf ("EE user page %d recall failed\n", page);
- return (0);
- }
-
- Tx[0] = READ_SCRATCHPAD;
- if (ee_do_command (Tx, 2, Rx + read, 9, TRUE)) {
- printf ("EE user page %d read failed\n", page);
- return (0);
- }
- /* Crc in 9:th byte */
- if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
- printf ("EE read failed, page %d. CRC error\n", page);
- return (0);
- }
- read += 8;
- }
-
- /* Add eos after eth addr */
- Rx[17] = 0;
-
- printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
-
- if ((Rx[2] != ':') |
- (Rx[5] != ':') |
- (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
- printf ("*** ethernet addr invalid, using default ***\n");
- } else {
- setenv ("ethaddr", (char *)Rx);
- }
- return (0);
-}
diff --git a/board/gth/pcmcia.c b/board/gth/pcmcia.c
deleted file mode 100644
index a4db16d..0000000
--- a/board/gth/pcmcia.c
+++ /dev/null
@@ -1,93 +0,0 @@
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "GTH COMPACT FLASH"
-
-int pcmcia_voltage_set (int slot, int vcc, int vpp)
-{ /* Do nothing */
- return 0;
-}
-
-int pcmcia_hardware_enable (int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, mask;
-
- debug ("hardware_enable: GTH Slot %c\n", 'A' + slot);
-
- immap = (immap_t *) CONFIG_SYS_IMMR;
- sysp = (sysconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_cpm));
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX (_slot_) = reg;
- udelay (500);
-
- /*
- * Make sure there is a card in the slot,
- * then configure the interface.
- */
- udelay (10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__, __FUNCTION__,
- &(pcmp->pcmc_pipr), pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & 0x98000000) {
- printf (" No Card found\n");
- return (1);
- }
-
- mask = PCMCIA_VS1 (slot) | PCMCIA_VS2 (slot);
- reg = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- reg,
- (reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
- (reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX (_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX (_slot_) = reg;
-
- udelay (250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return 0;
-}
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
- return 0; /* No hardware to disable */
-}
-#endif
-
-#endif /* CONFIG_PCMCIA */
diff --git a/board/gth/u-boot.lds b/board/gth/u-boot.lds
deleted file mode 100644
index 4145a91..0000000
--- a/board/gth/u-boot.lds
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o(.text)
- *(.text)
- common/env_embedded.o(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c
index 5dd0311..9a92941 100644
--- a/board/hymod/bsp.c
+++ b/board/hymod/bsp.c
@@ -272,8 +272,7 @@
break;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
fpga, 6, 1, do_fpga,
@@ -324,8 +323,7 @@
/* fall through ... */
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
memset (data, 0, HYMOD_EEPROM_SIZE);
diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c
index b5bebd4..d2ac7a5 100644
--- a/board/ibf-dsp561/ibf-dsp561.c
+++ b/board/ibf-dsp561/ibf-dsp561.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -16,3 +17,10 @@
printf(" Support: http://www.i-syst.com/\n");
return 0;
}
+
+#ifdef CONFIG_DRIVER_AX88180
+int board_eth_init(bd_t *bis)
+{
+ return ax88180_initialize(bis);
+}
+#endif
diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c
index 637bb5a..cf82f61 100644
--- a/board/inka4x0/inkadiag.c
+++ b/board/inka4x0/inkadiag.c
@@ -168,8 +168,7 @@
printf("exit code: 0x%X\n", val);
return 0;
default:
- cmd_usage(cmdtp);
- break;
+ return cmd_usage(cmdtp);
}
return -1;
@@ -244,10 +243,8 @@
int combrd, baudrate, i, j, len;
int address;
- if (argc < 5) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 5)
+ return cmd_usage(cmdtp);
argc--;
argv++;
@@ -394,10 +391,8 @@
unsigned int period, freq;
int prev, i;
- if (argc != 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 3)
+ return cmd_usage(cmdtp);
argc--;
argv++;
@@ -474,8 +469,7 @@
return c->cmd(c, flag, argc, argv);
} else {
/* Unrecognized command */
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
}
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 3a33b5a..d7cbd7a 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -186,10 +186,8 @@
int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 tmp;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
if ((strcmp(argv[1], "off") == 0)) {
printf("SPI FLASH disabled, NAND enabled\n");
@@ -214,8 +212,7 @@
tmp = readl(KW_GPIO0_BASE);
writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
} else {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return 0;
diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c
index 6455d1d..e9f6625 100644
--- a/board/logicpd/zoom2/zoom2.c
+++ b/board/logicpd/zoom2/zoom2.c
@@ -46,7 +46,7 @@
/*
* This the the zoom2, board specific, gpmc configuration for the
* quad uart on the debug board. The more general gpmc configurations
- * are setup at the cpu level in arch/arm/cpu/arm_cortexa8/omap3/mem.c
+ * are setup at the cpu level in arch/arm/cpu/armv7/omap3/mem.c
*
* The details of the setting of the serial gpmc setup are not available.
* The values were provided by another party.
diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index 61a1e14..9d6c21f 100644
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@@ -845,8 +845,7 @@
default:
break;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
pic, 4, 1, do_pic,
@@ -975,8 +974,7 @@
default:
break;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 3948c13..ec113e7 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -306,20 +306,15 @@
int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
- if ((strcmp(argv[1], "on") == 0)) {
+ if ((strcmp(argv[1], "on") == 0))
gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
- } else if ((strcmp(argv[1], "off") == 0)) {
+ else if ((strcmp(argv[1], "off") == 0))
gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
- } else {
- cmd_usage(cmdtp);
- return 1;
- }
-
+ else
+ return cmd_usage(cmdtp);
return 0;
}
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
index 7c27233..054d644 100644
--- a/board/mpc8540eval/mpc8540eval.c
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -69,7 +69,7 @@
long dram_size = 0;
#if !defined(CONFIG_RAM_AS_FLASH)
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
@@ -110,8 +110,8 @@
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
- lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
- lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index a3722b2..b4343d8 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -528,8 +528,7 @@
return 0;
}
#endif
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c
index 199def4..4a91458 100644
--- a/board/pcippc2/pcippc2.c
+++ b/board/pcippc2/pcippc2.c
@@ -232,8 +232,7 @@
default:
break;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index d7adff2..a61e945 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -616,9 +616,8 @@
int rcode = -1;
if (argc < 2) {
- usage:
- cmd_usage(cmdtp);
- return 1;
+usage:
+ return cmd_usage(cmdtp);
}
if (argc >= 3) {
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
index 29a095d..e3abeb8 100644
--- a/board/pdm360ng/pdm360ng.c
+++ b/board/pdm360ng/pdm360ng.c
@@ -635,10 +635,8 @@
static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
return set_lcd_brightness(argv[1]);
}
diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c
index 5353d73..a302b91 100644
--- a/board/pm854/pm854.c
+++ b/board/pm854/pm854.c
@@ -134,7 +134,7 @@
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c
index b14a3d3..f9d92d9 100644
--- a/board/pm856/pm856.c
+++ b/board/pm856/pm856.c
@@ -290,7 +290,7 @@
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c
index 7329435..692160c 100644
--- a/board/pn62/cmd_pn62.c
+++ b/board/pn62/cmd_pn62.c
@@ -36,20 +36,20 @@
/*
* Command led: controls the various LEDs 0..11 on the PN62 card.
*/
-int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_led(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
{
- unsigned int number, function;
+ unsigned int number, function;
- if (argc != 3) {
- cmd_usage(cmdtp);
- return 1;
- }
- number = simple_strtoul(argv[1], NULL, 10);
- if (number > PN62_LED_MAX)
- return 1;
- function = simple_strtoul(argv[2], NULL, 16);
- set_led (number, function);
- return 0;
+ if (argc != 3)
+ return cmd_usage(cmdtp);
+
+ number = simple_strtoul(argv[1], NULL, 10);
+ if (number > PN62_LED_MAX)
+ return 1;
+
+ function = simple_strtoul(argv[2], NULL, 16);
+ set_led(number, function);
+ return 0;
}
U_BOOT_CMD(
led , 3, 1, do_led,
@@ -83,8 +83,7 @@
addr = simple_strtoul(argv[1], NULL, 16);
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
printf ("## Ready for image download ...\n");
diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c
index 3f2deed..83b7914 100644
--- a/board/prodrive/pdnb3/pdnb3.c
+++ b/board/prodrive/pdnb3/pdnb3.c
@@ -214,10 +214,8 @@
{
ulong addr;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
addr = simple_strtoul(argv[1], NULL, 16);
diff --git a/board/renesas/sh7785lcr/rtl8169_mac.c b/board/renesas/sh7785lcr/rtl8169_mac.c
index dae01ec..e15013f 100644
--- a/board/renesas/sh7785lcr/rtl8169_mac.c
+++ b/board/renesas/sh7785lcr/rtl8169_mac.c
@@ -304,10 +304,8 @@
unsigned char mac[6];
char *s, *e;
- if (argc != 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 2)
+ return cmd_usage(cmdtp);
s = argv[1];
@@ -330,10 +328,8 @@
int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (argc != 1) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 1)
+ return cmd_usage(cmdtp);
mac_read();
diff --git a/board/renesas/sh7785lcr/selfcheck.c b/board/renesas/sh7785lcr/selfcheck.c
index 44247c8..6d92c83 100644
--- a/board/renesas/sh7785lcr/selfcheck.c
+++ b/board/renesas/sh7785lcr/selfcheck.c
@@ -112,10 +112,8 @@
{
char *cmd;
- if (argc != 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 2)
+ return cmd_usage(cmdtp);
cmd = argv[1];
switch (cmd[0]) {
@@ -150,8 +148,7 @@
test_net();
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return 0;
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index c7835de..e41c84c 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -387,13 +387,6 @@
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
-#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init(gd->bd);
-#endif
}
#endif
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 34861d4..50fae7c 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -160,7 +160,7 @@
void sdram_init(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbc = &immap->lbus;
+ volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: ");
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 194f6ab..733979c 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -116,7 +116,7 @@
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@@ -152,7 +152,7 @@
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint lsdmr_common;
@@ -163,22 +163,14 @@
/*
* Setup SDRAM Base and Option Registers
*/
- out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
- asm("msync");
-
- out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
- asm("msync");
-
- out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
- asm("msync");
-
- out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
- asm("msync");
+ set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
+ set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+ set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
+ set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
asm("msync");
-
out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
asm("msync");
@@ -406,11 +398,9 @@
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
+
+#ifdef CONFIG_FSL_PCI_INIT
+ FT_FSL_PCI_SETUP;
#endif
}
#endif
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index c40b5e3..10ba62f 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -269,7 +269,7 @@
#if 0
#if !defined(CONFIG_RAM_AS_FLASH)
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
@@ -310,8 +310,8 @@
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
- lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
- lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
index d20fa51..705e1c2 100644
--- a/board/sbc8641d/law.c
+++ b/board/sbc8641d/law.c
@@ -32,11 +32,11 @@
*
* 0x0000_0000 DDR 256M
* 0x1000_0000 DDR2 256M
- * 0x8000_0000 PCI1 MEM 512M
- * 0xa000_0000 PCI2 MEM 512M
+ * 0x8000_0000 PCIE1 MEM 512M
+ * 0xa000_0000 PCIE2 MEM 512M
* 0xc000_0000 RapidIO 512M
- * 0xe200_0000 PCI1 IO 16M
- * 0xe300_0000 PCI2 IO 16M
+ * 0xe200_0000 PCIE1 IO 16M
+ * 0xe300_0000 PCIE2 IO 16M
* 0xf800_0000 CCSRBAR 2M
* 0xfe00_0000 FLASH (boot bank) 32M
*
@@ -49,11 +49,11 @@
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
#endif
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index c4e9875..54b2d0b 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -191,16 +191,16 @@
};
#endif
-static struct pci_controller pci1_hose = {
+static struct pci_controller pcie1_hose = {
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc86xxcts_config_table
#endif
};
#endif /* CONFIG_PCI */
-#ifdef CONFIG_PCI2
-static struct pci_controller pci2_hose;
-#endif /* CONFIG_PCI2 */
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif /* CONFIG_PCIE2 */
int first_free_busno = 0;
@@ -212,10 +212,10 @@
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
-#ifdef CONFIG_PCI1
+#ifdef CONFIG_PCIE1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
+ struct pci_controller *hose = &pcie1_hose;
struct pci_region *r = hose->regions;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
@@ -236,16 +236,16 @@
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
+ CONFIG_SYS_PCIE1_IO_BUS,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
@@ -264,26 +264,26 @@
}
#else
puts("PCI-EXPRESS1: Disabled\n");
-#endif /* CONFIG_PCI1 */
+#endif /* CONFIG_PCIE1 */
-#ifdef CONFIG_PCI2
+#ifdef CONFIG_PCIE2
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
- struct pci_controller *hose = &pci2_hose;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
+ struct pci_controller *hose = &pcie2_hose;
struct pci_region *r = hose->regions;
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI2_MEM_BUS,
- CONFIG_SYS_PCI2_MEM_PHYS,
- CONFIG_SYS_PCI2_MEM_SIZE,
+ CONFIG_SYS_PCIE2_MEM_BUS,
+ CONFIG_SYS_PCIE2_MEM_PHYS,
+ CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI2_IO_BUS,
- CONFIG_SYS_PCI2_IO_PHYS,
- CONFIG_SYS_PCI2_IO_SIZE,
+ CONFIG_SYS_PCIE2_IO_BUS,
+ CONFIG_SYS_PCIE2_IO_PHYS,
+ CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
@@ -298,7 +298,7 @@
}
#else
puts("PCI-EXPRESS 2: Disabled\n");
-#endif /* CONFIG_PCI2 */
+#endif /* CONFIG_PCIE2 */
}
@@ -308,12 +308,7 @@
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCI2
- ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
-#endif
+ FT_FSL_PCI_SETUP;
}
#endif
diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c
index ebb70a2..ba59943 100644
--- a/board/sheldon/simpc8313/sdram.c
+++ b/board/sheldon/simpc8313/sdram.c
@@ -129,7 +129,7 @@
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbc= &im->lbus;
+ volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c
index cb30b48..c2164c9 100644
--- a/board/sheldon/simpc8313/simpc8313.c
+++ b/board/sheldon/simpc8313/simpc8313.c
@@ -93,7 +93,7 @@
{
int rc = 0;
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- fsl_lbus_t *lbus = &immap->lbus;
+ fsl_lbc_t *lbus = &immap->im_lbc;
u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
/* UPM Table Configuration Code */
diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c
index 5660c09..ef8bfde 100644
--- a/board/siemens/common/fpga.c
+++ b/board/siemens/common/fpga.c
@@ -286,8 +286,7 @@
return 0;
failure:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c
index 14d75ea..9795284 100644
--- a/board/siemens/pcu_e/pcu_e.c
+++ b/board/siemens/pcu_e/pcu_e.c
@@ -399,8 +399,7 @@
default:
break;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD (puma, 4, 1, do_puma,
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 9183c15..72e7401 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -87,8 +87,6 @@
int misc_init_r (void)
{
- volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
/*
* Adjust flash start and offset to detected values
*/
@@ -99,8 +97,10 @@
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
- memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
- memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
+ set_lbc_or(0, gd->bd->bi_flashstart |
+ (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+ set_lbc_br(0, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address
@@ -112,8 +112,8 @@
* Check if only one FLASH bank is available
*/
if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
- memctl->or1 = 0;
- memctl->br1 = 0;
+ set_lbc_or(1, 0);
+ set_lbc_br(1, 0);
/*
* Re-do flash protection upon new addresses
@@ -148,7 +148,7 @@
*/
void local_bus_init (void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
sys_info_t sysinfo;
uint clkdiv;
@@ -299,26 +299,25 @@
int lime_probe(void)
{
- volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint cfg_br2;
uint cfg_or2;
int type;
- cfg_br2 = memctl->br2;
- cfg_or2 = memctl->or2;
+ cfg_br2 = get_lbc_br(2);
+ cfg_or2 = get_lbc_or(2);
/* Configure GPCM for CS2 */
- memctl->br2 = 0;
- memctl->or2 = 0xfc000410;
- memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
+ set_lbc_br(2, 0);
+ set_lbc_or(2, 0xfc000410);
+ set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
/* Get controller type */
type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
/* Restore previous CS2 configuration */
- memctl->br2 = 0;
- memctl->or2 = cfg_or2;
- memctl->br2 = cfg_br2;
+ set_lbc_br(2, 0);
+ set_lbc_or(2, cfg_or2);
+ set_lbc_br(2, cfg_br2);
return (type == MB862XX_TYPE_LIME) ? 1 : 0;
}
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index d99036b..0562222 100644
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -215,10 +215,8 @@
char *s, *e;
char i2c_mac[20];
- if ((argc > 3) || (argc < 2)) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if ((argc > 3) || (argc < 2))
+ return cmd_usage(cmdtp);
if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
@@ -286,8 +284,7 @@
return 0;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
diff --git a/board/t3corp/chip_config.c b/board/t3corp/chip_config.c
index c00bf16..98ab49f 100644
--- a/board/t3corp/chip_config.c
+++ b/board/t3corp/chip_config.c
@@ -27,13 +27,27 @@
struct ppc4xx_config ppc4xx_config_val[] = {
{
- "600", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ "600-67", "CPU: 600 PLB: 200 OPB: 67 EBC: 67",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
{
0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
+ "667", "CPU: 667 PLB: 166 OPB: 83 EBC: 83",
+ {
+ 0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
+ 0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
"800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
{
0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
diff --git a/board/t3corp/init.S b/board/t3corp/init.S
index 4a4217f..ecd35ff 100644
--- a/board/t3corp/init.S
+++ b/board/t3corp/init.S
@@ -81,11 +81,13 @@
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
/* TLB-entry for FPGA(s) */
- tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4,
+ tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4,
+ tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
+ CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4,
+ tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
AC_RW | SA_IG)
/* TLB-entry for OCM */
diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c
index 8ffa321..ddf5897 100644
--- a/board/t3corp/t3corp.c
+++ b/board/t3corp/t3corp.c
@@ -45,7 +45,7 @@
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile
index 3812ba1..bad018a 100644
--- a/board/tcm-bf537/Makefile
+++ b/board/tcm-bf537/Makefile
@@ -29,7 +29,7 @@
LIB = $(obj)lib$(BOARD).a
-COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o
+COBJS-y := $(BOARD).o gpio_cfi_flash.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/tcm-bf537/flash.c b/board/tcm-bf537/flash.c
deleted file mode 100644
index 14055c6..0000000
--- a/board/tcm-bf537/flash.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * flash.c - helper commands for working with GPIO-assisted flash
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong faddr = CONFIG_SYS_FLASH_BASE;
- ushort data;
- ulong dflg;
-
- if (argc == 3) {
- dflg = simple_strtoul(argv[1], NULL, 16);
- faddr |= (dflg << 21);
- dflg = simple_strtoul(argv[2], NULL, 16);
- faddr |= (dflg << 22);
- gpio_cfi_flash_swizzle((void *)faddr);
- } else {
- data = bfin_read_PORTFIO();
- printf("Port F data %04x (PF4:%i PF5:%i)\n", data,
- !!(data & PF4), !!(data & PF5));
- }
-
- return 0;
-}
-
-U_BOOT_CMD(pf, 3, 0, do_pf,
- "set/clear PF4/PF5 GPIO flash bank switch\n",
- "<pf4> <pf5> - set PF4/PF5 GPIO pin state\n");
diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c
index ac8587c..08ea7af 100644
--- a/board/tcm-bf537/gpio_cfi_flash.c
+++ b/board/tcm-bf537/gpio_cfi_flash.c
@@ -8,12 +8,13 @@
#include <common.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include "gpio_cfi_flash.h"
-#define GPIO_PIN_1 PF4
+#define GPIO_PIN_1 GPIO_PF4
#define GPIO_MASK_1 (1 << 21)
-#define GPIO_PIN_2 PF5
+#define GPIO_PIN_2 GPIO_PF5
#define GPIO_MASK_2 (1 << 22)
#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2)
@@ -21,16 +22,10 @@
{
unsigned long addr = (unsigned long)vaddr;
- if (addr & GPIO_MASK_1)
- bfin_write_PORTFIO_SET(GPIO_PIN_1);
- else
- bfin_write_PORTFIO_CLEAR(GPIO_PIN_1);
+ gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
#ifdef GPIO_MASK_2
- if (addr & GPIO_MASK_2)
- bfin_write_PORTFIO_SET(GPIO_PIN_2);
- else
- bfin_write_PORTFIO_CLEAR(GPIO_PIN_2);
+ gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
#endif
SSYNC();
@@ -57,6 +52,9 @@
void gpio_cfi_flash_init(void)
{
- bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1 | GPIO_PIN_2);
+ gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
+#ifdef GPIO_MASK_2
+ gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+#endif
gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
}
diff --git a/board/gth/Makefile b/board/ti/panda/Makefile
similarity index 84%
copy from board/gth/Makefile
copy to board/ti/panda/Makefile
index 4b5c528..81e5469 100644
--- a/board/gth/Makefile
+++ b/board/ti/panda/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -12,7 +12,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@@ -25,15 +25,20 @@
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
+COBJS := panda.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
#########################################################################
# defines $(obj).depend target
diff --git a/board/altera/ep1c20/config.mk b/board/ti/panda/config.mk
similarity index 62%
rename from board/altera/ep1c20/config.mk
rename to board/ti/panda/config.mk
index dab2740..7382263 100644
--- a/board/altera/ep1c20/config.mk
+++ b/board/ti/panda/config.mk
@@ -1,6 +1,9 @@
#
-# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
-# Scott McNutt <smcnutt@psyent.com>
+# (C) Copyright 2006-2009
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# OMAP 4430 SDP
+# see http://www.ti.com/ for more information on Texas Instruments
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -12,7 +15,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@@ -20,12 +23,10 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
+# SDRAM Address Space:
+# 8000'0000 - 9fff'ffff (512 MB)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
-TEXT_BASE = 0x01fc0000
-
-PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
+# Let's place u-boot 1MB before the end of SDRAM.
+TEXT_BASE = 0x9ff00000
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
new file mode 100644
index 0000000..917bbec
--- /dev/null
+++ b/board/ti/panda/panda.c
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: OMAP4 Panda\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure Panda board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ return 0;
+}
diff --git a/board/gth/Makefile b/board/ti/sdp4430/Makefile
similarity index 84%
copy from board/gth/Makefile
copy to board/ti/sdp4430/Makefile
index 4b5c528..2554c7b 100644
--- a/board/gth/Makefile
+++ b/board/ti/sdp4430/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -12,7 +12,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@@ -25,15 +25,20 @@
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
+COBJS := sdp.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
#########################################################################
# defines $(obj).depend target
diff --git a/board/altera/ep1c20/config.mk b/board/ti/sdp4430/config.mk
similarity index 62%
copy from board/altera/ep1c20/config.mk
copy to board/ti/sdp4430/config.mk
index dab2740..7382263 100644
--- a/board/altera/ep1c20/config.mk
+++ b/board/ti/sdp4430/config.mk
@@ -1,6 +1,9 @@
#
-# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
-# Scott McNutt <smcnutt@psyent.com>
+# (C) Copyright 2006-2009
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# OMAP 4430 SDP
+# see http://www.ti.com/ for more information on Texas Instruments
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -12,7 +15,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@@ -20,12 +23,10 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
+# SDRAM Address Space:
+# 8000'0000 - 9fff'ffff (512 MB)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
-TEXT_BASE = 0x01fc0000
-
-PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
+# Let's place u-boot 1MB before the end of SDRAM.
+TEXT_BASE = 0x9ff00000
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
new file mode 100644
index 0000000..8ed7873
--- /dev/null
+++ b/board/ti/sdp4430/sdp.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: OMAP4430 SDP\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP;
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure SDP board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ return 0;
+}
diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c
index 0db7050..0789c58 100644
--- a/board/tqc/tqm5200/cmd_stk52xx.c
+++ b/board/tqc/tqm5200/cmd_stk52xx.c
@@ -327,8 +327,7 @@
switch (argc) {
case 0:
case 1:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
case 2:
if (strncmp(argv[1],"saw",3) == 0) {
printf ("Play sawtooth\n");
@@ -342,8 +341,7 @@
return rcode;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
case 3:
if (strncmp(argv[1],"saw",3) == 0) {
duration = simple_strtoul(argv[2], NULL, 10);
@@ -358,8 +356,7 @@
LEFT_RIGHT);
return rcode;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
case 4:
if (strncmp(argv[1],"saw",3) == 0) {
duration = simple_strtoul(argv[2], NULL, 10);
@@ -382,8 +379,7 @@
pcm1772_write_reg((uchar)reg, (uchar)val);
return 0;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
case 5:
if (strncmp(argv[1],"saw",3) == 0) {
duration = simple_strtoul(argv[2], NULL, 10);
@@ -412,8 +408,7 @@
channel);
return rcode;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
return 1;
@@ -513,8 +508,7 @@
channel = LEFT_RIGHT;
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
if ((tmp = getenv ("volume")) != NULL) {
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index e564879..8d046f4 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -253,10 +253,10 @@
debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
/* set OR0 and BR0 */
- im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH |
- (-(total_size) & OR_GPCM_AM);
- im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) |
- (BR_MS_GPCM | BR_PS_32 | BR_V);
+ set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
+ (-(total_size) & OR_GPCM_AM));
+ set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
+ (BR_MS_GPCM | BR_PS_32 | BR_V));
return (0);
}
diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
index 3da689a..4b16c31 100644
--- a/board/tqc/tqm85xx/nand.c
+++ b/board/tqc/tqm85xx/nand.c
@@ -377,7 +377,7 @@
*/
static void upmb_write (u_char addr, ulong val)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
out_be32 (&lbc->mdr, val);
@@ -393,14 +393,14 @@
/*
* Initialize UPM for NAND flash access.
*/
-static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
+static void nand_upm_setup (volatile fsl_lbc_t *lbc)
{
uint i, j;
uint or3 = CONFIG_SYS_OR3_PRELIM;
uint clock = get_lbc_clock ();
- out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */
- out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
+ set_lbc_br(3, 0); /* disable bank and reset all bits */
+ set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
/*
* Search appropriate UPM table for bus clock.
@@ -424,7 +424,7 @@
/* EAD must be set due to TQM8548 timing specification */
or3 |= OR_UPM_EAD;
- out_be32 (&lbc->or3, or3);
+ set_lbc_or(3, or3);
/* Assign address of table */
nand_upm_patt = upm_freq_table[i].upm_patt;
@@ -458,7 +458,7 @@
int board_nand_init (struct nand_chip *nand)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
if (!nand_upm_patt)
nand_upm_setup (lbc);
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 8c9d586..dda2cb6 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -269,8 +269,6 @@
int misc_init_r (void)
{
- volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
/*
* Adjust flash start and offset to detected values
*/
@@ -281,26 +279,27 @@
* Recalculate CS configuration if second FLASH bank is available
*/
if (flash_info[0].size > 0) {
- memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
- (CONFIG_SYS_OR1_PRELIM & 0x00007fff);
- memctl->br1 = gd->bd->bi_flashstart |
- (CONFIG_SYS_BR1_PRELIM & 0x00007fff);
+ set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
+ (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
+ set_lbc_br(1, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address for bank 1
*/
flash_get_size (gd->bd->bi_flashstart, 0);
} else {
- memctl->or1 = 0;
- memctl->br1 = 0;
+ set_lbc_or(1, 0);
+ set_lbc_br(1, 0);
}
/*
* If bank 1 is equipped, bank 0 is mapped after bank 1
*/
- memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
- (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
- memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
- (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
+ set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
+ (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+ set_lbc_br(0, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
/*
* Re-check to get correct base address for bank 0
*/
@@ -341,7 +340,7 @@
*/
static void upmc_write (u_char addr, uint val)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
out_be32 (&lbc->mdr, val);
@@ -358,7 +357,7 @@
uint get_lbc_clock (void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sys_info;
ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
@@ -386,7 +385,7 @@
void local_bus_init (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint lbc_mhz = get_lbc_clock () / 1000000;
#ifdef CONFIG_MPC8548
@@ -502,10 +501,10 @@
* set if Local Bus Clock is > 83 MHz.
*/
if (lbc_mhz > 83)
- out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
+ set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
else
- out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
- out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
+ set_lbc_or(2, CONFIG_SYS_OR2_CAN);
+ set_lbc_br(2, CONFIG_SYS_BR2_CAN);
/* LGPL4 is UPWAIT */
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
@@ -688,12 +687,7 @@
{
ft_cpu_setup (blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c
index 6d23470..ca4415c 100644
--- a/board/trab/cmd_trab.c
+++ b/board/trab/cmd_trab.c
@@ -167,10 +167,8 @@
int i;
int cycle_status;
- if (argc > 1) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc > 1)
+ return cmd_usage(cmdtp);
led_init ();
global_vars_init ();
@@ -270,14 +268,11 @@
{
int i, dip;
- if (argc > 1) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc > 1)
+ return cmd_usage(cmdtp);
- if ((dip = read_dip ()) == -1) {
+ if ((dip = read_dip ()) == -1)
return 1;
- }
for (i = 0; i < 4; i++) {
if ((dip & (1 << i)) == 0)
@@ -303,14 +298,11 @@
{
int vcc5v;
- if (argc > 1) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc > 1)
+ return cmd_usage(cmdtp);
- if ((vcc5v = read_vcc5v ()) == -1) {
+ if ((vcc5v = read_vcc5v ()) == -1)
return (1);
- }
printf ("%d", (vcc5v / 1000));
printf (".%d", (vcc5v % 1000) / 100);
@@ -331,10 +323,8 @@
{
int contact_temp;
- if (argc > 1) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc > 1)
+ return cmd_usage(cmdtp);
tsc2000_spi_init ();
@@ -354,36 +344,32 @@
int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (argc > 1) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc > 1)
+ return cmd_usage(cmdtp);
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
- (unsigned char*) &status, 1)) {
+ (unsigned char*) &status, 1))
return (1);
- }
+
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
- (unsigned char*) &pass_cycles, 2)) {
+ (unsigned char*) &pass_cycles, 2))
return (1);
- }
+
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
- 1, (unsigned char*) &first_error_cycle, 2)) {
+ 1, (unsigned char*) &first_error_cycle, 2))
return (1);
- }
+
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
- 1, (unsigned char*) &first_error_num, 1)) {
+ 1, (unsigned char*) &first_error_num, 1))
return (1);
- }
+
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
1, (unsigned char*)first_error_name,
- sizeof (first_error_name))) {
+ sizeof (first_error_name)))
return (1);
- }
- if (read_max_cycles () != 0) {
+ if (read_max_cycles () != 0)
return (1);
- }
printf ("max_cycles = %d\n", max_cycles);
printf ("status = %d\n", status);
@@ -850,14 +836,11 @@
struct rtc_time tm;
#endif
- if (argc > 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc > 2)
+ return cmd_usage(cmdtp);
- if (argc > 1) {
+ if (argc > 1)
delay = simple_strtoul(argv[1], NULL, 10);
- }
tsc2000_spi_init ();
while (1) {
diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c
index fede2e0..fd623df 100644
--- a/board/trizepsiv/eeprom.c
+++ b/board/trizepsiv/eeprom.c
@@ -42,36 +42,29 @@
static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
int offset,value;
- if (argc < 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 4)
+ return cmd_usage(cmdtp);
offset=simple_strtoul(argv[2],NULL,16);
value=simple_strtoul(argv[3],NULL,16);
if (offset > 0x40) {
printf("Wrong offset : 0x%x\n",offset);
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
dm9000_write_srom_word(offset, value);
return (0);
}
int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
- if (strcmp (argv[1],"read") == 0) {
+ if (strcmp (argv[1],"read") == 0)
return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
- } else if (strcmp (argv[1],"write") == 0) {
+ else if (strcmp (argv[1],"write") == 0)
return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
- } else {
- cmd_usage(cmdtp);
- return 1;
- }
+ else
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
diff --git a/board/gth/Makefile b/board/ve8313/Makefile
similarity index 90%
rename from board/gth/Makefile
rename to board/ve8313/Makefile
index 4b5c528..c95f90e 100644
--- a/board/gth/Makefile
+++ b/board/ve8313/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -25,7 +25,7 @@
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
+COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
@@ -34,6 +34,12 @@
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
#########################################################################
# defines $(obj).depend target
diff --git a/board/ve8313/config.mk b/board/ve8313/config.mk
new file mode 100644
index 0000000..02dd33e
--- /dev/null
+++ b/board/ve8313/config.mk
@@ -0,0 +1,7 @@
+ifndef NAND_SPL
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+endif
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xfe000000
+endif
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
new file mode 100644
index 0000000..8ba1b19
--- /dev/null
+++ b/board/ve8313/ve8313.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <ns16550.h>
+#include <nand.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void disable_addr_trans (void);
+extern void enable_addr_trans (void);
+
+int checkboard(void)
+{
+ puts("Board: ve8313\n");
+ return 0;
+}
+
+static long fixed_sdram(void)
+{
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ u32 msize_log2 = __ilog2(msize);
+
+ out_be32(&im->sysconf.ddrlaw[0].bar,
+ (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+ out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
+ out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+ /*
+ * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+ * or the DDR2 controller may fail to initialize correctly.
+ */
+ __udelay(50000);
+
+ out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+
+ /* Currently we use only one CS, so disable the other bank. */
+ out_be32(&im->ddr.cs_config[1], 0);
+
+ out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+ out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+ out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+
+ out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+ out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ sync();
+
+ /* enable DDR controller */
+ setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+
+ /* now check the real size */
+ disable_addr_trans ();
+ msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
+ enable_addr_trans ();
+#endif
+
+ return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile fsl_lbus_t *lbc = &im->lbus;
+ u32 msize;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ msize = fixed_sdram();
+
+ /* Local Bus setup lbcr and mrtpr */
+ out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+ out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+ sync();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
+
+#define VE8313_WDT_EN 0x00020000
+#define VE8313_WDT_TRIG 0x00040000
+
+int board_early_init_f (void)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
+
+#if defined(CONFIG_HW_WATCHDOG)
+ /* enable WDT */
+ clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
+#else
+ /* disable WDT */
+ setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
+#endif
+ /* set WDT pins as output */
+ setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
+
+ return 0;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
+ unsigned long reg;
+
+ reg = in_be32(&gpio->dat);
+ if (reg & VE8313_WDT_TRIG)
+ clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
+ else
+ setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
+}
+#endif
+
+
+#if defined(CONFIG_PCI)
+static struct pci_region pci_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ }
+};
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci_regions };
+ int warmboot;
+
+ /* Enable all 3 PCI_CLK_OUTPUTs. */
+ setbits_be32(&clk->occr, 0xe0000000);
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
+ out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
+ out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
+
+ warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
+
+ mpc83xx_pci_init(1, reg, warmboot);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+}
+#endif
diff --git a/board/gth/Makefile b/board/vpac270/Makefile
similarity index 74%
copy from board/gth/Makefile
copy to board/vpac270/Makefile
index 4b5c528..0f3eacd 100644
--- a/board/gth/Makefile
+++ b/board/vpac270/Makefile
@@ -1,5 +1,6 @@
+
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -23,22 +24,25 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
+OBJS := vpac270.o
+SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
#########################################################################
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-sinclude $(obj).depend
+-include .depend
#########################################################################
diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk
new file mode 100644
index 0000000..1d650ac
--- /dev/null
+++ b/board/vpac270/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1000000
diff --git a/board/altera/ep1s40/ep1s40.c b/board/vpac270/lowlevel_init.S
similarity index 64%
copy from board/altera/ep1s40/ep1s40.c
copy to board/vpac270/lowlevel_init.S
index 6395de7..ec0d12c 100644
--- a/board/altera/ep1s40/ep1s40.c
+++ b/board/vpac270/lowlevel_init.S
@@ -1,6 +1,8 @@
/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
+ * Voipac PXA270 Lowlevel Hardware Initialization
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -21,27 +23,18 @@
* MA 02111-1307 USA
*/
-#include <common.h>
-#include <netdev.h>
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/macro.h>
-int checkboard (void)
-{
- puts ("BOARD : Altera EP-1S40\n");
- return 0;
-}
+.globl lowlevel_init
+lowlevel_init:
+ pxa_gpio_setup
+ pxa_wait_ticks 0x8000
+ pxa_mem_setup
+ pxa_wakeup
+ pxa_intr_setup
+ pxa_clock_setup
-phys_size_t initdram (int board_type)
-{
- return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
+ mov pc, lr
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds b/board/vpac270/u-boot.lds
similarity index 76%
copy from arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
copy to board/vpac270/u-boot.lds
index 2953b93..58c371d 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
+++ b/board/vpac270/u-boot.lds
@@ -1,11 +1,6 @@
/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -17,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -34,9 +29,9 @@
. = 0x00000000;
. = ALIGN(4);
- .text :
+ .text :
{
- arch/arm/cpu/arm_cortexa8/start.o
+ cpu/pxa/start.o (.text)
*(.text)
}
@@ -49,7 +44,6 @@
. = ALIGN(4);
.got : { *(.got) }
- . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
new file mode 100644
index 0000000..48e93ab
--- /dev/null
+++ b/board/vpac270/vpac270.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+struct serial_device *default_serial_console (void)
+{
+ return &serial_ffuart_device;
+}
+
+int board_init (void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+ return 0;
+}
+
+int usb_board_init(void)
+{
+ UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+
+ UHCHR |= UHCHR_FSBIR;
+
+ while (UHCHR & UHCHR_FSBIR);
+
+ UHCHR &= ~UHCHR_SSE;
+ UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+
+ /* Clear any OTG Pin Hold */
+ if (PSSR & PSSR_OTGPH)
+ PSSR |= PSSR_OTGPH;
+
+ UHCRHDA &= ~(0x200);
+ UHCRHDA |= 0x100;
+
+ /* Set port power control mask bits, only 3 ports. */
+ UHCRHDB |= (0x7<<17);
+
+ /* enable port 2 */
+ UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+
+ return 0;
+}
+
+void usb_board_init_fail(void)
+{
+ return;
+}
+
+void usb_board_stop(void)
+{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+ CKEN &= ~CKEN10_USBHOST;
+
+ return;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c
index 44d40ee..cab9881 100644
--- a/board/w7o/cmd_vpd.c
+++ b/board/w7o/cmd_vpd.c
@@ -38,10 +38,8 @@
uchar dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
/* Validate usage */
- if (argc > 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc > 2)
+ return cmd_usage(cmdtp);
/* Passed in EEPROM address */
if (argc == 2)
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index 3a81827..ece7882 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -398,18 +398,6 @@
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_pci_setup(void *blob, bd_t *bd)
{
- /* TODO - make node name (eg pci0) dynamic */
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE3
- ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
+ FT_FSL_PCI_SETUP;
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/xes/xpedite5170/xpedite5170.c b/board/xes/xpedite5170/xpedite5170.c
index f4231a9..5822941 100644
--- a/board/xes/xpedite5170/xpedite5170.c
+++ b/board/xes/xpedite5170/xpedite5170.c
@@ -56,8 +56,6 @@
*/
static void flash_cs_fixup(void)
{
- immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- ccsr_lbc_t *lbc = &immap->im_lbc;
int flash_sel;
/*
@@ -70,11 +68,11 @@
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
- out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
- out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+ set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
- out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
- out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+ set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+ set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
}
}
diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite5200/xpedite5200.c
index 7109771..a2627f8 100644
--- a/board/xes/xpedite5200/xpedite5200.c
+++ b/board/xes/xpedite5200/xpedite5200.c
@@ -38,7 +38,7 @@
int checkboard(void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
char *s;
@@ -65,7 +65,6 @@
static void flash_cs_fixup(void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
int flash_sel;
/*
@@ -78,11 +77,11 @@
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
- out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
- out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+ set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
- out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
- out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+ set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+ set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
}
}
diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite5370/xpedite5370.c
index 48d9fc8..2a060c2 100644
--- a/board/xes/xpedite5370/xpedite5370.c
+++ b/board/xes/xpedite5370/xpedite5370.c
@@ -58,7 +58,6 @@
static void flash_cs_fixup(void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
int flash_sel;
/*
@@ -71,11 +70,11 @@
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
- out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
- out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+ set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
- out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
- out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+ set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+ set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
}
}
diff --git a/board/altera/ep1c20/Makefile b/board/zipitz2/Makefile
similarity index 81%
copy from board/altera/ep1c20/Makefile
copy to board/zipitz2/Makefile
index acad2aa..2673835 100644
--- a/board/altera/ep1c20/Makefile
+++ b/board/zipitz2/Makefile
@@ -1,6 +1,9 @@
+
#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (C) 2009
+# Marek Vasut <marek.vasut@gmail.com>
+#
+# Heavily based on pxa255_idp platform
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -22,22 +25,18 @@
#
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
LIB = $(obj)lib$(BOARD).a
-COMOBJS := ../common/AMDLV065D.o ../common/epled.o
-
-COBJS := $(BOARD).o $(COMOBJS)
+COBJS := zipitz2.o
+SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
diff --git a/board/zipitz2/config.mk b/board/zipitz2/config.mk
new file mode 100644
index 0000000..1d650ac
--- /dev/null
+++ b/board/zipitz2/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1000000
diff --git a/board/altera/ep1s40/ep1s40.c b/board/zipitz2/lowlevel_init.S
similarity index 64%
copy from board/altera/ep1s40/ep1s40.c
copy to board/zipitz2/lowlevel_init.S
index 6395de7..82a52e8 100644
--- a/board/altera/ep1s40/ep1s40.c
+++ b/board/zipitz2/lowlevel_init.S
@@ -1,6 +1,8 @@
/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
+ * Aeronix Zipit Z2 Lowlevel Hardware Initialization
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -21,27 +23,18 @@
* MA 02111-1307 USA
*/
-#include <common.h>
-#include <netdev.h>
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/macro.h>
-int checkboard (void)
-{
- puts ("BOARD : Altera EP-1S40\n");
- return 0;
-}
+.globl lowlevel_init
+lowlevel_init:
+ pxa_gpio_setup
+ pxa_wait_ticks 0x8000
+ pxa_mem_setup
+ pxa_wakeup
+ pxa_intr_setup
+ pxa_clock_setup
-phys_size_t initdram (int board_type)
-{
- return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
+ mov pc, lr
diff --git a/arch/arm/cpu/arm_cortexa8/u-boot.lds b/board/zipitz2/u-boot.lds
similarity index 77%
copy from arch/arm/cpu/arm_cortexa8/u-boot.lds
copy to board/zipitz2/u-boot.lds
index 820e3a1..fb4358b 100644
--- a/arch/arm/cpu/arm_cortexa8/u-boot.lds
+++ b/board/zipitz2/u-boot.lds
@@ -1,9 +1,6 @@
/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -15,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -32,10 +29,10 @@
. = 0x00000000;
. = ALIGN(4);
- .text :
+ .text :
{
- arch/arm/cpu/arm_cortexa8/start.o (.text)
- *(.text)
+ cpu/pxa/start.o (.text)
+ *(.text)
}
. = ALIGN(4);
@@ -47,12 +44,13 @@
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
- .bss : { *(.bss) }
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
}
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
new file mode 100644
index 0000000..14d1d76
--- /dev/null
+++ b/board/zipitz2/zipitz2.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2009
+ * Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Heavily based on pxa255_idp platform
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/arch/hardware.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_SPI
+void lcd_start(void);
+#else
+inline void lcd_start(void) {};
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of Lubbock-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Enable LCD */
+ lcd_start();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ return 0;
+}
+
+struct serial_device *default_serial_console (void)
+{
+ return &serial_stuart_device;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_SPI
+
+struct {
+ unsigned char reg;
+ unsigned short data;
+ unsigned char mdelay;
+} lcd_data[] = {
+ { 0x07, 0x0000, 0 },
+ { 0x13, 0x0000, 10 },
+ { 0x11, 0x3004, 0 },
+ { 0x14, 0x200F, 0 },
+ { 0x10, 0x1a20, 0 },
+ { 0x13, 0x0040, 50 },
+ { 0x13, 0x0060, 0 },
+ { 0x13, 0x0070, 200 },
+ { 0x01, 0x0127, 0 },
+ { 0x02, 0x0700, 0 },
+ { 0x03, 0x1030, 0 },
+ { 0x08, 0x0208, 0 },
+ { 0x0B, 0x0620, 0 },
+ { 0x0C, 0x0110, 0 },
+ { 0x30, 0x0120, 0 },
+ { 0x31, 0x0127, 0 },
+ { 0x32, 0x0000, 0 },
+ { 0x33, 0x0503, 0 },
+ { 0x34, 0x0727, 0 },
+ { 0x35, 0x0124, 0 },
+ { 0x36, 0x0706, 0 },
+ { 0x37, 0x0701, 0 },
+ { 0x38, 0x0F00, 0 },
+ { 0x39, 0x0F00, 0 },
+ { 0x40, 0x0000, 0 },
+ { 0x41, 0x0000, 0 },
+ { 0x42, 0x013f, 0 },
+ { 0x43, 0x0000, 0 },
+ { 0x44, 0x013f, 0 },
+ { 0x45, 0x0000, 0 },
+ { 0x46, 0xef00, 0 },
+ { 0x47, 0x013f, 0 },
+ { 0x48, 0x0000, 0 },
+ { 0x07, 0x0015, 30 },
+ { 0x07, 0x0017, 0 },
+ { 0x20, 0x0000, 0 },
+ { 0x21, 0x0000, 0 },
+ { 0x22, 0x0000, 0 },
+};
+
+void zipitz2_spi_sda(int set)
+{
+ /* GPIO 13 */
+ if (set)
+ GPSR0 = (1 << 13);
+ else
+ GPCR0 = (1 << 13);
+}
+
+void zipitz2_spi_scl(int set)
+{
+ /* GPIO 22 */
+ if (set)
+ GPCR0 = (1 << 22);
+ else
+ GPSR0 = (1 << 22);
+}
+
+unsigned char zipitz2_spi_read(void)
+{
+ /* GPIO 40 */
+ return !!(GPLR1 & (1 << 8));
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ /* Always valid */
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* GPIO 88 low */
+ GPCR2 = (1 << 24);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* GPIO 88 high */
+ GPSR2 = (1 << 24);
+
+}
+
+void lcd_start(void)
+{
+ int i;
+ unsigned char reg[3] = { 0x74, 0x00, 0 };
+ unsigned char data[3] = { 0x76, 0, 0 };
+ unsigned char dummy[3] = { 0, 0, 0 };
+
+ /* PWM2 AF */
+ GAFR0_L |= 0x00800000;
+ /* Enable clock to all PWM */
+ CKEN |= 0x3;
+ /* Configure PWM2 */
+ PWM_CTRL2 = 0x4f;
+ PWM_PWDUTY2 = 0x2ff;
+ PWM_PERVAL2 = 792;
+
+ /* Toggle the reset pin to reset the LCD */
+ GPSR0 = (1 << 19);
+ udelay(100000);
+ GPCR0 = (1 << 19);
+ udelay(20000);
+ GPSR0 = (1 << 19);
+ udelay(20000);
+
+ /* Program the LCD init sequence */
+ for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
+ reg[0] = 0x74;
+ reg[1] = 0x0;
+ reg[2] = lcd_data[i].reg;
+ spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ data[0] = 0x76;
+ data[1] = lcd_data[i].data >> 8;
+ data[2] = lcd_data[i].data & 0xff;
+ spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ if (lcd_data[i].mdelay)
+ udelay(lcd_data[i].mdelay * 1000);
+ }
+
+ GPSR0 = (1 << 11);
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index da31c36..b82f530 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -45,13 +45,14 @@
pm9263 arm arm926ejs - ronetix at91
suen3 arm arm926ejs km_arm keymile kirkwood
rd6281a arm arm926ejs - Marvell kirkwood
-mx51evk arm arm_cortexa8 mx51evk freescale mx51
+mx51evk arm armv7 mx51evk freescale mx51
actux1 arm ixp
actux2 arm ixp
actux3 arm ixp
actux4 arm ixp
ixdp425 arm ixp
cerf250 arm pxa
+colibri_pxa270 arm pxa
cradle arm pxa
csb226 arm pxa
delta arm pxa
@@ -61,6 +62,7 @@
pleb2 arm pxa
xaeniax arm pxa
xm250 arm pxa
+zipitz2 arm pxa
B2 arm s3c44b0 - dave
assabet arm sa1100
dnp1110 arm sa1100
@@ -75,9 +77,6 @@
EP2500 m68k mcf52x2 ep2500 Mercury
purple mips mips
tb0229 mips mips
-EP1C20 nios2 nios2 ep1c20 altera
-EP1S10 nios2 nios2 ep1s10 altera
-EP1S40 nios2 nios2 ep1s40 altera
PCI5441 nios2 nios2 pci5441 psyent
PK1C20 nios2 nios2 pk1c20 psyent
P3G4 powerpc 74xx_7xx evb64260
@@ -132,6 +131,7 @@
mgcoge powerpc mpc8260 - keymile
SCM powerpc mpc8260 - siemens
TQM8272 powerpc mpc8260 tqm8272 tqc
+ve8313 powerpc mpc83xx ve8313
kmeter1 powerpc mpc83xx kmeter1 keymile
MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
TQM834x powerpc mpc83xx tqm834x tqc
@@ -143,7 +143,6 @@
ETX094 powerpc mpc8xx etx094
FLAGADM powerpc mpc8xx flagadm
GENIETV powerpc mpc8xx genietv
-GTH powerpc mpc8xx gth
hermes powerpc mpc8xx
IP860 powerpc mpc8xx ip860
LANTEC powerpc mpc8xx lantec
@@ -255,17 +254,19 @@
magnesium arm arm926ejs imx27lite logicpd mx27
omap5912osk arm arm926ejs - ti omap
edminiv2 arm arm926ejs - LaCie orion5x
-omap3_overo arm arm_cortexa8 overo - omap3
-omap3_pandora arm arm_cortexa8 pandora - omap3
-omap3_zoom1 arm arm_cortexa8 zoom1 logicpd omap3
-omap3_zoom2 arm arm_cortexa8 zoom2 logicpd omap3
-omap3_beagle arm arm_cortexa8 beagle ti omap3
-omap3_evm arm arm_cortexa8 evm ti omap3
-omap3_sdp3430 arm arm_cortexa8 sdp3430 ti omap3
-am3517_evm arm arm_cortexa8 am3517evm logicpd omap3
-devkit8000 arm arm_cortexa8 devkit8000 timll omap3
-s5p_goni arm arm_cortexa8 goni samsung s5pc1xx
-smdkc100 arm arm_cortexa8 smdkc100 samsung s5pc1xx
+omap3_overo arm armv7 overo - omap3
+omap3_pandora arm armv7 pandora - omap3
+omap3_zoom1 arm armv7 zoom1 logicpd omap3
+omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_beagle arm armv7 beagle ti omap3
+omap3_evm arm armv7 evm ti omap3
+omap3_sdp3430 arm armv7 sdp3430 ti omap3
+omap4_panda arm armv7 panda ti omap4
+omap4_sdp4430 arm armv7 sdp4430 ti omap4
+am3517_evm arm armv7 am3517evm logicpd omap3
+devkit8000 arm armv7 devkit8000 timll omap3
+s5p_goni arm armv7 goni samsung s5pc1xx
+smdkc100 arm armv7 smdkc100 samsung s5pc1xx
ixdpg425 arm ixp
lpd7a400 arm lh7a40x lpd7a40x
lpd7a404 arm lh7a40x lpd7a40x
@@ -282,6 +283,7 @@
hammerhead avr32 at32ap - miromico at32ap700x
bf518f-ezbrd blackfin blackfin
bf526-ezbrd blackfin blackfin
+bf527-ad7160-eval blackfin blackfin
bf527-ezkit blackfin blackfin
bf533-ezkit blackfin blackfin
bf533-stamp blackfin blackfin
@@ -331,6 +333,7 @@
RPXsuper powerpc mpc8260 rpxsuper
rsdproto powerpc mpc8260
MPC8266ADS powerpc mpc8260 mpc8266ads freescale
+MPC8308RDB powerpc mpc83xx mpc8308rdb freescale
MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale
MPC8349EMDS powerpc mpc83xx mpc8349emds freescale
MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
@@ -342,6 +345,7 @@
MPC8568MDS powerpc mpc85xx mpc8568mds freescale
XPEDITE5200 powerpc mpc85xx xpedite5200 xes
XPEDITE5370 powerpc mpc85xx xpedite5370 xes
+P1022DS powerpc mpc85xx p1022ds freescale
sbc8641d powerpc mpc86xx
MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale
XPEDITE5170 powerpc mpc86xx xpedite5170 xes
diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c
index d01ee19..2bd62e2 100644
--- a/common/cmd_bedbug.c
+++ b/common/cmd_bedbug.c
@@ -84,10 +84,8 @@
addr = dis_last_addr;
len = dis_last_len;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
if ((flag & CMD_FLAG_REPEAT) == 0) {
/* New command */
@@ -125,10 +123,8 @@
/* -------------------------------------------------- */
int rcode = 0;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
printf ("\nEnter '.' when done\n");
mem_addr = simple_strtoul (argv[1], NULL, 16);
diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c
index 5ec798c..d51cc55 100644
--- a/common/cmd_bmp.c
+++ b/common/cmd_bmp.c
@@ -102,8 +102,7 @@
addr = simple_strtoul(argv[1], NULL, 16);
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return (bmp_info(addr));
@@ -127,8 +126,7 @@
y = simple_strtoul(argv[3], NULL, 10);
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return (bmp_display(addr, x, y));
@@ -159,12 +157,10 @@
c = find_cmd_tbl(argv[0], &cmd_bmp_sub[0], ARRAY_SIZE(cmd_bmp_sub));
- if (c) {
+ if (c)
return c->cmd(cmdtp, flag, argc, argv);
- } else {
- cmd_usage(cmdtp);
- return 1;
- }
+ else
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
diff --git a/common/cmd_boot.c b/common/cmd_boot.c
index 9ccc8c7..72dacaa 100644
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -40,10 +40,8 @@
ulong addr, rc;
int rcode = 0;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
addr = simple_strtoul(argv[1], NULL, 16);
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index bf77fb4..adfa6cd 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -491,17 +491,14 @@
argv++;
return bootm_start(cmdtp, flag, argc, argv);
}
- }
- /* Unrecognized command */
- else {
- cmd_usage(cmdtp);
- return 1;
+ } else {
+ /* Unrecognized command */
+ return cmd_usage(cmdtp);
}
if (images.state >= state) {
printf ("Trying to execute a command out of order\n");
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
images.state |= state;
diff --git a/common/cmd_cache.c b/common/cmd_cache.c
index be87b5c..5cdd834 100644
--- a/common/cmd_cache.c
+++ b/common/cmd_cache.c
@@ -34,10 +34,6 @@
switch (argc) {
case 2: /* on / off */
switch (on_off(argv[1])) {
-#if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */
- default: cmd_usage(cmdtp);
- return;
-#endif
case 0: icache_disable();
break;
case 1: icache_enable ();
@@ -49,8 +45,7 @@
icache_status() ? "ON" : "OFF");
return 0;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return 0;
}
@@ -60,10 +55,6 @@
switch (argc) {
case 2: /* on / off */
switch (on_off(argv[1])) {
-#if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */
- default: cmd_usage(cmdtp);
- return;
-#endif
case 0: dcache_disable();
break;
case 1: dcache_enable ();
@@ -75,8 +66,7 @@
dcache_status() ? "ON" : "OFF");
return 0;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return 0;
diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c
index 45de8cd..45fe66a 100644
--- a/common/cmd_dcr.c
+++ b/common/cmd_dcr.c
@@ -44,10 +44,8 @@
unsigned long get_dcr (unsigned short);
/* Validate arguments */
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
/* Get a DCR */
dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
@@ -73,10 +71,8 @@
extern char console_buffer[];
/* Validate arguments */
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
/* Set a DCR */
dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
@@ -120,10 +116,8 @@
char buf[80];
/* Validate arguments */
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
/* Find out whether ther is '.' (dot) symbol in the first parameter. */
strncpy (buf, argv[1], sizeof(buf)-1);
@@ -176,10 +170,8 @@
char buf[80];
/* Validate arguments */
- if (argc < 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 4)
+ return cmd_usage(cmdtp);
/* Find out whether ther is '.' (dot) symbol in the first parameter. */
strncpy (buf, argv[1], sizeof(buf)-1);
diff --git a/common/cmd_df.c b/common/cmd_df.c
index 6a08666..9a3c84c 100644
--- a/common/cmd_df.c
+++ b/common/cmd_df.c
@@ -27,8 +27,7 @@
}
usage:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
index 129162c..9f4b22c 100644
--- a/common/cmd_eeprom.c
+++ b/common/cmd_eeprom.c
@@ -104,8 +104,7 @@
}
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
#endif
diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c
index 49021cd..35fb361 100644
--- a/common/cmd_ext2.c
+++ b/common/cmd_ext2.c
@@ -65,10 +65,9 @@
block_dev_desc_t *dev_desc=NULL;
int part_length;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
dev = (int)simple_strtoul (argv[2], &ep, 16);
dev_desc = get_dev(argv[1],dev);
@@ -164,8 +163,7 @@
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
if (!filename) {
diff --git a/common/cmd_fat.c b/common/cmd_fat.c
index ede7308..0220494 100644
--- a/common/cmd_fat.c
+++ b/common/cmd_fat.c
@@ -45,39 +45,43 @@
char *ep;
if (argc < 5) {
- printf ("usage: fatload <interface> <dev[:part]> <addr> <filename> [bytes]\n");
+ printf( "usage: fatload <interface> <dev[:part]> "
+ "<addr> <filename> [bytes]\n");
return 1;
}
- dev = (int)simple_strtoul (argv[2], &ep, 16);
- dev_desc=get_dev(argv[1],dev);
- if (dev_desc==NULL) {
- puts ("\n** Invalid boot device **\n");
+
+ dev = (int)simple_strtoul(argv[2], &ep, 16);
+ dev_desc = get_dev(argv[1],dev);
+ if (dev_desc == NULL) {
+ puts("\n** Invalid boot device **\n");
return 1;
}
if (*ep) {
if (*ep != ':') {
- puts ("\n** Invalid boot device, use `dev[:part]' **\n");
+ puts("\n** Invalid boot device, use `dev[:part]' **\n");
return 1;
}
part = (int)simple_strtoul(++ep, NULL, 16);
}
if (fat_register_device(dev_desc,part)!=0) {
- printf ("\n** Unable to use %s %d:%d for fatload **\n",argv[1],dev,part);
+ printf("\n** Unable to use %s %d:%d for fatload **\n",
+ argv[1], dev, part);
return 1;
}
- offset = simple_strtoul (argv[3], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 16);
if (argc == 6)
- count = simple_strtoul (argv[5], NULL, 16);
+ count = simple_strtoul(argv[5], NULL, 16);
else
count = 0;
- size = file_fat_read (argv[4], (unsigned char *) offset, count);
+ size = file_fat_read(argv[4], (unsigned char *)offset, count);
if(size==-1) {
- printf("\n** Unable to read \"%s\" from %s %d:%d **\n",argv[4],argv[1],dev,part);
+ printf("\n** Unable to read \"%s\" from %s %d:%d **\n",
+ argv[4], argv[1], dev, part);
return 1;
}
- printf ("\n%ld bytes read\n", size);
+ printf("\n%ld bytes read\n", size);
sprintf(buf, "%lX", size);
setenv("filesize", buf);
@@ -104,34 +108,35 @@
block_dev_desc_t *dev_desc=NULL;
if (argc < 3) {
- printf ("usage: fatls <interface> <dev[:part]> [directory]\n");
- return (0);
+ printf("usage: fatls <interface> <dev[:part]> [directory]\n");
+ return 0;
}
- dev = (int)simple_strtoul (argv[2], &ep, 16);
- dev_desc=get_dev(argv[1],dev);
- if (dev_desc==NULL) {
- puts ("\n** Invalid boot device **\n");
+ dev = (int)simple_strtoul(argv[2], &ep, 16);
+ dev_desc = get_dev(argv[1],dev);
+ if (dev_desc == NULL) {
+ puts("\n** Invalid boot device **\n");
return 1;
}
if (*ep) {
if (*ep != ':') {
- puts ("\n** Invalid boot device, use `dev[:part]' **\n");
+ puts("\n** Invalid boot device, use `dev[:part]' **\n");
return 1;
}
part = (int)simple_strtoul(++ep, NULL, 16);
}
if (fat_register_device(dev_desc,part)!=0) {
- printf ("\n** Unable to use %s %d:%d for fatls **\n",argv[1],dev,part);
+ printf("\n** Unable to use %s %d:%d for fatls **\n",
+ argv[1], dev, part);
return 1;
}
if (argc == 4)
- ret = file_fat_ls (argv[3]);
+ ret = file_fat_ls(argv[3]);
else
- ret = file_fat_ls (filename);
+ ret = file_fat_ls(filename);
if(ret!=0)
printf("No Fat FS detected\n");
- return (ret);
+ return ret;
}
U_BOOT_CMD(
@@ -149,27 +154,28 @@
block_dev_desc_t *dev_desc=NULL;
if (argc < 2) {
- printf ("usage: fatinfo <interface> <dev[:part]>\n");
- return (0);
+ printf("usage: fatinfo <interface> <dev[:part]>\n");
+ return 0;
}
- dev = (int)simple_strtoul (argv[2], &ep, 16);
- dev_desc=get_dev(argv[1],dev);
- if (dev_desc==NULL) {
- puts ("\n** Invalid boot device **\n");
+ dev = (int)simple_strtoul(argv[2], &ep, 16);
+ dev_desc = get_dev(argv[1],dev);
+ if (dev_desc == NULL) {
+ puts("\n** Invalid boot device **\n");
return 1;
}
if (*ep) {
if (*ep != ':') {
- puts ("\n** Invalid boot device, use `dev[:part]' **\n");
+ puts("\n** Invalid boot device, use `dev[:part]' **\n");
return 1;
}
part = (int)simple_strtoul(++ep, NULL, 16);
}
if (fat_register_device(dev_desc,part)!=0) {
- printf ("\n** Unable to use %s %d:%d for fatinfo **\n",argv[1],dev,part);
+ printf("\n** Unable to use %s %d:%d for fatinfo **\n",
+ argv[1], dev, part);
return 1;
}
- return (file_fat_detectfs ());
+ return file_fat_detectfs();
}
U_BOOT_CMD(
@@ -178,143 +184,3 @@
"<interface> <dev[:part]>\n"
" - print information about filesystem from 'dev' on 'interface'"
);
-
-#ifdef NOT_IMPLEMENTED_YET
-/* find first device whose first partition is a DOS filesystem */
-int find_fat_partition (void)
-{
- int i, j;
- block_dev_desc_t *dev_desc;
- unsigned char *part_table;
- unsigned char buffer[ATA_BLOCKSIZE];
-
- for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; i++) {
- dev_desc = ide_get_dev (i);
- if (!dev_desc) {
- debug ("couldn't get ide device!\n");
- return (-1);
- }
- if (dev_desc->part_type == PART_TYPE_DOS) {
- if (dev_desc->
- block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) {
- debug ("can't perform block_read!\n");
- return (-1);
- }
- part_table = &buffer[0x1be]; /* start with partition #4 */
- for (j = 0; j < 4; j++) {
- if ((part_table[4] == 1 || /* 12-bit FAT */
- part_table[4] == 4 || /* 16-bit FAT */
- part_table[4] == 6) && /* > 32Meg part */
- part_table[0] == 0x80) { /* bootable? */
- curr_dev = i;
- part_offset = part_table[11];
- part_offset <<= 8;
- part_offset |= part_table[10];
- part_offset <<= 8;
- part_offset |= part_table[9];
- part_offset <<= 8;
- part_offset |= part_table[8];
- debug ("found partition start at %ld\n", part_offset);
- return (0);
- }
- part_table += 16;
- }
- }
- }
-
- debug ("no valid devices found!\n");
- return (-1);
-}
-
-int
-do_fat_dump (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
-{
- __u8 block[1024];
- int ret;
- int bknum;
-
- ret = 0;
-
- if (argc != 2) {
- printf ("needs an argument!\n");
- return (0);
- }
-
- bknum = simple_strtoul (argv[1], NULL, 10);
-
- if (disk_read (0, bknum, block) != 0) {
- printf ("Error: reading block\n");
- return -1;
- }
- printf ("FAT dump: %d\n", bknum);
- hexdump (512, block);
-
- return (ret);
-}
-
-int disk_read (__u32 startblock, __u32 getsize, __u8 *bufptr)
-{
- ulong tot;
- block_dev_desc_t *dev_desc;
-
- if (curr_dev < 0) {
- if (find_fat_partition () != 0)
- return (-1);
- }
-
- dev_desc = ide_get_dev (curr_dev);
- if (!dev_desc) {
- debug ("couldn't get ide device\n");
- return (-1);
- }
-
- tot = dev_desc->block_read (0, startblock + part_offset,
- getsize, (ulong *) bufptr);
-
- /* should we do this here?
- flush_cache ((ulong)buf, cnt*ide_dev_desc[device].blksz);
- */
-
- if (tot == getsize)
- return (0);
-
- debug ("unable to read from device!\n");
-
- return (-1);
-}
-
-
-static int isprint (unsigned char ch)
-{
- if (ch >= 32 && ch < 127)
- return (1);
-
- return (0);
-}
-
-
-void hexdump (int cnt, unsigned char *data)
-{
- int i;
- int run;
- int offset;
-
- offset = 0;
- while (cnt) {
- printf ("%04X : ", offset);
- if (cnt >= 16)
- run = 16;
- else
- run = cnt;
- cnt -= run;
- for (i = 0; i < run; i++)
- printf ("%02X ", (unsigned int) data[i]);
- printf (": ");
- for (i = 0; i < run; i++)
- printf ("%c", isprint (data[i]) ? data[i] : '.');
- printf ("\n");
- data = &data[16];
- offset += run;
- }
-}
-#endif /* NOT_IMPLEMENTED_YET */
diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c
index 486d5d4..831a07f 100644
--- a/common/cmd_fdc.c
+++ b/common/cmd_fdc.c
@@ -741,8 +741,7 @@
boot_drive=simple_strtoul(argv[2], NULL, 10);
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
/* setup FDC and scan for drives */
if(fdc_setup(boot_drive,pCMD,pFG)==FALSE) {
diff --git a/common/cmd_fdos.c b/common/cmd_fdos.c
index 00f7e88..a8822d9 100644
--- a/common/cmd_fdos.c
+++ b/common/cmd_fdos.c
@@ -73,8 +73,7 @@
name = argv [2];
break;
default:
- cmd_usage(cmdtp);
- break;
+ return cmd_usage(cmdtp);
}
/* Init physical layer */
diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c
index cd4c6de..3d0c2b7 100644
--- a/common/cmd_fdt.c
+++ b/common/cmd_fdt.c
@@ -65,14 +65,12 @@
*/
int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
- /********************************************************************
+ /*
* Set the address of the fdt
- ********************************************************************/
+ */
if (argv[1][0] == 'a') {
unsigned long addr;
/*
@@ -116,18 +114,16 @@
}
}
- /********************************************************************
+ /*
* Move the working_fdt
- ********************************************************************/
+ */
} else if (strncmp(argv[1], "mo", 2) == 0) {
struct fdt_header *newaddr;
int len;
int err;
- if (argc < 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 4)
+ return cmd_usage(cmdtp);
/*
* Set the address and length of the fdt.
@@ -166,9 +162,9 @@
}
working_fdt = newaddr;
- /********************************************************************
+ /*
* Make a new node
- ********************************************************************/
+ */
} else if (strncmp(argv[1], "mk", 2) == 0) {
char *pathp; /* path */
char *nodep; /* new node to add */
@@ -178,10 +174,8 @@
/*
* Parameters: Node path, new node to be appended to the path.
*/
- if (argc < 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 4)
+ return cmd_usage(cmdtp);
pathp = argv[2];
nodep = argv[3];
@@ -202,9 +196,9 @@
return 1;
}
- /********************************************************************
+ /*
* Set the value of a property in the working_fdt.
- ********************************************************************/
+ */
} else if (argv[1][0] == 's') {
char *pathp; /* path */
char *prop; /* property */
@@ -216,10 +210,8 @@
/*
* Parameters: Node path, property, optional value.
*/
- if (argc < 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 4)
+ return cmd_usage(cmdtp);
pathp = argv[2];
prop = argv[3];
@@ -247,9 +239,9 @@
return 1;
}
- /********************************************************************
+ /*
* Print (recursive) / List (single level)
- ********************************************************************/
+ */
} else if ((argv[1][0] == 'p') || (argv[1][0] == 'l')) {
int depth = MAX_LEVEL; /* how deep to print */
char *pathp; /* path */
@@ -281,9 +273,9 @@
if (ret != 0)
return ret;
- /********************************************************************
+ /*
* Remove a property/node
- ********************************************************************/
+ */
} else if (strncmp(argv[1], "rm", 2) == 0) {
int nodeoffset; /* node offset from libfdt */
int err;
@@ -321,9 +313,9 @@
}
}
- /********************************************************************
+ /*
* Display header info
- ********************************************************************/
+ */
} else if (argv[1][0] == 'h') {
u32 version = fdt_version(working_fdt);
printf("magic:\t\t\t0x%x\n", fdt_magic(working_fdt));
@@ -351,16 +343,16 @@
fdt_num_mem_rsv(working_fdt));
printf("\n");
- /********************************************************************
+ /*
* Set boot cpu id
- ********************************************************************/
+ */
} else if (strncmp(argv[1], "boo", 3) == 0) {
unsigned long tmp = simple_strtoul(argv[2], NULL, 16);
fdt_set_boot_cpuid_phys(working_fdt, tmp);
- /********************************************************************
+ /*
* memory command
- ********************************************************************/
+ */
} else if (strncmp(argv[1], "me", 2) == 0) {
uint64_t addr, size;
int err;
@@ -370,9 +362,9 @@
if (err < 0)
return err;
- /********************************************************************
+ /*
* mem reserve commands
- ********************************************************************/
+ */
} else if (strncmp(argv[1], "rs", 2) == 0) {
if (argv[2][0] == 'p') {
uint64_t addr, size;
@@ -417,8 +409,7 @@
}
} else {
/* Unrecognized command */
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
}
#ifdef CONFIG_OF_BOARD_SETUP
@@ -430,10 +421,8 @@
else if (argv[1][0] == 'c') {
unsigned long initrd_start = 0, initrd_end = 0;
- if ((argc != 2) && (argc != 4)) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if ((argc != 2) && (argc != 4))
+ return cmd_usage(cmdtp);
if (argc == 4) {
initrd_start = simple_strtoul(argv[2], NULL, 16);
@@ -449,8 +438,7 @@
}
else {
/* Unrecognized command */
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return 0;
diff --git a/common/cmd_flash.c b/common/cmd_flash.c
index 5d8fb7a..ff43965 100644
--- a/common/cmd_flash.c
+++ b/common/cmd_flash.c
@@ -332,10 +332,8 @@
#endif
int rcode = 0;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
if (strcmp(argv[1], "all") == 0) {
for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
@@ -383,10 +381,8 @@
}
#endif
- if (argc != 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 3)
+ return cmd_usage(cmdtp);
if (strcmp(argv[1], "bank") == 0) {
bank = simple_strtoul(argv[2], NULL, 16);
@@ -406,10 +402,8 @@
return 1;
}
- if (addr_first >= addr_last) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (addr_first >= addr_last)
+ return cmd_usage(cmdtp);
rcode = flash_sect_erase(addr_first, addr_last);
return rcode;
@@ -482,19 +476,15 @@
int p;
int rcode = 0;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
- if (strcmp(argv[1], "off") == 0) {
+ if (strcmp(argv[1], "off") == 0)
p = 0;
- } else if (strcmp(argv[1], "on") == 0) {
+ else if (strcmp(argv[1], "on") == 0)
p = 1;
- } else {
- cmd_usage(cmdtp);
- return 1;
- }
+ else
+ return cmd_usage(cmdtp);
#ifdef CONFIG_HAS_DATAFLASH
if ((strcmp(argv[2], "all") != 0) && (strcmp(argv[2], "bank") != 0)) {
@@ -592,10 +582,8 @@
}
#endif
- if (argc != 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 4)
+ return cmd_usage(cmdtp);
if (strcmp(argv[2], "bank") == 0) {
bank = simple_strtoul(argv[3], NULL, 16);
@@ -634,10 +622,9 @@
return 1;
}
- if (addr_first >= addr_last) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (addr_first >= addr_last)
+ return cmd_usage(cmdtp);
+
rcode = flash_sect_protect (p, addr_first, addr_last);
#endif /* CONFIG_SYS_NO_FLASH */
return rcode;
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index ddc7a05..e50c9de 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -44,7 +44,6 @@
#endif
/* Local functions */
-static void fpga_usage (cmd_tbl_t * cmdtp);
static int fpga_get_op (char *opstr);
/* Local defines */
@@ -232,8 +231,7 @@
switch (op) {
case FPGA_NONE:
- fpga_usage (cmdtp);
- break;
+ return cmd_usage(cmdtp);
case FPGA_INFO:
rc = fpga_info (dev);
@@ -312,17 +310,11 @@
default:
printf ("Unknown operation\n");
- fpga_usage (cmdtp);
- break;
+ return cmd_usage(cmdtp);
}
return (rc);
}
-static void fpga_usage (cmd_tbl_t * cmdtp)
-{
- cmd_usage(cmdtp);
-}
-
/*
* Map op to supported operations. We don't use a table since we
* would just have to relocate it from flash anyway.
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index fb9d3b0..371e022 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -184,10 +184,8 @@
uint devaddr, alen, length;
u_char *memaddr;
- if (argc != 5) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 5)
+ return cmd_usage(cmdtp);
/*
* I2C chip address
@@ -200,10 +198,8 @@
*/
devaddr = simple_strtoul(argv[2], NULL, 16);
alen = get_alen(argv[2]);
- if (alen == 0) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (alen == 0)
+ return cmd_usage(cmdtp);
/*
* Length is the number of objects, not number of bytes.
@@ -240,10 +236,8 @@
alen = i2c_dp_last_alen;
length = i2c_dp_last_length;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
if ((flag & CMD_FLAG_REPEAT) == 0) {
/*
@@ -261,10 +255,8 @@
*/
addr = simple_strtoul(argv[2], NULL, 16);
alen = get_alen(argv[2]);
- if (alen == 0) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (alen == 0)
+ return cmd_usage(cmdtp);
/*
* If another parameter, it is the length to display.
@@ -332,10 +324,8 @@
uchar byte;
int count;
- if ((argc < 4) || (argc > 5)) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if ((argc < 4) || (argc > 5))
+ return cmd_usage(cmdtp);
/*
* Chip is always specified.
@@ -347,10 +337,8 @@
*/
addr = simple_strtoul(argv[2], NULL, 16);
alen = get_alen(argv[2]);
- if (alen == 0) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (alen == 0)
+ return cmd_usage(cmdtp);
/*
* Value to write is always specified.
@@ -398,10 +386,8 @@
ulong crc;
ulong err;
- if (argc < 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 4)
+ return cmd_usage(cmdtp);
/*
* Chip is always specified.
@@ -413,10 +399,8 @@
*/
addr = simple_strtoul(argv[2], NULL, 16);
alen = get_alen(argv[2]);
- if (alen == 0) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (alen == 0)
+ return cmd_usage(cmdtp);
/*
* Count is always specified
@@ -462,10 +446,8 @@
int nbytes;
extern char console_buffer[];
- if (argc != 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 3)
+ return cmd_usage(cmdtp);
#ifdef CONFIG_BOOT_RETRY_TIME
reset_cmd_timeout(); /* got a good command to get here */
@@ -495,10 +477,8 @@
*/
addr = simple_strtoul(argv[2], NULL, 16);
alen = get_alen(argv[2]);
- if (alen == 0) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (alen == 0)
+ return cmd_usage(cmdtp);
}
/*
@@ -628,10 +608,8 @@
u_char bytes[16];
int delay;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
/*
* Chip is always specified.
@@ -643,10 +621,8 @@
*/
addr = simple_strtoul(argv[2], NULL, 16);
alen = get_alen(argv[2]);
- if (alen == 0) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (alen == 0)
+ return cmd_usage(cmdtp);
/*
* Length is the number of objects, not number of bytes.
@@ -784,10 +760,9 @@
"32 MiB", "16 MiB", "8 MiB", "4 MiB"
};
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
/*
* Chip is always specified.
*/
@@ -1322,12 +1297,10 @@
c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
- if (c) {
+ if (c)
return c->cmd(cmdtp, flag, argc, argv);
- } else {
- cmd_usage(cmdtp);
- return 1;
- }
+ else
+ return cmd_usage(cmdtp);
}
/***************************************************/
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index d486697..c0fb88d 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -179,8 +179,7 @@
switch (argc) {
case 0:
case 1:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
case 2:
if (strncmp(argv[1],"res",3) == 0) {
puts ("\nReset IDE"
@@ -229,8 +228,7 @@
}
return rcode;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
case 3:
if (strncmp(argv[1],"dev",3) == 0) {
int dev = (int)simple_strtoul(argv[2], NULL, 10);
@@ -278,8 +276,7 @@
#endif
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
default:
/* at least 4 args */
@@ -332,14 +329,12 @@
printf ("%ld blocks written: %s\n",
n, (n==cnt) ? "OK" : "ERROR");
- if (n==cnt) {
+ if (n==cnt)
return 0;
- } else {
+ else
return 1;
- }
} else {
- cmd_usage(cmdtp);
- rcode = 1;
+ return cmd_usage(cmdtp);
}
return rcode;
@@ -374,9 +369,8 @@
boot_device = argv[2];
break;
default:
- cmd_usage(cmdtp);
show_boot_progress (-42);
- return 1;
+ return cmd_usage(cmdtp);
}
show_boot_progress (42);
diff --git a/common/cmd_irq.c b/common/cmd_irq.c
index 4888328..d35a43f 100644
--- a/common/cmd_irq.c
+++ b/common/cmd_irq.c
@@ -27,17 +27,14 @@
int do_interrupts(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (argc != 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 2)
+ return cmd_usage(cmdtp);
/* on */
- if (strncmp(argv[1], "on", 2) == 0) {
+ if (strncmp(argv[1], "on", 2) == 0)
enable_interrupts();
- } else {
+ else
disable_interrupts();
- }
return 0;
}
diff --git a/common/cmd_itest.c b/common/cmd_itest.c
index e88d6e0..8dd8927 100644
--- a/common/cmd_itest.c
+++ b/common/cmd_itest.c
@@ -165,10 +165,8 @@
int value, w;
/* Validate arguments */
- if ((argc != 4)){
- cmd_usage(cmdtp);
- return 1;
- }
+ if ((argc != 4))
+ return cmd_usage(cmdtp);
/* Check for a data width specification.
* Defaults to long (4) if no specification.
diff --git a/common/cmd_load.c b/common/cmd_load.c
index 52ed1fa..dad0303 100644
--- a/common/cmd_load.c
+++ b/common/cmd_load.c
@@ -1102,7 +1102,7 @@
if (strcmp(argv[1], "on") == 0)
hwflow_onoff(1);
else
- cmd_usage(cmdtp);
+ return cmd_usage(cmdtp);
}
printf("RTS/CTS hardware flow control: %s\n", hwflow_onoff(0) ? "on" : "off");
return 0;
diff --git a/common/cmd_log.c b/common/cmd_log.c
index 49deddd..0e89357 100644
--- a/common/cmd_log.c
+++ b/common/cmd_log.c
@@ -241,12 +241,10 @@
}
return 0;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
}
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index bcea399..44834ea 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -76,10 +76,8 @@
size = dp_last_size;
length = dp_last_length;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
if ((flag & CMD_FLAG_REPEAT) == 0) {
/* New command specified. Check for a size specification.
@@ -172,10 +170,8 @@
ulong addr, writeval, count;
int size;
- if ((argc < 3) || (argc > 4)) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if ((argc < 3) || (argc > 4))
+ return cmd_usage(cmdtp);
/* Check for size specification.
*/
@@ -216,10 +212,8 @@
int i;
ulong count;
- if (argc < 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 4)
+ return cmd_usage(cmdtp);
count = simple_strtoul(argv[3], NULL, 10);
@@ -245,10 +239,8 @@
int i;
ulong count;
- if (argc < 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 4)
+ return cmd_usage(cmdtp);
count = simple_strtoul(argv[3], NULL, 10);
@@ -276,10 +268,8 @@
int size;
int rcode = 0;
- if (argc != 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 4)
+ return cmd_usage(cmdtp);
/* Check for size specification.
*/
@@ -360,10 +350,8 @@
ulong addr, dest, count;
int size;
- if (argc != 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 4)
+ return cmd_usage(cmdtp);
/* Check for size specification.
*/
@@ -484,10 +472,8 @@
volatile ushort *shortp;
volatile u_char *cp;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
/* Check for a size spefication.
* Defaults to long if no or incorrect specification.
@@ -555,10 +541,8 @@
volatile ushort *shortp;
volatile u_char *cp;
- if (argc < 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 4)
+ return cmd_usage(cmdtp);
/* Check for a size spefication.
* Defaults to long if no or incorrect specification.
@@ -990,10 +974,8 @@
int nbytes, size;
extern char console_buffer[];
- if (argc != 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 2)
+ return cmd_usage(cmdtp);
#ifdef CONFIG_BOOT_RETRY_TIME
reset_cmd_timeout(); /* got a good command to get here */
@@ -1095,10 +1077,8 @@
ulong crc;
ulong *ptr;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
addr = simple_strtoul (argv[1], NULL, 16);
addr += base_address;
@@ -1131,9 +1111,8 @@
char * const *av;
if (argc < 3) {
- usage:
- cmd_usage(cmdtp);
- return 1;
+usage:
+ return cmd_usage(cmdtp);
}
av = argv + 1;
@@ -1181,10 +1160,8 @@
unsigned int i;
u8 output[16];
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
addr = simple_strtoul(argv[1], NULL, 16);
len = simple_strtoul(argv[2], NULL, 16);
@@ -1206,10 +1183,8 @@
unsigned int i;
u8 output[20];
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
addr = simple_strtoul(argv[1], NULL, 16);
len = simple_strtoul(argv[2], NULL, 16);
@@ -1239,8 +1214,7 @@
dst = simple_strtoul(argv[2], NULL, 16);
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return !!gunzip((void *) dst, dst_len, (void *) src, &src_len);
diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index eeef2cd..00180b0 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -37,17 +37,14 @@
unsigned int num;
unsigned int blocking;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
fslnum = (unsigned int)simple_strtoul (argv[1], NULL, 16);
blocking = (unsigned int)simple_strtoul (argv[2], NULL, 16);
if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) {
puts ("Bad number of FSL\n");
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
switch (fslnum) {
@@ -195,18 +192,14 @@
unsigned int num;
unsigned int blocking;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
fslnum = (unsigned int)simple_strtoul (argv[1], NULL, 16);
num = (unsigned int)simple_strtoul (argv[2], NULL, 16);
blocking = (unsigned int)simple_strtoul (argv[3], NULL, 16);
- if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER)
+ return cmd_usage(cmdtp);
switch (fslnum) {
#if (XILINX_FSL_NUMBER > 0)
@@ -353,10 +346,9 @@
unsigned int reg = 0;
unsigned int val = 0;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
switch (reg) {
diff --git a/common/cmd_mii.c b/common/cmd_mii.c
index 1619a25..bb94186 100644
--- a/common/cmd_mii.c
+++ b/common/cmd_mii.c
@@ -301,10 +301,8 @@
int rcode = 0;
char *devname;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
#if defined(CONFIG_MII_INIT)
mii_init ();
@@ -431,8 +429,7 @@
else
miiphy_set_current_dev (argv[2]);
} else {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
/*
diff --git a/common/cmd_misc.c b/common/cmd_misc.c
index 8439da2..061b1bb 100644
--- a/common/cmd_misc.c
+++ b/common/cmd_misc.c
@@ -32,17 +32,15 @@
ulong start = get_timer(0);
ulong delay;
- if (argc != 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 2)
+ return cmd_usage(cmdtp);
delay = simple_strtoul(argv[1], NULL, 10) * CONFIG_SYS_HZ;
while (get_timer(start) < delay) {
- if (ctrlc ()) {
+ if (ctrlc ())
return (-1);
- }
+
udelay (100);
}
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 698157f..e5f5e94 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -32,10 +32,8 @@
{
int dev;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
if (strcmp(argv[1], "init") == 0) {
if (argc == 2) {
@@ -46,8 +44,7 @@
} else if (argc == 3) {
dev = (int)simple_strtoul(argv[2], NULL, 10);
} else {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
if (mmc_legacy_init(dev) != 0) {
@@ -72,14 +69,12 @@
#endif
curr_device = dev;
} else {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
printf("mmc%d is current device\n", curr_device);
} else {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
return 0;
diff --git a/common/cmd_mp.c b/common/cmd_mp.c
index 4d7b871..f19bf41 100644
--- a/common/cmd_mp.c
+++ b/common/cmd_mp.c
@@ -28,10 +28,8 @@
{
unsigned long cpuid;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
cpuid = simple_strtoul(argv[1], NULL, 10);
if (cpuid >= cpu_numcores()) {
@@ -42,29 +40,24 @@
if (argc == 3) {
- if (strncmp(argv[2], "reset", 5) == 0) {
+ if (strncmp(argv[2], "reset", 5) == 0)
cpu_reset(cpuid);
- } else if (strncmp(argv[2], "status", 6) == 0) {
+ else if (strncmp(argv[2], "status", 6) == 0)
cpu_status(cpuid);
- } else if (strncmp(argv[2], "disable", 7) == 0) {
+ else if (strncmp(argv[2], "disable", 7) == 0)
return cpu_disable(cpuid);
- } else {
- cmd_usage(cmdtp);
- return 1;
- }
+ else
+ return cmd_usage(cmdtp);
+
return 0;
}
/* 4 or greater, make sure its release */
- if (strncmp(argv[2], "release", 7) != 0) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (strncmp(argv[2], "release", 7) != 0)
+ return cmd_usage(cmdtp);
- if (cpu_release(cpuid, argc - 3, argv + 3)) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (cpu_release(cpuid, argc - 3, argv + 3))
+ return cmd_usage(cmdtp);
return 0;
}
diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c
index 447486b..ceec5a9 100644
--- a/common/cmd_mtdparts.c
+++ b/common/cmd_mtdparts.c
@@ -1845,8 +1845,7 @@
return delete_partition(argv[2]);
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
/***************************************************/
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index ea80555..0f47a25 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -4,6 +4,10 @@
* (c) 1999 Machine Vision Holdings, Inc.
* (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
*
+ * Ported 'dynenv' to 'nand env.oob' command
+ * (C) 2010 Nanometrics, Inc.
+ * 'dynenv' -- Dynamic environment offset in NAND OOB
+ * (C) Copyright 2006-2007 OpenMoko, Inc.
* Added 16-bit nand support
* (C) 2004 Texas Instruments
*/
@@ -193,6 +197,89 @@
}
#endif
+#ifdef CONFIG_ENV_OFFSET_OOB
+unsigned long nand_env_oob_offset;
+
+int do_nand_env_oob(cmd_tbl_t *cmdtp, nand_info_t *nand,
+ int argc, char * const argv[])
+{
+ int ret;
+ uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
+
+ char *cmd = argv[1];
+
+ if (!strcmp(cmd, "get")) {
+ ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+ if (ret)
+ return 1;
+
+ printf("0x%08lx\n", nand_env_oob_offset);
+ } else if (!strcmp(cmd, "set")) {
+ ulong addr;
+ size_t dummy_size;
+ struct mtd_oob_ops ops;
+
+ if (argc < 3)
+ goto usage;
+
+ if (arg_off_size(argc - 2, argv + 2, nand, &addr,
+ &dummy_size) < 0) {
+ printf("Offset or partition name expected\n");
+ return 1;
+ }
+
+ if (nand->oobavail < ENV_OFFSET_SIZE) {
+ printf("Insufficient available OOB bytes:\n"
+ "%d OOB bytes available but %d required for "
+ "env.oob support\n",
+ nand->oobavail, ENV_OFFSET_SIZE);
+ return 1;
+ }
+
+ if ((addr & (nand->erasesize - 1)) != 0) {
+ printf("Environment offset must be block-aligned\n");
+ return 1;
+ }
+
+ ops.datbuf = NULL;
+ ops.mode = MTD_OOB_AUTO;
+ ops.ooboffs = 0;
+ ops.ooblen = ENV_OFFSET_SIZE;
+ ops.oobbuf = (void *) oob_buf;
+
+ oob_buf[0] = ENV_OOB_MARKER;
+ oob_buf[1] = addr / nand->erasesize;
+
+ ret = nand->write_oob(nand, ENV_OFFSET_SIZE, &ops);
+ if (ret) {
+ printf("Error writing OOB block 0\n");
+ return ret;
+ }
+
+ ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+ if (ret) {
+ printf("Error reading env offset in OOB\n");
+ return ret;
+ }
+
+ if (addr != nand_env_oob_offset) {
+ printf("Verification of env offset in OOB failed: "
+ "0x%08lx expected but got 0x%08lx\n",
+ addr, nand_env_oob_offset);
+ return 1;
+ }
+ } else {
+ goto usage;
+ }
+
+ return ret;
+
+usage:
+ return cmd_usage(cmdtp);
+}
+
+#endif
+
static void nand_print_info(int idx)
{
nand_info_t *nand = &nand_info[idx];
@@ -272,9 +359,21 @@
strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 &&
strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 &&
strcmp(cmd, "biterr") != 0 &&
- strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 )
+ strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0
+#ifdef CONFIG_ENV_OFFSET_OOB
+ && strcmp(cmd, "env.oob") != 0
+#endif
+ )
goto usage;
+#ifdef CONFIG_ENV_OFFSET_OOB
+ /* this command operates only on the first nand device */
+ if (strcmp(cmd, "env.oob") == 0) {
+ return do_nand_env_oob(cmdtp, &nand_info[0],
+ argc - 1, argv + 1);
+ }
+#endif
+
/* the following commands operate on the current device */
if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
!nand_info[nand_curr_device].name) {
@@ -477,8 +576,7 @@
#endif
usage:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(nand, CONFIG_SYS_MAXARGS, 1, do_nand,
@@ -502,6 +600,13 @@
" bring nand to lock state or display locked pages\n"
"nand unlock [offset] [size] - unlock section"
#endif
+#ifdef CONFIG_ENV_OFFSET_OOB
+ "\n"
+ "nand env.oob - environment offset in OOB of block 0 of"
+ " first device.\n"
+ "nand env.oob set off|partition - set enviromnent offset\n"
+ "nand env.oob get - get environment offset"
+#endif
);
static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
@@ -652,9 +757,8 @@
#if defined(CONFIG_CMD_MTDPARTS)
usage:
#endif
- cmd_usage(cmdtp);
show_boot_progress(-53);
- return 1;
+ return cmd_usage(cmdtp);
}
show_boot_progress(53);
diff --git a/common/cmd_net.c b/common/cmd_net.c
index 3cdb07f..3ffb9df 100644
--- a/common/cmd_net.c
+++ b/common/cmd_net.c
@@ -186,9 +186,9 @@
break;
- default: cmd_usage(cmdtp);
+ default:
show_boot_progress (-80);
- return 1;
+ return cmd_usage(cmdtp);
}
show_boot_progress (80);
@@ -236,10 +236,8 @@
return -1;
NetPingIP = string_to_ip(argv[1]);
- if (NetPingIP == 0) {
- cmd_usage(cmdtp);
- return -1;
- }
+ if (NetPingIP == 0)
+ return cmd_usage(cmdtp);
if (NetLoop(PING) < 0) {
printf("ping failed; host %s is not alive\n", argv[1]);
@@ -342,10 +340,8 @@
#if defined(CONFIG_CMD_DNS)
int do_dns(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (argc == 1) {
- cmd_usage(cmdtp);
- return -1;
- }
+ if (argc == 1)
+ return cmd_usage(cmdtp);
/*
* We should check for a valid hostname:
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 13325bc..1198954 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -407,10 +407,8 @@
int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
return _do_setenv (flag, argc, argv);
}
@@ -433,15 +431,13 @@
local_args[2] = NULL;
local_args[3] = NULL;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
/* Check the syntax */
switch (argc) {
case 1:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
case 2: /* askenv envname */
sprintf (message, "Please enter '%s':", argv[1]);
@@ -503,10 +499,8 @@
char *init_val;
int len;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
/* Set read buffer to initial value or empty sting */
init_val = getenv(argv[1]);
diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c
index a3e46a3..83d967b 100644
--- a/common/cmd_onenand.c
+++ b/common/cmd_onenand.c
@@ -361,10 +361,7 @@
size_t retlen = 0;
if (argc < 3)
- {
- cmd_usage(cmdtp);
- return 1;
- }
+ return cmd_usage(cmdtp);
s = strchr(argv[0], '.');
if ((s != NULL) && (!strcmp(s, ".oob")))
@@ -391,10 +388,7 @@
size_t retlen = 0;
if (argc < 3)
- {
- cmd_usage(cmdtp);
- return 1;
- }
+ return cmd_usage(cmdtp);
addr = (ulong)simple_strtoul(argv[1], NULL, 16);
@@ -477,10 +471,7 @@
char *s;
if (argc < 2)
- {
- cmd_usage(cmdtp);
- return 1;
- }
+ return cmd_usage(cmdtp);
s = strchr(argv[0], '.');
ofs = (int)simple_strtoul(argv[1], NULL, 16);
@@ -502,10 +493,7 @@
argv += 2;
if (argc <= 0)
- {
- cmd_usage(cmdtp);
- return 1;
- }
+ return cmd_usage(cmdtp);
while (argc > 0) {
addr = simple_strtoul(*argv, NULL, 16);
@@ -549,12 +537,10 @@
c = find_cmd_tbl(argv[0], &cmd_onenand_sub[0], ARRAY_SIZE(cmd_onenand_sub));
- if (c) {
- return c->cmd(cmdtp, flag, argc, argv);
- } else {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
diff --git a/common/cmd_otp.c b/common/cmd_otp.c
index a8c73b5..43f7c69 100644
--- a/common/cmd_otp.c
+++ b/common/cmd_otp.c
@@ -88,8 +88,7 @@
if (argc < 4) {
usage:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
prompt_user = false;
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
index 358ca60..4bde059 100644
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -534,8 +534,7 @@
return 1;
usage:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
/***************************************************/
diff --git a/common/cmd_portio.c b/common/cmd_portio.c
index 92d61d2..4f2f499 100644
--- a/common/cmd_portio.c
+++ b/common/cmd_portio.c
@@ -43,13 +43,12 @@
uint size = out_last_size;
uint value = out_last_value;
- if (argc != 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 3)
+ return cmd_usage(cmdtp);
if ((flag & CMD_FLAG_REPEAT) == 0) {
- /* New command specified. Check for a size specification.
+ /*
+ * New command specified. Check for a size specification.
* Defaults to long if no or incorrect specification.
*/
size = cmd_get_data_size (argv[0], 1);
@@ -102,13 +101,12 @@
uint addr = in_last_addr;
uint size = in_last_size;
- if (argc != 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 2)
+ return cmd_usage(cmdtp);
if ((flag & CMD_FLAG_REPEAT) == 0) {
- /* New command specified. Check for a size specification.
+ /*
+ * New command specified. Check for a size specification.
* Defaults to long if no or incorrect specification.
*/
size = cmd_get_data_size (argv[0], 1);
diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c
index 94b8d58..908876c 100644
--- a/common/cmd_reginfo.c
+++ b/common/cmd_reginfo.c
@@ -33,6 +33,8 @@
#include <mpc5xxx.h>
#elif defined (CONFIG_MPC86xx)
extern void mpc86xx_reginfo(void);
+#elif defined(CONFIG_MPC85xx)
+extern void mpc85xx_reginfo(void);
#endif
int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -183,6 +185,9 @@
#elif defined(CONFIG_MPC86xx)
mpc86xx_reginfo();
+#elif defined(CONFIG_MPC85xx)
+ mpc85xx_reginfo();
+
#elif defined(CONFIG_BLACKFIN)
puts("\nSystem Configuration registers\n");
diff --git a/common/cmd_reiser.c b/common/cmd_reiser.c
index 2133a1f..ced1d40 100644
--- a/common/cmd_reiser.c
+++ b/common/cmd_reiser.c
@@ -56,10 +56,9 @@
block_dev_desc_t *dev_desc=NULL;
int part_length;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
dev = (int)simple_strtoul (argv[2], &ep, 16);
dev_desc = get_dev(argv[1],dev);
@@ -150,8 +149,7 @@
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
if (!filename) {
diff --git a/common/cmd_sata.c b/common/cmd_sata.c
index 7be58e5..7efa859 100644
--- a/common/cmd_sata.c
+++ b/common/cmd_sata.c
@@ -77,8 +77,7 @@
switch (argc) {
case 0:
case 1:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
case 2:
if (strncmp(argv[1],"inf", 3) == 0) {
int i;
@@ -115,8 +114,7 @@
}
return rc;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
case 3:
if (strncmp(argv[1], "dev", 3) == 0) {
int dev = (int)simple_strtoul(argv[2], NULL, 10);
@@ -147,8 +145,7 @@
}
return rc;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
default: /* at least 4 args */
if (strcmp(argv[1], "read") == 0) {
@@ -184,8 +181,7 @@
n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? 0 : 1;
} else {
- cmd_usage(cmdtp);
- rc = 1;
+ return cmd_usage(cmdtp);
}
return rc;
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index 5b2df28..6b937f9 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -229,8 +229,7 @@
boot_device = argv[2];
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
if (!boot_device) {
@@ -346,7 +345,8 @@
{
switch (argc) {
case 0:
- case 1: cmd_usage(cmdtp); return 1;
+ case 1: return cmd_usage(cmdtp);
+
case 2:
if (strncmp(argv[1],"res",3) == 0) {
printf("\nReset SCSI\n");
@@ -392,8 +392,7 @@
printf("\nno SCSI devices available\n");
return 1;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
case 3:
if (strncmp(argv[1],"dev",3) == 0) {
int dev = (int)simple_strtoul(argv[2], NULL, 10);
@@ -421,8 +420,7 @@
}
return 1;
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
default:
/* at least 4 args */
if (strcmp(argv[1],"read") == 0) {
@@ -437,8 +435,7 @@
return 0;
}
} /* switch */
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
/****************************************************************************************
diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c
index b3e489f..1ff1232 100644
--- a/common/cmd_setexpr.c
+++ b/common/cmd_setexpr.c
@@ -57,10 +57,8 @@
int w;
/* Validate arguments */
- if ((argc != 5) || (strlen(argv[3]) != 1)) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if ((argc != 5) || (strlen(argv[3]) != 1))
+ return cmd_usage(cmdtp);
w = cmd_get_data_size(argv[0], 4);
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 4826e9f..6e7be81 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -177,8 +177,7 @@
return do_spi_flash_erase(argc - 1, argv + 1);
usage:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
diff --git a/common/cmd_strings.c b/common/cmd_strings.c
index bbbb6b4..144a6c1 100644
--- a/common/cmd_strings.c
+++ b/common/cmd_strings.c
@@ -14,10 +14,8 @@
int do_strings(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (argc == 1) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc == 1)
+ return cmd_usage(cmdtp);
if ((flag & CMD_FLAG_REPEAT) == 0) {
start_addr = (char *)simple_strtoul(argv[1], NULL, 16);
diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c
index 2faf8d8..77ca0a5 100644
--- a/common/cmd_ubi.c
+++ b/common/cmd_ubi.c
@@ -442,10 +442,8 @@
ulong addr = 0;
int err = 0;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
if (mtdparts_init() != 0) {
printf("Error initializing mtdparts!\n");
@@ -471,10 +469,8 @@
return 0;
}
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
/* todo: get dev number for NAND... */
ubi_dev.nr = 0;
diff --git a/common/cmd_ubifs.c b/common/cmd_ubifs.c
index 9017041..2cab793 100644
--- a/common/cmd_ubifs.c
+++ b/common/cmd_ubifs.c
@@ -47,10 +47,9 @@
char *vol_name;
int ret;
- if (argc != 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 2)
+ return cmd_usage(cmdtp);
+
vol_name = argv[1];
debug("Using volume %s\n", vol_name);
@@ -102,25 +101,19 @@
return -1;
}
- if (argc < 3) {
- cmd_usage(cmdtp);
- return -1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
addr = simple_strtoul(argv[1], &endp, 16);
- if (endp == argv[1]) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (endp == argv[1])
+ return cmd_usage(cmdtp);
filename = argv[2];
if (argc == 4) {
size = simple_strtoul(argv[3], &endp, 16);
- if (endp == argv[3]) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (endp == argv[3])
+ return cmd_usage(cmdtp);
}
debug("Loading file '%s' to address 0x%08x (size %d)\n", filename, addr, size);
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index 73d74ac..dc63f24 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -376,8 +376,7 @@
boot_device = argv[2];
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
if (!boot_device) {
@@ -516,10 +515,8 @@
block_dev_desc_t *stor_dev;
#endif
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
if ((strncmp(argv[1], "reset", 5) == 0) ||
(strncmp(argv[1], "start", 5) == 0)) {
@@ -699,8 +696,7 @@
return 0;
}
#endif /* CONFIG_USB_STORAGE */
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
#ifdef CONFIG_USB_STORAGE
diff --git a/common/cmd_vfd.c b/common/cmd_vfd.c
index 1429d31..18c14d1 100644
--- a/common/cmd_vfd.c
+++ b/common/cmd_vfd.c
@@ -49,10 +49,8 @@
{
ulong bitmap;
- if (argc != 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 2)
+ return cmd_usage(cmdtp);
if (argv[1][0] == '/') { /* select bitmap by number */
bitmap = simple_strtoul(argv[1]+1, NULL, 10);
diff --git a/common/command.c b/common/command.c
index a1fc592..30a9801 100644
--- a/common/command.c
+++ b/common/command.c
@@ -153,7 +153,7 @@
puts (cmdtp->help);
putc ('\n');
#endif /* CONFIG_SYS_LONGHELP */
- return 0;
+ return 1;
}
#ifdef CONFIG_AUTO_COMPLETE
diff --git a/common/env_common.c b/common/env_common.c
index 82e4936..460309b 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -227,7 +227,7 @@
#endif
if (gd->env_valid == 0) {
-#if defined(CONFIG_GTH) || defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */
+#if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */
puts ("Using default environment\n\n");
#else
puts ("*** Warning - bad CRC, using default environment\n\n");
diff --git a/common/env_nand.c b/common/env_nand.c
index 50bc111..a5e1038 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -38,6 +38,7 @@
#include <linux/stddef.h>
#include <malloc.h>
#include <nand.h>
+#include <asm/errno.h>
#if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_NAND)
#define CMD_SAVEENV
@@ -284,6 +285,38 @@
return 0;
}
+#ifdef CONFIG_ENV_OFFSET_OOB
+int get_nand_env_oob(nand_info_t *nand, unsigned long *result)
+{
+ struct mtd_oob_ops ops;
+ uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
+ int ret;
+
+ ops.datbuf = NULL;
+ ops.mode = MTD_OOB_AUTO;
+ ops.ooboffs = 0;
+ ops.ooblen = ENV_OFFSET_SIZE;
+ ops.oobbuf = (void *) oob_buf;
+
+ ret = nand->read_oob(nand, ENV_OFFSET_SIZE, &ops);
+ if (ret) {
+ printf("error reading OOB block 0\n");
+ return ret;
+ }
+
+ if (oob_buf[0] == ENV_OOB_MARKER) {
+ *result = oob_buf[1] * nand->erasesize;
+ } else if (oob_buf[0] == ENV_OOB_MARKER_OLD) {
+ *result = oob_buf[1];
+ } else {
+ printf("No dynamic environment marker in OOB block 0\n");
+ return -ENOENT;
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_ENV_OFFSET_REDUND
void env_relocate_spec (void)
{
@@ -353,6 +386,17 @@
#if !defined(ENV_IS_EMBEDDED)
int ret;
+#if defined(CONFIG_ENV_OFFSET_OOB)
+ ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset);
+ /* If unable to read environment offset from NAND OOB then fall through
+ * to the normal environment reading code below
+ */
+ if (!ret)
+ printf("Found Environment offset in OOB..\n");
+ else
+ return use_default();
+#endif
+
ret = readenv(CONFIG_ENV_OFFSET, (u_char *) env_ptr);
if (ret)
return use_default();
diff --git a/common/fdt_support.c b/common/fdt_support.c
index a8ac617..718b635 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -2,6 +2,8 @@
* (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -474,135 +476,6 @@
}
}
-#ifdef CONFIG_HAS_FSL_DR_USB
-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
-{
- char *mode;
- char *type;
- const char *compat = "fsl-usb2-dr";
- const char *prop_mode = "dr_mode";
- const char *prop_type = "phy_type";
- int node_offset;
- int err;
-
- mode = getenv("usb_dr_mode");
- type = getenv("usb_phy_type");
- if (!mode && !type)
- return;
-
- node_offset = fdt_node_offset_by_compatible(blob, 0, compat);
- if (node_offset < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- compat, fdt_strerror(node_offset));
- return;
- }
-
- if (mode) {
- err = fdt_setprop(blob, node_offset, prop_mode, mode,
- strlen(mode) + 1);
- if (err < 0)
- printf("WARNING: could not set %s for %s: %s.\n",
- prop_mode, compat, fdt_strerror(err));
- }
-
- if (type) {
- err = fdt_setprop(blob, node_offset, prop_type, type,
- strlen(type) + 1);
- if (err < 0)
- printf("WARNING: could not set %s for %s: %s.\n",
- prop_type, compat, fdt_strerror(err));
- }
-}
-#endif /* CONFIG_HAS_FSL_DR_USB */
-
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx)
-/*
- * update crypto node properties to a specified revision of the SEC
- * called with sec_rev == 0 if not on an mpc8xxxE processor
- */
-void fdt_fixup_crypto_node(void *blob, int sec_rev)
-{
- const struct sec_rev_prop {
- u32 sec_rev;
- u32 num_channels;
- u32 channel_fifo_len;
- u32 exec_units_mask;
- u32 descriptor_types_mask;
- } sec_rev_prop_list [] = {
- { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
- { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
- { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
- { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
- { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
- { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
- { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
- };
- char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
- sizeof("fsl,secX.Y")];
- int crypto_node, sec_idx, err;
- char *p;
- u32 val;
-
- /* locate crypto node based on lowest common compatible */
- crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
- if (crypto_node == -FDT_ERR_NOTFOUND)
- return;
-
- /* delete it if not on an E-processor */
- if (crypto_node > 0 && !sec_rev) {
- fdt_del_node(blob, crypto_node);
- return;
- }
-
- /* else we got called for possible uprev */
- for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
- if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
- break;
-
- if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
- puts("warning: unknown SEC revision number\n");
- return;
- }
-
- val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
- err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
- if (err < 0)
- printf("WARNING: could not set crypto property: %s\n",
- fdt_strerror(err));
-
- val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
- err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4);
- if (err < 0)
- printf("WARNING: could not set crypto property: %s\n",
- fdt_strerror(err));
-
- val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
- err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
- if (err < 0)
- printf("WARNING: could not set crypto property: %s\n",
- fdt_strerror(err));
-
- val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
- err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
- if (err < 0)
- printf("WARNING: could not set crypto property: %s\n",
- fdt_strerror(err));
-
- val = 0;
- while (sec_idx >= 0) {
- p = compat_strlist + val;
- val += sprintf(p, "fsl,sec%d.%d",
- (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
- sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
- sec_idx--;
- }
- err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val);
- if (err < 0)
- printf("WARNING: could not set crypto property: %s\n",
- fdt_strerror(err));
-}
-#endif /* defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) */
-
/* Resize the fdt to its actual size + a bit of padding */
int fdt_resize(void *blob)
{
@@ -990,3 +863,292 @@
off = fdt_path_offset(blob, "/aliases");
fdt_delprop(blob, off, alias);
}
+
+/* Helper to read a big number; size is in cells (not bytes) */
+static inline u64 of_read_number(const __be32 *cell, int size)
+{
+ u64 r = 0;
+ while (size--)
+ r = (r << 32) | be32_to_cpu(*(cell++));
+ return r;
+}
+
+static int of_n_cells(const void *blob, int nodeoffset, const char *name)
+{
+ int np;
+ const int *ip;
+
+ do {
+ np = fdt_parent_offset(blob, nodeoffset);
+
+ if (np >= 0)
+ nodeoffset = np;
+ ip = (int *)fdt_getprop(blob, nodeoffset, name, NULL);
+ if (ip)
+ return be32_to_cpup(ip);
+ } while (np >= 0);
+
+ /* No #<NAME>-cells property for the root node */
+ return 1;
+}
+
+int of_n_addr_cells(const void *blob, int nodeoffset)
+{
+ return of_n_cells(blob, nodeoffset, "#address-cells");
+}
+
+int of_n_size_cells(const void *blob, int nodeoffset)
+{
+ return of_n_cells(blob, nodeoffset, "#size-cells");
+}
+
+#define PRu64 "%llx"
+
+/* Max address size we deal with */
+#define OF_MAX_ADDR_CELLS 4
+#define OF_BAD_ADDR ((u64)-1)
+#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
+ (ns) > 0)
+
+/* Debug utility */
+#ifdef DEBUG
+static void of_dump_addr(const char *s, const u32 *addr, int na)
+{
+ printf("%s", s);
+ while(na--)
+ printf(" %08x", *(addr++));
+ printf("\n");
+}
+#else
+static void of_dump_addr(const char *s, const u32 *addr, int na) { }
+#endif
+
+/* Callbacks for bus specific translators */
+struct of_bus {
+ const char *name;
+ const char *addresses;
+ void (*count_cells)(void *blob, int offset,
+ int *addrc, int *sizec);
+ u64 (*map)(u32 *addr, const u32 *range,
+ int na, int ns, int pna);
+ int (*translate)(u32 *addr, u64 offset, int na);
+};
+
+/* Default translator (generic bus) */
+static void of_bus_default_count_cells(void *blob, int offset,
+ int *addrc, int *sizec)
+{
+ if (addrc)
+ *addrc = of_n_addr_cells(blob, offset);
+ if (sizec)
+ *sizec = of_n_size_cells(blob, offset);
+}
+
+static u64 of_bus_default_map(u32 *addr, const u32 *range,
+ int na, int ns, int pna)
+{
+ u64 cp, s, da;
+
+ cp = of_read_number(range, na);
+ s = of_read_number(range + na + pna, ns);
+ da = of_read_number(addr, na);
+
+ debug("OF: default map, cp="PRu64", s="PRu64", da="PRu64"\n",
+ cp, s, da);
+
+ if (da < cp || da >= (cp + s))
+ return OF_BAD_ADDR;
+ return da - cp;
+}
+
+static int of_bus_default_translate(u32 *addr, u64 offset, int na)
+{
+ u64 a = of_read_number(addr, na);
+ memset(addr, 0, na * 4);
+ a += offset;
+ if (na > 1)
+ addr[na - 2] = a >> 32;
+ addr[na - 1] = a & 0xffffffffu;
+
+ return 0;
+}
+
+/* Array of bus specific translators */
+static struct of_bus of_busses[] = {
+ /* Default */
+ {
+ .name = "default",
+ .addresses = "reg",
+ .count_cells = of_bus_default_count_cells,
+ .map = of_bus_default_map,
+ .translate = of_bus_default_translate,
+ },
+};
+
+static int of_translate_one(void * blob, int parent, struct of_bus *bus,
+ struct of_bus *pbus, u32 *addr,
+ int na, int ns, int pna, const char *rprop)
+{
+ const u32 *ranges;
+ int rlen;
+ int rone;
+ u64 offset = OF_BAD_ADDR;
+
+ /* Normally, an absence of a "ranges" property means we are
+ * crossing a non-translatable boundary, and thus the addresses
+ * below the current not cannot be converted to CPU physical ones.
+ * Unfortunately, while this is very clear in the spec, it's not
+ * what Apple understood, and they do have things like /uni-n or
+ * /ht nodes with no "ranges" property and a lot of perfectly
+ * useable mapped devices below them. Thus we treat the absence of
+ * "ranges" as equivalent to an empty "ranges" property which means
+ * a 1:1 translation at that level. It's up to the caller not to try
+ * to translate addresses that aren't supposed to be translated in
+ * the first place. --BenH.
+ */
+ ranges = (u32 *)fdt_getprop(blob, parent, rprop, &rlen);
+ if (ranges == NULL || rlen == 0) {
+ offset = of_read_number(addr, na);
+ memset(addr, 0, pna * 4);
+ debug("OF: no ranges, 1:1 translation\n");
+ goto finish;
+ }
+
+ debug("OF: walking ranges...\n");
+
+ /* Now walk through the ranges */
+ rlen /= 4;
+ rone = na + pna + ns;
+ for (; rlen >= rone; rlen -= rone, ranges += rone) {
+ offset = bus->map(addr, ranges, na, ns, pna);
+ if (offset != OF_BAD_ADDR)
+ break;
+ }
+ if (offset == OF_BAD_ADDR) {
+ debug("OF: not found !\n");
+ return 1;
+ }
+ memcpy(addr, ranges + na, 4 * pna);
+
+ finish:
+ of_dump_addr("OF: parent translation for:", addr, pna);
+ debug("OF: with offset: "PRu64"\n", offset);
+
+ /* Translate it into parent bus space */
+ return pbus->translate(addr, offset, pna);
+}
+
+/*
+ * Translate an address from the device-tree into a CPU physical address,
+ * this walks up the tree and applies the various bus mappings on the
+ * way.
+ *
+ * Note: We consider that crossing any level with #size-cells == 0 to mean
+ * that translation is impossible (that is we are not dealing with a value
+ * that can be mapped to a cpu physical address). This is not really specified
+ * that way, but this is traditionally the way IBM at least do things
+ */
+u64 __of_translate_address(void *blob, int node_offset, const u32 *in_addr,
+ const char *rprop)
+{
+ int parent;
+ struct of_bus *bus, *pbus;
+ u32 addr[OF_MAX_ADDR_CELLS];
+ int na, ns, pna, pns;
+ u64 result = OF_BAD_ADDR;
+
+ debug("OF: ** translation for device %s **\n",
+ fdt_get_name(blob, node_offset, NULL));
+
+ /* Get parent & match bus type */
+ parent = fdt_parent_offset(blob, node_offset);
+ if (parent < 0)
+ goto bail;
+ bus = &of_busses[0];
+
+ /* Cound address cells & copy address locally */
+ bus->count_cells(blob, node_offset, &na, &ns);
+ if (!OF_CHECK_COUNTS(na, ns)) {
+ printf("%s: Bad cell count for %s\n", __FUNCTION__,
+ fdt_get_name(blob, node_offset, NULL));
+ goto bail;
+ }
+ memcpy(addr, in_addr, na * 4);
+
+ debug("OF: bus is %s (na=%d, ns=%d) on %s\n",
+ bus->name, na, ns, fdt_get_name(blob, parent, NULL));
+ of_dump_addr("OF: translating address:", addr, na);
+
+ /* Translate */
+ for (;;) {
+ /* Switch to parent bus */
+ node_offset = parent;
+ parent = fdt_parent_offset(blob, node_offset);
+
+ /* If root, we have finished */
+ if (parent < 0) {
+ debug("OF: reached root node\n");
+ result = of_read_number(addr, na);
+ break;
+ }
+
+ /* Get new parent bus and counts */
+ pbus = &of_busses[0];
+ pbus->count_cells(blob, node_offset, &pna, &pns);
+ if (!OF_CHECK_COUNTS(pna, pns)) {
+ printf("%s: Bad cell count for %s\n", __FUNCTION__,
+ fdt_get_name(blob, node_offset, NULL));
+ break;
+ }
+
+ debug("OF: parent bus is %s (na=%d, ns=%d) on %s\n",
+ pbus->name, pna, pns, fdt_get_name(blob, parent, NULL));
+
+ /* Apply bus translation */
+ if (of_translate_one(blob, node_offset, bus, pbus,
+ addr, na, ns, pna, rprop))
+ break;
+
+ /* Complete the move up one level */
+ na = pna;
+ ns = pns;
+ bus = pbus;
+
+ of_dump_addr("OF: one level translation:", addr, na);
+ }
+ bail:
+
+ return result;
+}
+
+u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr)
+{
+ return __of_translate_address(blob, node_offset, in_addr, "ranges");
+}
+
+/**
+ * fdt_node_offset_by_compat_reg: Find a node that matches compatiable and
+ * who's reg property matches a physical cpu address
+ *
+ * @blob: ptr to device tree
+ * @compat: compatiable string to match
+ * @compat_off: property name
+ *
+ */
+int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
+ phys_addr_t compat_off)
+{
+ int len, off = fdt_node_offset_by_compatible(blob, -1, compat);
+ while (off != -FDT_ERR_NOTFOUND) {
+ u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
+ if (reg) {
+ if (compat_off == fdt_translate_address(blob, off, reg))
+ return off;
+ }
+ off = fdt_node_offset_by_compatible(blob, off, compat);
+ }
+
+ return -FDT_ERR_NOTFOUND;
+}
+
+
diff --git a/common/hush.c b/common/hush.c
index 8a74d22..4dd9513 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -1694,10 +1694,8 @@
}
#endif
/* found - check max args */
- if ((child->argc - i) > cmdtp->maxargs) {
- cmd_usage(cmdtp);
- return -1;
- }
+ if ((child->argc - i) > cmdtp->maxargs)
+ return cmd_usage(cmdtp);
#endif
child->argv+=i; /* XXX horrible hack */
#ifndef __U_BOOT__
diff --git a/common/lcd.c b/common/lcd.c
index 93ddedf..d854c21 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -41,7 +41,7 @@
#include <lcd.h>
#include <watchdog.h>
-#if defined(CONFIG_PXA250)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
#include <asm/byteorder.h>
#endif
@@ -503,7 +503,7 @@
uchar *bmap;
uchar *fb;
ushort *fb16;
-#if defined(CONFIG_PXA250)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
struct pxafb_info *fbi = &panel_info.pxa;
#elif defined(CONFIG_MPC823)
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
@@ -519,7 +519,7 @@
if (NBITS(panel_info.vl_bpix) < 12) {
/* Leave room for default color map */
-#if defined(CONFIG_PXA250)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
@@ -615,7 +615,7 @@
unsigned long pwidth = panel_info.vl_col;
unsigned colors, bpix, bmp_bpix;
unsigned long compression;
-#if defined(CONFIG_PXA250)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
struct pxafb_info *fbi = &panel_info.pxa;
#elif defined(CONFIG_MPC823)
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
@@ -656,7 +656,7 @@
#if !defined(CONFIG_MCC200)
/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
if (bmp_bpix == 8) {
-#if defined(CONFIG_PXA250)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
@@ -745,7 +745,7 @@
WATCHDOG_RESET();
for (j = 0; j < width; j++) {
if (bpix != 16) {
-#if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS || defined(CONFIG_ATMEL_LCD)
*(fb++) = *(bmap++);
#elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
*(fb++) = 255 - *(bmap++);
diff --git a/common/main.c b/common/main.c
index 20090ee..54ef79e 100644
--- a/common/main.c
+++ b/common/main.c
@@ -1418,10 +1418,8 @@
{
int i;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
for (i=1; i<argc; ++i) {
char *arg;
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 4fc01a2..76949b8 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -181,7 +181,7 @@
void usb_show_progress(void)
{
- printf(".");
+ debug(".");
}
/*******************************************************************************
@@ -224,10 +224,11 @@
for (i = 0; i < USB_MAX_STOR_DEV; i++) {
memset(&usb_dev_desc[i], 0, sizeof(block_dev_desc_t));
- usb_dev_desc[i].target = 0xff;
usb_dev_desc[i].if_type = IF_TYPE_USB;
usb_dev_desc[i].dev = i;
usb_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+ usb_dev_desc[i].target = 0xff;
+ usb_dev_desc[i].type = DEV_TYPE_UNKNOWN;
usb_dev_desc[i].block_read = usb_stor_read;
usb_dev_desc[i].block_write = usb_stor_write;
}
@@ -1080,7 +1081,7 @@
usb_disable_asynch(0); /* asynch transfer allowed */
if (blkcnt >= USB_MAX_READ_BLK)
- printf("\n");
+ debug("\n");
return blkcnt;
}
@@ -1160,7 +1161,7 @@
usb_disable_asynch(0); /* asynch transfer allowed */
if (blkcnt >= USB_MAX_WRITE_BLK)
- printf("\n");
+ debug("\n");
return blkcnt;
}
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 887b75e..2de1bb8 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -77,8 +77,10 @@
(buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) {
return (-1);
} /* no DOS Signature at all */
- if(strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0)
+ if (strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0 ||
+ strncmp((char *)&buffer[DOS_PBR32_FSTYPE_OFFSET],"FAT32",5)==0) {
return DOS_PBR; /* is PBR */
+ }
return DOS_MBR; /* Is MBR */
}
diff --git a/disk/part_dos.h b/disk/part_dos.h
index ac93f20..195a32c 100644
--- a/disk/part_dos.h
+++ b/disk/part_dos.h
@@ -28,13 +28,14 @@
#ifdef CONFIG_ISO_PARTITION
/* Make the buffers bigger if ISO partition support is enabled -- CD-ROMS
have 2048 byte blocks */
-#define DEFAULT_SECTOR_SIZE 2048
+#define DEFAULT_SECTOR_SIZE 2048
#else
#define DEFAULT_SECTOR_SIZE 512
#endif
#define DOS_PART_TBL_OFFSET 0x1be
#define DOS_PART_MAGIC_OFFSET 0x1fe
#define DOS_PBR_FSTYPE_OFFSET 0x36
+#define DOS_PBR32_FSTYPE_OFFSET 0x52
#define DOS_PBR_MEDIA_TYPE_OFFSET 0x15
#define DOS_MBR 0
#define DOS_PBR 1
diff --git a/doc/README.designware_eth b/doc/README.designware_eth
new file mode 100644
index 0000000..25ec6bd
--- /dev/null
+++ b/doc/README.designware_eth
@@ -0,0 +1,25 @@
+This driver supports Designware Ethernet Controller provided by Synopsis.
+
+The driver is enabled by CONFIG_DESIGNWARE_ETH.
+
+The driver has been developed and tested on SPEAr platforms. By default, the
+MDIO interface works at 100/Full. #defining the below options in board
+configuration file changes this behavior.
+
+Call an subroutine from respective board/.../board.c
+designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
+
+The various options suported by the driver are
+1. CONFIG_DW_ALTDESCRIPTOR
+ Define this to use the Alternate/Enhanced Descriptor configurations.
+1. CONFIG_DW_AUTONEG
+ Define this to autonegotiate with the host before proceeding with mac
+ level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
+ and CONFIG_DW_DUPLEXHALF.
+2. CONFIG_DW_SPEED10M
+ Define this to change the default behavior from 100Mbps to 10Mbps.
+3. CONFIG_DW_DUPLEXHALF
+ Define this to change the default behavior from Full Duplex to Half.
+4. CONFIG_DW_SEARCH_PHY
+ Define this to search the phy address. This would overwrite the value
+ passed as 3rd arg from designware_initialize routine.
diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c
index f16dabe..847c032 100644
--- a/drivers/block/pata_bfin.c
+++ b/drivers/block/pata_bfin.c
@@ -14,6 +14,7 @@
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/errno.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/pata.h>
#include <ata.h>
#include <libata.h>
@@ -769,19 +770,17 @@
*/
static int bfin_config_atapi_gpio(struct ata_port *ap)
{
- bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0x4);
- bfin_write_PORTH_MUX(bfin_read_PORTH_MUX() & ~0x30);
- bfin_write_PORTH_DIR_SET(0x4);
+ const unsigned short pins[] = {
+ P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0,
+ P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ,
+ P_ATAPI_IORDY, P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A,
+ P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A,
+ P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A,
+ P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
+ P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, 0,
+ };
- bfin_write_PORTJ_FER(0x7f8);
- bfin_write_PORTJ_MUX(bfin_read_PORTI_MUX() & ~0x3fffc0);
- bfin_write_PORTJ_DIR_SET(0x5f8);
- bfin_write_PORTJ_DIR_CLEAR(0x200);
- bfin_write_PORTJ_INEN(0x200);
-
- bfin_write_PINT2_ASSIGN(0x0707);
- bfin_write_PINT2_MASK_SET(0x200);
- SSYNC();
+ peripheral_request_list(pins, "pata_bfin");
return 0;
}
diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
index d1065f4..6e82bd6 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/pca953x.c
@@ -164,8 +164,7 @@
if (!c || !((argc == (c->maxargs)) ||
(((int)c->cmd == PCA953X_CMD_DEVICE) &&
(argc == (c->maxargs - 1))))) {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
/* arg2 used as chip number or pin number */
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index ff18991..3256133 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -25,6 +25,8 @@
#include <asm/arch/i2c.h>
#include <asm/io.h>
+#include "omap24xx_i2c.h"
+
static void wait_for_bb (void);
static u16 wait_for_pin (void);
static void flush_fifo(void);
@@ -176,7 +178,8 @@
status = wait_for_pin ();
if (status & I2C_STAT_RRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX)
*value = readb (&i2c_base->data);
#else
*value = readw (&i2c_base->data);
@@ -221,7 +224,8 @@
status = wait_for_pin ();
if (status & I2C_STAT_XRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX)
/* send out 1 byte */
writeb (regoffset, &i2c_base->data);
writew (I2C_STAT_XRDY, &i2c_base->stat);
@@ -274,7 +278,8 @@
while(1){
stat = readw(&i2c_base->stat);
if(stat == I2C_STAT_RRDY){
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX)
readb(&i2c_base->data);
#else
readw(&i2c_base->data);
@@ -435,3 +440,9 @@
return 0;
}
+
+int i2c_get_bus_num(void)
+{
+ return (int) current_bus;
+}
+
diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h
new file mode 100644
index 0000000..92a3416
--- /dev/null
+++ b/drivers/i2c/omap24xx_i2c.h
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP24XX_I2C_H_
+#define _OMAP24XX_I2C_H_
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE (1 << 5)
+#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD (1 << 15) /* Single byte data */
+#define I2C_STAT_BB (1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS (1 << 9) /* Address as slave */
+#define I2C_STAT_GC (1 << 5)
+#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
+#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
+#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
+#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK 7
+#define I2C_INTCODE_NONE 0
+#define I2C_INTCODE_AL 1 /* Arbitration lost */
+#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY 3 /* Register access ready */
+#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
+#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
+#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN (1 << 15) /* I2C module enable */
+#define I2C_CON_BE (1 << 14) /* Big endian mode */
+#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
+#define I2C_CON_MST (1 << 10) /* Master/slave mode */
+#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
+ /* (master mode only) */
+#define I2C_CON_XA (1 << 8) /* Expand address */
+#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
+#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
+#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
+#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
+#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
+
+#define I2C_SCLL_SCLL 0
+#define I2C_SCLL_SCLL_M 0xFF
+#define I2C_SCLL_HSSCLL 8
+#define I2C_SCLH_HSSCLL_M 0xFF
+#define I2C_SCLH_SCLH 0
+#define I2C_SCLH_SCLH_M 0xFF
+#define I2C_SCLH_HSSCLH 8
+#define I2C_SCLH_HSSCLH_M 0xFF
+
+#define OMAP_I2C_STANDARD 100000
+#define OMAP_I2C_FAST_MODE 400000
+#define OMAP_I2C_HIGH_SPEED 3400000
+
+#define SYSTEM_CLOCK_12 12000000
+#define SYSTEM_CLOCK_13 13000000
+#define SYSTEM_CLOCK_192 19200000
+#define SYSTEM_CLOCK_96 96000000
+
+/* Use the reference value of 96MHz if not explicitly set by the board */
+#ifndef I2C_IP_CLK
+#define I2C_IP_CLK SYSTEM_CLOCK_96
+#endif
+
+/*
+ * The reference minimum clock for high speed is 19.2MHz.
+ * The linux 2.6.30 kernel uses this value.
+ * The reference minimum clock for fast mode is 9.6MHz
+ * The reference minimum clock for standard mode is 4MHz
+ * In TRM, the value of 12MHz is used.
+ */
+#ifndef I2C_INTERNAL_SAMPLING_CLK
+#define I2C_INTERNAL_SAMPLING_CLK 19200000
+#endif
+
+/*
+ * The equation for the low and high time is
+ * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
+ * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
+ *
+ * If the duty cycle is 50%
+ *
+ * tlow = scll + scll_trim = sampling clock / (2 * speed)
+ * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
+ *
+ * In TRM
+ * scll_trim = 7
+ * sclh_trim = 5
+ *
+ * The linux 2.6.30 kernel uses
+ * scll_trim = 6
+ * sclh_trim = 6
+ *
+ * These are the trim values for standard and fast speed
+ */
+#ifndef I2C_FASTSPEED_SCLL_TRIM
+#define I2C_FASTSPEED_SCLL_TRIM 6
+#endif
+#ifndef I2C_FASTSPEED_SCLH_TRIM
+#define I2C_FASTSPEED_SCLH_TRIM 6
+#endif
+
+/* These are the trim values for high speed */
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+
+#define I2C_PSC_MAX 0x0f
+#define I2C_PSC_MIN 0x00
+
+#endif /* _OMAP24XX_I2C_H_ */
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index e0cf1e1..1a1809a 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -51,6 +51,58 @@
#endif
#include <i2c.h>
+#if defined(CONFIG_SOFT_I2C_GPIO_SCL)
+# include <asm/gpio.h>
+
+# ifndef I2C_GPIO_SYNC
+# define I2C_GPIO_SYNC
+# endif
+
+# ifndef I2C_INIT
+# define I2C_INIT \
+ do { \
+ gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \
+ gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \
+ } while (0)
+# endif
+
+# ifndef I2C_ACTIVE
+# define I2C_ACTIVE do { } while (0)
+# endif
+
+# ifndef I2C_TRISTATE
+# define I2C_TRISTATE do { } while (0)
+# endif
+
+# ifndef I2C_READ
+# define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA)
+# endif
+
+# ifndef I2C_SDA
+# define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \
+ else \
+ gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \
+ I2C_GPIO_SYNC; \
+ } while (0)
+# endif
+
+# ifndef I2C_SCL
+# define I2C_SCL(bit) \
+ do { \
+ gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \
+ I2C_GPIO_SYNC; \
+ } while (0)
+# endif
+
+# ifndef I2C_DELAY
+# define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+# endif
+
+#endif
+
/* #define DEBUG_I2C */
#ifdef DEBUG_I2C
diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c
index 5b33c1f..aa893c3 100644
--- a/drivers/misc/ds4510.c
+++ b/drivers/misc/ds4510.c
@@ -294,8 +294,7 @@
if (!c || !((argc == (c->maxargs)) ||
(((int)c->cmd == DS4510_CMD_DEVICE) &&
(argc == (c->maxargs - 1))))) {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
/* arg2 used as chip addr and pin number */
@@ -366,14 +365,12 @@
#ifdef CONFIG_CMD_DS4510_MEM
/* Only eeprom, seeprom, and sram commands should make it here */
- if (strcmp(argv[2], "read") == 0) {
+ if (strcmp(argv[2], "read") == 0)
rw_func = ds4510_mem_read;
- } else if (strcmp(argv[2], "write") == 0) {
+ else if (strcmp(argv[2], "write") == 0)
rw_func = ds4510_mem_write;
- } else {
- cmd_usage(cmdtp);
- return 1;
- }
+ else
+ return cmd_usage(cmdtp);
addr = simple_strtoul(argv[3], NULL, 16);
off += simple_strtoul(argv[4], NULL, 16);
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index 8255175..6589076 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -43,40 +43,69 @@
defined(CONFIG_P1013) || defined(CONFIG_P1022) || \
defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
-#elif defined(CONFIG_PPC_P4080)
+#elif defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P4080) || \
+ defined(CONFIG_PPC_P5020)
#define FSL_HW_NUM_LAWS 32
#else
#error FSL_HW_NUM_LAWS not defined for this platform
#endif
#ifdef CONFIG_FSL_CORENET
+#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
+#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
+#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
+#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
+#define LAWBAR_SHIFT 0
+#else
+#define LAW_BASE (CONFIG_SYS_IMMR + 0xc08)
+#define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2)
+#define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x)
+#define LAWBAR_SHIFT 12
+#endif
+
+
+static inline phys_addr_t get_law_base_addr(int idx)
+{
+#ifdef CONFIG_FSL_CORENET
+ return (phys_addr_t)
+ ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) |
+ in_be32(LAWBARL_ADDR(idx));
+#else
+ return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
+#endif
+}
+
+static inline void set_law_base_addr(int idx, phys_addr_t addr)
+{
+#ifdef CONFIG_FSL_CORENET
+ out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff);
+ out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32);
+#else
+ out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
+#endif
+}
+
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
- volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
-
gd->used_laws |= (1 << idx);
- out_be32(&ccm->law[idx].lawar, 0);
- out_be32(&ccm->law[idx].lawbarh, ((u64)addr >> 32));
- out_be32(&ccm->law[idx].lawbarl, addr & 0xffffffff);
- out_be32(&ccm->law[idx].lawar, LAW_EN | ((u32)id << 20) | (u32)sz);
+ out_be32(LAWAR_ADDR(idx), 0);
+ set_law_base_addr(idx, addr);
+ out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
/* Read back so that we sync the writes */
- in_be32(&ccm->law[idx].lawar);
+ in_be32(LAWAR_ADDR(idx));
}
void disable_law(u8 idx)
{
- volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
-
gd->used_laws &= ~(1 << idx);
- out_be32(&ccm->law[idx].lawar, 0);
- out_be32(&ccm->law[idx].lawbarh, 0);
- out_be32(&ccm->law[idx].lawbarl, 0);
+ out_be32(LAWAR_ADDR(idx), 0);
+ set_law_base_addr(idx, 0);
/* Read back so that we sync the writes */
- in_be32(&ccm->law[idx].lawar);
+ in_be32(LAWAR_ADDR(idx));
return;
}
@@ -84,77 +113,20 @@
#ifndef CONFIG_NAND_SPL
static int get_law_entry(u8 i, struct law_entry *e)
{
- volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
u32 lawar;
- lawar = in_be32(&ccm->law[i].lawar);
+ lawar = in_be32(LAWAR_ADDR(i));
if (!(lawar & LAW_EN))
return 0;
- e->addr = ((u64)in_be32(&ccm->law[i].lawbarh) << 32) |
- in_be32(&ccm->law[i].lawbarl);
+ e->addr = get_law_base_addr(i);
e->size = lawar & 0x3f;
e->trgt_id = (lawar >> 20) & 0xff;
return 1;
}
#endif
-#else
-void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
-{
- volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
- volatile u32 *lawbar = base + 8 * idx;
- volatile u32 *lawar = base + 8 * idx + 2;
-
- gd->used_laws |= (1 << idx);
-
- out_be32(lawar, 0);
- out_be32(lawbar, addr >> 12);
- out_be32(lawar, LAW_EN | ((u32)id << 20) | (u32)sz);
-
- /* Read back so that we sync the writes */
- in_be32(lawar);
-}
-
-void disable_law(u8 idx)
-{
- volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
- volatile u32 *lawbar = base + 8 * idx;
- volatile u32 *lawar = base + 8 * idx + 2;
-
- gd->used_laws &= ~(1 << idx);
-
- out_be32(lawar, 0);
- out_be32(lawbar, 0);
-
- /* Read back so that we sync the writes */
- in_be32(lawar);
-
- return;
-}
-
-#ifndef CONFIG_NAND_SPL
-static int get_law_entry(u8 i, struct law_entry *e)
-{
- volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
- volatile u32 *lawbar = base + 8 * i;
- volatile u32 *lawar = base + 8 * i + 2;
- u32 temp;
-
- temp = in_be32(lawar);
-
- if (!(temp & LAW_EN))
- return 0;
-
- e->addr = (u64)in_be32(lawbar) << 12;
- e->size = temp & 0x3f;
- e->trgt_id = (temp >> 20) & 0xff;
-
- return 1;
-}
-#endif
-#endif
int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
@@ -216,17 +188,23 @@
void print_laws(void)
{
- volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
- volatile u32 *lawbar = base;
- volatile u32 *lawar = base + 2;
int i;
+ u32 lawar;
printf("\nLocal Access Window Configuration\n");
- for(i = 0; i < FSL_HW_NUM_LAWS; i++) {
- printf("\tLAWBAR%d : 0x%08x, LAWAR%d : 0x%08x\n",
- i, in_be32(lawbar), i, in_be32(lawar));
- lawbar += 8;
- lawar += 8;
+ for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
+ lawar = in_be32(LAWAR_ADDR(i));
+#ifdef CONFIG_FSL_CORENET
+ printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
+ i, in_be32(LAWBARH_ADDR(i)),
+ i, in_be32(LAWBARL_ADDR(i)));
+#else
+ printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
+#endif
+ printf(" LAWAR0x%02d: 0x%08x\n", i, lawar);
+ printf("\t(EN: %d TGT: 0x%02x SIZE: ",
+ (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
+ print_size(lawar_size(lawar), ")\n");
}
return;
diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c
index 274327f..dca0a1d 100644
--- a/drivers/misc/fsl_pmic.c
+++ b/drivers/misc/fsl_pmic.c
@@ -163,26 +163,22 @@
u32 val;
/* at least two arguments please */
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
cmd = argv[1];
if (strcmp(cmd, "dump") == 0) {
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
nregs = simple_strtoul(argv[2], NULL, 16);
pmic_dump(nregs);
return 0;
}
if (strcmp(cmd, "write") == 0) {
- if (argc < 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 4)
+ return cmd_usage(cmdtp);
+
nregs = simple_strtoul(argv[2], NULL, 16);
val = simple_strtoul(argv[3], NULL, 16);
pmic_reg_write(nregs, val);
diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c
index acd6a90..3fedddc 100644
--- a/drivers/misc/gpio_led.c
+++ b/drivers/misc/gpio_led.c
@@ -2,26 +2,22 @@
* Status LED driver based on GPIO access conventions of Linux
*
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <status_led.h>
#include <asm/gpio.h>
-/* assume led is active low */
-
void __led_init(led_id_t mask, int state)
{
- gpio_direction_output(mask, (state == STATUS_LED_ON) ? 0 : 1);
+ gpio_request(mask, "gpio_led");
+ gpio_direction_output(mask, state == STATUS_LED_ON);
}
void __led_set(led_id_t mask, int state)
{
- gpio_set_value(mask, (state == STATUS_LED_ON) ? 0 : 1);
+ gpio_set_value(mask, state == STATUS_LED_ON);
}
void __led_toggle(led_id_t mask)
diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c
index f9d560a..4a77779 100644
--- a/drivers/mmc/bfin_sdh.c
+++ b/drivers/mmc/bfin_sdh.c
@@ -15,6 +15,7 @@
#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/blackfin.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/sdh.h>
#include <asm/mach-common/bits/dma.h>
@@ -41,11 +42,15 @@
# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
+# define PORTMUX_PINS \
+ { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
#elif defined(__ADSPBF54x__)
# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
+# define PORTMUX_PINS \
+ { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
#else
# error no support for this proc yet
#endif
@@ -208,18 +213,13 @@
static int bfin_sdh_init(struct mmc *mmc)
{
-
+ const unsigned short pins[] = PORTMUX_PINS;
u16 pwr_ctl = 0;
-/* Initialize sdh controller */
+
+ /* Initialize sdh controller */
+ peripheral_request_list(pins, "bfin_sdh");
#if defined(__ADSPBF54x__)
bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
- bfin_write_PORTC_FER(bfin_read_PORTC_FER() | 0x3F00);
- bfin_write_PORTC_MUX(bfin_read_PORTC_MUX() & ~0xFFF0000);
-#elif defined(__ADSPBF51x__)
- bfin_write_PORTG_FER(bfin_read_PORTG_FER() | 0x01F8);
- bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~0x3FC) | 0x154);
-#else
-# error no portmux for this proc yet
#endif
bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
/* Disable card detect pin */
diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c
index 96c0e65..9506cca 100644
--- a/drivers/mmc/omap3_mmc.c
+++ b/drivers/mmc/omap3_mmc.c
@@ -30,7 +30,8 @@
#include <i2c.h>
#include <twl4030.h>
#include <asm/io.h>
-#include <asm/arch/mmc.h>
+
+#include "omap3_mmc.h"
const unsigned short mmc_transspeed_val[15][4] = {
{CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
@@ -52,7 +53,27 @@
mmc_card_data cur_card_data;
static block_dev_desc_t mmc_blk_dev;
-static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC_BASE;
+static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+
+int mmc_set_dev(int dev_num)
+{
+ switch (dev_num) {
+ case 1:
+ mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+ break;
+ case 2:
+ mmc_base = (hsmmc_t *)OMAP_HSMMC2_BASE;
+ break;
+ case 3:
+ mmc_base = (hsmmc_t *)OMAP_HSMMC3_BASE;
+ break;
+ default:
+ mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+ return 1;
+ }
+
+ return 0;
+}
block_dev_desc_t *mmc_get_dev(int dev)
{
@@ -61,12 +82,14 @@
unsigned char mmc_board_init(void)
{
- t2_t *t2_base = (t2_t *)T2_BASE;
-
#if defined(CONFIG_TWL4030_POWER)
twl4030_power_mmc_init();
#endif
+#if defined(CONFIG_OMAP34XX)
+ t2_t *t2_base = (t2_t *)T2_BASE;
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
&t2_base->pbias_lite);
@@ -74,6 +97,20 @@
writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
&t2_base->devconf0);
+ writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
+ &t2_base->devconf1);
+
+ writel(readl(&prcm_base->fclken1_core) |
+ EN_MMC1 | EN_MMC2 | EN_MMC3,
+ &prcm_base->fclken1_core);
+
+ writel(readl(&prcm_base->iclken1_core) |
+ EN_MMC1 | EN_MMC2 | EN_MMC3,
+ &prcm_base->iclken1_core);
+#endif
+
+/* TODO add appropriate OMAP4 init */
+
return 1;
}
@@ -512,8 +549,11 @@
return 1;
}
-int mmc_legacy_init(int verbose)
+int mmc_legacy_init(int dev)
{
+ if (mmc_set_dev(dev) != 0)
+ return 1;
+
if (configure_mmc(&cur_card_data) != 1)
return 1;
diff --git a/arch/arm/include/asm/arch-omap3/mmc.h b/drivers/mmc/omap3_mmc.h
similarity index 98%
rename from arch/arm/include/asm/arch-omap3/mmc.h
rename to drivers/mmc/omap3_mmc.h
index 196ffdc..cbb3dc3 100644
--- a/arch/arm/include/asm/arch-omap3/mmc.h
+++ b/drivers/mmc/omap3_mmc.h
@@ -25,7 +25,7 @@
#ifndef MMC_H
#define MMC_H
-#include "mmc_host_def.h"
+#include <asm/arch/mmc_host_def.h>
/* Responses */
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
diff --git a/drivers/mtd/nand/bfin_nand.c b/drivers/mtd/nand/bfin_nand.c
index 6d3d450..3ee060f 100644
--- a/drivers/mtd/nand/bfin_nand.c
+++ b/drivers/mtd/nand/bfin_nand.c
@@ -26,6 +26,7 @@
#include <nand.h>
#include <asm/blackfin.h>
+#include <asm/portmux.h>
/* Bit masks for NFC_CTL */
@@ -337,6 +338,12 @@
*/
int board_nand_init(struct nand_chip *chip)
{
+ const unsigned short pins[] = {
+ P_NAND_CE, P_NAND_RB, P_NAND_D0, P_NAND_D1, P_NAND_D2,
+ P_NAND_D3, P_NAND_D4, P_NAND_D5, P_NAND_D6, P_NAND_D7,
+ P_NAND_WE, P_NAND_RE, P_NAND_CLE, P_NAND_ALE, 0,
+ };
+
pr_stamp();
/* set width/ecc/timings/etc... */
@@ -347,14 +354,7 @@
bfin_write_NFC_IRQSTAT(0xffff);
/* enable GPIO function enable register */
-#ifdef __ADSPBF54x__
- bfin_write_PORTJ_FER(bfin_read_PORTJ_FER() | 6);
-#elif defined(__ADSPBF52x__)
- bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0xFCFF);
- bfin_write_PORTH_MUX(0);
-#else
-# error no support for this variant
-#endif
+ peripheral_request_list(pins, "bfin_nand");
chip->cmd_ctrl = bfin_nfc_cmd_ctrl;
chip->read_buf = bfin_nfc_read_buf;
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 146e9bf..acdb431 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -75,7 +75,7 @@
struct fsl_elbc_mtd *chips[MAX_BANKS];
/* device info */
- fsl_lbus_t *regs;
+ fsl_lbc_t *regs;
u8 __iomem *addr; /* Address of assigned FCM buffer */
unsigned int page; /* Last page written to / read from */
unsigned int read_bytes; /* Number of bytes read during command */
@@ -171,7 +171,7 @@
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- fsl_lbus_t *lbc = ctrl->regs;
+ fsl_lbc_t *lbc = ctrl->regs;
int buf_num;
ctrl->page = page_addr;
@@ -211,7 +211,7 @@
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- fsl_lbus_t *lbc = ctrl->regs;
+ fsl_lbc_t *lbc = ctrl->regs;
long long end_tick;
u32 ltesr;
@@ -261,7 +261,7 @@
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- fsl_lbus_t *lbc = ctrl->regs;
+ fsl_lbc_t *lbc = ctrl->regs;
if (priv->page_size) {
out_be32(&lbc->fir,
@@ -295,7 +295,7 @@
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- fsl_lbus_t *lbc = ctrl->regs;
+ fsl_lbc_t *lbc = ctrl->regs;
ctrl->use_mdr = 0;
@@ -633,7 +633,7 @@
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- fsl_lbus_t *lbc = ctrl->regs;
+ fsl_lbc_t *lbc = ctrl->regs;
if (ctrl->status != LTESR_CC)
return NAND_STATUS_FAIL;
@@ -697,11 +697,7 @@
if (!elbc_ctrl)
return;
-#ifdef CONFIG_MPC85xx
- elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
-#else
- elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
-#endif
+ elbc_ctrl->regs = LBC_BASE_ADDR;
/* clear event registers */
out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 7171bdd..ed1c9c9 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2652,8 +2652,12 @@
}
}
- if (!type)
+ if (!type) {
+ printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:"
+ " 0x%02x, Chip ID: 0x%02x\n", __func__,
+ *maf_id, dev_id);
return ERR_PTR(-ENODEV);
+ }
if (!mtd->name)
mtd->name = type->name;
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 077c305..25b22ec 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -83,6 +83,7 @@
/* 1 Gigabit */
{"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
{"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
+ {"NAND 128MiB 3,3V 8-bit", 0xD1, 0, 128, 0, LP_OPTIONS},
{"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
{"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
diff --git a/drivers/mtd/nand/nand_plat.c b/drivers/mtd/nand/nand_plat.c
index b35492b..37a0206 100644
--- a/drivers/mtd/nand/nand_plat.c
+++ b/drivers/mtd/nand/nand_plat.c
@@ -16,6 +16,10 @@
#include <common.h>
#include <asm/io.h>
+#ifdef NAND_PLAT_GPIO_DEV_READY
+# include <asm/gpio.h>
+# define NAND_PLAT_DEV_READY(chip) gpio_get_value(NAND_PLAT_GPIO_DEV_READY)
+#endif
#include <nand.h>
@@ -43,7 +47,14 @@
int board_nand_init(struct nand_chip *nand)
{
+#ifdef NAND_PLAT_GPIO_DEV_READY
+ gpio_request(NAND_PLAT_GPIO_DEV_READY, "nand-plat");
+ gpio_direction_input(NAND_PLAT_GPIO_DEV_READY);
+#endif
+
+#ifdef NAND_PLAT_INIT
NAND_PLAT_INIT();
+#endif
nand->cmd_ctrl = plat_cmd_ctrl;
nand->dev_ready = plat_dev_ready;
diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
index 2fac641..144b851 100644
--- a/drivers/net/4xx_enet.c
+++ b/drivers/net/4xx_enet.c
@@ -1095,6 +1095,11 @@
miiphy_write (dev->name, reg, 0x18, 0x4101);
miiphy_write (dev->name, reg, 0x09, 0x0e00);
miiphy_write (dev->name, reg, 0x04, 0x01e1);
+#if defined(CONFIG_M88E1111_DISABLE_FIBER)
+ miiphy_read(dev->name, reg, 0x1b, ®_short);
+ reg_short |= 0x8000;
+ miiphy_write(dev->name, reg, 0x1b, reg_short);
+#endif
#endif
#if defined(CONFIG_M88E1112_PHY)
if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b75c02f..218eeff 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -34,6 +34,7 @@
COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
COBJS-$(CONFIG_CS8900) += cs8900.o
COBJS-$(CONFIG_TULIP) += dc2114x.o
+COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o
COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
COBJS-$(CONFIG_DNET) += dnet.o
COBJS-$(CONFIG_E1000) += e1000.o
@@ -46,13 +47,13 @@
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
COBJS-$(CONFIG_GRETH) += greth.o
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
-COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
COBJS-$(CONFIG_LAN91C96) += lan91c96.o
COBJS-$(CONFIG_MACB) += macb.o
COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
+COBJS-$(CONFIG_MVGBE) += mvgbe.o
COBJS-$(CONFIG_NATSEMI) += natsemi.o
COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index 2399569..245da12 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -53,6 +53,10 @@
Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
#endif
+#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
+#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
+#endif
+
/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
#if (AT91C_MASTER_CLOCK > 80000000)
#define HCLK_DIV AT91_EMAC_CFG_MCLK_64
@@ -198,12 +202,15 @@
emac = (at91_emac_t *) netdev->iobase;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
- at91emac_write(emac, 0, MII_ADVERTISE, adv);
+ at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_ADVERTISE, adv);
VERBOSEP("%s: Starting autonegotiation...\n", netdev->name);
- at91emac_write(emac, 0, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
+ at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
+ (BMCR_ANENABLE | BMCR_ANRESTART));
for (i = 0; i < 100000 / 100; i++) {
- at91emac_read(emac, 0, MII_BMSR, &status);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_BMSR, &status);
if (status & BMSR_ANEGCOMPLETE)
break;
udelay(100);
@@ -229,13 +236,15 @@
emac = (at91_emac_t *) netdev->iobase;
/* Check if the PHY is up to snuff... */
- at91emac_read(emac, 0, MII_PHYSID1, &phy_id);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_PHYSID1, &phy_id);
if (phy_id == 0xffff) {
printf("%s: No PHY present\n", netdev->name);
return 1;
}
- at91emac_read(emac, 0, MII_BMSR, &status);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_BMSR, &status);
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
@@ -243,7 +252,8 @@
return 2;
for (i = 0; i < 100000 / 100; i++) {
- at91emac_read(emac, 0, MII_BMSR, &status);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_BMSR, &status);
if (status & BMSR_LSTATUS)
break;
udelay(100);
@@ -253,8 +263,10 @@
VERBOSEP("%s: link down\n", netdev->name);
return 3;
} else {
- at91emac_read(emac, 0, MII_ADVERTISE, &adv);
- at91emac_read(emac, 0, MII_LPA, &lpa);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_ADVERTISE, &adv);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_LPA, &lpa);
media = mii_nway_result(lpa & adv);
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
? 1 : 0);
@@ -271,7 +283,7 @@
{
unsigned short stat1;
- at91emac_read(emac, 0, MII_BMSR, &stat1);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
return 1;
@@ -348,14 +360,6 @@
writel(1 << AT91_ID_EMAC, &pmc->pcer);
writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
- DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
- cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))),
- cpu_to_le32(*((u32 *)netdev->enetaddr)));
- writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l);
- writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h);
- DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
- readl(&emac->sa2h), readl(&emac->sa2l));
-
/* Init Ethernet buffers */
for (i = 0; i < RBF_FRAMEMAX; i++) {
dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
@@ -372,7 +376,7 @@
value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC |
HCLK_DIV;
#ifdef CONFIG_RMII
- value |= AT91C_EMAC_RMII;
+ value |= AT91_EMAC_CFG_RMII;
#endif
writel(value, &emac->cfg);
@@ -456,6 +460,25 @@
return 0;
}
+static int at91emac_write_hwaddr(struct eth_device *netdev)
+{
+ emac_device *dev;
+ at91_emac_t *emac;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ emac = (at91_emac_t *) netdev->iobase;
+ dev = (emac_device *) netdev->priv;
+
+ writel(1 << AT91_ID_EMAC, &pmc->pcer);
+ DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
+ cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))),
+ cpu_to_le32(*((u32 *)netdev->enetaddr)));
+ writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l);
+ writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h);
+ DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
+ readl(&emac->sa2h), readl(&emac->sa2l));
+ return 0;
+}
+
int at91emac_register(bd_t *bis, unsigned long iobase)
{
emac_device *emac;
@@ -488,6 +511,7 @@
dev->halt = at91emac_halt;
dev->send = at91emac_send;
dev->recv = at91emac_recv;
+ dev->write_hwaddr = at91emac_write_hwaddr;
eth_register(dev);
diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c
index d843397..bc3e6ad 100644
--- a/drivers/net/ax88180.c
+++ b/drivers/net/ax88180.c
@@ -41,6 +41,7 @@
#include <command.h>
#include <net.h>
#include <malloc.h>
+#include <linux/mii.h>
#include "ax88180.h"
/*
@@ -50,9 +51,9 @@
*/
static void ax88180_rx_handler (struct eth_device *dev);
static int ax88180_phy_initial (struct eth_device *dev);
-static void ax88180_meidia_config (struct eth_device *dev);
-static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev);
-static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev);
+static void ax88180_media_config (struct eth_device *dev);
+static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev);
+static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev);
static unsigned short ax88180_mdio_read (struct eth_device *dev,
unsigned long regaddr);
static void ax88180_mdio_write (struct eth_device *dev,
@@ -112,10 +113,10 @@
{
unsigned short delay_cnt = 500;
- ax88180_mdio_write (dev, BMCR, (PHY_RESET | AUTONEG_EN));
+ ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE));
/* Wait for the reset to complete, or time out (500 ms) */
- while (ax88180_mdio_read (dev, BMCR) & PHY_RESET) {
+ while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
udelay (1000);
if (--delay_cnt == 0) {
printf ("Failed to reset PHY!\n");
@@ -255,52 +256,78 @@
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned long tmp_regval;
+ unsigned short phyaddr;
- /* Check avaliable PHY chipset */
- priv->PhyAddr = MARVELL_88E1111_PHYADDR;
- priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0);
+ /* Search for first avaliable PHY chipset */
+#ifdef CONFIG_PHY_ADDR
+ phyaddr = CONFIG_PHY_ADDR;
+#else
+ for (phyaddr = 0; phyaddr < 32; ++phyaddr)
+#endif
+ {
+ priv->PhyAddr = phyaddr;
+ priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1);
+ priv->PhyID1 = ax88180_mdio_read(dev, MII_PHYSID2);
- if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) {
+ switch (priv->PhyID0) {
+ case MARVELL_ALASKA_PHYSID0:
+ debug("ax88180: Found Marvell Alaska PHY family."
+ " (PHY Addr=0x%x)\n", priv->PhyAddr);
- debug ("ax88180: Found Marvell 88E1111 PHY."
- " (PHY Addr=0x%x)\n", priv->PhyAddr);
+ switch (priv->PhyID1) {
+ case MARVELL_88E1118_PHYSID1:
+ ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 2);
+ ax88180_mdio_write(dev, M88E1118_CR,
+ M88E1118_CR_DEFAULT);
+ ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 3);
+ ax88180_mdio_write(dev, M88E1118_LEDCTL,
+ M88E1118_LEDCTL_DEFAULT);
+ ax88180_mdio_write(dev, M88E1118_LEDMIX,
+ M88E1118_LEDMIX_LED050 | M88E1118_LEDMIX_LED150 | 0x15);
+ ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 0);
+ default: /* Default to 88E1111 Phy */
+ tmp_regval = ax88180_mdio_read(dev, M88E1111_EXT_SSR);
+ if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE)
+ ax88180_mdio_write(dev, M88E1111_EXT_SCR,
+ DEFAULT_EXT_SCR);
+ }
- tmp_regval = ax88180_mdio_read (dev, M88_EXT_SSR);
- if ((tmp_regval & HWCFG_MODE_MASK) == RGMII_COPPER_MODE) {
-
- ax88180_mdio_write (dev, M88_EXT_SCR, DEFAULT_EXT_SCR);
- if (ax88180_phy_reset (dev) < 0)
+ if (ax88180_phy_reset(dev) < 0)
return 0;
- ax88180_mdio_write (dev, M88_IER, LINK_CHANGE_INT);
- }
- } else {
+ ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT);
- priv->PhyAddr = CICADA_CIS8201_PHYADDR;
- priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0);
+ return 1;
- if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) {
+ case CICADA_CIS8201_PHYSID0:
+ debug("ax88180: Found CICADA CIS8201 PHY"
+ " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
- debug ("ax88180: Found CICADA CIS8201 PHY"
- " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
- ax88180_mdio_write (dev, CIS_IMR,
+ ax88180_mdio_write(dev, CIS_IMR,
(CIS_INT_ENABLE | LINK_CHANGE_INT));
/* Set CIS_SMI_PRIORITY bit before force the media mode */
- tmp_regval =
- ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
+ tmp_regval = ax88180_mdio_read(dev, CIS_AUX_CTRL_STATUS);
tmp_regval &= ~CIS_SMI_PRIORITY;
- ax88180_mdio_write (dev, CIS_AUX_CTRL_STATUS,
- tmp_regval);
- } else {
- printf ("ax88180: Unknown PHY chipset!!\n");
- return 0;
+ ax88180_mdio_write(dev, CIS_AUX_CTRL_STATUS, tmp_regval);
+
+ return 1;
+
+ case 0xffff:
+ /* No PHY at this addr */
+ break;
+
+ default:
+ printf("ax88180: Unknown PHY chipset %#x at addr %#x\n",
+ priv->PhyID0, priv->PhyAddr);
+ break;
}
}
- return 1;
+ printf("ax88180: Unknown PHY chipset!!\n");
+ return 0;
}
-static void ax88180_meidia_config (struct eth_device *dev)
+static void ax88180_media_config (struct eth_device *dev)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned long bmcr_val, bmsr_val;
@@ -310,20 +337,20 @@
/* Waiting 2 seconds for PHY link stable */
for (i = 0; i < 20000; i++) {
- bmsr_val = ax88180_mdio_read (dev, BMSR);
- if (bmsr_val & LINKOK) {
+ bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
+ if (bmsr_val & BMSR_LSTATUS) {
break;
}
udelay (100);
}
- bmsr_val = ax88180_mdio_read (dev, BMSR);
+ bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
- if (bmsr_val & LINKOK) {
- bmcr_val = ax88180_mdio_read (dev, BMCR);
+ if (bmsr_val & BMSR_LSTATUS) {
+ bmcr_val = ax88180_mdio_read (dev, MII_BMCR);
- if (bmcr_val & AUTONEG_EN) {
+ if (bmcr_val & BMCR_ANENABLE) {
/*
* Waiting for Auto-negotiation completion, this may
@@ -332,8 +359,8 @@
debug ("ax88180: Auto-negotiation is "
"enabled. Waiting for NWay completion..\n");
for (i = 0; i < 50000; i++) {
- bmsr_val = ax88180_mdio_read (dev, BMSR);
- if (bmsr_val & AUTONEG_COMPLETE) {
+ bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
+ if (bmsr_val & BMSR_ANEGCOMPLETE) {
break;
}
udelay (100);
@@ -345,12 +372,16 @@
(unsigned int)bmcr_val, (unsigned int)bmsr_val);
/* Get real media mode here */
- if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) {
- RealMediaMode = get_MarvellPHY_meida_mode (dev);
- } else if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) {
- RealMediaMode = get_CicadaPHY_meida_mode (dev);
- } else {
+ switch (priv->PhyID0) {
+ case MARVELL_ALASKA_PHYSID0:
+ RealMediaMode = get_MarvellPHY_media_mode(dev);
+ break;
+ case CICADA_CIS8201_PHYSID0:
+ RealMediaMode = get_CicadaPHY_media_mode(dev);
+ break;
+ default:
RealMediaMode = MEDIA_1000FULL;
+ break;
}
priv->LinkState = INS_LINK_UP;
@@ -424,7 +455,7 @@
return;
}
-static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev)
+static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev)
{
unsigned long m88_ssr;
unsigned long MediaMode;
@@ -457,7 +488,7 @@
return MediaMode;
}
-static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev)
+static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev)
{
unsigned long tmp_regval;
unsigned long MediaMode;
@@ -522,7 +553,7 @@
dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
OUTW (dev, tmp_regval, MACID2);
- ax88180_meidia_config (dev);
+ ax88180_media_config (dev);
OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
@@ -558,7 +589,7 @@
if (ISR_Status & ISR_PHY) {
/* Read ISR register once to clear PHY interrupt bit */
tmp_regval = ax88180_mdio_read (dev, M88_ISR);
- ax88180_meidia_config (dev);
+ ax88180_media_config (dev);
}
if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {
diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h
index d2113df..daf18e0 100644
--- a/drivers/net/ax88180.h
+++ b/drivers/net/ax88180.h
@@ -19,6 +19,7 @@
#ifndef _AX88180_H_
#define _AX88180_H_
+#include <asm/io.h>
#include <asm/types.h>
#include <config.h>
@@ -33,6 +34,7 @@
unsigned char PadSize;
unsigned short PhyAddr;
unsigned short PhyID0;
+ unsigned short PhyID1;
unsigned short FirstTxDesc;
unsigned short NextTxDesc;
ax88180_link_state LinkState;
@@ -63,11 +65,10 @@
/* Max Rx Jumbo size is 15K Bytes */
#define MAX_RX_SIZE 0x3C00
-#define MARVELL_88E1111_PHYADDR 0x18
-#define MARVELL_88E1111_PHYIDR0 0x0141
+#define MARVELL_ALASKA_PHYSID0 0x141
+#define MARVELL_88E1118_PHYSID1 0xE40
-#define CICADA_CIS8201_PHYADDR 0x01
-#define CICADA_CIS8201_PHYIDR0 0x000F
+#define CICADA_CIS8201_PHYSID0 0x000F
#define MEDIA_AUTO 0
#define MEDIA_1000FULL 1
@@ -278,50 +279,6 @@
#define SOFTRST_NORMAL 0x00000003
#define SOFTRST_RESET_MAC 0x00000002
-/* External PHY Register Definition */
-#define BMCR 0x0000
- #define LINE_SPEED_MSB 0x0040
- #define DUPLEX_MODE 0x0100
- #define RESTART_AUTONEG 0x0200
- #define POWER_DOWN 0x0800
- #define AUTONEG_EN 0x1000
- #define LINE_SPEED_LSB 0x2000
- #define PHY_RESET 0x8000
-
- #define MEDIAMODE_MASK (LINE_SPEED_MSB | LINE_SPEED_LSB |\
- DUPLEX_MODE)
- #define BMCR_SPEED_1000 LINE_SPEED_MSB
- #define BMCR_SPEED_100 LINE_SPEED_LSB
- #define BMCR_SPEED_10 0x0000
-
- #define BMCR_1000FULL (BMCR_SPEED_1000 | DUPLEX_MODE)
- #define BMCR_100FULL (BMCR_SPEED_100 | DUPLEX_MODE)
- #define BMCR_100HALF BMCR_SPEED_100
- #define BMCR_10FULL DUPLEX_MODE
- #define BMCR_10HALF 0x0000
-#define BMSR 0x0001
- #define LINKOK 0x0004
- #define AUTONEG_ENABLE_STS 0x0008
- #define AUTONEG_COMPLETE 0x0020
-#define PHYIDR0 0x0002
-#define PHYIDR1 0x0003
-#define ANAR 0x0004
- #define ANAR_PAUSE 0x0400
- #define ANAR_100FULL 0x0100
- #define ANAR_100HALF 0x0080
- #define ANAR_10FULL 0x0040
- #define ANAR_10HALF 0x0020
- #define ANAR_8023BIT 0x0001
-#define ANLPAR 0x0005
-#define ANER 0x0006
-#define AUX_1000_CTRL 0x0009
- #define ENABLE_1000HALF 0x0100
- #define ENABLE_1000FULL 0x0200
- #define DEFAULT_AUX_1000_CTRL (ENABLE_1000HALF | ENABLE_1000FULL)
-#define AUX_1000_STATUS 0x000A
- #define LP_1000HALF 0x0400
- #define LP_1000FULL 0x0800
-
/* Marvell 88E1111 Gigabit PHY Register Definition */
#define M88_SSR 0x0011
#define SSR_SPEED_MASK 0xC000
@@ -342,14 +299,36 @@
#define LINK_CHANGE_INT 0x0400
#define M88_ISR 0x0013
#define LINK_CHANGE_STATUS 0x0400
-#define M88_EXT_SCR 0x0014
+#define M88E1111_EXT_SCR 0x0014
#define RGMII_RXCLK_DELAY 0x0080
#define RGMII_TXCLK_DELAY 0x0002
#define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
-#define M88_EXT_SSR 0x001B
+#define M88E1111_EXT_SSR 0x001B
#define HWCFG_MODE_MASK 0x000F
#define RGMII_COPPER_MODE 0x000B
+/* Marvell 88E1118 Gigabit PHY Register Definition */
+#define M88E1118_CR 0x14
+ #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
+ #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
+ #define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \
+ M88E1118_CR_RGMII_RXCLK_DELAY)
+#define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
+ #define M88E1118_LEDCTL_LED2INT 0x200
+ #define M88E1118_LEDCTL_LED2BLNK 0x400
+ #define M88E1118_LEDCTL_LED0DUALMODE1 0xc
+ #define M88E1118_LEDCTL_LED0DUALMODE2 0xd
+ #define M88E1118_LEDCTL_LED0DUALMODE3 0xe
+ #define M88E1118_LEDCTL_LED0DUALMODE4 0xf
+ #define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \
+ M88E1118_LEDCTL_LED0DUALMODE4)
+
+#define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
+ #define M88E1118_LEDMIX_LED050 0x4
+ #define M88E1118_LEDMIX_LED150 0x8
+
+#define M88E1118_PAGE_SEL 0x16 /* Reg page select */
+
/* CICADA CIS8201 Gigabit PHY Register Definition */
#define CIS_IMR 0x0019
#define CIS_INT_ENABLE 0x8000
@@ -376,36 +355,41 @@
static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
{
- return le16_to_cpu (*(volatile unsigned short *) (addr + dev->iobase));
-}
-
-static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
-{
- *(volatile unsigned short *) ((addr + dev->iobase)) = cpu_to_le16 (command);
+ return le16_to_cpu(readw(addr + (void *)dev->iobase));
}
/*
Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
*/
#if defined (CONFIG_DRIVER_AX88180_16BIT)
+static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
+{
+ writew(cpu_to_le16(command), addr + (void *)dev->iobase);
+}
+
static inline unsigned short READ_RXBUF (struct eth_device *dev)
{
- return le16_to_cpu (*(volatile unsigned short *) (RXBUFFER_START + dev->iobase));
+ return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase));
}
static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
{
- *(volatile unsigned short *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le16 (data);
+ writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase);
}
#else
+static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
+{
+ writel(cpu_to_le32(command), addr + (void *)dev->iobase);
+}
+
static inline unsigned long READ_RXBUF (struct eth_device *dev)
{
- return le32_to_cpu (*(volatile unsigned long *) (RXBUFFER_START + dev->iobase));
+ return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase));
}
static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
{
- *(volatile unsigned long *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le32 (data);
+ writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase);
}
#endif
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index 720e126..e691bdf 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -16,6 +16,7 @@
#include <linux/mii.h>
#include <asm/blackfin.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
#include <asm/mach-common/bits/pll.h>
@@ -98,7 +99,7 @@
hang();
memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "Blackfin EMAC");
+ strcpy(dev->name, "bfin_mac");
dev->iobase = 0;
dev->priv = 0;
@@ -213,8 +214,17 @@
/* MDC = SCLK / MDC_freq / 2 - 1 */
#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
+#ifndef CONFIG_BFIN_MAC_PINS
+# ifdef CONFIG_RMII
+# define CONFIG_BFIN_MAC_PINS P_RMII0
+# else
+# define CONFIG_BFIN_MAC_PINS P_MII0
+# endif
+#endif
+
static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
{
+ const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
u16 phydat;
size_t count;
@@ -222,42 +232,7 @@
*pVR_CTL |= CLKBUFOE;
/* Set all the pins to peripheral mode */
-#ifdef CONFIG_RMII
- /* grab RMII pins */
-# if defined(__ADSPBF51x__)
- *pPORTF_MUX = (*pPORTF_MUX & \
- ~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
- PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
- *pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
- *pPORTG_FER |= PG0 | PG1 | PG2;
-# elif defined(__ADSPBF52x__)
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
- *pPORTG_FER |= PG14 | PG15;
- *pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
- PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
- *pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
-# else
- *pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
-# endif
-#else
- /* grab MII & RMII pins */
-# if defined(__ADSPBF51x__)
- *pPORTF_MUX = (*pPORTF_MUX & \
- ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
- PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
- *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
- *pPORTG_FER |= PG0 | PG1 | PG2;
-# elif defined(__ADSPBF52x__)
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
- *pPORTG_FER |= PG14 | PG15;
- *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
- *pPORTH_FER = -1; /* all pins */
-# else
- *pPORTH_FER = -1; /* all pins */
-# endif
-#endif
+ peripheral_request_list(pins, "bfin_mac");
/* Odd word alignment for Receive Frame DMA word */
/* Configure checksum support and rcve frame word alignment */
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
new file mode 100644
index 0000000..d0d9827
--- /dev/null
+++ b/drivers/net/designware.c
@@ -0,0 +1,531 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Designware ethernet IP driver for u-boot
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include "designware.h"
+
+static void tx_descs_init(struct eth_device *dev)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ struct eth_dma_regs *dma_p = priv->dma_regs_p;
+ struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
+ char *txbuffs = &priv->txbuffs[0];
+ struct dmamacdescr *desc_p;
+ u32 idx;
+
+ for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
+ desc_p = &desc_table_p[idx];
+ desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
+ desc_p->dmamac_next = &desc_table_p[idx + 1];
+
+#if defined(CONFIG_DW_ALTDESCRIPTOR)
+ desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
+ DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
+ DESC_TXSTS_TXCHECKINSCTRL | \
+ DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
+
+ desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
+ desc_p->dmamac_cntl = 0;
+ desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
+#else
+ desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
+ desc_p->txrx_status = 0;
+#endif
+ }
+
+ /* Correcting the last pointer of the chain */
+ desc_p->dmamac_next = &desc_table_p[0];
+
+ writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
+}
+
+static void rx_descs_init(struct eth_device *dev)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ struct eth_dma_regs *dma_p = priv->dma_regs_p;
+ struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
+ char *rxbuffs = &priv->rxbuffs[0];
+ struct dmamacdescr *desc_p;
+ u32 idx;
+
+ for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
+ desc_p = &desc_table_p[idx];
+ desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
+ desc_p->dmamac_next = &desc_table_p[idx + 1];
+
+ desc_p->dmamac_cntl =
+ (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
+ DESC_RXCTRL_RXCHAIN;
+
+ desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
+ }
+
+ /* Correcting the last pointer of the chain */
+ desc_p->dmamac_next = &desc_table_p[0];
+
+ writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
+}
+
+static void descs_init(struct eth_device *dev)
+{
+ tx_descs_init(dev);
+ rx_descs_init(dev);
+}
+
+static int mac_reset(struct eth_device *dev)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+ struct eth_dma_regs *dma_p = priv->dma_regs_p;
+
+ int timeout = CONFIG_MACRESET_TIMEOUT;
+
+ writel(DMAMAC_SRST, &dma_p->busmode);
+ writel(MII_PORTSELECT, &mac_p->conf);
+
+ do {
+ if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
+ return 0;
+ udelay(1000);
+ } while (timeout--);
+
+ return -1;
+}
+
+static int dw_write_hwaddr(struct eth_device *dev)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+ u32 macid_lo, macid_hi;
+ u8 *mac_id = &dev->enetaddr[0];
+
+ macid_lo = mac_id[0] + (mac_id[1] << 8) + \
+ (mac_id[2] << 16) + (mac_id[3] << 24);
+ macid_hi = mac_id[4] + (mac_id[5] << 8);
+
+ writel(macid_hi, &mac_p->macaddr0hi);
+ writel(macid_lo, &mac_p->macaddr0lo);
+
+ return 0;
+}
+
+static int dw_eth_init(struct eth_device *dev, bd_t *bis)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+ struct eth_dma_regs *dma_p = priv->dma_regs_p;
+ u32 conf;
+
+ /* Reset ethernet hardware */
+ if (mac_reset(dev) < 0)
+ return -1;
+
+ writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
+ &dma_p->busmode);
+
+ writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
+ writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
+
+ conf = FRAMEBURSTENABLE | DISABLERXOWN;
+
+ if (priv->speed != SPEED_1000M)
+ conf |= MII_PORTSELECT;
+
+ if (priv->duplex == FULL_DUPLEX)
+ conf |= FULLDPLXMODE;
+
+ writel(conf, &mac_p->conf);
+
+ descs_init(dev);
+
+ /*
+ * Start/Enable xfer at dma as well as mac level
+ */
+ writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
+ writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
+
+ writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf);
+ writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf);
+
+ return 0;
+}
+
+static int dw_eth_send(struct eth_device *dev, volatile void *packet,
+ int length)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ struct eth_dma_regs *dma_p = priv->dma_regs_p;
+ u32 desc_num = priv->tx_currdescnum;
+ struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
+
+ /* Check if the descriptor is owned by CPU */
+ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
+ printf("CPU not owner of tx frame\n");
+ return -1;
+ }
+
+ memcpy((void *)desc_p->dmamac_addr, (void *)packet, length);
+
+#if defined(CONFIG_DW_ALTDESCRIPTOR)
+ desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
+ desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
+ DESC_TXCTRL_SIZE1MASK;
+
+ desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
+ desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
+#else
+ desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
+ DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
+ DESC_TXCTRL_TXFIRST;
+
+ desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
+#endif
+
+ /* Test the wrap-around condition. */
+ if (++desc_num >= CONFIG_TX_DESCR_NUM)
+ desc_num = 0;
+
+ priv->tx_currdescnum = desc_num;
+
+ /* Start the transmission */
+ writel(POLL_DATA, &dma_p->txpolldemand);
+
+ return 0;
+}
+
+static int dw_eth_recv(struct eth_device *dev)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ u32 desc_num = priv->rx_currdescnum;
+ struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
+
+ u32 status = desc_p->txrx_status;
+ int length = 0;
+
+ /* Check if the owner is the CPU */
+ if (!(status & DESC_RXSTS_OWNBYDMA)) {
+
+ length = (status & DESC_RXSTS_FRMLENMSK) >> \
+ DESC_RXSTS_FRMLENSHFT;
+
+ NetReceive(desc_p->dmamac_addr, length);
+
+ /*
+ * Make the current descriptor valid again and go to
+ * the next one
+ */
+ desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
+
+ /* Test the wrap-around condition. */
+ if (++desc_num >= CONFIG_RX_DESCR_NUM)
+ desc_num = 0;
+ }
+
+ priv->rx_currdescnum = desc_num;
+
+ return length;
+}
+
+static void dw_eth_halt(struct eth_device *dev)
+{
+ struct dw_eth_dev *priv = dev->priv;
+
+ mac_reset(dev);
+ priv->tx_currdescnum = priv->rx_currdescnum = 0;
+}
+
+static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+ u32 miiaddr;
+ int timeout = CONFIG_MDIO_TIMEOUT;
+
+ miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
+ ((reg << MIIREGSHIFT) & MII_REGMSK);
+
+ writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
+
+ do {
+ if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
+ *val = readl(&mac_p->miidata);
+ return 0;
+ }
+ udelay(1000);
+ } while (timeout--);
+
+ return -1;
+}
+
+static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+ u32 miiaddr;
+ int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
+ u16 value;
+
+ writel(val, &mac_p->miidata);
+ miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
+ ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
+
+ writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
+
+ do {
+ if (!(readl(&mac_p->miiaddr) & MII_BUSY))
+ ret = 0;
+ udelay(1000);
+ } while (timeout--);
+
+ /* Needed as a fix for ST-Phy */
+ eth_mdio_read(dev, addr, reg, &value);
+
+ return ret;
+}
+
+#if defined(CONFIG_DW_SEARCH_PHY)
+static int find_phy(struct eth_device *dev)
+{
+ int phy_addr = 0;
+ u16 ctrl, oldctrl;
+
+ do {
+ eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
+ oldctrl = ctrl & PHY_BMCR_AUTON;
+
+ ctrl ^= PHY_BMCR_AUTON;
+ eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
+ eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
+ ctrl &= PHY_BMCR_AUTON;
+
+ if (ctrl == oldctrl) {
+ phy_addr++;
+ } else {
+ ctrl ^= PHY_BMCR_AUTON;
+ eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
+
+ return phy_addr;
+ }
+ } while (phy_addr < 32);
+
+ return -1;
+}
+#endif
+
+static int dw_reset_phy(struct eth_device *dev)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ u16 ctrl;
+ int timeout = CONFIG_PHYRESET_TIMEOUT;
+ u32 phy_addr = priv->address;
+
+ eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET);
+ do {
+ eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
+ if (!(ctrl & PHY_BMCR_RESET))
+ break;
+ udelay(1000);
+ } while (timeout--);
+
+ if (timeout < 0)
+ return -1;
+
+#ifdef CONFIG_PHY_RESET_DELAY
+ udelay(CONFIG_PHY_RESET_DELAY);
+#endif
+ return 0;
+}
+
+static int configure_phy(struct eth_device *dev)
+{
+ struct dw_eth_dev *priv = dev->priv;
+ int phy_addr;
+ u16 bmcr, ctrl;
+#if defined(CONFIG_DW_AUTONEG)
+ u16 bmsr;
+ u32 timeout;
+ u16 anlpar, btsr;
+#endif
+
+#if defined(CONFIG_DW_SEARCH_PHY)
+ phy_addr = find_phy(dev);
+ if (phy_addr > 0)
+ priv->address = phy_addr;
+ else
+ return -1;
+#endif
+ if (dw_reset_phy(dev) < 0)
+ return -1;
+
+#if defined(CONFIG_DW_AUTONEG)
+ bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \
+ PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS;
+#else
+ bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX;
+
+#if defined(CONFIG_DW_SPEED10M)
+ bmcr &= ~PHY_BMCR_100MB;
+#endif
+#if defined(CONFIG_DW_DUPLEXHALF)
+ bmcr &= ~PHY_BMCR_DPLX;
+#endif
+#endif
+ if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0)
+ return -1;
+
+ /* Read the phy status register and populate priv structure */
+#if defined(CONFIG_DW_AUTONEG)
+ timeout = CONFIG_AUTONEG_TIMEOUT;
+ do {
+ eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr);
+ if (bmsr & PHY_BMSR_AUTN_COMP)
+ break;
+ udelay(1000);
+ } while (timeout--);
+
+ eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar);
+ eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr);
+
+ if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
+ priv->speed = SPEED_1000M;
+ if (btsr & PHY_1000BTSR_1000FD)
+ priv->duplex = FULL_DUPLEX;
+ else
+ priv->duplex = HALF_DUPLEX;
+ } else {
+ if (anlpar & PHY_ANLPAR_100)
+ priv->speed = SPEED_100M;
+ else
+ priv->speed = SPEED_10M;
+
+ if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
+ priv->duplex = FULL_DUPLEX;
+ else
+ priv->duplex = HALF_DUPLEX;
+ }
+#else
+ if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0)
+ return -1;
+
+ if (ctrl & PHY_BMCR_DPLX)
+ priv->duplex = FULL_DUPLEX;
+ else
+ priv->duplex = HALF_DUPLEX;
+
+ if (ctrl & PHY_BMCR_1000_MBPS)
+ priv->speed = SPEED_1000M;
+ else if (ctrl & PHY_BMCR_100_MBPS)
+ priv->speed = SPEED_100M;
+ else
+ priv->speed = SPEED_10M;
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_MII)
+static int dw_mii_read(char *devname, u8 addr, u8 reg, u16 *val)
+{
+ struct eth_device *dev;
+
+ dev = eth_get_dev_by_name(devname);
+ if (dev)
+ eth_mdio_read(dev, addr, reg, val);
+
+ return 0;
+}
+
+static int dw_mii_write(char *devname, u8 addr, u8 reg, u16 val)
+{
+ struct eth_device *dev;
+
+ dev = eth_get_dev_by_name(devname);
+ if (dev)
+ eth_mdio_write(dev, addr, reg, val);
+
+ return 0;
+}
+#endif
+
+int designware_initialize(u32 id, ulong base_addr, u32 phy_addr)
+{
+ struct eth_device *dev;
+ struct dw_eth_dev *priv;
+
+ dev = (struct eth_device *) malloc(sizeof(struct eth_device));
+ if (!dev)
+ return -ENOMEM;
+
+ /*
+ * Since the priv structure contains the descriptors which need a strict
+ * buswidth alignment, memalign is used to allocate memory
+ */
+ priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
+ if (!priv) {
+ free(dev);
+ return -ENOMEM;
+ }
+
+ memset(dev, 0, sizeof(struct eth_device));
+ memset(priv, 0, sizeof(struct dw_eth_dev));
+
+ sprintf(dev->name, "mii%d", id);
+ dev->iobase = (int)base_addr;
+ dev->priv = priv;
+
+ eth_getenv_enetaddr_by_index(id, &dev->enetaddr[0]);
+
+ priv->dev = dev;
+ priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
+ priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
+ DW_DMA_BASE_OFFSET);
+ priv->address = phy_addr;
+
+ if (mac_reset(dev) < 0)
+ return -1;
+
+ if (configure_phy(dev) < 0) {
+ printf("Phy could not be configured\n");
+ return -1;
+ }
+
+ dev->init = dw_eth_init;
+ dev->send = dw_eth_send;
+ dev->recv = dw_eth_recv;
+ dev->halt = dw_eth_halt;
+ dev->write_hwaddr = dw_write_hwaddr;
+
+ eth_register(dev);
+
+#if defined(CONFIG_MII)
+ miiphy_register(dev->name, dw_mii_read, dw_mii_write);
+#endif
+ return 1;
+}
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
new file mode 100644
index 0000000..e5828a6
--- /dev/null
+++ b/drivers/net/designware.h
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DW_ETH_H
+#define _DW_ETH_H
+
+#define CONFIG_TX_DESCR_NUM 16
+#define CONFIG_RX_DESCR_NUM 16
+#define CONFIG_ETH_BUFSIZE 2048
+#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+
+#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
+#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
+#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
+#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ)
+
+struct eth_mac_regs {
+ u32 conf; /* 0x00 */
+ u32 framefilt; /* 0x04 */
+ u32 hashtablehigh; /* 0x08 */
+ u32 hashtablelow; /* 0x0c */
+ u32 miiaddr; /* 0x10 */
+ u32 miidata; /* 0x14 */
+ u32 flowcontrol; /* 0x18 */
+ u32 vlantag; /* 0x1c */
+ u32 version; /* 0x20 */
+ u8 reserved_1[20];
+ u32 intreg; /* 0x38 */
+ u32 intmask; /* 0x3c */
+ u32 macaddr0hi; /* 0x40 */
+ u32 macaddr0lo; /* 0x44 */
+};
+
+/* MAC configuration register definitions */
+#define FRAMEBURSTENABLE (1 << 21)
+#define MII_PORTSELECT (1 << 15)
+#define FES_100 (1 << 14)
+#define DISABLERXOWN (1 << 13)
+#define FULLDPLXMODE (1 << 11)
+#define RXENABLE (1 << 2)
+#define TXENABLE (1 << 3)
+
+/* MII address register definitions */
+#define MII_BUSY (1 << 0)
+#define MII_WRITE (1 << 1)
+#define MII_CLKRANGE_60_100M (0)
+#define MII_CLKRANGE_100_150M (0x4)
+#define MII_CLKRANGE_20_35M (0x8)
+#define MII_CLKRANGE_35_60M (0xC)
+#define MII_CLKRANGE_150_250M (0x10)
+#define MII_CLKRANGE_250_300M (0x14)
+
+#define MIIADDRSHIFT (11)
+#define MIIREGSHIFT (6)
+#define MII_REGMSK (0x1F << 6)
+#define MII_ADDRMSK (0x1F << 11)
+
+
+struct eth_dma_regs {
+ u32 busmode; /* 0x00 */
+ u32 txpolldemand; /* 0x04 */
+ u32 rxpolldemand; /* 0x08 */
+ u32 rxdesclistaddr; /* 0x0c */
+ u32 txdesclistaddr; /* 0x10 */
+ u32 status; /* 0x14 */
+ u32 opmode; /* 0x18 */
+ u32 intenable; /* 0x1c */
+ u8 reserved[40];
+ u32 currhosttxdesc; /* 0x48 */
+ u32 currhostrxdesc; /* 0x4c */
+ u32 currhosttxbuffaddr; /* 0x50 */
+ u32 currhostrxbuffaddr; /* 0x54 */
+};
+
+#define DW_DMA_BASE_OFFSET (0x1000)
+
+/* Bus mode register definitions */
+#define FIXEDBURST (1 << 16)
+#define PRIORXTX_41 (3 << 14)
+#define PRIORXTX_31 (2 << 14)
+#define PRIORXTX_21 (1 << 14)
+#define PRIORXTX_11 (0 << 14)
+#define BURST_1 (1 << 8)
+#define BURST_2 (2 << 8)
+#define BURST_4 (4 << 8)
+#define BURST_8 (8 << 8)
+#define BURST_16 (16 << 8)
+#define BURST_32 (32 << 8)
+#define RXHIGHPRIO (1 << 1)
+#define DMAMAC_SRST (1 << 0)
+
+/* Poll demand definitions */
+#define POLL_DATA (0xFFFFFFFF)
+
+/* Operation mode definitions */
+#define STOREFORWARD (1 << 21)
+#define FLUSHTXFIFO (1 << 20)
+#define TXSTART (1 << 13)
+#define TXSECONDFRAME (1 << 2)
+#define RXSTART (1 << 1)
+
+/* Descriptior related definitions */
+#define MAC_MAX_FRAME_SZ (2048)
+
+struct dmamacdescr {
+ u32 txrx_status;
+ u32 dmamac_cntl;
+ void *dmamac_addr;
+ struct dmamacdescr *dmamac_next;
+};
+
+/*
+ * txrx_status definitions
+ */
+
+/* tx status bits definitions */
+#if defined(CONFIG_DW_ALTDESCRIPTOR)
+
+#define DESC_TXSTS_OWNBYDMA (1 << 31)
+#define DESC_TXSTS_TXINT (1 << 30)
+#define DESC_TXSTS_TXLAST (1 << 29)
+#define DESC_TXSTS_TXFIRST (1 << 28)
+#define DESC_TXSTS_TXCRCDIS (1 << 27)
+
+#define DESC_TXSTS_TXPADDIS (1 << 26)
+#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
+#define DESC_TXSTS_TXRINGEND (1 << 21)
+#define DESC_TXSTS_TXCHAIN (1 << 20)
+#define DESC_TXSTS_MSK (0x1FFFF << 0)
+
+#else
+
+#define DESC_TXSTS_OWNBYDMA (1 << 31)
+#define DESC_TXSTS_MSK (0x1FFFF << 0)
+
+#endif
+
+/* rx status bits definitions */
+#define DESC_RXSTS_OWNBYDMA (1 << 31)
+#define DESC_RXSTS_DAFILTERFAIL (1 << 30)
+#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
+#define DESC_RXSTS_FRMLENSHFT (16)
+
+#define DESC_RXSTS_ERROR (1 << 15)
+#define DESC_RXSTS_RXTRUNCATED (1 << 14)
+#define DESC_RXSTS_SAFILTERFAIL (1 << 13)
+#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
+#define DESC_RXSTS_RXDAMAGED (1 << 11)
+#define DESC_RXSTS_RXVLANTAG (1 << 10)
+#define DESC_RXSTS_RXFIRST (1 << 9)
+#define DESC_RXSTS_RXLAST (1 << 8)
+#define DESC_RXSTS_RXIPC_GIANT (1 << 7)
+#define DESC_RXSTS_RXCOLLISION (1 << 6)
+#define DESC_RXSTS_RXFRAMEETHER (1 << 5)
+#define DESC_RXSTS_RXWATCHDOG (1 << 4)
+#define DESC_RXSTS_RXMIIERROR (1 << 3)
+#define DESC_RXSTS_RXDRIBBLING (1 << 2)
+#define DESC_RXSTS_RXCRC (1 << 1)
+
+/*
+ * dmamac_cntl definitions
+ */
+
+/* tx control bits definitions */
+#if defined(CONFIG_DW_ALTDESCRIPTOR)
+
+#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
+#define DESC_TXCTRL_SIZE1SHFT (0)
+#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
+#define DESC_TXCTRL_SIZE2SHFT (16)
+
+#else
+
+#define DESC_TXCTRL_TXINT (1 << 31)
+#define DESC_TXCTRL_TXLAST (1 << 30)
+#define DESC_TXCTRL_TXFIRST (1 << 29)
+#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
+#define DESC_TXCTRL_TXCRCDIS (1 << 26)
+#define DESC_TXCTRL_TXRINGEND (1 << 25)
+#define DESC_TXCTRL_TXCHAIN (1 << 24)
+
+#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
+#define DESC_TXCTRL_SIZE1SHFT (0)
+#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
+#define DESC_TXCTRL_SIZE2SHFT (11)
+
+#endif
+
+/* rx control bits definitions */
+#if defined(CONFIG_DW_ALTDESCRIPTOR)
+
+#define DESC_RXCTRL_RXINTDIS (1 << 31)
+#define DESC_RXCTRL_RXRINGEND (1 << 15)
+#define DESC_RXCTRL_RXCHAIN (1 << 14)
+
+#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
+#define DESC_RXCTRL_SIZE1SHFT (0)
+#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
+#define DESC_RXCTRL_SIZE2SHFT (16)
+
+#else
+
+#define DESC_RXCTRL_RXINTDIS (1 << 31)
+#define DESC_RXCTRL_RXRINGEND (1 << 25)
+#define DESC_RXCTRL_RXCHAIN (1 << 24)
+
+#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
+#define DESC_RXCTRL_SIZE1SHFT (0)
+#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
+#define DESC_RXCTRL_SIZE2SHFT (11)
+
+#endif
+
+struct dw_eth_dev {
+ u32 address;
+ u32 speed;
+ u32 duplex;
+ u32 tx_currdescnum;
+ u32 rx_currdescnum;
+ u32 padding;
+
+ struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
+ struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+
+ char txbuffs[TX_TOTAL_BUFSIZE];
+ char rxbuffs[RX_TOTAL_BUFSIZE];
+
+ struct eth_mac_regs *mac_regs_p;
+ struct eth_dma_regs *dma_regs_p;
+
+ struct eth_device *dev;
+} __attribute__ ((aligned(8)));
+
+/* Speed specific definitions */
+#define SPEED_10M 1
+#define SPEED_100M 2
+#define SPEED_1000M 3
+
+/* Duplex mode specific definitions */
+#define HALF_DUPLEX 1
+#define FULL_DUPLEX 2
+
+#endif
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index 137e41f..709f67a 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -117,12 +117,12 @@
/* DM9000 network board routine ---------------------------- */
-#define DM9000_outb(d,r) writeb(d, r)
-#define DM9000_outw(d,r) writew(d, r)
-#define DM9000_outl(d,r) writel(d, r)
-#define DM9000_inb(r) readb(r)
-#define DM9000_inw(r) readw(r)
-#define DM9000_inl(r) readl(r)
+#define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r))
+#define DM9000_outw(d,r) writew(d, (volatile u16 *)(r))
+#define DM9000_outl(d,r) writel(d, (volatile u32 *)(r))
+#define DM9000_inb(r) readb((volatile u8 *)(r))
+#define DM9000_inw(r) readw((volatile u16 *)(r))
+#define DM9000_inl(r) readl((volatile u32 *)(r))
#ifdef CONFIG_DM9000_DEBUG
static void
diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c
deleted file mode 100644
index 932792e..0000000
--- a/drivers/net/kirkwood_egiga.c
+++ /dev/null
@@ -1,719 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <asm/errno.h>
-#include <asm/types.h>
-#include <asm/byteorder.h>
-#include <asm/arch/kirkwood.h>
-#include "kirkwood_egiga.h"
-
-#define KIRKWOOD_PHY_ADR_REQUEST 0xee
-#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
-
-/*
- * smi_reg_read - miiphy_read callback function.
- *
- * Returns 16bit phy register value, or 0xffff on error
- */
-static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
-{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
- u32 smi_reg;
- u32 timeout;
-
- /* Phyadr read request */
- if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
- reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
- /* */
- *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
- return 0;
- }
- /* check parameters */
- if (phy_adr > PHYADR_MASK) {
- printf("Err..(%s) Invalid PHY address %d\n",
- __FUNCTION__, phy_adr);
- return -EFAULT;
- }
- if (reg_ofs > PHYREG_MASK) {
- printf("Err..(%s) Invalid register offset %d\n",
- __FUNCTION__, reg_ofs);
- return -EFAULT;
- }
-
- timeout = KWGBE_PHY_SMI_TIMEOUT;
- /* wait till the SMI is not busy */
- do {
- /* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
- if (timeout-- == 0) {
- printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
- return -EFAULT;
- }
- } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
-
- /* fill the phy address and regiser offset and read opcode */
- smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
- | KWGBE_PHY_SMI_OPCODE_READ;
-
- /* write the smi register */
- KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
-
- /*wait till read value is ready */
- timeout = KWGBE_PHY_SMI_TIMEOUT;
-
- do {
- /* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
- if (timeout-- == 0) {
- printf("Err..(%s) SMI read ready timeout\n",
- __FUNCTION__);
- return -EFAULT;
- }
- } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
-
- /* Wait for the data to update in the SMI register */
- for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
-
- *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
-
- debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
- reg_ofs, *data);
-
- return 0;
-}
-
-/*
- * smi_reg_write - imiiphy_write callback function.
- *
- * Returns 0 if write succeed, -EINVAL on bad parameters
- * -ETIME on timeout
- */
-static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
-{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
- u32 smi_reg;
- u32 timeout;
-
- /* Phyadr write request*/
- if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
- reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
- KWGBEREG_WR(regs->phyadr, data);
- return 0;
- }
-
- /* check parameters */
- if (phy_adr > PHYADR_MASK) {
- printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
- return -EINVAL;
- }
- if (reg_ofs > PHYREG_MASK) {
- printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
- return -EINVAL;
- }
-
- /* wait till the SMI is not busy */
- timeout = KWGBE_PHY_SMI_TIMEOUT;
- do {
- /* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
- if (timeout-- == 0) {
- printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
- return -ETIME;
- }
- } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
-
- /* fill the phy addr and reg offset and write opcode and data */
- smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
- smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
- smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
-
- /* write the smi register */
- KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
-
- return 0;
-}
-
-/* Stop and checks all queues */
-static void stop_queue(u32 * qreg)
-{
- u32 reg_data;
-
- reg_data = readl(qreg);
-
- if (reg_data & 0xFF) {
- /* Issue stop command for active channels only */
- writel((reg_data << 8), qreg);
-
- /* Wait for all queue activity to terminate. */
- do {
- /*
- * Check port cause register that all queues
- * are stopped
- */
- reg_data = readl(qreg);
- }
- while (reg_data & 0xFF);
- }
-}
-
-/*
- * set_access_control - Config address decode parameters for Ethernet unit
- *
- * This function configures the address decode parameters for the Gigabit
- * Ethernet Controller according the given parameters struct.
- *
- * @regs Register struct pointer.
- * @param Address decode parameter struct.
- */
-static void set_access_control(struct kwgbe_registers *regs,
- struct kwgbe_winparam *param)
-{
- u32 access_prot_reg;
-
- /* Set access control register */
- access_prot_reg = KWGBEREG_RD(regs->epap);
- /* clear window permission */
- access_prot_reg &= (~(3 << (param->win * 2)));
- access_prot_reg |= (param->access_ctrl << (param->win * 2));
- KWGBEREG_WR(regs->epap, access_prot_reg);
-
- /* Set window Size reg (SR) */
- KWGBEREG_WR(regs->barsz[param->win].size,
- (((param->size / 0x10000) - 1) << 16));
-
- /* Set window Base address reg (BA) */
- KWGBEREG_WR(regs->barsz[param->win].bar,
- (param->target | param->attrib | param->base_addr));
- /* High address remap reg (HARR) */
- if (param->win < 4)
- KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
-
- /* Base address enable reg (BARER) */
- if (param->enable == 1)
- KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
- else
- KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
-}
-
-static void set_dram_access(struct kwgbe_registers *regs)
-{
- struct kwgbe_winparam win_param;
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- /* Set access parameters for DRAM bank i */
- win_param.win = i; /* Use Ethernet window i */
- /* Window target - DDR */
- win_param.target = KWGBE_TARGET_DRAM;
- /* Enable full access */
- win_param.access_ctrl = EWIN_ACCESS_FULL;
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = kw_sdram_bar(i);
- win_param.size = kw_sdram_bs(i); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
-
- /* Enable DRAM bank */
- switch (i) {
- case 0:
- win_param.attrib = EBAR_DRAM_CS0;
- break;
- case 1:
- win_param.attrib = EBAR_DRAM_CS1;
- break;
- case 2:
- win_param.attrib = EBAR_DRAM_CS2;
- break;
- case 3:
- win_param.attrib = EBAR_DRAM_CS3;
- break;
- default:
- /* invalide bank, disable access */
- win_param.enable = 0;
- win_param.attrib = 0;
- break;
- }
- /* Set the access control for address window(EPAPR) RD/WR */
- set_access_control(regs, &win_param);
- }
-}
-
-/*
- * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
- *
- * Go through all the DA filter tables (Unicast, Special Multicast & Other
- * Multicast) and set each entry to 0.
- */
-static void port_init_mac_tables(struct kwgbe_registers *regs)
-{
- int table_index;
-
- /* Clear DA filter unicast table (Ex_dFUT) */
- for (table_index = 0; table_index < 4; ++table_index)
- KWGBEREG_WR(regs->dfut[table_index], 0);
-
- for (table_index = 0; table_index < 64; ++table_index) {
- /* Clear DA filter special multicast table (Ex_dFSMT) */
- KWGBEREG_WR(regs->dfsmt[table_index], 0);
- /* Clear DA filter other multicast table (Ex_dFOMT) */
- KWGBEREG_WR(regs->dfomt[table_index], 0);
- }
-}
-
-/*
- * port_uc_addr - This function Set the port unicast address table
- *
- * This function locates the proper entry in the Unicast table for the
- * specified MAC nibble and sets its properties according to function
- * parameters.
- * This function add/removes MAC addresses from the port unicast address
- * table.
- *
- * @uc_nibble Unicast MAC Address last nibble.
- * @option 0 = Add, 1 = remove address.
- *
- * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
- */
-static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
- int option)
-{
- u32 unicast_reg;
- u32 tbl_offset;
- u32 reg_offset;
-
- /* Locate the Unicast table entry */
- uc_nibble = (0xf & uc_nibble);
- /* Register offset from unicast table base */
- tbl_offset = (uc_nibble / 4);
- /* Entry offset within the above register */
- reg_offset = uc_nibble % 4;
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /*
- * Clear accepts frame bit at specified unicast
- * DA table entry
- */
- unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
- unicast_reg &= (0xFF << (8 * reg_offset));
- KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
- break;
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at unicast DA filter table entry */
- unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
- unicast_reg &= (0xFF << (8 * reg_offset));
- unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
- KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
- break;
- default:
- return 0;
- }
- return 1;
-}
-
-/*
- * port_uc_addr_set - This function Set the port Unicast address.
- */
-static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
-{
- u32 mac_h;
- u32 mac_l;
-
- mac_l = (p_addr[4] << 8) | (p_addr[5]);
- mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
- (p_addr[3] << 0);
-
- KWGBEREG_WR(regs->macal, mac_l);
- KWGBEREG_WR(regs->macah, mac_h);
-
- /* Accept frames of this address */
- port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
-}
-
-/*
- * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
- */
-static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
-{
- struct kwgbe_rxdesc *p_rx_desc;
- int i;
-
- /* initialize the Rx descriptors ring */
- p_rx_desc = dkwgbe->p_rxdesc;
- for (i = 0; i < RINGSZ; i++) {
- p_rx_desc->cmd_sts =
- KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
- p_rx_desc->buf_size = PKTSIZE_ALIGN;
- p_rx_desc->byte_cnt = 0;
- p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
- if (i == (RINGSZ - 1))
- p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
- else {
- p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
- ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
- p_rx_desc = p_rx_desc->nxtdesc_p;
- }
- }
- dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
-}
-
-static int kwgbe_init(struct eth_device *dev)
-{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
- && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
- int i;
-#endif
- /* setup RX rings */
- kwgbe_init_rx_desc_ring(dkwgbe);
-
- /* Clear the ethernet port interrupts */
- KWGBEREG_WR(regs->ic, 0);
- KWGBEREG_WR(regs->ice, 0);
- /* Unmask RX buffer and TX end interrupt */
- KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
- /* Unmask phy and link status changes interrupts */
- KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
-
- set_dram_access(regs);
- port_init_mac_tables(regs);
- port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
-
- /* Assign port configuration and command. */
- KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
- KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
- KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
-
- /* Assign port SDMA configuration */
- KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
- KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
- KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
- /* Turn off the port/RXUQ bandwidth limitation */
- KWGBEREG_WR(regs->pmtu, 0);
-
- /* Set maximum receive buffer to 9700 bytes */
- KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
- | (KWGBEREG_RD(regs->psc0) & MRU_MASK));
-
- /* Enable port initially */
- KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
-
- /*
- * Set ethernet MTU for leaky bucket mechanism to 0 - this will
- * disable the leaky bucket mechanism .
- */
- KWGBEREG_WR(regs->pmtu, 0);
-
- /* Assignment of Rx CRDB of given RXUQ */
- KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
- /* Enable port Rx. */
- KWGBEREG_WR(regs->rqc, (1 << RXUQ));
-
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
- && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
- /* Wait up to 5s for the link status */
- for (i = 0; i < 5; i++) {
- u16 phyadr;
-
- miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
- KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
- /* Return if we get link up */
- if (miiphy_link(dev->name, phyadr))
- return 0;
- udelay(1000000);
- }
-
- printf("No link on %s\n", dev->name);
- return -1;
-#endif
- return 0;
-}
-
-static int kwgbe_halt(struct eth_device *dev)
-{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
-
- /* Disable all gigE address decoder */
- KWGBEREG_WR(regs->bare, 0x3f);
-
- stop_queue(®s->tqc);
- stop_queue(®s->rqc);
-
- /* Disable port */
- KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
- /* Set port is not reset */
- KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
-#ifdef CONFIG_SYS_MII_MODE
- /* Set MMI interface up */
- KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
-#endif
- /* Disable & mask ethernet port interrupts */
- KWGBEREG_WR(regs->ic, 0);
- KWGBEREG_WR(regs->ice, 0);
- KWGBEREG_WR(regs->pim, 0);
- KWGBEREG_WR(regs->peim, 0);
-
- return 0;
-}
-
-static int kwgbe_write_hwaddr(struct eth_device *dev)
-{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
-
- /* Programs net device MAC address after initialization */
- port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
- return 0;
-}
-
-static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
- int datasize)
-{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
- struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
- void *p = (void *)dataptr;
- u32 cmd_sts;
-
- /* Copy buffer if it's misaligned */
- if ((u32) dataptr & 0x07) {
- if (datasize > PKTSIZE_ALIGN) {
- printf("Non-aligned data too large (%d)\n",
- datasize);
- return -1;
- }
-
- memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
- p = dkwgbe->p_aligned_txbuf;
- }
-
- p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
- p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
- p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
- p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
- p_txdesc->buf_ptr = (u8 *) p;
- p_txdesc->byte_cnt = datasize;
-
- /* Apply send command using zeroth TXUQ */
- KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
- KWGBEREG_WR(regs->tqc, (1 << TXUQ));
-
- /*
- * wait for packet xmit completion
- */
- cmd_sts = readl(&p_txdesc->cmd_sts);
- while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
- /* return fail if error is detected */
- if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
- (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
- cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
- printf("Err..(%s) in xmit packet\n", __FUNCTION__);
- return -1;
- }
- cmd_sts = readl(&p_txdesc->cmd_sts);
- };
- return 0;
-}
-
-static int kwgbe_recv(struct eth_device *dev)
-{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
- u32 cmd_sts;
- u32 timeout = 0;
-
- /* wait untill rx packet available or timeout */
- do {
- if (timeout < KWGBE_PHY_SMI_TIMEOUT)
- timeout++;
- else {
- debug("%s time out...\n", __FUNCTION__);
- return -1;
- }
- } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
-
- if (p_rxdesc_curr->byte_cnt != 0) {
- debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
- __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
- (u32) p_rxdesc_curr->buf_ptr,
- (u32) p_rxdesc_curr->cmd_sts);
- }
-
- /*
- * In case received a packet without first/last bits on
- * OR the error summary bit is on,
- * the packets needs to be dropeed.
- */
- cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
-
- if ((cmd_sts &
- (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
- != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
-
- printf("Err..(%s) Dropping packet spread on"
- " multiple descriptors\n", __FUNCTION__);
-
- } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
-
- printf("Err..(%s) Dropping packet with errors\n",
- __FUNCTION__);
-
- } else {
- /* !!! call higher layer processing */
- debug("%s: Sending Received packet to"
- " upper layer (NetReceive)\n", __FUNCTION__);
-
- /* let the upper layer handle the packet */
- NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
- (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
- }
- /*
- * free these descriptors and point next in the ring
- */
- p_rxdesc_curr->cmd_sts =
- KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
- p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
- p_rxdesc_curr->byte_cnt = 0;
-
- writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
-
- return 0;
-}
-
-int kirkwood_egiga_initialize(bd_t * bis)
-{
- struct kwgbe_device *dkwgbe;
- struct eth_device *dev;
- int devnum;
- char *s;
- u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
-
- for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
- /*skip if port is configured not to use */
- if (used_ports[devnum] == 0)
- continue;
-
- if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
- goto error1;
-
- memset(dkwgbe, 0, sizeof(struct kwgbe_device));
-
- if (!(dkwgbe->p_rxdesc =
- (struct kwgbe_rxdesc *)memalign(PKTALIGN,
- KW_RXQ_DESC_ALIGNED_SIZE
- * RINGSZ + 1)))
- goto error2;
-
- if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
- * PKTSIZE_ALIGN + 1)))
- goto error3;
-
- if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
- goto error4;
-
- if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
- memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
- free(dkwgbe->p_aligned_txbuf);
- error4:
- free(dkwgbe->p_rxbuf);
- error3:
- free(dkwgbe->p_rxdesc);
- error2:
- free(dkwgbe);
- error1:
- printf("Err.. %s Failed to allocate memory\n",
- __FUNCTION__);
- return -1;
- }
-
- dev = &dkwgbe->dev;
-
- /* must be less than NAMESIZE (16) */
- sprintf(dev->name, "egiga%d", devnum);
-
- /* Extract the MAC address from the environment */
- switch (devnum) {
- case 0:
- dkwgbe->regs = (void *)KW_EGIGA0_BASE;
- s = "ethaddr";
- break;
- case 1:
- dkwgbe->regs = (void *)KW_EGIGA1_BASE;
- s = "eth1addr";
- break;
- default: /* this should never happen */
- printf("Err..(%s) Invalid device number %d\n",
- __FUNCTION__, devnum);
- return -1;
- }
-
- while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
- /* Generate Random Private MAC addr if not set */
- dev->enetaddr[0] = 0x02;
- dev->enetaddr[1] = 0x50;
- dev->enetaddr[2] = 0x43;
- dev->enetaddr[3] = get_random_hex();
- dev->enetaddr[4] = get_random_hex();
- dev->enetaddr[5] = get_random_hex();
- eth_setenv_enetaddr(s, dev->enetaddr);
- }
-
- dev->init = (void *)kwgbe_init;
- dev->halt = (void *)kwgbe_halt;
- dev->send = (void *)kwgbe_send;
- dev->recv = (void *)kwgbe_recv;
- dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- miiphy_register(dev->name, smi_reg_read, smi_reg_write);
- /* Set phy address of the port */
- miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
- KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
-#endif
- }
- return 0;
-}
diff --git a/drivers/net/kirkwood_egiga.h b/drivers/net/kirkwood_egiga.h
deleted file mode 100644
index 30c773c..0000000
--- a/drivers/net/kirkwood_egiga.h
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __EGIGA_H__
-#define __EGIGA_H__
-
-#define MAX_KWGBE_DEVS 2 /*controller has two ports */
-
-/* PHY_BASE_ADR is board specific and can be configured */
-#if defined (CONFIG_PHY_BASE_ADR)
-#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
-#else
-#define PHY_BASE_ADR 0x08 /* default phy base addr */
-#endif
-
-/* Constants */
-#define INT_CAUSE_UNMASK_ALL 0x0007ffff
-#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
-#define MRU_MASK 0xfff1ffff
-#define PHYADR_MASK 0x0000001f
-#define PHYREG_MASK 0x0000001f
-#define QTKNBKT_DEF_VAL 0x3fffffff
-#define QMTBS_DEF_VAL 0x000003ff
-#define QTKNRT_DEF_VAL 0x0000fcff
-#define RXUQ 0 /* Used Rx queue */
-#define TXUQ 0 /* Used Rx queue */
-
-#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
-#define KWGBEREG_WR(adr, val) writel(val, &adr)
-#define KWGBEREG_RD(adr) readl(&adr)
-#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
-#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
-
-/* Default port configuration value */
-#define PRT_CFG_VAL ( \
- KWGBE_UCAST_MOD_NRML | \
- KWGBE_DFLT_RXQ(RXUQ) | \
- KWGBE_DFLT_RX_ARPQ(RXUQ) | \
- KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \
- KWGBE_RX_BC_IF_IP | \
- KWGBE_RX_BC_IF_ARP | \
- KWGBE_CPTR_TCP_FRMS_DIS | \
- KWGBE_CPTR_UDP_FRMS_DIS | \
- KWGBE_DFLT_RX_TCPQ(RXUQ) | \
- KWGBE_DFLT_RX_UDPQ(RXUQ) | \
- KWGBE_DFLT_RX_BPDUQ(RXUQ))
-
-/* Default port extend configuration value */
-#define PORT_CFG_EXTEND_VALUE \
- KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
- KWGBE_PARTITION_DIS | \
- KWGBE_TX_CRC_GENERATION_EN
-
-#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
-
-/* Default sdma control value */
-#define PORT_SDMA_CFG_VALUE ( \
- KWGBE_RX_BURST_SIZE_16_64BIT | \
- KWGBE_BLM_RX_NO_SWAP | \
- KWGBE_BLM_TX_NO_SWAP | \
- GT_KWGBE_IPG_INT_RX(RXUQ) | \
- KWGBE_TX_BURST_SIZE_16_64BIT)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE ( \
- KWGBE_FORCE_LINK_PASS | \
- KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \
- KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
- KWGBE_ADV_NO_FLOW_CTRL | \
- KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- KWGBE_FORCE_BP_MODE_NO_JAM | \
- (1 << 9) /* Reserved bit has to be 1 */ | \
- KWGBE_DO_NOT_FORCE_LINK_FAIL | \
- KWGBE_EN_AUTO_NEG_SPEED_GMII | \
- KWGBE_DTE_ADV_0 | \
- KWGBE_MIIPHY_MAC_MODE | \
- KWGBE_AUTO_NEG_NO_CHANGE | \
- KWGBE_MAX_RX_PACKET_1552BYTE | \
- KWGBE_CLR_EXT_LOOPBACK | \
- KWGBE_SET_FULL_DUPLEX_MODE | \
- KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
-#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR 0
-#define REJECT_MAC_ADDR 1
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define KW_RXQ_DESC_ALIGNED_SIZE \
- (((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET 0x2
-
-/* Port serial status reg (PSR) */
-#define KWGBE_INTERFACE_GMII_MII 0
-#define KWGBE_INTERFACE_PCM 1
-#define KWGBE_LINK_IS_DOWN 0
-#define KWGBE_LINK_IS_UP (1 << 1)
-#define KWGBE_PORT_AT_HALF_DUPLEX 0
-#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2)
-#define KWGBE_RX_FLOW_CTRL_DISD 0
-#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
-#define KWGBE_GMII_SPEED_100_10 0
-#define KWGBE_GMII_SPEED_1000 (1 << 4)
-#define KWGBE_MII_SPEED_10 0
-#define KWGBE_MII_SPEED_100 (1 << 5)
-#define KWGBE_NO_TX 0
-#define KWGBE_TX_IN_PROGRESS (1 << 7)
-#define KWGBE_BYPASS_NO_ACTIVE 0
-#define KWGBE_BYPASS_ACTIVE (1 << 8)
-#define KWGBE_PORT_NOT_AT_PARTN_STT 0
-#define KWGBE_PORT_AT_PARTN_STT (1 << 9)
-#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0
-#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10)
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define KWGBE_UCAST_MOD_NRML 0
-#define KWGBE_UNICAST_PROMISCUOUS_MODE 1
-#define KWGBE_DFLT_RXQ(_x) (_x << 1)
-#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4)
-#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0
-#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
-#define KWGBE_RX_BC_IF_IP 0
-#define KWGBE_REJECT_BC_IF_IP (1 << 8)
-#define KWGBE_RX_BC_IF_ARP 0
-#define KWGBE_REJECT_BC_IF_ARP (1 << 9)
-#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
-#define KWGBE_CPTR_TCP_FRMS_DIS 0
-#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14)
-#define KWGBE_CPTR_UDP_FRMS_DIS 0
-#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15)
-#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16)
-#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19)
-#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
-#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define KWGBE_CLASSIFY_EN 1
-#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
-#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
-#define KWGBE_PARTITION_DIS 0
-#define KWGBE_PARTITION_EN (1 << 2)
-#define KWGBE_TX_CRC_GENERATION_EN 0
-#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3)
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define KWGBE_RIFB 1
-#define KWGBE_RX_BURST_SIZE_1_64BIT 0
-#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
-#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
-#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
-#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
-#define KWGBE_BLM_RX_NO_SWAP (1 << 4)
-#define KWGBE_BLM_RX_BYTE_SWAP 0
-#define KWGBE_BLM_TX_NO_SWAP (1 << 5)
-#define KWGBE_BLM_TX_BYTE_SWAP 0
-#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
-#define KWGBE_DESCRIPTORS_NO_SWAP 0
-#define KWGBE_TX_BURST_SIZE_1_64BIT 0
-#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
-#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
-#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
-#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define KWGBE_SERIAL_PORT_DIS 0
-#define KWGBE_SERIAL_PORT_EN 1
-#define KWGBE_FORCE_LINK_PASS (1 << 1)
-#define KWGBE_DO_NOT_FORCE_LINK_PASS 0
-#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0
-#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
-#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
-#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
-#define KWGBE_ADV_NO_FLOW_CTRL 0
-#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
-#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
-#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
-#define KWGBE_FORCE_BP_MODE_NO_JAM 0
-#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
-#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
-#define KWGBE_FORCE_LINK_FAIL 0
-#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
-#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
-#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0
-#define KWGBE_DTE_ADV_0 0
-#define KWGBE_DTE_ADV_1 (1 << 14)
-#define KWGBE_MIIPHY_MAC_MODE 0
-#define KWGBE_MIIPHY_PHY_MODE (1 << 15)
-#define KWGBE_AUTO_NEG_NO_CHANGE 0
-#define KWGBE_RESTART_AUTO_NEG (1 << 16)
-#define KWGBE_MAX_RX_PACKET_1518BYTE 0
-#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
-#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
-#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
-#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
-#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
-#define KWGBE_SET_EXT_LOOPBACK (1 << 20)
-#define KWGBE_CLR_EXT_LOOPBACK 0
-#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21)
-#define KWGBE_SET_HALF_DUPLEX_MODE 0
-#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
-#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-#define KWGBE_SET_GMII_SPEED_TO_10_100 0
-#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
-#define KWGBE_SET_MII_SPEED_TO_10 0
-#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24)
-
-/* SMI register fields */
-#define KWGBE_PHY_SMI_TIMEOUT 10000
-#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */
-#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS)
-#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
-#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
-#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
-#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
-#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
-#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
-
-/* SDMA command status fields macros */
-/* Tx & Rx descriptors status */
-#define KWGBE_ERROR_SUMMARY 1
-/* Tx & Rx descriptors command */
-#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31)
-/* Tx descriptors status */
-#define KWGBE_LC_ERROR 0
-#define KWGBE_UR_ERROR (1 << 1)
-#define KWGBE_RL_ERROR (1 << 2)
-#define KWGBE_LLC_SNAP_FORMAT (1 << 9)
-#define KWGBE_TX_LAST_FRAME (1 << 20)
-
-/* Rx descriptors status */
-#define KWGBE_CRC_ERROR 0
-#define KWGBE_OVERRUN_ERROR (1 << 1)
-#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
-#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
-#define KWGBE_VLAN_TAGGED (1 << 19)
-#define KWGBE_BPDU_FRAME (1 << 20)
-#define KWGBE_TCP_FRAME_OVER_IP_V_4 0
-#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
-#define KWGBE_OTHER_FRAME_TYPE (1 << 22)
-#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23)
-#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24)
-#define KWGBE_FRAME_HEADER_OK (1 << 25)
-#define KWGBE_RX_LAST_DESC (1 << 26)
-#define KWGBE_RX_FIRST_DESC (1 << 27)
-#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
-#define KWGBE_RX_EN_INTERRUPT (1 << 29)
-#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30)
-
-/* Rx descriptors byte count */
-#define KWGBE_FRAME_FRAGMENTED (1 << 2)
-
-/* Tx descriptors command */
-#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
-#define KWGBE_FRAME_SET_TO_VLAN (1 << 15)
-#define KWGBE_TCP_FRAME 0
-#define KWGBE_UDP_FRAME (1 << 16)
-#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
-#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
-#define KWGBE_ZERO_PADDING (1 << 19)
-#define KWGBE_TX_LAST_DESC (1 << 20)
-#define KWGBE_TX_FIRST_DESC (1 << 21)
-#define KWGBE_GEN_CRC (1 << 22)
-#define KWGBE_TX_EN_INTERRUPT (1 << 23)
-#define KWGBE_AUTO_MODE (1 << 30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM 0x00000000
-#define EBAR_TARGET_DEVICE 0x00000001
-#define EBAR_TARGET_CBS 0x00000002
-#define EBAR_TARGET_PCI0 0x00000003
-#define EBAR_TARGET_PCI1 0x00000004
-#define EBAR_TARGET_CUNIT 0x00000005
-#define EBAR_TARGET_AUNIT 0x00000006
-#define EBAR_TARGET_GUNIT 0x00000007
-
-/* Window attrib */
-#define EBAR_DRAM_CS0 0x00000E00
-#define EBAR_DRAM_CS1 0x00000D00
-#define EBAR_DRAM_CS2 0x00000B00
-#define EBAR_DRAM_CS3 0x00000700
-
-/* DRAM Target interface */
-#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
-#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
-#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_DEVICE_DEVCS0 0x00001E00
-#define EBAR_DEVICE_DEVCS1 0x00001D00
-#define EBAR_DEVICE_DEVCS2 0x00001B00
-#define EBAR_DEVICE_DEVCS3 0x00001700
-#define EBAR_DEVICE_BOOTCS3 0x00000F00
-
-/* PCI Target interface */
-#define EBAR_PCI_BYTE_SWAP 0x00000000
-#define EBAR_PCI_NO_SWAP 0x00000100
-#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
-#define EBAR_PCI_WORD_SWAP 0x00000300
-#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
-#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
-#define EBAR_PCI_IO_SPACE 0x00000000
-#define EBAR_PCI_MEMORY_SPACE 0x00000800
-#define EBAR_PCI_REQ64_FORCE 0x00000000
-#define EBAR_PCI_REQ64_SIZE 0x00001000
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY 1
-#define EWIN_ACCESS_FULL ((1 << 1) | 1)
-
-/* structures represents Controller registers */
-struct kwgbe_barsz {
- u32 bar;
- u32 size;
-};
-
-struct kwgbe_rxcdp {
- struct kwgbe_rxdesc *rxcdp;
- u32 rxcdp_pad[3];
-};
-
-struct kwgbe_tqx {
- u32 qxttbc;
- u32 tqxtbc;
- u32 tqxac;
- u32 tqxpad;
-};
-
-struct kwgbe_registers {
- u32 phyadr;
- u32 smi;
- u32 euda;
- u32 eudid;
- u8 pad1[0x080 - 0x00c - 4];
- u32 euic;
- u32 euim;
- u8 pad2[0x094 - 0x084 - 4];
- u32 euea;
- u32 euiae;
- u8 pad3[0x0b0 - 0x098 - 4];
- u32 euc;
- u8 pad3a[0x200 - 0x0b0 - 4];
- struct kwgbe_barsz barsz[6];
- u8 pad4[0x280 - 0x22c - 4];
- u32 ha_remap[4];
- u32 bare;
- u32 epap;
- u8 pad5[0x400 - 0x294 - 4];
- u32 pxc;
- u32 pxcx;
- u32 mii_ser_params;
- u8 pad6[0x410 - 0x408 - 4];
- u32 evlane;
- u32 macal;
- u32 macah;
- u32 sdc;
- u32 dscp[7];
- u32 psc0;
- u32 vpt2p;
- u32 ps0;
- u32 tqc;
- u32 psc1;
- u32 ps1;
- u32 mrvl_header;
- u8 pad7[0x460 - 0x454 - 4];
- u32 ic;
- u32 ice;
- u32 pim;
- u32 peim;
- u8 pad8[0x474 - 0x46c - 4];
- u32 pxtfut;
- u32 pad9;
- u32 pxmfs;
- u32 pad10;
- u32 pxdfc;
- u32 pxofc;
- u8 pad11[0x494 - 0x488 - 4];
- u32 peuiae;
- u8 pad12[0x4bc - 0x494 - 4];
- u32 eth_type_prio;
- u8 pad13[0x4dc - 0x4bc - 4];
- u32 tqfpc;
- u32 pttbrc;
- u32 tqc1;
- u32 pmtu;
- u32 pmtbs;
- u8 pad14[0x60c - 0x4ec - 4];
- struct kwgbe_rxcdp rxcdp[7];
- struct kwgbe_rxdesc *rxcdp7;
- u32 rqc;
- struct kwgbe_txdesc *tcsdp;
- u8 pad15[0x6c0 - 0x684 - 4];
- struct kwgbe_txdesc *tcqdp[8];
- u8 pad16[0x700 - 0x6dc - 4];
- struct kwgbe_tqx tqx[8];
- u32 pttbc;
- u8 pad17[0x7a8 - 0x780 - 4];
- u32 tqxipg0;
- u32 pad18[3];
- u32 tqxipg1;
- u8 pad19[0x7c0 - 0x7b8 - 4];
- u32 hitkninlopkt;
- u32 hitkninasyncpkt;
- u32 lotkninasyncpkt;
- u32 pad20;
- u32 ts;
- u8 pad21[0x3000 - 0x27d0 - 4];
- u32 pad20_1[32]; /* mib counter registes */
- u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
- u32 dfsmt[64];
- u32 dfomt[64];
- u32 dfut[4];
- u8 pad23[0xe20c0 - 0x7360c - 4];
- u32 pmbus_top_arbiter;
-};
-
-/* structures/enums needed by driver */
-enum kwgbe_adrwin {
- KWGBE_WIN0,
- KWGBE_WIN1,
- KWGBE_WIN2,
- KWGBE_WIN3,
- KWGBE_WIN4,
- KWGBE_WIN5
-};
-
-enum kwgbe_target {
- KWGBE_TARGET_DRAM,
- KWGBE_TARGET_DEV,
- KWGBE_TARGET_CBS,
- KWGBE_TARGET_PCI0,
- KWGBE_TARGET_PCI1
-};
-
-struct kwgbe_winparam {
- enum kwgbe_adrwin win; /* Window number */
- enum kwgbe_target target; /* System targets */
- u16 attrib; /* BAR attrib. See above macros */
- u32 base_addr; /* Window base address in u32 form */
- u32 high_addr; /* Window high address in u32 form */
- u32 size; /* Size in MBytes. Must be % 64Kbyte. */
- int enable; /* Enable/disable access to the window. */
- u16 access_ctrl; /*Access ctrl register. see above macros */
-};
-
-struct kwgbe_rxdesc {
- u32 cmd_sts; /* Descriptor command status */
- u16 buf_size; /* Buffer size */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u8 *buf_ptr; /* Descriptor buffer pointer */
- struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
-};
-
-struct kwgbe_txdesc {
- u32 cmd_sts; /* Descriptor command status */
- u16 l4i_chk; /* CPU provided TCP Checksum */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u8 *buf_ptr; /* Descriptor buffer ptr */
- struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
-};
-
-/* port device data struct */
-struct kwgbe_device {
- struct eth_device dev;
- struct kwgbe_registers *regs;
- struct kwgbe_txdesc *p_txdesc;
- struct kwgbe_rxdesc *p_rxdesc;
- struct kwgbe_rxdesc *p_rxdesc_curr;
- u8 *p_rxbuf;
- u8 *p_aligned_txbuf;
-};
-
-#endif /* __EGIGA_H__ */
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index dcb8850..6a58a37 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -439,8 +439,6 @@
{
struct macb_device *macb = to_macb(netdev);
unsigned long paddr;
- u32 hwaddr_bottom;
- u16 hwaddr_top;
int i;
/*
@@ -469,12 +467,6 @@
macb_writel(macb, RBQP, macb->rx_ring_dma);
macb_writel(macb, TBQP, macb->tx_ring_dma);
- /* set hardware address */
- hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr));
- macb_writel(macb, SA1B, hwaddr_bottom);
- hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4)));
- macb_writel(macb, SA1T, hwaddr_top);
-
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
@@ -521,6 +513,20 @@
macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
}
+static int macb_write_hwaddr(struct eth_device *dev)
+{
+ struct macb_device *macb = to_macb(dev);
+ u32 hwaddr_bottom;
+ u16 hwaddr_top;
+
+ /* set hardware address */
+ hwaddr_bottom = cpu_to_le32(*((u32 *)dev->enetaddr));
+ macb_writel(macb, SA1B, hwaddr_bottom);
+ hwaddr_top = cpu_to_le16(*((u16 *)(dev->enetaddr + 4)));
+ macb_writel(macb, SA1T, hwaddr_top);
+ return 0;
+}
+
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
@@ -554,6 +560,7 @@
netdev->halt = macb_halt;
netdev->send = macb_send;
netdev->recv = macb_recv;
+ netdev->write_hwaddr = macb_write_hwaddr;
/*
* Do some basic initialization so that we at least can talk
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
new file mode 100644
index 0000000..cad4023
--- /dev/null
+++ b/drivers/net/mvgbe.c
@@ -0,0 +1,756 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <asm/errno.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+
+#if defined(CONFIG_KIRKWOOD)
+#include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_ORION5X)
+#include <asm/arch/orion5x.h>
+#endif
+
+#include "mvgbe.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MV_PHY_ADR_REQUEST 0xee
+#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
+
+/*
+ * smi_reg_read - miiphy_read callback function.
+ *
+ * Returns 16bit phy register value, or 0xffff on error
+ */
+static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+ struct mvgbe_registers *regs = dmvgbe->regs;
+ u32 smi_reg;
+ u32 timeout;
+
+ /* Phyadr read request */
+ if (phy_adr == MV_PHY_ADR_REQUEST &&
+ reg_ofs == MV_PHY_ADR_REQUEST) {
+ /* */
+ *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
+ return 0;
+ }
+ /* check parameters */
+ if (phy_adr > PHYADR_MASK) {
+ printf("Err..(%s) Invalid PHY address %d\n",
+ __FUNCTION__, phy_adr);
+ return -EFAULT;
+ }
+ if (reg_ofs > PHYREG_MASK) {
+ printf("Err..(%s) Invalid register offset %d\n",
+ __FUNCTION__, reg_ofs);
+ return -EFAULT;
+ }
+
+ timeout = MVGBE_PHY_SMI_TIMEOUT;
+ /* wait till the SMI is not busy */
+ do {
+ /* read smi register */
+ smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
+ if (timeout-- == 0) {
+ printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
+ return -EFAULT;
+ }
+ } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
+
+ /* fill the phy address and regiser offset and read opcode */
+ smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
+ | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
+ | MVGBE_PHY_SMI_OPCODE_READ;
+
+ /* write the smi register */
+ MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
+
+ /*wait till read value is ready */
+ timeout = MVGBE_PHY_SMI_TIMEOUT;
+
+ do {
+ /* read smi register */
+ smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
+ if (timeout-- == 0) {
+ printf("Err..(%s) SMI read ready timeout\n",
+ __FUNCTION__);
+ return -EFAULT;
+ }
+ } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
+
+ /* Wait for the data to update in the SMI register */
+ for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
+ ;
+
+ *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
+
+ debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
+ reg_ofs, *data);
+
+ return 0;
+}
+
+/*
+ * smi_reg_write - imiiphy_write callback function.
+ *
+ * Returns 0 if write succeed, -EINVAL on bad parameters
+ * -ETIME on timeout
+ */
+static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+ struct mvgbe_registers *regs = dmvgbe->regs;
+ u32 smi_reg;
+ u32 timeout;
+
+ /* Phyadr write request*/
+ if (phy_adr == MV_PHY_ADR_REQUEST &&
+ reg_ofs == MV_PHY_ADR_REQUEST) {
+ MVGBE_REG_WR(regs->phyadr, data);
+ return 0;
+ }
+
+ /* check parameters */
+ if (phy_adr > PHYADR_MASK) {
+ printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
+ return -EINVAL;
+ }
+ if (reg_ofs > PHYREG_MASK) {
+ printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ /* wait till the SMI is not busy */
+ timeout = MVGBE_PHY_SMI_TIMEOUT;
+ do {
+ /* read smi register */
+ smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
+ if (timeout-- == 0) {
+ printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
+ return -ETIME;
+ }
+ } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
+
+ /* fill the phy addr and reg offset and write opcode and data */
+ smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
+ smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
+ | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
+ smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
+
+ /* write the smi register */
+ MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
+
+ return 0;
+}
+
+/* Stop and checks all queues */
+static void stop_queue(u32 * qreg)
+{
+ u32 reg_data;
+
+ reg_data = readl(qreg);
+
+ if (reg_data & 0xFF) {
+ /* Issue stop command for active channels only */
+ writel((reg_data << 8), qreg);
+
+ /* Wait for all queue activity to terminate. */
+ do {
+ /*
+ * Check port cause register that all queues
+ * are stopped
+ */
+ reg_data = readl(qreg);
+ }
+ while (reg_data & 0xFF);
+ }
+}
+
+/*
+ * set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * This function configures the address decode parameters for the Gigabit
+ * Ethernet Controller according the given parameters struct.
+ *
+ * @regs Register struct pointer.
+ * @param Address decode parameter struct.
+ */
+static void set_access_control(struct mvgbe_registers *regs,
+ struct mvgbe_winparam *param)
+{
+ u32 access_prot_reg;
+
+ /* Set access control register */
+ access_prot_reg = MVGBE_REG_RD(regs->epap);
+ /* clear window permission */
+ access_prot_reg &= (~(3 << (param->win * 2)));
+ access_prot_reg |= (param->access_ctrl << (param->win * 2));
+ MVGBE_REG_WR(regs->epap, access_prot_reg);
+
+ /* Set window Size reg (SR) */
+ MVGBE_REG_WR(regs->barsz[param->win].size,
+ (((param->size / 0x10000) - 1) << 16));
+
+ /* Set window Base address reg (BA) */
+ MVGBE_REG_WR(regs->barsz[param->win].bar,
+ (param->target | param->attrib | param->base_addr));
+ /* High address remap reg (HARR) */
+ if (param->win < 4)
+ MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
+
+ /* Base address enable reg (BARER) */
+ if (param->enable == 1)
+ MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
+ else
+ MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
+}
+
+static void set_dram_access(struct mvgbe_registers *regs)
+{
+ struct mvgbe_winparam win_param;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /* Set access parameters for DRAM bank i */
+ win_param.win = i; /* Use Ethernet window i */
+ /* Window target - DDR */
+ win_param.target = MVGBE_TARGET_DRAM;
+ /* Enable full access */
+ win_param.access_ctrl = EWIN_ACCESS_FULL;
+ win_param.high_addr = 0;
+ /* Get bank base and size */
+ win_param.base_addr = gd->bd->bi_dram[i].start;
+ win_param.size = gd->bd->bi_dram[i].size;
+ if (win_param.size == 0)
+ win_param.enable = 0;
+ else
+ win_param.enable = 1; /* Enable the access */
+
+ /* Enable DRAM bank */
+ switch (i) {
+ case 0:
+ win_param.attrib = EBAR_DRAM_CS0;
+ break;
+ case 1:
+ win_param.attrib = EBAR_DRAM_CS1;
+ break;
+ case 2:
+ win_param.attrib = EBAR_DRAM_CS2;
+ break;
+ case 3:
+ win_param.attrib = EBAR_DRAM_CS3;
+ break;
+ default:
+ /* invalid bank, disable access */
+ win_param.enable = 0;
+ win_param.attrib = 0;
+ break;
+ }
+ /* Set the access control for address window(EPAPR) RD/WR */
+ set_access_control(regs, &win_param);
+ }
+}
+
+/*
+ * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+ *
+ * Go through all the DA filter tables (Unicast, Special Multicast & Other
+ * Multicast) and set each entry to 0.
+ */
+static void port_init_mac_tables(struct mvgbe_registers *regs)
+{
+ int table_index;
+
+ /* Clear DA filter unicast table (Ex_dFUT) */
+ for (table_index = 0; table_index < 4; ++table_index)
+ MVGBE_REG_WR(regs->dfut[table_index], 0);
+
+ for (table_index = 0; table_index < 64; ++table_index) {
+ /* Clear DA filter special multicast table (Ex_dFSMT) */
+ MVGBE_REG_WR(regs->dfsmt[table_index], 0);
+ /* Clear DA filter other multicast table (Ex_dFOMT) */
+ MVGBE_REG_WR(regs->dfomt[table_index], 0);
+ }
+}
+
+/*
+ * port_uc_addr - This function Set the port unicast address table
+ *
+ * This function locates the proper entry in the Unicast table for the
+ * specified MAC nibble and sets its properties according to function
+ * parameters.
+ * This function add/removes MAC addresses from the port unicast address
+ * table.
+ *
+ * @uc_nibble Unicast MAC Address last nibble.
+ * @option 0 = Add, 1 = remove address.
+ *
+ * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
+ */
+static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
+ int option)
+{
+ u32 unicast_reg;
+ u32 tbl_offset;
+ u32 reg_offset;
+
+ /* Locate the Unicast table entry */
+ uc_nibble = (0xf & uc_nibble);
+ /* Register offset from unicast table base */
+ tbl_offset = (uc_nibble / 4);
+ /* Entry offset within the above register */
+ reg_offset = uc_nibble % 4;
+
+ switch (option) {
+ case REJECT_MAC_ADDR:
+ /*
+ * Clear accepts frame bit at specified unicast
+ * DA table entry
+ */
+ unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
+ unicast_reg &= (0xFF << (8 * reg_offset));
+ MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
+ break;
+ case ACCEPT_MAC_ADDR:
+ /* Set accepts frame bit at unicast DA filter table entry */
+ unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
+ unicast_reg &= (0xFF << (8 * reg_offset));
+ unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
+ MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
+ break;
+ default:
+ return 0;
+ }
+ return 1;
+}
+
+/*
+ * port_uc_addr_set - This function Set the port Unicast address.
+ */
+static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
+{
+ u32 mac_h;
+ u32 mac_l;
+
+ mac_l = (p_addr[4] << 8) | (p_addr[5]);
+ mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
+ (p_addr[3] << 0);
+
+ MVGBE_REG_WR(regs->macal, mac_l);
+ MVGBE_REG_WR(regs->macah, mac_h);
+
+ /* Accept frames of this address */
+ port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
+}
+
+/*
+ * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ */
+static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
+{
+ struct mvgbe_rxdesc *p_rx_desc;
+ int i;
+
+ /* initialize the Rx descriptors ring */
+ p_rx_desc = dmvgbe->p_rxdesc;
+ for (i = 0; i < RINGSZ; i++) {
+ p_rx_desc->cmd_sts =
+ MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
+ p_rx_desc->buf_size = PKTSIZE_ALIGN;
+ p_rx_desc->byte_cnt = 0;
+ p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
+ if (i == (RINGSZ - 1))
+ p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
+ else {
+ p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
+ ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
+ p_rx_desc = p_rx_desc->nxtdesc_p;
+ }
+ }
+ dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
+}
+
+static int mvgbe_init(struct eth_device *dev)
+{
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+ struct mvgbe_registers *regs = dmvgbe->regs;
+#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
+ && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+ int i;
+#endif
+ /* setup RX rings */
+ mvgbe_init_rx_desc_ring(dmvgbe);
+
+ /* Clear the ethernet port interrupts */
+ MVGBE_REG_WR(regs->ic, 0);
+ MVGBE_REG_WR(regs->ice, 0);
+ /* Unmask RX buffer and TX end interrupt */
+ MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
+ /* Unmask phy and link status changes interrupts */
+ MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
+
+ set_dram_access(regs);
+ port_init_mac_tables(regs);
+ port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
+
+ /* Assign port configuration and command. */
+ MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
+ MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
+ MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
+
+ /* Assign port SDMA configuration */
+ MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
+ MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
+ MVGBE_REG_WR(regs->tqx[0].tqxtbc,
+ (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
+ /* Turn off the port/RXUQ bandwidth limitation */
+ MVGBE_REG_WR(regs->pmtu, 0);
+
+ /* Set maximum receive buffer to 9700 bytes */
+ MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
+ | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
+
+ /* Enable port initially */
+ MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
+
+ /*
+ * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+ * disable the leaky bucket mechanism .
+ */
+ MVGBE_REG_WR(regs->pmtu, 0);
+
+ /* Assignment of Rx CRDB of given RXUQ */
+ MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
+ /* ensure previous write is done before enabling Rx DMA */
+ isb();
+ /* Enable port Rx. */
+ MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
+
+#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
+ && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+ /* Wait up to 5s for the link status */
+ for (i = 0; i < 5; i++) {
+ u16 phyadr;
+
+ miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
+ MV_PHY_ADR_REQUEST, &phyadr);
+ /* Return if we get link up */
+ if (miiphy_link(dev->name, phyadr))
+ return 0;
+ udelay(1000000);
+ }
+
+ printf("No link on %s\n", dev->name);
+ return -1;
+#endif
+ return 0;
+}
+
+static int mvgbe_halt(struct eth_device *dev)
+{
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+ struct mvgbe_registers *regs = dmvgbe->regs;
+
+ /* Disable all gigE address decoder */
+ MVGBE_REG_WR(regs->bare, 0x3f);
+
+ stop_queue(®s->tqc);
+ stop_queue(®s->rqc);
+
+ /* Disable port */
+ MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
+ /* Set port is not reset */
+ MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
+#ifdef CONFIG_SYS_MII_MODE
+ /* Set MMI interface up */
+ MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
+#endif
+ /* Disable & mask ethernet port interrupts */
+ MVGBE_REG_WR(regs->ic, 0);
+ MVGBE_REG_WR(regs->ice, 0);
+ MVGBE_REG_WR(regs->pim, 0);
+ MVGBE_REG_WR(regs->peim, 0);
+
+ return 0;
+}
+
+static int mvgbe_write_hwaddr(struct eth_device *dev)
+{
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+ struct mvgbe_registers *regs = dmvgbe->regs;
+
+ /* Programs net device MAC address after initialization */
+ port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
+ return 0;
+}
+
+static int mvgbe_send(struct eth_device *dev, void *dataptr,
+ int datasize)
+{
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+ struct mvgbe_registers *regs = dmvgbe->regs;
+ struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
+ void *p = (void *)dataptr;
+ u32 cmd_sts;
+
+ /* Copy buffer if it's misaligned */
+ if ((u32) dataptr & 0x07) {
+ if (datasize > PKTSIZE_ALIGN) {
+ printf("Non-aligned data too large (%d)\n",
+ datasize);
+ return -1;
+ }
+
+ memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
+ p = dmvgbe->p_aligned_txbuf;
+ }
+
+ p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
+ p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
+ p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
+ p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
+ p_txdesc->buf_ptr = (u8 *) p;
+ p_txdesc->byte_cnt = datasize;
+
+ /* Set this tc desc as zeroth TXUQ */
+ MVGBE_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
+
+ /* ensure tx desc writes above are performed before we start Tx DMA */
+ isb();
+
+ /* Apply send command using zeroth TXUQ */
+ MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
+
+ /*
+ * wait for packet xmit completion
+ */
+ cmd_sts = readl(&p_txdesc->cmd_sts);
+ while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
+ /* return fail if error is detected */
+ if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
+ (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
+ cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
+ printf("Err..(%s) in xmit packet\n", __FUNCTION__);
+ return -1;
+ }
+ cmd_sts = readl(&p_txdesc->cmd_sts);
+ };
+ return 0;
+}
+
+static int mvgbe_recv(struct eth_device *dev)
+{
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+ struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
+ u32 cmd_sts;
+ u32 timeout = 0;
+
+ /* wait untill rx packet available or timeout */
+ do {
+ if (timeout < MVGBE_PHY_SMI_TIMEOUT)
+ timeout++;
+ else {
+ debug("%s time out...\n", __FUNCTION__);
+ return -1;
+ }
+ } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
+
+ if (p_rxdesc_curr->byte_cnt != 0) {
+ debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
+ __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
+ (u32) p_rxdesc_curr->buf_ptr,
+ (u32) p_rxdesc_curr->cmd_sts);
+ }
+
+ /*
+ * In case received a packet without first/last bits on
+ * OR the error summary bit is on,
+ * the packets needs to be dropeed.
+ */
+ cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
+
+ if ((cmd_sts &
+ (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
+ != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
+
+ printf("Err..(%s) Dropping packet spread on"
+ " multiple descriptors\n", __FUNCTION__);
+
+ } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
+
+ printf("Err..(%s) Dropping packet with errors\n",
+ __FUNCTION__);
+
+ } else {
+ /* !!! call higher layer processing */
+ debug("%s: Sending Received packet to"
+ " upper layer (NetReceive)\n", __FUNCTION__);
+
+ /* let the upper layer handle the packet */
+ NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
+ (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
+ }
+ /*
+ * free these descriptors and point next in the ring
+ */
+ p_rxdesc_curr->cmd_sts =
+ MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
+ p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
+ p_rxdesc_curr->byte_cnt = 0;
+
+ writel((unsigned)p_rxdesc_curr->nxtdesc_p,
+ (u32) &dmvgbe->p_rxdesc_curr);
+
+ return 0;
+}
+
+int mvgbe_initialize(bd_t *bis)
+{
+ struct mvgbe_device *dmvgbe;
+ struct eth_device *dev;
+ int devnum;
+ char *s;
+ u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
+
+ for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
+ /*skip if port is configured not to use */
+ if (used_ports[devnum] == 0)
+ continue;
+
+ dmvgbe = malloc(sizeof(struct mvgbe_device));
+
+ if (!dmvgbe)
+ goto error1;
+
+ memset(dmvgbe, 0, sizeof(struct mvgbe_device));
+
+ dmvgbe->p_rxdesc =
+ (struct mvgbe_rxdesc *)memalign(PKTALIGN,
+ MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
+
+ if (!dmvgbe->p_rxdesc)
+ goto error2;
+
+ dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
+ RINGSZ*PKTSIZE_ALIGN + 1);
+
+ if (!dmvgbe->p_rxbuf)
+ goto error3;
+
+ dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
+
+ if (!dmvgbe->p_aligned_txbuf)
+ goto error4;
+
+ dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
+ PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
+
+ if (!dmvgbe->p_txdesc) {
+ free(dmvgbe->p_aligned_txbuf);
+error4:
+ free(dmvgbe->p_rxbuf);
+error3:
+ free(dmvgbe->p_rxdesc);
+error2:
+ free(dmvgbe);
+error1:
+ printf("Err.. %s Failed to allocate memory\n",
+ __FUNCTION__);
+ return -1;
+ }
+
+ dev = &dmvgbe->dev;
+
+ /* must be less than NAMESIZE (16) */
+ sprintf(dev->name, "egiga%d", devnum);
+
+ /* Extract the MAC address from the environment */
+ switch (devnum) {
+ case 0:
+ dmvgbe->regs = (void *)MVGBE0_BASE;
+ s = "ethaddr";
+ break;
+#if defined(MVGBE1_BASE)
+ case 1:
+ dmvgbe->regs = (void *)MVGBE1_BASE;
+ s = "eth1addr";
+ break;
+#endif
+ default: /* this should never happen */
+ printf("Err..(%s) Invalid device number %d\n",
+ __FUNCTION__, devnum);
+ return -1;
+ }
+
+ while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
+ /* Generate Private MAC addr if not set */
+ dev->enetaddr[0] = 0x02;
+ dev->enetaddr[1] = 0x50;
+ dev->enetaddr[2] = 0x43;
+#if defined (CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION)
+ /* Generate fixed lower MAC half using devnum */
+ dev->enetaddr[3] = 0;
+ dev->enetaddr[4] = 0;
+ dev->enetaddr[5] = devnum;
+#else
+ /* Generate random lower MAC half */
+ dev->enetaddr[3] = get_random_hex();
+ dev->enetaddr[4] = get_random_hex();
+ dev->enetaddr[5] = get_random_hex();
+#endif
+ eth_setenv_enetaddr(s, dev->enetaddr);
+ }
+
+ dev->init = (void *)mvgbe_init;
+ dev->halt = (void *)mvgbe_halt;
+ dev->send = (void *)mvgbe_send;
+ dev->recv = (void *)mvgbe_recv;
+ dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
+
+ eth_register(dev);
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+ miiphy_register(dev->name, smi_reg_read, smi_reg_write);
+ /* Set phy address of the port */
+ miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
+ MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
+#endif
+ }
+ return 0;
+}
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
new file mode 100644
index 0000000..3de98d0
--- /dev/null
+++ b/drivers/net/mvgbe.h
@@ -0,0 +1,505 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __MVGBE_H__
+#define __MVGBE_H__
+
+/* PHY_BASE_ADR is board specific and can be configured */
+#if defined (CONFIG_PHY_BASE_ADR)
+#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
+#else
+#define PHY_BASE_ADR 0x08 /* default phy base addr */
+#endif
+
+/* Constants */
+#define INT_CAUSE_UNMASK_ALL 0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
+#define MRU_MASK 0xfff1ffff
+#define PHYADR_MASK 0x0000001f
+#define PHYREG_MASK 0x0000001f
+#define QTKNBKT_DEF_VAL 0x3fffffff
+#define QMTBS_DEF_VAL 0x000003ff
+#define QTKNRT_DEF_VAL 0x0000fcff
+#define RXUQ 0 /* Used Rx queue */
+#define TXUQ 0 /* Used Rx queue */
+
+#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
+#define MVGBE_REG_WR(adr, val) writel(val, &adr)
+#define MVGBE_REG_RD(adr) readl(&adr)
+#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
+#define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
+
+/* Default port configuration value */
+#define PRT_CFG_VAL ( \
+ MVGBE_UCAST_MOD_NRML | \
+ MVGBE_DFLT_RXQ(RXUQ) | \
+ MVGBE_DFLT_RX_ARPQ(RXUQ) | \
+ MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \
+ MVGBE_RX_BC_IF_IP | \
+ MVGBE_RX_BC_IF_ARP | \
+ MVGBE_CPTR_TCP_FRMS_DIS | \
+ MVGBE_CPTR_UDP_FRMS_DIS | \
+ MVGBE_DFLT_RX_TCPQ(RXUQ) | \
+ MVGBE_DFLT_RX_UDPQ(RXUQ) | \
+ MVGBE_DFLT_RX_BPDUQ(RXUQ))
+
+/* Default port extend configuration value */
+#define PORT_CFG_EXTEND_VALUE \
+ MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
+ MVGBE_PARTITION_DIS | \
+ MVGBE_TX_CRC_GENERATION_EN
+
+#define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
+
+/* Default sdma control value */
+#define PORT_SDMA_CFG_VALUE ( \
+ MVGBE_RX_BURST_SIZE_16_64BIT | \
+ MVGBE_BLM_RX_NO_SWAP | \
+ MVGBE_BLM_TX_NO_SWAP | \
+ GT_MVGBE_IPG_INT_RX(RXUQ) | \
+ MVGBE_TX_BURST_SIZE_16_64BIT)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE ( \
+ MVGBE_FORCE_LINK_PASS | \
+ MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
+ MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
+ MVGBE_ADV_NO_FLOW_CTRL | \
+ MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ MVGBE_FORCE_BP_MODE_NO_JAM | \
+ (1 << 9) /* Reserved bit has to be 1 */ | \
+ MVGBE_DO_NOT_FORCE_LINK_FAIL | \
+ MVGBE_EN_AUTO_NEG_SPEED_GMII | \
+ MVGBE_DTE_ADV_0 | \
+ MVGBE_MIIPHY_MAC_MODE | \
+ MVGBE_AUTO_NEG_NO_CHANGE | \
+ MVGBE_MAX_RX_PACKET_1552BYTE | \
+ MVGBE_CLR_EXT_LOOPBACK | \
+ MVGBE_SET_FULL_DUPLEX_MODE | \
+ MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
+#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR 0
+#define REJECT_MAC_ADDR 1
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define MV_RXQ_DESC_ALIGNED_SIZE \
+ (((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET 0x2
+
+/* Port serial status reg (PSR) */
+#define MVGBE_INTERFACE_GMII_MII 0
+#define MVGBE_INTERFACE_PCM 1
+#define MVGBE_LINK_IS_DOWN 0
+#define MVGBE_LINK_IS_UP (1 << 1)
+#define MVGBE_PORT_AT_HALF_DUPLEX 0
+#define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2)
+#define MVGBE_RX_FLOW_CTRL_DISD 0
+#define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
+#define MVGBE_GMII_SPEED_100_10 0
+#define MVGBE_GMII_SPEED_1000 (1 << 4)
+#define MVGBE_MII_SPEED_10 0
+#define MVGBE_MII_SPEED_100 (1 << 5)
+#define MVGBE_NO_TX 0
+#define MVGBE_TX_IN_PROGRESS (1 << 7)
+#define MVGBE_BYPASS_NO_ACTIVE 0
+#define MVGBE_BYPASS_ACTIVE (1 << 8)
+#define MVGBE_PORT_NOT_AT_PARTN_STT 0
+#define MVGBE_PORT_AT_PARTN_STT (1 << 9)
+#define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0
+#define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10)
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define MVGBE_UCAST_MOD_NRML 0
+#define MVGBE_UNICAST_PROMISCUOUS_MODE 1
+#define MVGBE_DFLT_RXQ(_x) (_x << 1)
+#define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4)
+#define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0
+#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
+#define MVGBE_RX_BC_IF_IP 0
+#define MVGBE_REJECT_BC_IF_IP (1 << 8)
+#define MVGBE_RX_BC_IF_ARP 0
+#define MVGBE_REJECT_BC_IF_ARP (1 << 9)
+#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
+#define MVGBE_CPTR_TCP_FRMS_DIS 0
+#define MVGBE_CPTR_TCP_FRMS_EN (1 << 14)
+#define MVGBE_CPTR_UDP_FRMS_DIS 0
+#define MVGBE_CPTR_UDP_FRMS_EN (1 << 15)
+#define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16)
+#define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19)
+#define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
+#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define MVGBE_CLASSIFY_EN 1
+#define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
+#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
+#define MVGBE_PARTITION_DIS 0
+#define MVGBE_PARTITION_EN (1 << 2)
+#define MVGBE_TX_CRC_GENERATION_EN 0
+#define MVGBE_TX_CRC_GENERATION_DIS (1 << 3)
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define MVGBE_RIFB 1
+#define MVGBE_RX_BURST_SIZE_1_64BIT 0
+#define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
+#define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
+#define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
+#define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
+#define MVGBE_BLM_RX_NO_SWAP (1 << 4)
+#define MVGBE_BLM_RX_BYTE_SWAP 0
+#define MVGBE_BLM_TX_NO_SWAP (1 << 5)
+#define MVGBE_BLM_TX_BYTE_SWAP 0
+#define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
+#define MVGBE_DESCRIPTORS_NO_SWAP 0
+#define MVGBE_TX_BURST_SIZE_1_64BIT 0
+#define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
+#define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
+#define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
+#define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define MVGBE_SERIAL_PORT_DIS 0
+#define MVGBE_SERIAL_PORT_EN 1
+#define MVGBE_FORCE_LINK_PASS (1 << 1)
+#define MVGBE_DO_NOT_FORCE_LINK_PASS 0
+#define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0
+#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
+#define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
+#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
+#define MVGBE_ADV_NO_FLOW_CTRL 0
+#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
+#define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
+#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
+#define MVGBE_FORCE_BP_MODE_NO_JAM 0
+#define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
+#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
+#define MVGBE_FORCE_LINK_FAIL 0
+#define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
+#define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
+#define MVGBE_EN_AUTO_NEG_SPEED_GMII 0
+#define MVGBE_DTE_ADV_0 0
+#define MVGBE_DTE_ADV_1 (1 << 14)
+#define MVGBE_MIIPHY_MAC_MODE 0
+#define MVGBE_MIIPHY_PHY_MODE (1 << 15)
+#define MVGBE_AUTO_NEG_NO_CHANGE 0
+#define MVGBE_RESTART_AUTO_NEG (1 << 16)
+#define MVGBE_MAX_RX_PACKET_1518BYTE 0
+#define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
+#define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
+#define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
+#define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
+#define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
+#define MVGBE_SET_EXT_LOOPBACK (1 << 20)
+#define MVGBE_CLR_EXT_LOOPBACK 0
+#define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21)
+#define MVGBE_SET_HALF_DUPLEX_MODE 0
+#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
+#define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
+#define MVGBE_SET_GMII_SPEED_TO_10_100 0
+#define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
+#define MVGBE_SET_MII_SPEED_TO_10 0
+#define MVGBE_SET_MII_SPEED_TO_100 (1 << 24)
+
+/* SMI register fields */
+#define MVGBE_PHY_SMI_TIMEOUT 10000
+#define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */
+#define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS)
+#define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
+#define MVGBE_PHY_SMI_DEV_ADDR_MASK \
+ (PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
+#define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
+#define MVGBE_SMI_REG_ADDR_MASK \
+ (PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS)
+#define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
+#define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS)
+#define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS)
+#define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS)
+#define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
+#define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
+
+/* SDMA command status fields macros */
+/* Tx & Rx descriptors status */
+#define MVGBE_ERROR_SUMMARY 1
+/* Tx & Rx descriptors command */
+#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31)
+/* Tx descriptors status */
+#define MVGBE_LC_ERROR 0
+#define MVGBE_UR_ERROR (1 << 1)
+#define MVGBE_RL_ERROR (1 << 2)
+#define MVGBE_LLC_SNAP_FORMAT (1 << 9)
+#define MVGBE_TX_LAST_FRAME (1 << 20)
+
+/* Rx descriptors status */
+#define MVGBE_CRC_ERROR 0
+#define MVGBE_OVERRUN_ERROR (1 << 1)
+#define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
+#define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
+#define MVGBE_VLAN_TAGGED (1 << 19)
+#define MVGBE_BPDU_FRAME (1 << 20)
+#define MVGBE_TCP_FRAME_OVER_IP_V_4 0
+#define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
+#define MVGBE_OTHER_FRAME_TYPE (1 << 22)
+#define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23)
+#define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24)
+#define MVGBE_FRAME_HEADER_OK (1 << 25)
+#define MVGBE_RX_LAST_DESC (1 << 26)
+#define MVGBE_RX_FIRST_DESC (1 << 27)
+#define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
+#define MVGBE_RX_EN_INTERRUPT (1 << 29)
+#define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30)
+
+/* Rx descriptors byte count */
+#define MVGBE_FRAME_FRAGMENTED (1 << 2)
+
+/* Tx descriptors command */
+#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
+#define MVGBE_FRAME_SET_TO_VLAN (1 << 15)
+#define MVGBE_TCP_FRAME 0
+#define MVGBE_UDP_FRAME (1 << 16)
+#define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
+#define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
+#define MVGBE_ZERO_PADDING (1 << 19)
+#define MVGBE_TX_LAST_DESC (1 << 20)
+#define MVGBE_TX_FIRST_DESC (1 << 21)
+#define MVGBE_GEN_CRC (1 << 22)
+#define MVGBE_TX_EN_INTERRUPT (1 << 23)
+#define MVGBE_AUTO_MODE (1 << 30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM 0x00000000
+#define EBAR_TARGET_DEVICE 0x00000001
+#define EBAR_TARGET_CBS 0x00000002
+#define EBAR_TARGET_PCI0 0x00000003
+#define EBAR_TARGET_PCI1 0x00000004
+#define EBAR_TARGET_CUNIT 0x00000005
+#define EBAR_TARGET_AUNIT 0x00000006
+#define EBAR_TARGET_GUNIT 0x00000007
+
+/* Window attrib */
+#define EBAR_DRAM_CS0 0x00000E00
+#define EBAR_DRAM_CS1 0x00000D00
+#define EBAR_DRAM_CS2 0x00000B00
+#define EBAR_DRAM_CS3 0x00000700
+
+/* DRAM Target interface */
+#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
+#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
+#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_DEVICE_DEVCS0 0x00001E00
+#define EBAR_DEVICE_DEVCS1 0x00001D00
+#define EBAR_DEVICE_DEVCS2 0x00001B00
+#define EBAR_DEVICE_DEVCS3 0x00001700
+#define EBAR_DEVICE_BOOTCS3 0x00000F00
+
+/* PCI Target interface */
+#define EBAR_PCI_BYTE_SWAP 0x00000000
+#define EBAR_PCI_NO_SWAP 0x00000100
+#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
+#define EBAR_PCI_WORD_SWAP 0x00000300
+#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
+#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
+#define EBAR_PCI_IO_SPACE 0x00000000
+#define EBAR_PCI_MEMORY_SPACE 0x00000800
+#define EBAR_PCI_REQ64_FORCE 0x00000000
+#define EBAR_PCI_REQ64_SIZE 0x00001000
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY 1
+#define EWIN_ACCESS_FULL ((1 << 1) | 1)
+
+/* structures represents Controller registers */
+struct mvgbe_barsz {
+ u32 bar;
+ u32 size;
+};
+
+struct mvgbe_rxcdp {
+ struct mvgbe_rxdesc *rxcdp;
+ u32 rxcdp_pad[3];
+};
+
+struct mvgbe_tqx {
+ u32 qxttbc;
+ u32 tqxtbc;
+ u32 tqxac;
+ u32 tqxpad;
+};
+
+struct mvgbe_registers {
+ u32 phyadr;
+ u32 smi;
+ u32 euda;
+ u32 eudid;
+ u8 pad1[0x080 - 0x00c - 4];
+ u32 euic;
+ u32 euim;
+ u8 pad2[0x094 - 0x084 - 4];
+ u32 euea;
+ u32 euiae;
+ u8 pad3[0x0b0 - 0x098 - 4];
+ u32 euc;
+ u8 pad3a[0x200 - 0x0b0 - 4];
+ struct mvgbe_barsz barsz[6];
+ u8 pad4[0x280 - 0x22c - 4];
+ u32 ha_remap[4];
+ u32 bare;
+ u32 epap;
+ u8 pad5[0x400 - 0x294 - 4];
+ u32 pxc;
+ u32 pxcx;
+ u32 mii_ser_params;
+ u8 pad6[0x410 - 0x408 - 4];
+ u32 evlane;
+ u32 macal;
+ u32 macah;
+ u32 sdc;
+ u32 dscp[7];
+ u32 psc0;
+ u32 vpt2p;
+ u32 ps0;
+ u32 tqc;
+ u32 psc1;
+ u32 ps1;
+ u32 mrvl_header;
+ u8 pad7[0x460 - 0x454 - 4];
+ u32 ic;
+ u32 ice;
+ u32 pim;
+ u32 peim;
+ u8 pad8[0x474 - 0x46c - 4];
+ u32 pxtfut;
+ u32 pad9;
+ u32 pxmfs;
+ u32 pad10;
+ u32 pxdfc;
+ u32 pxofc;
+ u8 pad11[0x494 - 0x488 - 4];
+ u32 peuiae;
+ u8 pad12[0x4bc - 0x494 - 4];
+ u32 eth_type_prio;
+ u8 pad13[0x4dc - 0x4bc - 4];
+ u32 tqfpc;
+ u32 pttbrc;
+ u32 tqc1;
+ u32 pmtu;
+ u32 pmtbs;
+ u8 pad14[0x60c - 0x4ec - 4];
+ struct mvgbe_rxcdp rxcdp[7];
+ struct mvgbe_rxdesc *rxcdp7;
+ u32 rqc;
+ struct mvgbe_txdesc *tcsdp;
+ u8 pad15[0x6c0 - 0x684 - 4];
+ struct mvgbe_txdesc *tcqdp[8];
+ u8 pad16[0x700 - 0x6dc - 4];
+ struct mvgbe_tqx tqx[8];
+ u32 pttbc;
+ u8 pad17[0x7a8 - 0x780 - 4];
+ u32 tqxipg0;
+ u32 pad18[3];
+ u32 tqxipg1;
+ u8 pad19[0x7c0 - 0x7b8 - 4];
+ u32 hitkninlopkt;
+ u32 hitkninasyncpkt;
+ u32 lotkninasyncpkt;
+ u32 pad20;
+ u32 ts;
+ u8 pad21[0x3000 - 0x27d0 - 4];
+ u32 pad20_1[32]; /* mib counter registes */
+ u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
+ u32 dfsmt[64];
+ u32 dfomt[64];
+ u32 dfut[4];
+ u8 pad23[0xe20c0 - 0x7360c - 4];
+ u32 pmbus_top_arbiter;
+};
+
+/* structures/enums needed by driver */
+enum mvgbe_adrwin {
+ MVGBE_WIN0,
+ MVGBE_WIN1,
+ MVGBE_WIN2,
+ MVGBE_WIN3,
+ MVGBE_WIN4,
+ MVGBE_WIN5
+};
+
+enum mvgbe_target {
+ MVGBE_TARGET_DRAM,
+ MVGBE_TARGET_DEV,
+ MVGBE_TARGET_CBS,
+ MVGBE_TARGET_PCI0,
+ MVGBE_TARGET_PCI1
+};
+
+struct mvgbe_winparam {
+ enum mvgbe_adrwin win; /* Window number */
+ enum mvgbe_target target; /* System targets */
+ u16 attrib; /* BAR attrib. See above macros */
+ u32 base_addr; /* Window base address in u32 form */
+ u32 high_addr; /* Window high address in u32 form */
+ u32 size; /* Size in MBytes. Must be % 64Kbyte. */
+ int enable; /* Enable/disable access to the window. */
+ u16 access_ctrl; /*Access ctrl register. see above macros */
+};
+
+struct mvgbe_rxdesc {
+ u32 cmd_sts; /* Descriptor command status */
+ u16 buf_size; /* Buffer size */
+ u16 byte_cnt; /* Descriptor buffer byte count */
+ u8 *buf_ptr; /* Descriptor buffer pointer */
+ struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
+};
+
+struct mvgbe_txdesc {
+ u32 cmd_sts; /* Descriptor command status */
+ u16 l4i_chk; /* CPU provided TCP Checksum */
+ u16 byte_cnt; /* Descriptor buffer byte count */
+ u8 *buf_ptr; /* Descriptor buffer ptr */
+ struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
+};
+
+/* port device data struct */
+struct mvgbe_device {
+ struct eth_device dev;
+ struct mvgbe_registers *regs;
+ struct mvgbe_txdesc *p_txdesc;
+ struct mvgbe_rxdesc *p_rxdesc;
+ struct mvgbe_rxdesc *p_rxdesc_curr;
+ u8 *p_rxbuf;
+ u8 *p_aligned_txbuf;
+};
+
+#endif /* __MVGBE_H__ */
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 5fa6f61..54c4a70 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -95,14 +95,23 @@
#endif
};
+/*
+ * Initialize all the TSEC devices
+ *
+ * Returns the number of TSEC devices that were initialized
+ */
int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
{
int i;
+ int ret, count = 0;
- for (i = 0; i < num; i++)
- tsec_initialize(bis, &tsecs[i]);
+ for (i = 0; i < num; i++) {
+ ret = tsec_initialize(bis, &tsecs[i]);
+ if (ret > 0)
+ count += ret;
+ }
- return 0;
+ return count;
}
int tsec_standard_init(bd_t *bis)
@@ -1631,6 +1640,27 @@
},
};
+/* micrel KSZ804 */
+static struct phy_info phy_info_ksz804 = {
+ 0x0022151,
+ "Micrel KSZ804 PHY",
+ 4,
+ (struct phy_cmd[]) { /* config */
+ {PHY_BMCR, PHY_BMCR_RESET, NULL},
+ {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* startup */
+ {PHY_BMSR, miim_read, NULL},
+ {PHY_BMSR, miim_read, &mii_parse_sr},
+ {PHY_BMSR, miim_read, &mii_parse_link},
+ {miim_end,}
+ },
+ (struct phy_cmd[]) { /* shutdown */
+ {miim_end,}
+ }
+};
+
/* a generic flavor. */
static struct phy_info phy_info_generic = {
0,
@@ -1794,6 +1824,7 @@
&phy_info_M88E1145,
&phy_info_M88E1149S,
&phy_info_dm9161,
+ &phy_info_ksz804,
&phy_info_lxt971,
&phy_info_VSC8211,
&phy_info_VSC8244,
diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c
index 9477851..56eee7b 100644
--- a/drivers/net/uli526x.c
+++ b/drivers/net/uli526x.c
@@ -225,7 +225,7 @@
iobase &= ~0xf;
dev = (struct eth_device *)malloc(sizeof *dev);
- sprintf(dev->name, "uli526x#%d\n", card_number);
+ sprintf(dev->name, "uli526x#%d", card_number);
db = (struct uli526x_board_info *)
malloc(sizeof(struct uli526x_board_info));
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 5a63fa2..001e6eb 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -510,18 +510,25 @@
#include <libfdt.h>
#include <fdt_support.h>
-void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose)
+void ft_fsl_pci_setup(void *blob, const char *pci_compat,
+ struct pci_controller *hose, unsigned long ctrl_addr)
{
- int off = fdt_path_offset(blob, pci_alias);
+ int off;
u32 bus_range[2];
+ phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
+
+ /* convert ctrl_addr to true physical address */
+ p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
+ p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
+
+ off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
if (off < 0)
return;
/* We assume a cfg_addr not being set means we didn't setup the controller */
if ((hose == NULL) || (hose->cfg_addr == NULL)) {
- fdt_del_node_and_alias(blob, pci_alias);
+ fdt_del_node(blob, off);
} else {
bus_range[0] = 0;
bus_range[1] = hose->last_busno - hose->first_busno;
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 63cc68e..c4ec2f4 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -440,10 +440,8 @@
{
ulong addr;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
if (strcmp(argv[1], "fw") == 0) {
addr = simple_strtoul(argv[2], NULL, 16);
@@ -471,8 +469,7 @@
return qe_upload_firmware((const struct qe_firmware *) addr);
}
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
index f28d42b..e0ad029 100644
--- a/drivers/spi/bfin_spi.c
+++ b/drivers/spi/bfin_spi.c
@@ -13,6 +13,8 @@
#include <spi.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/spi.h>
struct bfin_spi_slave {
@@ -33,54 +35,110 @@
#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
-__attribute__((weak))
+#define MAX_CTRL_CS 7
+
+#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
+#ifdef CONFIG_BFIN_SPI_GPIO_CS
+# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
+#else
+# define is_gpio_cs(cs) 0
+#endif
+
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
-#if defined(__ADSPBF538__) || defined(__ADSPBF539__)
- /* The SPI1/SPI2 buses are weird ... only 1 CS */
- if (bus > 0 && cs != 1)
- return 0;
-#endif
- return (cs >= 1 && cs <= 7);
+ if (is_gpio_cs(cs))
+ return gpio_is_valid(gpio_cs(cs));
+ else
+ return (cs >= 1 && cs <= MAX_CTRL_CS);
}
-__attribute__((weak))
void spi_cs_activate(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- write_SPI_FLG(bss,
- (read_SPI_FLG(bss) &
- ~((!bss->flg << 8) << slave->cs)) |
- (1 << slave->cs));
+
+ if (is_gpio_cs(slave->cs)) {
+ unsigned int cs = gpio_cs(slave->cs);
+ gpio_set_value(cs, bss->flg);
+ debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
+ } else {
+ write_SPI_FLG(bss,
+ (read_SPI_FLG(bss) &
+ ~((!bss->flg << 8) << slave->cs)) |
+ (1 << slave->cs));
+ debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+ }
+
SSYNC();
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
}
-__attribute__((weak))
void spi_cs_deactivate(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- u16 flg;
- /* make sure we force the cs to deassert rather than let the
- * pin float back up. otherwise, exact timings may not be
- * met some of the time leading to random behavior (ugh).
- */
- flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
- write_SPI_FLG(bss, flg);
- SSYNC();
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+ if (is_gpio_cs(slave->cs)) {
+ unsigned int cs = gpio_cs(slave->cs);
+ gpio_set_value(cs, !bss->flg);
+ debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
+ } else {
+ u16 flg;
- flg &= ~(1 << slave->cs);
- write_SPI_FLG(bss, flg);
+ /* make sure we force the cs to deassert rather than let the
+ * pin float back up. otherwise, exact timings may not be
+ * met some of the time leading to random behavior (ugh).
+ */
+ flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
+ write_SPI_FLG(bss, flg);
+ SSYNC();
+ debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+
+ flg &= ~(1 << slave->cs);
+ write_SPI_FLG(bss, flg);
+ debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+ }
+
SSYNC();
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
}
void spi_init()
{
}
+#ifdef SPI_CTL
+# define SPI0_CTL SPI_CTL
+#endif
+
+#define SPI_PINS(n) \
+ [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
+static unsigned short pins[][5] = {
+#ifdef SPI0_CTL
+ SPI_PINS(0),
+#endif
+#ifdef SPI1_CTL
+ SPI_PINS(1),
+#endif
+#ifdef SPI2_CTL
+ SPI_PINS(2),
+#endif
+};
+
+#define SPI_CS_PINS(n) \
+ [n] = { \
+ P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
+ P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
+ P_SPI##n##_SSEL7, \
+ }
+static const unsigned short cs_pins[][7] = {
+#ifdef SPI0_CTL
+ SPI_CS_PINS(0),
+#endif
+#ifdef SPI1_CTL
+ SPI_CS_PINS(1),
+#endif
+#ifdef SPI2_CTL
+ SPI_CS_PINS(2),
+#endif
+};
+
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
@@ -92,11 +150,14 @@
if (!spi_cs_is_valid(bus, cs))
return NULL;
+ if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
+ debug("%s: invalid bus %u\n", __func__, bus);
+ return NULL;
+ }
switch (bus) {
-#ifdef SPI_CTL
-# define SPI0_CTL SPI_CTL
-#endif
+#ifdef SPI0_CTL
case 0: mmr_base = SPI0_CTL; break;
+#endif
#ifdef SPI1_CTL
case 1: mmr_base = SPI1_CTL; break;
#endif
@@ -142,168 +203,21 @@
free(bss);
}
-static void spi_portmux(struct spi_slave *slave)
-{
-#if defined(__ADSPBF51x__)
-#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
- u16 f_mux = bfin_read_PORTF_MUX();
- u16 f_fer = bfin_read_PORTF_FER();
- u16 g_mux = bfin_read_PORTG_MUX();
- u16 g_fer = bfin_read_PORTG_FER();
- u16 h_mux = bfin_read_PORTH_MUX();
- u16 h_fer = bfin_read_PORTH_FER();
- switch (slave->bus) {
- case 0:
- /* set SCK/MISO/MOSI */
- SET_MUX(g, 7, 1);
- g_fer |= PG12 | PG13 | PG14;
- switch (slave->cs) {
- case 1: SET_MUX(f, 2, 1); f_fer |= PF7; break;
- case 2: /* see G above */ g_fer |= PG15; break;
- case 3: SET_MUX(h, 1, 3); f_fer |= PH4; break;
- case 4: /* no muxing */ h_fer |= PH8; break;
- case 5: SET_MUX(g, 1, 3); h_fer |= PG3; break;
- case 6: /* no muxing */ break;
- case 7: /* no muxing */ break;
- }
- case 1:
- /* set SCK/MISO/MOSI */
- SET_MUX(h, 0, 2);
- h_fer |= PH1 | PH2 | PH3;
- switch (slave->cs) {
- case 1: SET_MUX(h, 2, 3); h_fer |= PH6; break;
- case 2: SET_MUX(f, 0, 3); f_fer |= PF0; break;
- case 3: SET_MUX(g, 0, 3); g_fer |= PG0; break;
- case 4: SET_MUX(f, 3, 3); f_fer |= PF8; break;
- case 5: SET_MUX(g, 6, 3); h_fer |= PG11; break;
- case 6: /* no muxing */ break;
- case 7: /* no muxing */ break;
- }
- }
- bfin_write_PORTF_MUX(f_mux);
- bfin_write_PORTF_FER(f_fer);
- bfin_write_PORTG_MUX(g_mux);
- bfin_write_PORTG_FER(g_fer);
- bfin_write_PORTH_MUX(h_mux);
- bfin_write_PORTH_FER(h_fer);
-#elif defined(__ADSPBF52x__)
-#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
- u16 f_mux = bfin_read_PORTF_MUX();
- u16 f_fer = bfin_read_PORTF_FER();
- u16 g_mux = bfin_read_PORTG_MUX();
- u16 g_fer = bfin_read_PORTG_FER();
- u16 h_mux = bfin_read_PORTH_MUX();
- u16 h_fer = bfin_read_PORTH_FER();
- /* set SCK/MISO/MOSI */
- SET_MUX(g, 0, 3);
- g_fer |= PG2 | PG3 | PG4;
- switch (slave->cs) {
- case 1: /* see G above */ g_fer |= PG1; break;
- case 2: SET_MUX(f, 4, 3); f_fer |= PF12; break;
- case 3: SET_MUX(f, 4, 3); f_fer |= PF13; break;
- case 4: SET_MUX(h, 1, 1); h_fer |= PH8; break;
- case 5: SET_MUX(h, 2, 1); h_fer |= PH9; break;
- case 6: SET_MUX(f, 1, 3); f_fer |= PF9; break;
- case 7: SET_MUX(f, 2, 3); f_fer |= PF10; break;
- }
- bfin_write_PORTF_MUX(f_mux);
- bfin_write_PORTF_FER(f_fer);
- bfin_write_PORTG_MUX(g_mux);
- bfin_write_PORTG_FER(g_fer);
- bfin_write_PORTH_MUX(h_mux);
- bfin_write_PORTH_FER(h_fer);
-#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
- u16 mux = bfin_read_PORT_MUX();
- u16 f_fer = bfin_read_PORTF_FER();
- /* set SCK/MISO/MOSI */
- f_fer |= PF11 | PF12 | PF13;
- switch (slave->cs) {
- case 1: f_fer |= PF10; break;
- case 2: mux |= PJSE; break;
- case 3: mux |= PJSE; break;
- case 4: mux |= PFS4E; f_fer |= PF6; break;
- case 5: mux |= PFS5E; f_fer |= PF5; break;
- case 6: mux |= PFS6E; f_fer |= PF4; break;
- case 7: mux |= PJCE_SPI; break;
- }
- bfin_write_PORT_MUX(mux);
- bfin_write_PORTF_FER(f_fer);
-#elif defined(__ADSPBF538__) || defined(__ADSPBF539__)
- u16 fer, pins;
- if (slave->bus == 1)
- pins = PD0 | PD1 | PD2 | (slave->cs == 1 ? PD4 : 0);
- else if (slave->bus == 2)
- pins = PD5 | PD6 | PD7 | (slave->cs == 1 ? PD9 : 0);
- else
- pins = 0;
- if (pins) {
- fer = bfin_read_PORTDIO_FER();
- fer &= ~pins;
- bfin_write_PORTDIO_FER(fer);
- }
-#elif defined(__ADSPBF54x__)
-#define DO_MUX(port, pin) \
- mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \
- fer |= P##port##pin;
- u32 mux;
- u16 fer;
- switch (slave->bus) {
- case 0:
- mux = bfin_read_PORTE_MUX();
- fer = bfin_read_PORTE_FER();
- /* set SCK/MISO/MOSI */
- DO_MUX(E, 0);
- DO_MUX(E, 1);
- DO_MUX(E, 2);
- switch (slave->cs) {
- case 1: DO_MUX(E, 4); break;
- case 2: DO_MUX(E, 5); break;
- case 3: DO_MUX(E, 6); break;
- }
- bfin_write_PORTE_MUX(mux);
- bfin_write_PORTE_FER(fer);
- break;
- case 1:
- mux = bfin_read_PORTG_MUX();
- fer = bfin_read_PORTG_FER();
- /* set SCK/MISO/MOSI */
- DO_MUX(G, 8);
- DO_MUX(G, 9);
- DO_MUX(G, 10);
- switch (slave->cs) {
- case 1: DO_MUX(G, 5); break;
- case 2: DO_MUX(G, 6); break;
- case 3: DO_MUX(G, 7); break;
- }
- bfin_write_PORTG_MUX(mux);
- bfin_write_PORTG_FER(fer);
- break;
- case 2:
- mux = bfin_read_PORTB_MUX();
- fer = bfin_read_PORTB_FER();
- /* set SCK/MISO/MOSI */
- DO_MUX(B, 12);
- DO_MUX(B, 13);
- DO_MUX(B, 14);
- switch (slave->cs) {
- case 1: DO_MUX(B, 9); break;
- case 2: DO_MUX(B, 10); break;
- case 3: DO_MUX(B, 11); break;
- }
- bfin_write_PORTB_MUX(mux);
- bfin_write_PORTB_FER(fer);
- break;
- }
-#endif
-}
-
int spi_claim_bus(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- spi_portmux(slave);
+ if (is_gpio_cs(slave->cs)) {
+ unsigned int cs = gpio_cs(slave->cs);
+ gpio_request(cs, "bfin-spi");
+ gpio_direction_output(cs, !bss->flg);
+ pins[slave->bus][0] = P_DONTCARE;
+ } else
+ pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
+ peripheral_request_list(pins[slave->bus], "bfin-spi");
+
write_SPI_CTL(bss, bss->ctl);
write_SPI_BAUD(bss, bss->baud);
SSYNC();
@@ -314,7 +228,13 @@
void spi_release_bus(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+
+ peripheral_free_list(pins[slave->bus]);
+ if (is_gpio_cs(slave->cs))
+ gpio_free(gpio_cs(slave->cs));
+
write_SPI_CTL(bss, 0);
SSYNC();
}
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 4518ecb..13aca52 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -173,7 +173,7 @@
}
static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
- const u8 *txp, unsigned long flags)
+ const u8 *txp, unsigned long flags)
{
struct davinci_spi_slave *ds = to_davinci_spi(slave);
unsigned int data1_reg_val;
@@ -237,7 +237,7 @@
#endif
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+ const void *dout, void *din, unsigned long flags)
{
unsigned int len;
@@ -266,6 +266,10 @@
#ifndef CONFIG_SPI_HALF_DUPLEX
else
return davinci_spi_read_write(slave, len, din, dout, flags);
+#else
+ printf("SPI full duplex transaction requested with "
+ "CONFIG_SPI_HALF_DUPLEX defined.\n");
+ flags |= SPI_XFER_END;
#endif
out:
diff --git a/drivers/usb/musb/omap3.h b/drivers/usb/musb/omap3.h
index c934e0c..2886d7e 100644
--- a/drivers/usb/musb/omap3.h
+++ b/drivers/usb/musb/omap3.h
@@ -45,7 +45,7 @@
int musb_platform_init(void);
#ifdef CONFIG_OMAP3_EVM
-extern u8 omap3_evm_use_extvbus(void);
+extern u8 omap3_evm_need_extvbus(void);
#endif
#endif /* _MUSB_OMAP3_H */
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 96d52fb..fae5417 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -1119,7 +1119,7 @@
case 8:
padded_line -= width;
if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) {
- /* Copy colormap */
+ /* Copy colormap */
for (xcount = 0; xcount < colors; ++xcount) {
cte = bmp->color_table[xcount];
video_set_lut (xcount, cte.red, cte.green, cte.blue);
@@ -1321,11 +1321,11 @@
#ifdef CONFIG_VIDEO_BMP_LOGO
source = bmp_logo_bitmap;
- /* Allocate temporary space for computing colormap */
+ /* Allocate temporary space for computing colormap */
logo_red = malloc (BMP_LOGO_COLORS);
logo_green = malloc (BMP_LOGO_COLORS);
logo_blue = malloc (BMP_LOGO_COLORS);
- /* Compute color map */
+ /* Compute color map */
for (i = 0; i < VIDEO_LOGO_COLORS; i++) {
logo_red[i] = (bmp_logo_palette[i] & 0x0f00) >> 4;
logo_green[i] = (bmp_logo_palette[i] & 0x00f0);
diff --git a/examples/standalone/smc911x_eeprom.c b/examples/standalone/smc911x_eeprom.c
index c51a050..00e8266 100644
--- a/examples/standalone/smc911x_eeprom.c
+++ b/examples/standalone/smc911x_eeprom.c
@@ -240,7 +240,7 @@
static int smc911x_init(struct eth_device *dev)
{
/* See if there is anything there */
- if (!smc911x_detect_chip(dev))
+ if (smc911x_detect_chip(dev))
return 1;
smc911x_reset(dev);
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 6b3a274..003666e 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -34,8 +34,7 @@
/*
* Convert a string to lowercase.
*/
-static void
-downcase(char *str)
+static void downcase (char *str)
{
while (*str != '\0') {
TOLOWER(*str);
@@ -43,43 +42,49 @@
}
}
-static block_dev_desc_t *cur_dev = NULL;
+static block_dev_desc_t *cur_dev = NULL;
+
static unsigned long part_offset = 0;
+
static int cur_part = 1;
#define DOS_PART_TBL_OFFSET 0x1be
#define DOS_PART_MAGIC_OFFSET 0x1fe
#define DOS_FS_TYPE_OFFSET 0x36
+#define DOS_FS32_TYPE_OFFSET 0x52
-int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr)
+static int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr)
{
- startblock += part_offset;
if (cur_dev == NULL)
return -1;
+
+ startblock += part_offset;
+
if (cur_dev->block_read) {
- return cur_dev->block_read (cur_dev->dev
- , startblock, getsize, (unsigned long *)bufptr);
+ return cur_dev->block_read(cur_dev->dev, startblock, getsize,
+ (unsigned long *) bufptr);
}
return -1;
}
-
-int
-fat_register_device(block_dev_desc_t *dev_desc, int part_no)
+int fat_register_device (block_dev_desc_t * dev_desc, int part_no)
{
unsigned char buffer[SECTOR_SIZE];
+
disk_partition_t info;
if (!dev_desc->block_read)
return -1;
+
cur_dev = dev_desc;
/* check if we have a MBR (on floppies we have only a PBR) */
- if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) {
- printf ("** Can't read from device %d **\n", dev_desc->dev);
+ if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)buffer) != 1) {
+ printf("** Can't read from device %d **\n",
+ dev_desc->dev);
return -1;
}
if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 ||
- buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) {
+ buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) {
/* no signature found */
return -1;
}
@@ -90,22 +95,24 @@
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE) )
- /* First we assume, there is a MBR */
- if (!get_partition_info (dev_desc, part_no, &info)) {
+ /* First we assume there is a MBR */
+ if (!get_partition_info(dev_desc, part_no, &info)) {
part_offset = info.start;
cur_part = part_no;
- } else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) {
+ } else if ((strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3) == 0) ||
+ (strncmp((char *)&buffer[DOS_FS32_TYPE_OFFSET], "FAT32", 5) == 0)) {
/* ok, we assume we are on a PBR only */
cur_part = 1;
part_offset = 0;
} else {
- printf ("** Partition %d not valid on device %d **\n",
- part_no, dev_desc->dev);
+ printf("** Partition %d not valid on device %d **\n",
+ part_no, dev_desc->dev);
return -1;
}
#else
- if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
+ if ((strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3) == 0) ||
+ (strncmp((char *)&buffer[DOS_FS32_TYPE_OFFSET], "FAT32", 5) == 0)) {
/* ok, we assume we are on a PBR only */
cur_part = 1;
part_offset = 0;
@@ -123,18 +130,17 @@
return 0;
}
-
/*
* Get the first occurence of a directory delimiter ('/' or '\') in a string.
* Return index into string if found, -1 otherwise.
*/
-static int
-dirdelim(char *str)
+static int dirdelim (char *str)
{
char *start = str;
while (*str != '\0') {
- if (ISDIRDELIM(*str)) return str - start;
+ if (ISDIRDELIM(*str))
+ return str - start;
str++;
}
return -1;
@@ -147,7 +153,7 @@
{
char *ptr;
- memcpy (s_name, dirent->name, 8);
+ memcpy(s_name, dirent->name, 8);
s_name[8] = '\0';
ptr = s_name;
while (*ptr && *ptr != ' ')
@@ -155,7 +161,7 @@
if (dirent->ext[0] && dirent->ext[0] != ' ') {
*ptr = '.';
ptr++;
- memcpy (ptr, dirent->ext, 3);
+ memcpy(ptr, dirent->ext, 3);
ptr[3] = '\0';
while (*ptr && *ptr != ' ')
ptr++;
@@ -165,19 +171,19 @@
*s_name = '\0';
else if (*s_name == aRING)
*s_name = DELETED_FLAG;
- downcase (s_name);
+ downcase(s_name);
}
/*
* Get the entry at index 'entry' in a FAT (12/16/32) table.
* On failure 0x00 is returned.
*/
-static __u32
-get_fatent(fsdata *mydata, __u32 entry)
+static __u32 get_fatent (fsdata *mydata, __u32 entry)
{
__u32 bufnum;
- __u32 offset;
+ __u32 off16, offset;
__u32 ret = 0x00;
+ __u16 val1, val2;
switch (mydata->fatsize) {
case 32:
@@ -198,9 +204,12 @@
return ret;
}
+ debug("FAT%d: entry: 0x%04x = %d, offset: 0x%04x = %d\n",
+ mydata->fatsize, entry, entry, offset, offset);
+
/* Read a new block of FAT entries into the cache. */
if (bufnum != mydata->fatbufnum) {
- int getsize = FATBUFSIZE/FS_BLOCK_SIZE;
+ int getsize = FATBUFSIZE / FS_BLOCK_SIZE;
__u8 *bufptr = mydata->fatbuf;
__u32 fatlength = mydata->fatlength;
__u32 startblock = bufnum * FATBUFBLOCKS;
@@ -208,9 +217,10 @@
fatlength *= SECTOR_SIZE; /* We want it in bytes now */
startblock += mydata->fat_sect; /* Offset from start of disk */
- if (getsize > fatlength) getsize = fatlength;
+ if (getsize > fatlength)
+ getsize = fatlength;
if (disk_read(startblock, getsize, bufptr) < 0) {
- FAT_DPRINT("Error reading FAT blocks\n");
+ debug("Error reading FAT blocks\n");
return ret;
}
mydata->fatbufnum = bufnum;
@@ -219,79 +229,81 @@
/* Get the actual entry from the table */
switch (mydata->fatsize) {
case 32:
- ret = FAT2CPU32(((__u32*)mydata->fatbuf)[offset]);
+ ret = FAT2CPU32(((__u32 *) mydata->fatbuf)[offset]);
break;
case 16:
- ret = FAT2CPU16(((__u16*)mydata->fatbuf)[offset]);
+ ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[offset]);
break;
- case 12: {
- __u32 off16 = (offset*3)/4;
- __u16 val1, val2;
+ case 12:
+ off16 = (offset * 3) / 4;
switch (offset & 0x3) {
case 0:
- ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]);
+ ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[off16]);
ret &= 0xfff;
break;
case 1:
- val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]);
+ val1 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16]);
val1 &= 0xf000;
- val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]);
+ val2 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16 + 1]);
val2 &= 0x00ff;
ret = (val2 << 4) | (val1 >> 12);
break;
case 2:
- val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]);
+ val1 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16]);
val1 &= 0xff00;
- val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]);
+ val2 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16 + 1]);
val2 &= 0x000f;
ret = (val2 << 8) | (val1 >> 8);
break;
case 3:
- ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]);;
+ ret = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16]);
ret = (ret & 0xfff0) >> 4;
break;
default:
break;
}
+ break;
}
- break;
- }
- FAT_DPRINT("ret: %d, offset: %d\n", ret, offset);
+ debug("FAT%d: ret: %08x, offset: %04x\n",
+ mydata->fatsize, ret, offset);
return ret;
}
-
/*
* Read at most 'size' bytes from the specified cluster into 'buffer'.
* Return 0 on success, -1 otherwise.
*/
static int
-get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size)
+get_cluster (fsdata *mydata, __u32 clustnum, __u8 *buffer,
+ unsigned long size)
{
int idx = 0;
__u32 startsect;
if (clustnum > 0) {
- startsect = mydata->data_begin + clustnum*mydata->clust_size;
+ startsect = mydata->data_begin +
+ clustnum * mydata->clust_size;
} else {
startsect = mydata->rootdir_sect;
}
- FAT_DPRINT("gc - clustnum: %d, startsect: %d\n", clustnum, startsect);
- if (disk_read(startsect, size/FS_BLOCK_SIZE , buffer) < 0) {
- FAT_DPRINT("Error reading data\n");
+ debug("gc - clustnum: %d, startsect: %d\n", clustnum, startsect);
+
+ if (disk_read(startsect, size / FS_BLOCK_SIZE, buffer) < 0) {
+ debug("Error reading data\n");
return -1;
}
- if(size % FS_BLOCK_SIZE) {
+ if (size % FS_BLOCK_SIZE) {
__u8 tmpbuf[FS_BLOCK_SIZE];
- idx= size/FS_BLOCK_SIZE;
+
+ idx = size / FS_BLOCK_SIZE;
if (disk_read(startsect + idx, 1, tmpbuf) < 0) {
- FAT_DPRINT("Error reading data\n");
+ debug("Error reading data\n");
return -1;
}
- buffer += idx*FS_BLOCK_SIZE;
+ buffer += idx * FS_BLOCK_SIZE;
memcpy(buffer, tmpbuf, size % FS_BLOCK_SIZE);
return 0;
@@ -300,15 +312,14 @@
return 0;
}
-
/*
* Read at most 'maxsize' bytes from the file associated with 'dentptr'
* into 'buffer'.
* Return the number of bytes read or -1 on fatal errors.
*/
static long
-get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer,
- unsigned long maxsize)
+get_contents (fsdata *mydata, dir_entry *dentptr, __u8 *buffer,
+ unsigned long maxsize)
{
unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0;
unsigned int bytesperclust = mydata->clust_size * SECTOR_SIZE;
@@ -316,161 +327,174 @@
__u32 endclust, newclust;
unsigned long actsize;
- FAT_DPRINT("Filesize: %ld bytes\n", filesize);
+ debug("Filesize: %ld bytes\n", filesize);
- if (maxsize > 0 && filesize > maxsize) filesize = maxsize;
+ if (maxsize > 0 && filesize > maxsize)
+ filesize = maxsize;
- FAT_DPRINT("Reading: %ld bytes\n", filesize);
+ debug("%ld bytes\n", filesize);
- actsize=bytesperclust;
- endclust=curclust;
+ actsize = bytesperclust;
+ endclust = curclust;
+
do {
/* search for consecutive clusters */
- while(actsize < filesize) {
+ while (actsize < filesize) {
newclust = get_fatent(mydata, endclust);
- if((newclust -1)!=endclust)
+ if ((newclust - 1) != endclust)
goto getit;
if (CHECK_CLUST(newclust, mydata->fatsize)) {
- FAT_DPRINT("curclust: 0x%x\n", newclust);
- FAT_DPRINT("Invalid FAT entry\n");
+ debug("curclust: 0x%x\n", newclust);
+ debug("Invalid FAT entry\n");
return gotsize;
}
- endclust=newclust;
- actsize+= bytesperclust;
+ endclust = newclust;
+ actsize += bytesperclust;
}
+
/* actsize >= file size */
actsize -= bytesperclust;
+
/* get remaining clusters */
if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
- FAT_ERROR("Error reading cluster\n");
+ printf("Error reading cluster\n");
return -1;
}
+
/* get remaining bytes */
gotsize += (int)actsize;
filesize -= actsize;
buffer += actsize;
- actsize= filesize;
+ actsize = filesize;
if (get_cluster(mydata, endclust, buffer, (int)actsize) != 0) {
- FAT_ERROR("Error reading cluster\n");
+ printf("Error reading cluster\n");
return -1;
}
- gotsize+=actsize;
+ gotsize += actsize;
return gotsize;
getit:
if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
- FAT_ERROR("Error reading cluster\n");
+ printf("Error reading cluster\n");
return -1;
}
gotsize += (int)actsize;
filesize -= actsize;
buffer += actsize;
+
curclust = get_fatent(mydata, endclust);
if (CHECK_CLUST(curclust, mydata->fatsize)) {
- FAT_DPRINT("curclust: 0x%x\n", curclust);
- FAT_ERROR("Invalid FAT entry\n");
+ debug("curclust: 0x%x\n", curclust);
+ printf("Invalid FAT entry\n");
return gotsize;
}
- actsize=bytesperclust;
- endclust=curclust;
+ actsize = bytesperclust;
+ endclust = curclust;
} while (1);
}
-
#ifdef CONFIG_SUPPORT_VFAT
/*
* Extract the file name information from 'slotptr' into 'l_name',
* starting at l_name[*idx].
* Return 1 if terminator (zero byte) is found, 0 otherwise.
*/
-static int
-slot2str(dir_slot *slotptr, char *l_name, int *idx)
+static int slot2str (dir_slot *slotptr, char *l_name, int *idx)
{
int j;
for (j = 0; j <= 8; j += 2) {
l_name[*idx] = slotptr->name0_4[j];
- if (l_name[*idx] == 0x00) return 1;
+ if (l_name[*idx] == 0x00)
+ return 1;
(*idx)++;
}
for (j = 0; j <= 10; j += 2) {
l_name[*idx] = slotptr->name5_10[j];
- if (l_name[*idx] == 0x00) return 1;
+ if (l_name[*idx] == 0x00)
+ return 1;
(*idx)++;
}
for (j = 0; j <= 2; j += 2) {
l_name[*idx] = slotptr->name11_12[j];
- if (l_name[*idx] == 0x00) return 1;
+ if (l_name[*idx] == 0x00)
+ return 1;
(*idx)++;
}
return 0;
}
-
/*
* Extract the full long filename starting at 'retdent' (which is really
* a slot) into 'l_name'. If successful also copy the real directory entry
* into 'retdent'
* Return 0 on success, -1 otherwise.
*/
-__attribute__ ((__aligned__(__alignof__(dir_entry))))
+__attribute__ ((__aligned__ (__alignof__ (dir_entry))))
__u8 get_vfatname_block[MAX_CLUSTSIZE];
+
static int
-get_vfatname(fsdata *mydata, int curclust, __u8 *cluster,
- dir_entry *retdent, char *l_name)
+get_vfatname (fsdata *mydata, int curclust, __u8 *cluster,
+ dir_entry *retdent, char *l_name)
{
dir_entry *realdent;
- dir_slot *slotptr = (dir_slot*) retdent;
- __u8 *nextclust = cluster + mydata->clust_size * SECTOR_SIZE;
- __u8 counter = (slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff;
+ dir_slot *slotptr = (dir_slot *)retdent;
+ __u8 *nextclust = cluster + mydata->clust_size * SECTOR_SIZE;
+ __u8 counter = (slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff;
int idx = 0;
- while ((__u8*)slotptr < nextclust) {
- if (counter == 0) break;
+ while ((__u8 *)slotptr < nextclust) {
+ if (counter == 0)
+ break;
if (((slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff) != counter)
return -1;
slotptr++;
counter--;
}
- if ((__u8*)slotptr >= nextclust) {
+ if ((__u8 *)slotptr >= nextclust) {
dir_slot *slotptr2;
slotptr--;
curclust = get_fatent(mydata, curclust);
if (CHECK_CLUST(curclust, mydata->fatsize)) {
- FAT_DPRINT("curclust: 0x%x\n", curclust);
- FAT_ERROR("Invalid FAT entry\n");
+ debug("curclust: 0x%x\n", curclust);
+ printf("Invalid FAT entry\n");
return -1;
}
+
if (get_cluster(mydata, curclust, get_vfatname_block,
mydata->clust_size * SECTOR_SIZE) != 0) {
- FAT_DPRINT("Error: reading directory block\n");
+ debug("Error: reading directory block\n");
return -1;
}
- slotptr2 = (dir_slot*) get_vfatname_block;
- while (slotptr2->id > 0x01) {
+
+ slotptr2 = (dir_slot *)get_vfatname_block;
+ while (slotptr2->id > 0x01)
slotptr2++;
- }
+
/* Save the real directory entry */
- realdent = (dir_entry*)slotptr2 + 1;
- while ((__u8*)slotptr2 >= get_vfatname_block) {
+ realdent = (dir_entry *)slotptr2 + 1;
+ while ((__u8 *)slotptr2 >= get_vfatname_block) {
slot2str(slotptr2, l_name, &idx);
slotptr2--;
}
} else {
/* Save the real directory entry */
- realdent = (dir_entry*)slotptr;
+ realdent = (dir_entry *)slotptr;
}
do {
slotptr--;
- if (slot2str(slotptr, l_name, &idx)) break;
+ if (slot2str(slotptr, l_name, &idx))
+ break;
} while (!(slotptr->id & LAST_LONG_ENTRY_MASK));
l_name[idx] = '\0';
- if (*l_name == DELETED_FLAG) *l_name = '\0';
- else if (*l_name == aRING) *l_name = DELETED_FLAG;
+ if (*l_name == DELETED_FLAG)
+ *l_name = '\0';
+ else if (*l_name == aRING)
+ *l_name = DELETED_FLAG;
downcase(l_name);
/* Return the real directory entry */
@@ -479,214 +503,226 @@
return 0;
}
-
/* Calculate short name checksum */
-static __u8
-mkcksum(const char *str)
+static __u8 mkcksum (const char *str)
{
int i;
+
__u8 ret = 0;
for (i = 0; i < 11; i++) {
- ret = (((ret&1)<<7)|((ret&0xfe)>>1)) + str[i];
+ ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + str[i];
}
return ret;
}
-#endif
-
+#endif /* CONFIG_SUPPORT_VFAT */
/*
* Get the directory entry associated with 'filename' from the directory
* starting at 'startsect'
*/
-__attribute__ ((__aligned__(__alignof__(dir_entry))))
+__attribute__ ((__aligned__ (__alignof__ (dir_entry))))
__u8 get_dentfromdir_block[MAX_CLUSTSIZE];
-static dir_entry *get_dentfromdir (fsdata * mydata, int startsect,
- char *filename, dir_entry * retdent,
+
+static dir_entry *get_dentfromdir (fsdata *mydata, int startsect,
+ char *filename, dir_entry *retdent,
int dols)
{
- __u16 prevcksum = 0xffff;
- __u32 curclust = START (retdent);
- int files = 0, dirs = 0;
+ __u16 prevcksum = 0xffff;
+ __u32 curclust = START(retdent);
+ int files = 0, dirs = 0;
- FAT_DPRINT ("get_dentfromdir: %s\n", filename);
- while (1) {
- dir_entry *dentptr;
- int i;
+ debug("get_dentfromdir: %s\n", filename);
- if (get_cluster (mydata, curclust, get_dentfromdir_block,
- mydata->clust_size * SECTOR_SIZE) != 0) {
- FAT_DPRINT ("Error: reading directory block\n");
- return NULL;
- }
- dentptr = (dir_entry *) get_dentfromdir_block;
- for (i = 0; i < DIRENTSPERCLUST; i++) {
- char s_name[14], l_name[256];
+ while (1) {
+ dir_entry *dentptr;
- l_name[0] = '\0';
- if (dentptr->name[0] == DELETED_FLAG) {
- dentptr++;
- continue;
- }
- if ((dentptr->attr & ATTR_VOLUME)) {
-#ifdef CONFIG_SUPPORT_VFAT
- if ((dentptr->attr & ATTR_VFAT) &&
- (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
- prevcksum = ((dir_slot *) dentptr)
- ->alias_checksum;
- get_vfatname (mydata, curclust, get_dentfromdir_block,
- dentptr, l_name);
- if (dols) {
- int isdir = (dentptr->attr & ATTR_DIR);
- char dirc;
- int doit = 0;
+ int i;
- if (isdir) {
- dirs++;
- dirc = '/';
- doit = 1;
- } else {
- dirc = ' ';
- if (l_name[0] != 0) {
- files++;
- doit = 1;
- }
+ if (get_cluster(mydata, curclust, get_dentfromdir_block,
+ mydata->clust_size * SECTOR_SIZE) != 0) {
+ debug("Error: reading directory block\n");
+ return NULL;
+ }
+
+ dentptr = (dir_entry *)get_dentfromdir_block;
+
+ for (i = 0; i < DIRENTSPERCLUST; i++) {
+ char s_name[14], l_name[256];
+
+ l_name[0] = '\0';
+ if (dentptr->name[0] == DELETED_FLAG) {
+ dentptr++;
+ continue;
}
- if (doit) {
- if (dirc == ' ') {
- printf (" %8ld %s%c\n",
- (long) FAT2CPU32 (dentptr->size),
- l_name, dirc);
- } else {
- printf (" %s%c\n", l_name, dirc);
- }
- }
- dentptr++;
- continue;
- }
- FAT_DPRINT ("vfatname: |%s|\n", l_name);
- } else
-#endif
- {
- /* Volume label or VFAT entry */
- dentptr++;
- continue;
- }
- }
- if (dentptr->name[0] == 0) {
- if (dols) {
- printf ("\n%d file(s), %d dir(s)\n\n", files, dirs);
- }
- FAT_DPRINT ("Dentname == NULL - %d\n", i);
- return NULL;
- }
+ if ((dentptr->attr & ATTR_VOLUME)) {
#ifdef CONFIG_SUPPORT_VFAT
- if (dols && mkcksum (dentptr->name) == prevcksum) {
- dentptr++;
- continue;
- }
+ if ((dentptr->attr & ATTR_VFAT) &&
+ (dentptr-> name[0] & LAST_LONG_ENTRY_MASK)) {
+ prevcksum = ((dir_slot *)dentptr)->alias_checksum;
+ get_vfatname(mydata, curclust,
+ get_dentfromdir_block,
+ dentptr, l_name);
+ if (dols) {
+ int isdir;
+ char dirc;
+ int doit = 0;
+
+ isdir = (dentptr->attr & ATTR_DIR);
+
+ if (isdir) {
+ dirs++;
+ dirc = '/';
+ doit = 1;
+ } else {
+ dirc = ' ';
+ if (l_name[0] != 0) {
+ files++;
+ doit = 1;
+ }
+ }
+ if (doit) {
+ if (dirc == ' ') {
+ printf(" %8ld %s%c\n",
+ (long)FAT2CPU32(dentptr->size),
+ l_name,
+ dirc);
+ } else {
+ printf(" %s%c\n",
+ l_name,
+ dirc);
+ }
+ }
+ dentptr++;
+ continue;
+ }
+ debug("vfatname: |%s|\n", l_name);
+ } else
#endif
- get_name (dentptr, s_name);
- if (dols) {
- int isdir = (dentptr->attr & ATTR_DIR);
- char dirc;
- int doit = 0;
+ {
+ /* Volume label or VFAT entry */
+ dentptr++;
+ continue;
+ }
+ }
+ if (dentptr->name[0] == 0) {
+ if (dols) {
+ printf("\n%d file(s), %d dir(s)\n\n",
+ files, dirs);
+ }
+ debug("Dentname == NULL - %d\n", i);
+ return NULL;
+ }
+#ifdef CONFIG_SUPPORT_VFAT
+ if (dols && mkcksum(dentptr->name) == prevcksum) {
+ dentptr++;
+ continue;
+ }
+#endif
+ get_name(dentptr, s_name);
+ if (dols) {
+ int isdir = (dentptr->attr & ATTR_DIR);
+ char dirc;
+ int doit = 0;
- if (isdir) {
- dirs++;
- dirc = '/';
- doit = 1;
- } else {
- dirc = ' ';
- if (s_name[0] != 0) {
- files++;
- doit = 1;
- }
+ if (isdir) {
+ dirs++;
+ dirc = '/';
+ doit = 1;
+ } else {
+ dirc = ' ';
+ if (s_name[0] != 0) {
+ files++;
+ doit = 1;
+ }
+ }
+
+ if (doit) {
+ if (dirc == ' ') {
+ printf(" %8ld %s%c\n",
+ (long)FAT2CPU32(dentptr->size),
+ s_name, dirc);
+ } else {
+ printf(" %s%c\n",
+ s_name, dirc);
+ }
+ }
+
+ dentptr++;
+ continue;
+ }
+
+ if (strcmp(filename, s_name)
+ && strcmp(filename, l_name)) {
+ debug("Mismatch: |%s|%s|\n", s_name, l_name);
+ dentptr++;
+ continue;
+ }
+
+ memcpy(retdent, dentptr, sizeof(dir_entry));
+
+ debug("DentName: %s", s_name);
+ debug(", start: 0x%x", START(dentptr));
+ debug(", size: 0x%x %s\n",
+ FAT2CPU32(dentptr->size),
+ (dentptr->attr & ATTR_DIR) ? "(DIR)" : "");
+
+ return retdent;
}
- if (doit) {
- if (dirc == ' ') {
- printf (" %8ld %s%c\n",
- (long) FAT2CPU32 (dentptr->size), s_name,
- dirc);
- } else {
- printf (" %s%c\n", s_name, dirc);
- }
+
+ curclust = get_fatent(mydata, curclust);
+ if (CHECK_CLUST(curclust, mydata->fatsize)) {
+ debug("curclust: 0x%x\n", curclust);
+ printf("Invalid FAT entry\n");
+ return NULL;
}
- dentptr++;
- continue;
- }
- if (strcmp (filename, s_name) && strcmp (filename, l_name)) {
- FAT_DPRINT ("Mismatch: |%s|%s|\n", s_name, l_name);
- dentptr++;
- continue;
- }
- memcpy (retdent, dentptr, sizeof (dir_entry));
-
- FAT_DPRINT ("DentName: %s", s_name);
- FAT_DPRINT (", start: 0x%x", START (dentptr));
- FAT_DPRINT (", size: 0x%x %s\n",
- FAT2CPU32 (dentptr->size),
- (dentptr->attr & ATTR_DIR) ? "(DIR)" : "");
-
- return retdent;
}
- curclust = get_fatent (mydata, curclust);
- if (CHECK_CLUST(curclust, mydata->fatsize)) {
- FAT_DPRINT ("curclust: 0x%x\n", curclust);
- FAT_ERROR ("Invalid FAT entry\n");
- return NULL;
- }
- }
- return NULL;
+ return NULL;
}
-
/*
* Read boot sector and volume info from a FAT filesystem
*/
static int
-read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize)
+read_bootsectandvi (boot_sector *bs, volume_info *volinfo, int *fatsize)
{
__u8 block[FS_BLOCK_SIZE];
+
volume_info *vistart;
- if (disk_read(0, 1, block) < 0) {
- FAT_DPRINT("Error: reading block\n");
+ if (disk_read (0, 1, block) < 0) {
+ debug("Error: reading block\n");
return -1;
}
memcpy(bs, block, sizeof(boot_sector));
- bs->reserved = FAT2CPU16(bs->reserved);
- bs->fat_length = FAT2CPU16(bs->fat_length);
- bs->secs_track = FAT2CPU16(bs->secs_track);
- bs->heads = FAT2CPU16(bs->heads);
-#if 0 /* UNUSED */
- bs->hidden = FAT2CPU32(bs->hidden);
-#endif
- bs->total_sect = FAT2CPU32(bs->total_sect);
+ bs->reserved = FAT2CPU16(bs->reserved);
+ bs->fat_length = FAT2CPU16(bs->fat_length);
+ bs->secs_track = FAT2CPU16(bs->secs_track);
+ bs->heads = FAT2CPU16(bs->heads);
+ bs->total_sect = FAT2CPU32(bs->total_sect);
/* FAT32 entries */
if (bs->fat_length == 0) {
/* Assume FAT32 */
bs->fat32_length = FAT2CPU32(bs->fat32_length);
- bs->flags = FAT2CPU16(bs->flags);
+ bs->flags = FAT2CPU16(bs->flags);
bs->root_cluster = FAT2CPU32(bs->root_cluster);
- bs->info_sector = FAT2CPU16(bs->info_sector);
- bs->backup_boot = FAT2CPU16(bs->backup_boot);
- vistart = (volume_info*) (block + sizeof(boot_sector));
+ bs->info_sector = FAT2CPU16(bs->info_sector);
+ bs->backup_boot = FAT2CPU16(bs->backup_boot);
+ vistart = (volume_info *)(block + sizeof(boot_sector));
*fatsize = 32;
} else {
- vistart = (volume_info*) &(bs->fat32_length);
+ vistart = (volume_info *)&(bs->fat32_length);
*fatsize = 0;
}
memcpy(volinfo, vistart, sizeof(volume_info));
if (*fatsize == 32) {
- if (strncmp(FAT32_SIGN, vistart->fs_type, SIGNLEN) == 0) {
+ if (strncmp(FAT32_SIGN, vistart->fs_type, SIGNLEN) == 0)
return 0;
- }
} else {
if (strncmp(FAT12_SIGN, vistart->fs_type, SIGNLEN) == 0) {
*fatsize = 12;
@@ -698,262 +734,338 @@
}
}
- FAT_DPRINT("Error: broken fs_type sign\n");
+ debug("Error: broken fs_type sign\n");
return -1;
}
-__attribute__ ((__aligned__(__alignof__(dir_entry))))
+__attribute__ ((__aligned__ (__alignof__ (dir_entry))))
__u8 do_fat_read_block[MAX_CLUSTSIZE];
+
long
do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
int dols)
{
- char fnamecopy[2048];
- boot_sector bs;
- volume_info volinfo;
- fsdata datablock;
- fsdata *mydata = &datablock;
- dir_entry *dentptr;
- __u16 prevcksum = 0xffff;
- char *subname = "";
- int rootdir_size, cursect;
- int idx, isdir = 0;
- int files = 0, dirs = 0;
- long ret = 0;
- int firsttime;
+ char fnamecopy[2048];
+ boot_sector bs;
+ volume_info volinfo;
+ fsdata datablock;
+ fsdata *mydata = &datablock;
+ dir_entry *dentptr;
+ __u16 prevcksum = 0xffff;
+ char *subname = "";
+ int cursect;
+ int idx, isdir = 0;
+ int files = 0, dirs = 0;
+ long ret = 0;
+ int firsttime;
+ int root_cluster;
+ int j;
- if (read_bootsectandvi (&bs, &volinfo, &mydata->fatsize)) {
- FAT_DPRINT ("Error: reading boot sector\n");
- return -1;
- }
- if (mydata->fatsize == 32) {
- mydata->fatlength = bs.fat32_length;
- } else {
- mydata->fatlength = bs.fat_length;
- }
- mydata->fat_sect = bs.reserved;
- cursect = mydata->rootdir_sect
- = mydata->fat_sect + mydata->fatlength * bs.fats;
- mydata->clust_size = bs.cluster_size;
- if (mydata->fatsize == 32) {
- rootdir_size = mydata->clust_size;
- mydata->data_begin = mydata->rootdir_sect /* + rootdir_size */
- - (mydata->clust_size * 2);
- } else {
- rootdir_size = ((bs.dir_entries[1] * (int) 256 + bs.dir_entries[0])
- * sizeof (dir_entry)) / SECTOR_SIZE;
- mydata->data_begin = mydata->rootdir_sect + rootdir_size
- - (mydata->clust_size * 2);
- }
- mydata->fatbufnum = -1;
-
- FAT_DPRINT ("FAT%d, fatlength: %d\n", mydata->fatsize,
- mydata->fatlength);
- FAT_DPRINT ("Rootdir begins at sector: %d, offset: %x, size: %d\n"
- "Data begins at: %d\n",
- mydata->rootdir_sect, mydata->rootdir_sect * SECTOR_SIZE,
- rootdir_size, mydata->data_begin);
- FAT_DPRINT ("Cluster size: %d\n", mydata->clust_size);
-
- /* "cwd" is always the root... */
- while (ISDIRDELIM (*filename))
- filename++;
- /* Make a copy of the filename and convert it to lowercase */
- strcpy (fnamecopy, filename);
- downcase (fnamecopy);
- if (*fnamecopy == '\0') {
- if (!dols)
- return -1;
- dols = LS_ROOT;
- } else if ((idx = dirdelim (fnamecopy)) >= 0) {
- isdir = 1;
- fnamecopy[idx] = '\0';
- subname = fnamecopy + idx + 1;
- /* Handle multiple delimiters */
- while (ISDIRDELIM (*subname))
- subname++;
- } else if (dols) {
- isdir = 1;
- }
-
- while (1) {
- int i;
-
- if (disk_read (cursect, mydata->clust_size, do_fat_read_block) < 0) {
- FAT_DPRINT ("Error: reading rootdir block\n");
- return -1;
- }
- dentptr = (dir_entry *) do_fat_read_block;
- for (i = 0; i < DIRENTSPERBLOCK; i++) {
- char s_name[14], l_name[256];
-
- l_name[0] = '\0';
- if ((dentptr->attr & ATTR_VOLUME)) {
-#ifdef CONFIG_SUPPORT_VFAT
- if ((dentptr->attr & ATTR_VFAT) &&
- (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
- prevcksum = ((dir_slot *) dentptr)->alias_checksum;
- get_vfatname (mydata, 0, do_fat_read_block, dentptr, l_name);
- if (dols == LS_ROOT) {
- int isdir = (dentptr->attr & ATTR_DIR);
- char dirc;
- int doit = 0;
-
- if (isdir) {
- dirs++;
- dirc = '/';
- doit = 1;
- } else {
- dirc = ' ';
- if (l_name[0] != 0) {
- files++;
- doit = 1;
- }
- }
- if (doit) {
- if (dirc == ' ') {
- printf (" %8ld %s%c\n",
- (long) FAT2CPU32 (dentptr->size),
- l_name, dirc);
- } else {
- printf (" %s%c\n", l_name, dirc);
- }
- }
- dentptr++;
- continue;
- }
- FAT_DPRINT ("Rootvfatname: |%s|\n", l_name);
- } else
-#endif
- {
- /* Volume label or VFAT entry */
- dentptr++;
- continue;
- }
- } else if (dentptr->name[0] == 0) {
- FAT_DPRINT ("RootDentname == NULL - %d\n", i);
- if (dols == LS_ROOT) {
- printf ("\n%d file(s), %d dir(s)\n\n", files, dirs);
- return 0;
- }
+ if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) {
+ debug("Error: reading boot sector\n");
return -1;
- }
-#ifdef CONFIG_SUPPORT_VFAT
- else if (dols == LS_ROOT
- && mkcksum (dentptr->name) == prevcksum) {
- dentptr++;
- continue;
- }
-#endif
- get_name (dentptr, s_name);
- if (dols == LS_ROOT) {
- int isdir = (dentptr->attr & ATTR_DIR);
- char dirc;
- int doit = 0;
-
- if (isdir) {
- dirc = '/';
- if (s_name[0] != 0) {
- dirs++;
- doit = 1;
- }
- } else {
- dirc = ' ';
- if (s_name[0] != 0) {
- files++;
- doit = 1;
- }
- }
- if (doit) {
- if (dirc == ' ') {
- printf (" %8ld %s%c\n",
- (long) FAT2CPU32 (dentptr->size), s_name,
- dirc);
- } else {
- printf (" %s%c\n", s_name, dirc);
- }
- }
- dentptr++;
- continue;
- }
- if (strcmp (fnamecopy, s_name) && strcmp (fnamecopy, l_name)) {
- FAT_DPRINT ("RootMismatch: |%s|%s|\n", s_name, l_name);
- dentptr++;
- continue;
- }
- if (isdir && !(dentptr->attr & ATTR_DIR))
- return -1;
-
- FAT_DPRINT ("RootName: %s", s_name);
- FAT_DPRINT (", start: 0x%x", START (dentptr));
- FAT_DPRINT (", size: 0x%x %s\n",
- FAT2CPU32 (dentptr->size), isdir ? "(DIR)" : "");
-
- goto rootdir_done; /* We got a match */
}
- cursect++;
- }
- rootdir_done:
- firsttime = 1;
- while (isdir) {
- int startsect = mydata->data_begin
- + START (dentptr) * mydata->clust_size;
- dir_entry dent;
- char *nextname = NULL;
+ root_cluster = bs.root_cluster;
- dent = *dentptr;
- dentptr = &dent;
+ if (mydata->fatsize == 32)
+ mydata->fatlength = bs.fat32_length;
+ else
+ mydata->fatlength = bs.fat_length;
- idx = dirdelim (subname);
- if (idx >= 0) {
- subname[idx] = '\0';
- nextname = subname + idx + 1;
- /* Handle multiple delimiters */
- while (ISDIRDELIM (*nextname))
- nextname++;
- if (dols && *nextname == '\0')
- firsttime = 0;
+ mydata->fat_sect = bs.reserved;
+
+ cursect = mydata->rootdir_sect
+ = mydata->fat_sect + mydata->fatlength * bs.fats;
+
+ mydata->clust_size = bs.cluster_size;
+
+ if (mydata->fatsize == 32) {
+ mydata->data_begin = mydata->rootdir_sect -
+ (mydata->clust_size * 2);
} else {
- if (dols && firsttime) {
- firsttime = 0;
- } else {
- isdir = 0;
- }
+ int rootdir_size;
+
+ rootdir_size = ((bs.dir_entries[1] * (int)256 +
+ bs.dir_entries[0]) *
+ sizeof(dir_entry)) /
+ SECTOR_SIZE;
+ mydata->data_begin = mydata->rootdir_sect +
+ rootdir_size -
+ (mydata->clust_size * 2);
}
- if (get_dentfromdir (mydata, startsect, subname, dentptr,
- isdir ? 0 : dols) == NULL) {
- if (dols && !isdir)
- return 0;
- return -1;
+ mydata->fatbufnum = -1;
+
+#ifdef CONFIG_SUPPORT_VFAT
+ debug("VFAT Support enabled\n");
+#endif
+ debug("FAT%d, fat_sect: %d, fatlength: %d\n",
+ mydata->fatsize, mydata->fat_sect, mydata->fatlength);
+ debug("Rootdir begins at cluster: %d, sector: %d, offset: %x\n"
+ "Data begins at: %d\n",
+ root_cluster,
+ mydata->rootdir_sect,
+ mydata->rootdir_sect * SECTOR_SIZE, mydata->data_begin);
+ debug("Cluster size: %d\n", mydata->clust_size);
+
+ /* "cwd" is always the root... */
+ while (ISDIRDELIM(*filename))
+ filename++;
+
+ /* Make a copy of the filename and convert it to lowercase */
+ strcpy(fnamecopy, filename);
+ downcase(fnamecopy);
+
+ if (*fnamecopy == '\0') {
+ if (!dols)
+ return -1;
+
+ dols = LS_ROOT;
+ } else if ((idx = dirdelim(fnamecopy)) >= 0) {
+ isdir = 1;
+ fnamecopy[idx] = '\0';
+ subname = fnamecopy + idx + 1;
+
+ /* Handle multiple delimiters */
+ while (ISDIRDELIM(*subname))
+ subname++;
+ } else if (dols) {
+ isdir = 1;
}
- if (idx >= 0) {
- if (!(dentptr->attr & ATTR_DIR))
- return -1;
- subname = nextname;
- }
- }
- ret = get_contents (mydata, dentptr, buffer, maxsize);
- FAT_DPRINT ("Size: %d, got: %ld\n", FAT2CPU32 (dentptr->size), ret);
+ j = 0;
+ while (1) {
+ int i;
- return ret;
+ debug("FAT read sect=%d, clust_size=%d, DIRENTSPERBLOCK=%d\n",
+ cursect, mydata->clust_size, DIRENTSPERBLOCK);
+
+ if (disk_read(cursect, mydata->clust_size, do_fat_read_block) < 0) {
+ debug("Error: reading rootdir block\n");
+ return -1;
+ }
+
+ dentptr = (dir_entry *) do_fat_read_block;
+
+ for (i = 0; i < DIRENTSPERBLOCK; i++) {
+ char s_name[14], l_name[256];
+
+ l_name[0] = '\0';
+ if ((dentptr->attr & ATTR_VOLUME)) {
+#ifdef CONFIG_SUPPORT_VFAT
+ if ((dentptr->attr & ATTR_VFAT) &&
+ (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
+ prevcksum =
+ ((dir_slot *)dentptr)->alias_checksum;
+
+ get_vfatname(mydata, 0,
+ do_fat_read_block,
+ dentptr, l_name);
+
+ if (dols == LS_ROOT) {
+ char dirc;
+ int doit = 0;
+ int isdir =
+ (dentptr->attr & ATTR_DIR);
+
+ if (isdir) {
+ dirs++;
+ dirc = '/';
+ doit = 1;
+ } else {
+ dirc = ' ';
+ if (l_name[0] != 0) {
+ files++;
+ doit = 1;
+ }
+ }
+ if (doit) {
+ if (dirc == ' ') {
+ printf(" %8ld %s%c\n",
+ (long)FAT2CPU32(dentptr->size),
+ l_name,
+ dirc);
+ } else {
+ printf(" %s%c\n",
+ l_name,
+ dirc);
+ }
+ }
+ dentptr++;
+ continue;
+ }
+ debug("Rootvfatname: |%s|\n",
+ l_name);
+ } else
+#endif
+ {
+ /* Volume label or VFAT entry */
+ dentptr++;
+ continue;
+ }
+ } else if (dentptr->name[0] == 0) {
+ debug("RootDentname == NULL - %d\n", i);
+ if (dols == LS_ROOT) {
+ printf("\n%d file(s), %d dir(s)\n\n",
+ files, dirs);
+ return 0;
+ }
+ return -1;
+ }
+#ifdef CONFIG_SUPPORT_VFAT
+ else if (dols == LS_ROOT &&
+ mkcksum(dentptr->name) == prevcksum) {
+ dentptr++;
+ continue;
+ }
+#endif
+ get_name(dentptr, s_name);
+
+ if (dols == LS_ROOT) {
+ int isdir = (dentptr->attr & ATTR_DIR);
+ char dirc;
+ int doit = 0;
+
+ if (isdir) {
+ dirc = '/';
+ if (s_name[0] != 0) {
+ dirs++;
+ doit = 1;
+ }
+ } else {
+ dirc = ' ';
+ if (s_name[0] != 0) {
+ files++;
+ doit = 1;
+ }
+ }
+ if (doit) {
+ if (dirc == ' ') {
+ printf(" %8ld %s%c\n",
+ (long)FAT2CPU32(dentptr->size),
+ s_name, dirc);
+ } else {
+ printf(" %s%c\n",
+ s_name, dirc);
+ }
+ }
+ dentptr++;
+ continue;
+ }
+
+ if (strcmp(fnamecopy, s_name)
+ && strcmp(fnamecopy, l_name)) {
+ debug("RootMismatch: |%s|%s|\n", s_name,
+ l_name);
+ dentptr++;
+ continue;
+ }
+
+ if (isdir && !(dentptr->attr & ATTR_DIR))
+ return -1;
+
+ debug("RootName: %s", s_name);
+ debug(", start: 0x%x", START(dentptr));
+ debug(", size: 0x%x %s\n",
+ FAT2CPU32(dentptr->size),
+ isdir ? "(DIR)" : "");
+
+ goto rootdir_done; /* We got a match */
+ }
+ debug("END LOOP: j=%d clust_size=%d\n", j,
+ mydata->clust_size);
+
+ /*
+ * On FAT32 we must fetch the FAT entries for the next
+ * root directory clusters when a cluster has been
+ * completely processed.
+ */
+ if ((mydata->fatsize == 32) && (++j == mydata->clust_size)) {
+ int nxtsect;
+ int nxt_clust;
+
+ nxt_clust = get_fatent(mydata, root_cluster);
+
+ nxtsect = mydata->data_begin +
+ (nxt_clust * mydata->clust_size);
+
+ debug("END LOOP: sect=%d, root_clust=%d, "
+ "n_sect=%d, n_clust=%d\n",
+ cursect, root_cluster,
+ nxtsect, nxt_clust);
+
+ root_cluster = nxt_clust;
+
+ cursect = nxtsect;
+ j = 0;
+ } else {
+ cursect++;
+ }
+ }
+rootdir_done:
+
+ firsttime = 1;
+
+ while (isdir) {
+ int startsect = mydata->data_begin
+ + START(dentptr) * mydata->clust_size;
+ dir_entry dent;
+ char *nextname = NULL;
+
+ dent = *dentptr;
+ dentptr = &dent;
+
+ idx = dirdelim(subname);
+
+ if (idx >= 0) {
+ subname[idx] = '\0';
+ nextname = subname + idx + 1;
+ /* Handle multiple delimiters */
+ while (ISDIRDELIM(*nextname))
+ nextname++;
+ if (dols && *nextname == '\0')
+ firsttime = 0;
+ } else {
+ if (dols && firsttime) {
+ firsttime = 0;
+ } else {
+ isdir = 0;
+ }
+ }
+
+ if (get_dentfromdir(mydata, startsect, subname, dentptr,
+ isdir ? 0 : dols) == NULL) {
+ if (dols && !isdir)
+ return 0;
+ return -1;
+ }
+
+ if (idx >= 0) {
+ if (!(dentptr->attr & ATTR_DIR))
+ return -1;
+ subname = nextname;
+ }
+ }
+
+ ret = get_contents(mydata, dentptr, buffer, maxsize);
+ debug("Size: %d, got: %ld\n", FAT2CPU32(dentptr->size), ret);
+
+ return ret;
}
-
-int
-file_fat_detectfs(void)
+int file_fat_detectfs (void)
{
- boot_sector bs;
- volume_info volinfo;
- int fatsize;
- char vol_label[12];
+ boot_sector bs;
+ volume_info volinfo;
+ int fatsize;
+ char vol_label[12];
- if(cur_dev==NULL) {
+ if (cur_dev == NULL) {
printf("No current device\n");
return 1;
}
+
#if defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_MG_DISK) || \
defined(CONFIG_CMD_SATA) || \
@@ -961,42 +1073,58 @@
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC)
printf("Interface: ");
- switch(cur_dev->if_type) {
- case IF_TYPE_IDE : printf("IDE"); break;
- case IF_TYPE_SATA : printf("SATA"); break;
- case IF_TYPE_SCSI : printf("SCSI"); break;
- case IF_TYPE_ATAPI : printf("ATAPI"); break;
- case IF_TYPE_USB : printf("USB"); break;
- case IF_TYPE_DOC : printf("DOC"); break;
- case IF_TYPE_MMC : printf("MMC"); break;
- default : printf("Unknown");
+ switch (cur_dev->if_type) {
+ case IF_TYPE_IDE:
+ printf("IDE");
+ break;
+ case IF_TYPE_SATA:
+ printf("SATA");
+ break;
+ case IF_TYPE_SCSI:
+ printf("SCSI");
+ break;
+ case IF_TYPE_ATAPI:
+ printf("ATAPI");
+ break;
+ case IF_TYPE_USB:
+ printf("USB");
+ break;
+ case IF_TYPE_DOC:
+ printf("DOC");
+ break;
+ case IF_TYPE_MMC:
+ printf("MMC");
+ break;
+ default:
+ printf("Unknown");
}
- printf("\n Device %d: ",cur_dev->dev);
+
+ printf("\n Device %d: ", cur_dev->dev);
dev_print(cur_dev);
#endif
- if(read_bootsectandvi(&bs, &volinfo, &fatsize)) {
+
+ if (read_bootsectandvi(&bs, &volinfo, &fatsize)) {
printf("\nNo valid FAT fs found\n");
return 1;
}
- memcpy (vol_label, volinfo.volume_label, 11);
+
+ memcpy(vol_label, volinfo.volume_label, 11);
vol_label[11] = '\0';
- volinfo.fs_type[5]='\0';
- printf("Partition %d: Filesystem: %s \"%s\"\n"
- ,cur_part,volinfo.fs_type,vol_label);
+ volinfo.fs_type[5] = '\0';
+
+ printf("Partition %d: Filesystem: %s \"%s\"\n", cur_part,
+ volinfo.fs_type, vol_label);
+
return 0;
}
-
-int
-file_fat_ls(const char *dir)
+int file_fat_ls (const char *dir)
{
return do_fat_read(dir, NULL, 0, LS_YES);
}
-
-long
-file_fat_read(const char *filename, void *buffer, unsigned long maxsize)
+long file_fat_read (const char *filename, void *buffer, unsigned long maxsize)
{
- printf("reading %s\n",filename);
+ printf("reading %s\n", filename);
return do_fat_read(filename, buffer, maxsize, LS_NO);
}
diff --git a/fs/fat/file.c b/fs/fat/file.c
index e870734..59c5d37 100644
--- a/fs/fat/file.c
+++ b/fs/fat/file.c
@@ -48,12 +48,12 @@
const char *
file_getfsname(int idx)
{
- if (idx < 0 || idx >= NUM_FILESYS) return NULL;
+ if (idx < 0 || idx >= NUM_FILESYS)
+ return NULL;
return filesystems[idx].name;
}
-
static void
pathcpy(char *dest, const char *src)
{
@@ -72,15 +72,14 @@
return;
}
++dest;
- if (ISDIRDELIM(*src)) {
+
+ if (ISDIRDELIM(*src))
while (ISDIRDELIM(*src)) src++;
- } else {
+ else
src++;
- }
} while (1);
}
-
int
file_cd(const char *path)
{
@@ -141,7 +140,6 @@
return 0;
}
-
int
file_detectfs(void)
{
@@ -160,7 +158,6 @@
return current_filesystem;
}
-
int
file_ls(const char *dir)
{
@@ -181,7 +178,6 @@
return filesystems[current_filesystem].ls(arg);
}
-
long
file_read(const char *filename, void *buffer, unsigned long maxsize)
{
diff --git a/include/commproc.h b/include/commproc.h
index 9d28abc..762238e 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -828,38 +828,6 @@
#endif /* CONFIG_GENIETV */
-/*** GTH ******************************************************/
-
-#ifdef CONFIG_GTH
-#ifdef CONFIG_FEC_ENET
-#define FEC_ENET /* use FEC for EThernet */
-#endif /* CONFIG_FEC_ETHERNET */
-
-/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-
-#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
-#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
-#define PA_ENET_RCLK ((ushort)0x0400) /* PA5 */
-
-#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
-
-#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
-#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
-
-/* NOTE. This is reset for 10Mbit port only */
-#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 */
-
-#define SICR_ENET_MASK ((uint)0x000000ff)
-
-/* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
-#define SICR_ENET_CLKRT ((uint)0x00000037)
-
-#endif /* CONFIG_GTH */
-
/*** HERMES-PRO ******************************************************/
/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 49a86fd..c133033 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -91,9 +91,6 @@
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
/* DDR Setup */
#define CONFIG_FSL_DDR2
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
deleted file mode 100644
index 3920d35..0000000
--- a/include/configs/EP1C20.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*------------------------------------------------------------------------
- * BOARD/CPU
- *----------------------------------------------------------------------*/
-#define CONFIG_EP1C20 1 /* EP1C20 board */
-#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
-
-#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
-#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
-#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
-
-/*------------------------------------------------------------------------
- * CACHE -- the following will support II/s and II/f. The II/s does not
- * have dcache, so the cache instructions will behave as NOPs.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
-#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
-#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
-#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
-
-/*------------------------------------------------------------------------
- * MEMORY BASE ADDRESSES
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
-#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
-#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
-#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
-#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
-#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
-
-/*------------------------------------------------------------------------
- * MEMORY ORGANIZATION
- * -Monitor at top.
- * -The heap is placed below the monitor.
- * -Global data is placed below the heap.
- * -The stack is placed below global data (&grows down).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
-
-/*------------------------------------------------------------------------
- * FLASH (AM29LV065D)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */
-
-/*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
- * reset address, no? This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
-#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
-
-/*------------------------------------------------------------------------
- * CONSOLE
- *----------------------------------------------------------------------*/
-#define CONFIG_ALTERA_UART 1 /* Use altera uart */
-#if defined(CONFIG_ALTERA_JTAG_UART)
-#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
-#else
-#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
-#endif
-
-#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
-#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
-#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
-
-/*------------------------------------------------------------------------
- * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
- * epcs device access is enabled. The base address is the epcs
- * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
- * The register base is currently at offset 0x600 from the memory base.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
-
-/*------------------------------------------------------------------------
- * DEBUG
- *----------------------------------------------------------------------*/
-#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
-
-/*------------------------------------------------------------------------
- * TIMEBASE --
- *
- * The high res timer defaults to 1 msec. Since it includes the period
- * registers, the interrupt frequency can be reduced using TMRCNT.
- * If the default period is acceptable, TMRCNT can be left undefined.
- * TMRMS represents the desired mecs per tick (msecs per interrupt).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HZ 1000 /* Always 1000 */
-#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
-#define CONFIG_SYS_NIOS_TMRCNT \
- (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-
-/*------------------------------------------------------------------------
- * STATUS LED -- Provides a simple blinking led. For Nios2 each board
- * must implement its own led routines -- leds are, after all,
- * board-specific, no?
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
-#define CONFIG_STATUS_LED /* Enable status driver */
-
-#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
-#define STATUS_LED_STATE 1 /* Blinking */
-#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
-
-/*------------------------------------------------------------------------
- * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
- * and really doesn't need any additional clutter. So I choose the lazy
- * way out to avoid changes there -- define the base address to ensure
- * cache bypass so there's no need to monkey with inx/outx macros.
- *----------------------------------------------------------------------*/
-#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111 /* Using SMC91c111 */
-#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
-#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
-
-#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.2.21
-#define CONFIG_SERVERIP 192.168.2.16
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#undef CONFIG_CMD_BOOTD
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_ITEST
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
-
-
-/*------------------------------------------------------------------------
- * MISC
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* Provide extended help*/
-#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
-#define CONFIG_SYS_MAXARGS 16 /* Max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
-#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h
deleted file mode 100644
index bfbf8c1..0000000
--- a/include/configs/EP1S10.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*------------------------------------------------------------------------
- * BOARD/CPU
- *----------------------------------------------------------------------*/
-#define CONFIG_EP1S10 1 /* EP1S10 board */
-#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
-
-#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
-#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
-#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
-
-/*------------------------------------------------------------------------
- * CACHE -- the following will support II/s and II/f. The II/s does not
- * have dcache, so the cache instructions will behave as NOPs.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
-#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
-#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
-#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
-
-/*------------------------------------------------------------------------
- * MEMORY BASE ADDRESSES
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
-#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
-#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
-#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
-#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
-#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB */
-
-/*------------------------------------------------------------------------
- * MEMORY ORGANIZATION
- * -Monitor at top.
- * -The heap is placed below the monitor.
- * -Global data is placed below the heap.
- * -The stack is placed below global data (&grows down).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) /* 256k heap */
-
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
-
-/*------------------------------------------------------------------------
- * FLASH (AM29LV065D)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
-
-/*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom
- * of flash memory. This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
-#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/*------------------------------------------------------------------------
- * CONSOLE
- *----------------------------------------------------------------------*/
-#define CONFIG_ALTERA_UART 1 /* Use altera uart */
-#if defined(CONFIG_ALTERA_JTAG_UART)
-#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
-#else
-#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
-#endif
-
-#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
-#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
-#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
-
-/*------------------------------------------------------------------------
- * EPCS Device -- None for stratix.
- *----------------------------------------------------------------------*/
-#undef CONFIG_SYS_NIOS_EPCSBASE
-
-/*------------------------------------------------------------------------
- * DEBUG
- *----------------------------------------------------------------------*/
-#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
-
-/*------------------------------------------------------------------------
- * TIMEBASE --
- *
- * The high res timer defaults to 1 msec. Since it includes the period
- * registers, the interrupt frequency can be reduced using TMRCNT.
- * If the default period is acceptable, TMRCNT can be left undefined.
- * TMRMS represents the desired mecs per tick (msecs per interrupt).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HZ 1000 /* Always 1000 */
-#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
-#define CONFIG_SYS_NIOS_TMRCNT \
- (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-
-/*------------------------------------------------------------------------
- * STATUS LED -- Provides a simple blinking led. For Nios2 each board
- * must implement its own led routines -- since leds are board-specific.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
-#define CONFIG_STATUS_LED /* Enable status driver */
-
-#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
-#define STATUS_LED_STATE 1 /* Blinking */
-#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
-
-/*------------------------------------------------------------------------
- * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
- * and really doesn't need any additional clutter. So I choose the lazy
- * way out to avoid changes there -- define the base address to ensure
- * cache bypass so there's no need to monkey with inx/outx macros.
- *----------------------------------------------------------------------*/
-#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111 /* Using SMC91c111 */
-#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
-#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
-
-#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.2.21
-#define CONFIG_SERVERIP 192.168.2.16
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVES
-
-
-/*------------------------------------------------------------------------
- * MISC
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* Provide extended help*/
-#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
-#define CONFIG_SYS_MAXARGS 16 /* Max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
-#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h
deleted file mode 100644
index 4d905fe..0000000
--- a/include/configs/EP1S40.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*------------------------------------------------------------------------
- * BOARD/CPU
- *----------------------------------------------------------------------*/
-#define CONFIG_EP1S40 1 /* EP1S40 board */
-#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
-
-#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
-#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
-#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
-
-/*------------------------------------------------------------------------
- * CACHE -- the following will support II/s and II/f. The II/s does not
- * have dcache, so the cache instructions will behave as NOPs.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
-#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
-#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
-#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
-
-/*------------------------------------------------------------------------
- * MEMORY BASE ADDRESSES
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
-#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
-#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
-#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
-#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
-#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB */
-
-/*------------------------------------------------------------------------
- * MEMORY ORGANIZATION
- * -Monitor at top.
- * -The heap is placed below the monitor.
- * -Global data is placed below the heap.
- * -The stack is placed below global data (&grows down).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) /* 256k heap */
-
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
-
-/*------------------------------------------------------------------------
- * FLASH (AM29LV065D)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
-
-/*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom
- * of flash memory. This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
-#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/*------------------------------------------------------------------------
- * CONSOLE
- *----------------------------------------------------------------------*/
-#define CONFIG_ALTERA_UART 1 /* Use altera uart */
-#if defined(CONFIG_ALTERA_JTAG_UART)
-#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
-#else
-#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
-#endif
-
-#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
-#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
-#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
-
-/*------------------------------------------------------------------------
- * EPCS Device -- None for stratix.
- *----------------------------------------------------------------------*/
-#undef CONFIG_SYS_NIOS_EPCSBASE
-
-/*------------------------------------------------------------------------
- * DEBUG
- *----------------------------------------------------------------------*/
-#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
-
-/*------------------------------------------------------------------------
- * TIMEBASE --
- *
- * The high res timer defaults to 1 msec. Since it includes the period
- * registers, the interrupt frequency can be reduced using TMRCNT.
- * If the default period is acceptable, TMRCNT can be left undefined.
- * TMRMS represents the desired mecs per tick (msecs per interrupt).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HZ 1000 /* Always 1000 */
-#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec) */
-#define CONFIG_SYS_NIOS_TMRCNT \
- (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-
-/*------------------------------------------------------------------------
- * STATUS LED -- Provides a simple blinking led. For Nios2 each board
- * must implement its own led routines -- since leds are board-specific.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
-#define CONFIG_STATUS_LED /* Enable status driver */
-
-#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
-#define STATUS_LED_STATE 1 /* Blinking */
-#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
-
-/*------------------------------------------------------------------------
- * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
- * and really doesn't need any additional clutter. So I choose the lazy
- * way out to avoid changes there -- define the base address to ensure
- * cache bypass so there's no need to monkey with inx/outx macros.
- *----------------------------------------------------------------------*/
-#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111 /* Using SMC91c111 */
-#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
-#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
-
-#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.2.21
-#define CONFIG_SERVERIP 192.168.2.16
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVES
-
-
-/*------------------------------------------------------------------------
- * MISC
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* Provide extended help*/
-#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
-#define CONFIG_SYS_MAXARGS 16 /* Max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
-#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/GTH.h b/include/configs/GTH.h
deleted file mode 100644
index c2cf852..0000000
--- a/include/configs/GTH.h
+++ /dev/null
@@ -1,389 +0,0 @@
-/*
- * Parameters for GTH board
- * Based on FADS860T
- * by thomas.lange@corelatus.com
-
- * A collection of structures, addresses, and values associated with
- * the Motorola 860T FADS board. Copied from the MBX stuff.
- * Magnus Damm added defines for 8xxrom and extended bd_info.
- * Helmut Buchsbaum added bitvalues for BCSRx
- *
- * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
- */
-
-/*
- * ff000000 -> ff00ffff : IMAP internal in the cpu
- * e0000000 -> ennnnnnn : pcmcia
- * 98000000 -> 983nnnnn : FPGA 4MB
- * 90000000 -> 903nnnnn : FPGA 4MB
- * 80000000 -> 80nnnnnn : flash connected to CS0, final ( real ) location
- * 00000000 -> nnnnnnnn : sdram
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#include <mpc8xx_irq.h>
-
-#define CONFIG_MPC860 1
-#define CONFIG_MPC860T 1
-#define CONFIG_GTH 1
-
-#define CONFIG_MISC_INIT_R 1
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-
-#define MPC8XX_FACT 3 /* Multiply by 3 */
-#define MPC8XX_XIN 16384000 /* 16.384 MHz */
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
-
-#define CONFIG_BOOTDELAY 1 /* autoboot after 0 seconds */
-
-#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
-
-#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
-
-#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
-
-/* Only interrupt boot if space is pressed */
-/* If a long serial cable is connected but */
-/* other end is dead, garbage will be read */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT \
- "Press space to abort autoboot in %d second\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#if 0
-/* Net boot */
-/* Loads a tftp image and starts it */
-#define CONFIG_BOOTCOMMAND "bootp;bootm 100000" /* autoboot command */
-#define CONFIG_BOOTARGS "panic=1"
-#else
-/* Compact flash boot */
-#define CONFIG_BOOTARGS "panic=1 root=/dev/hda7"
-#define CONFIG_BOOTCOMMAND "disk 100000 0:5;bootm 100000"
-#endif
-
-/* Enable watchdog */
-#define CONFIG_WATCHDOG 1
-
-/* choose SCC1 ethernet (10BASET on motherboard)
- * or FEC ethernet (10/100 on daughterboard)
- */
-#if 1
-#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
-#undef CONFIG_FEC_ENET /* disable FEC ethernet */
-#define CONFIG_SYS_DISCOVER_PHY
-#else
-#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
-#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
-#define CONFIG_SYS_DISCOVER_PHY
-#endif
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IDE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-
-/* Default location to load data from net */
-#define CONFIG_SYS_LOAD_ADDR 0x100000
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_FLASH_BASE 0x80000000
-
-#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
-
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-
-#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#undef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_OFFSET 0x000E0000
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-#define CONFIG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-
-/*FIXME dont use for now */
-/*#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-/*#define CONFIG_SYS_RTCSC (RTCSC_RTF) */
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-/* PITE */
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-
-/* FIXME check values */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently. Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register. For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-
-#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* 4 MB OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
-
-#define FPGA_2_BASE 0x90000000
-#define FPGA_3_BASE 0x98000000
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 )
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#define CONFIG_ETHADDR DE:AD:BE:EF:00:01 /* Ethernet address */
-
-#ifdef CONFIG_MPC860T
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
-
-#endif /* CONFIG_MPC860T */
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS 0
-
-/* Machine type
-*/
-#define _MACH_8xx (_MACH_gth)
-
-#ifdef CONFIG_MPC860
-#define PCMCIA_SLOT_A 1
-#define CONFIG_PCMCIA_SLOT_A 1
-#endif
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
-
-#define PA_FRONT_LED ((u16)0x4) /* PA 13 */
-#define PA_FL_CONFIG ((u16)0x20) /* PA 10 */
-#define PA_FL_CE ((u16)0x1000) /* PA 3 */
-
-#define PB_ID_GND ((u32)1) /* PB 31 */
-#define PB_REV_1 ((u32)2) /* PB 30 */
-#define PB_REV_0 ((u32)4) /* PB 29 */
-#define PB_BLUE_LED ((u32)0x400) /* PB 21 */
-#define PB_EEPROM ((u32)0x800) /* PB 20 */
-#define PB_ID_3 ((u32)0x2000) /* PB 18 */
-#define PB_ID_2 ((u32)0x4000) /* PB 17 */
-#define PB_ID_1 ((u32)0x8000) /* PB 16 */
-#define PB_ID_0 ((u32)0x10000) /* PB 15 */
-
-/* NOTE. This is reset for 100Mbit port only */
-#define PC_ENET100_RESET ((ushort)0x0080) /* PC 8 */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
new file mode 100644
index 0000000..6cd5da7
--- /dev/null
+++ b/include/configs/MPC8308RDB.h
@@ -0,0 +1,560 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
+#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is SoC TSEC
+ * TSEC2 is VSC switch
+ */
+#define CONFIG_TSEC1
+#define CONFIG_VSC7385_ENET
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_SVCOD_DIV_2 |\
+ HRCWL_CSB_TO_CLKIN_4X1 |\
+ HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_RL_EXT_LEGACY |\
+ HRCWH_TSEC1M_IN_RGMII |\
+ HRCWH_TSEC2M_IN_RGMII |\
+ HRCWH_BIG_ENDIAN)
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH 0x01b7d103
+#define CONFIG_SYS_SICRL 0x00000040 /* 3.3V, no delay */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR 0xE0000000
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1 0xe3000
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
+ | DDRCDR_PZ_LOZ \
+ | DDRCDR_NZ_LOZ \
+ | DDRCDR_ODT \
+ | DDRCDR_Q_DRN)
+ /* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | 0x00010000 /* ODT_WR to CSn */ \
+ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+ /* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+ /* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (6 << TIMING_CFG1_REFREC_SHIFT) \
+ | (2 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
+ /* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (4 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+ /* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+ /* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_32_BE)
+ /* 0x43080000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0232 << SDRAM_MODE_SD_SHIFT))
+ /* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2 0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR 0x00040000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
+
+#define CONFIG_SYS_BR0_PRELIM (\
+ CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\
+ (2 << BR_PS_SHIFT) /* 16 bit port size */ |\
+ BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+/* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
+#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V ) /* valid */
+#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR )
+ /* 0xFFFF8396 */
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+
+#ifdef CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+#define CONFIG_SYS_VSC7385_BASE 0xF0000000
+#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
+#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
+/* Access window base at VSC7385 base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
+/* Access window size 128K */
+#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE 0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE 8192
+#endif
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+
+/*
+ * Board info - revision and where boot from
+ */
+#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
+
+/*
+ * Fake PCIE2 definitions: there is no PCIE2 on this board but the code
+ * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this
+ */
+#define CONFIG_SYS_PCIE2_BASE 0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
+
+#define CONFIG_PCI
+#define CONFIG_PCIE
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define TSEC1_PHY_ADDR 2
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME "eTSEC0"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE | \
+ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2 HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
+ BATU_VP)
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=${consoledev},${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addmisc=setenv bootargs ${bootargs}\0" \
+ "kernel_addr=FE080000\0" \
+ "fdt_addr=FE280000\0" \
+ "ramdisk_addr=FE290000\0" \
+ "u-boot=mpc8308rdb/u-boot.bin\0" \
+ "kernel_addr_r=1000000\0" \
+ "fdt_addr_r=C00000\0" \
+ "hostname=mpc8308rdb\0" \
+ "bootfile=mpc8308rdb/uImage\0" \
+ "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
+ "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${fdt_addr_r} ${fdtfile};" \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "bootcmd=run flash_self\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};cp.b ${fileaddr} " \
+ xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ "upd=run load update\0" \
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 9a40adc..524afa5 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -36,6 +36,7 @@
#define CONFIG_MPC8313ERDB 1
#define CONFIG_PCI
+#define CONFIG_FSL_ELBC 1
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 6972fe8..f1b110b 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -197,6 +197,7 @@
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00040000
+#define CONFIG_FSL_ELBC 1
/*
* FLASH on the Local Bus
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index b30d0e3..9092755 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -223,6 +223,7 @@
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
#define CONFIG_SYS_LBC_LBCR 0x00000000
+#define CONFIG_FSL_ELBC 1
/*
* FLASH on the Local Bus
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 1654f46..79dadc4 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -246,6 +246,7 @@
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
#define CONFIG_SYS_LBC_LBCR 0x00000000
+#define CONFIG_FSL_ELBC 1
/*
* FLASH on the Local Bus
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index da4313a..890a6c9 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2009,2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include "../board/freescale/common/ics307_clk.h"
+
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT 1
#endif
@@ -63,6 +65,7 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#define CONFIG_SYS_HAS_SERDES /* has SERDES */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
@@ -70,15 +73,9 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-extern unsigned long get_board_ddr_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
- from ICS307 instead of switches */
/*
* These can be toggled for performance analysis, otherwise use default.
@@ -129,11 +126,6 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
-#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000)
-
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR2
@@ -669,6 +661,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 95ea275..7daf934 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -294,6 +294,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index e945da2..ae4fba8 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -403,6 +403,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 799d946..96fd024 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -79,11 +79,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
-
/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
@@ -420,6 +415,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 3eb0049..23594a7 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -80,10 +80,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-
/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
@@ -462,6 +458,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 07a8e61..5011e5a 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -401,6 +401,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 4a4a9ed..98677e5 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -416,6 +416,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 6973538..bc6c5c7 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -75,9 +75,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-
/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
@@ -421,6 +418,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 0c43b2b..92c2b49 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -103,9 +103,6 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-
/* DDR Setup */
#define CONFIG_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE
@@ -539,6 +536,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 78b7369..51e5d06 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include "../board/freescale/common/ics307_clk.h"
+
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT
#endif
@@ -53,15 +55,9 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-extern unsigned long get_board_ddr_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
- from ICS307 instead of switches */
/*
* These can be toggled for performance analysis, otherwise use default.
@@ -93,10 +89,6 @@
#endif
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR2
@@ -574,6 +566,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 8382e3c..4d9606e 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -82,10 +82,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000)
/* DDR Setup */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 94e4d24..0d1f779 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2006 Freescale Semiconductor.
+ * Copyright 2006, 2010 Freescale Semiconductor.
*
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
@@ -58,8 +58,8 @@
#ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
-#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */
+#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif
@@ -122,9 +122,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
#endif
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-
/*
* DDR Setup
*/
@@ -328,43 +325,43 @@
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL
#else
-#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT
#endif
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \
| CONFIG_SYS_PHYS_ADDR_HIGH)
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
#ifdef CONFIG_PHYS_64BIT
/*
- * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT.
+ * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
* This will increase the amount of PCI address space available for
* for mapping RAM.
*/
-#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
#else
-#define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \
- + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
+ + CONFIG_SYS_PCIE1_MEM_SIZE)
#endif
-#define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \
- + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \
- + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
- + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
- + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
+#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
+ + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
+ + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
+ + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
+ + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
#if defined(CONFIG_PCI)
@@ -393,10 +390,10 @@
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT
+#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
+/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
/* video */
#define CONFIG_VIDEO
@@ -409,7 +406,7 @@
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
/*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -425,8 +422,6 @@
#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
#endif
-#define CONFIG_MPC86XX_PCI2
-
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
@@ -497,17 +492,17 @@
#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
/* if CONFIG_PCI:
- * BAT2 PCI1 and PCI1 MEM
+ * BAT2 PCIE1 and PCIE1 MEM
* if CONFIG_RIO
* BAT2 Rapidio Memory
*/
#ifdef CONFIG_PCI
-#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \
| BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
| BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \
| BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
#else /* CONFIG_RIO */
@@ -556,14 +551,14 @@
#endif
/*
- * BAT4 PCI1_IO and PCI2_IO
+ * BAT4 PCIE1_IO and PCIE2_IO
*/
-#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \
| BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
| BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \
| BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
new file mode 100644
index 0000000..f9d12f5
--- /dev/null
+++ b/include/configs/P1022DS.h
@@ -0,0 +1,467 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/freescale/common/ics307_clk.h"
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE /* BOOKE */
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
+#define CONFIG_P1022
+#define CONFIG_P1022DS
+#define CONFIG_MP /* support multiple processors */
+
+#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+#define CONFIG_SYS_HAS_SERDES /* has SERDES */
+
+#define CONFIG_PHYS_64BIT
+#define CONFIG_ENABLE_36BIT_PHYS
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_SYS_MEMTEST_START 0x00000000
+#define CONFIG_SYS_MEMTEST_END 0x7fffffff
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_FSL_DDR3
+
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
+ * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
+ * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
+ * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
+ * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
+ * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
+
+#define CONFIG_FLASH_BR_PRELIM \
+ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
+
+#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+
+#define CONFIG_SYS_BR1_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
+
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+ {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_FSL_NGPIXIS
+#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
+#define PIXIS_BASE_PHYS 0xfffdf0000ull
+
+#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
+
+#define PIXIS_LBMAP_SWITCH 7
+#define PIXIS_LBMAP_MASK 0xE0
+#define PIXIS_LBMAP_ALTBANK 0x20
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
+
+/* Video */
+/* #define CONFIG_VIDEO */
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM 1
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_TSEC_ENET
+#ifdef CONFIG_TSEC_ENET
+
+#define CONFIG_TSECV2
+#define CONFIG_NET_MULTI
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+
+#define TSEC1_PHY_ADDR 1
+#define TSEC2_PHY_ADDR 2
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_HOSTNAME p1022ds
+#define CONFIG_ROOTPATH /opt/nfsroot
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#define CONFIG_BOOTARGS
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "perf_mode=stable\0" \
+ "memctl_intlv_ctl=2\0" \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=uramdisk\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=p1022ds.dtb\0" \
+ "bdev=sda3\0" \
+ "diuregs=md e002c000 1d\0" \
+ "dium=mw e002c01c\0" \
+ "diuerr=md e002c014 1\0" \
+ "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
+ "monitor=0-DVI\0"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index b891730..fca3cdd 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -74,6 +74,7 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
+#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
@@ -84,6 +85,8 @@
#define CONFIG_MP
#endif
+#define CONFIG_HWCONFIG
+
/*
* These can be toggled for performance analysis, otherwise use default.
*/
@@ -126,9 +129,6 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-
/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
@@ -475,6 +475,7 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_NET
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 66be725..bf2acbf 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include "../board/freescale/common/ics307_clk.h"
+
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT
#endif
@@ -54,17 +56,9 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#ifndef __ASSEMBLY__
-extern unsigned long calculate_board_sys_clk(unsigned long dummy);
-extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
-/* extern unsigned long get_board_sys_clk(unsigned long dummy); */
-/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */
-#endif
-#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
- from ICS307 instead of switches */
/*
* These can be toggled for performance analysis, otherwise use default.
@@ -96,10 +90,6 @@
#endif
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR3 1
@@ -553,6 +543,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index 4b9bcca..7426bca 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -326,6 +326,7 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 1db20bc..0bd28fc 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -325,6 +325,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 1989e5a..5d424dd 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -380,6 +380,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index eb8657b..70b7489 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -37,6 +37,7 @@
#define CONFIG_MPC8313 1
#define CONFIG_PCI
+#define CONFIG_FSL_ELBC 1
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index d44fb07..d8f2602 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -137,10 +137,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
-#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
-
/*
* DDR Setup
*/
@@ -593,6 +589,7 @@
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DTT
#define CONFIG_CMD_MII
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index c63fd42..8770a8d 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -97,8 +97,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
/*
* Diagnostics
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index 1a56c60..83aeffd 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -81,7 +81,6 @@
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
/*
* Diagnostics
@@ -338,6 +337,7 @@
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
/*
* Miscellaneous configurable options
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 7fd3668..fc4a986 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -47,6 +47,7 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_FSL_ELBC 1
/*
* Multicore config
@@ -98,8 +99,6 @@
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
/*
* Diagnostics
@@ -396,6 +395,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
/*
* Miscellaneous configurable options
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 513d005..10af21b 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -28,7 +28,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 1e821d9..6eec1c9 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -63,6 +63,26 @@
#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
+#define CONFIG_BFIN_MAC_PINS \
+ { \
+ P_MII0_ETxD0, \
+ P_MII0_ETxD1, \
+ P_MII0_ETxD2, \
+ P_MII0_ETxD3, \
+ P_MII0_ETxEN, \
+ P_MII0_TxCLK, \
+ P_MII0_PHYINT, \
+ P_MII0_COL, \
+ P_MII0_ERxD0, \
+ P_MII0_ERxD1, \
+ P_MII0_ERxD2, \
+ P_MII0_ERxD3, \
+ P_MII0_ERxDV, \
+ P_MII0_ERxCLK, \
+ P_MII0_CRS, \
+ P_MII0_MDC, \
+ P_MII0_MDIO, \
+ 0 }
#define CONFIG_NETCONSOLE 1
#define CONFIG_NET_MULTI 1
#endif
@@ -117,8 +137,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 711fa27..82396d0 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -134,8 +134,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
@@ -160,23 +158,19 @@
/* define to enable run status via led */
/* #define CONFIG_STATUS_LED */
#ifdef CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
#define CONFIG_BOARD_SPECIFIC_LED
-#ifndef __ASSEMBLY__
-typedef unsigned int led_id_t;
-void __led_init(led_id_t mask, int state);
-void __led_set(led_id_t mask, int state);
-void __led_toggle(led_id_t mask);
-#endif
/* use LED0 to indicate booting/alive */
#define STATUS_LED_BOOT 0
-#define STATUS_LED_BIT 1
+#define STATUS_LED_BIT GPIO_PF8
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
/* use LED1 to indicate crash */
#define STATUS_LED_CRASH 1
-#define STATUS_LED_BIT1 2
+#define STATUS_LED_BIT1 GPIO_PG11
#define STATUS_LED_STATE1 STATUS_LED_ON
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* #define STATUS_LED_BIT2 GPIO_PG12 */
#endif
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
new file mode 100644
index 0000000..eb3a2b7
--- /dev/null
+++ b/include/configs/bf527-ad7160-eval.h
@@ -0,0 +1,148 @@
+/*
+ * U-boot - Configuration file for BF527 AD7160-EVAL board
+ */
+
+#ifndef __CONFIG_BF527_AD7160_EVAL_H__
+#define __CONFIG_BF527_AD7160_EVAL_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf527-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 24000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 25
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_SDRRC_VAL 0x03F6
+#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
+
+
+/*
+ * NAND Settings
+ * (can't be used same time as ethernet)
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+# define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC_BOOTROM_ECC
+#endif
+#ifdef CONFIG_BFIN_NFC
+#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
+#define CONFIG_DRIVER_NAND_BFIN
+#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#endif
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 259
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x10000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SIZE 0x20000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+
+
+/*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_SPI_MMC
+#define CONFIG_SPI_MMC_DEFAULT_CS (7 + GPIO_PH3)
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE 0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 7800c32..07e4ce8 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -138,8 +138,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index c80ddca..37a7059 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -136,8 +136,6 @@
} while (0)
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
#endif
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 80c4884..02c8bc3 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -180,8 +180,6 @@
} while (0)
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
#endif
@@ -230,23 +228,19 @@
/* define to enable run status via led */
/* #define CONFIG_STATUS_LED */
#ifdef CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
#define CONFIG_BOARD_SPECIFIC_LED
-#ifndef __ASSEMBLY__
-typedef unsigned int led_id_t;
-void __led_init(led_id_t mask, int state);
-void __led_set(led_id_t mask, int state);
-void __led_toggle(led_id_t mask);
-#endif
-/* use LED1 to indicate booting/alive */
+/* use LED0 to indicate booting/alive */
#define STATUS_LED_BOOT 0
-#define STATUS_LED_BIT 1
+#define STATUS_LED_BIT GPIO_PF2
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
-/* use LED2 to indicate crash */
+/* use LED1 to indicate crash */
#define STATUS_LED_CRASH 1
-#define STATUS_LED_BIT1 2
+#define STATUS_LED_BIT1 GPIO_PF3
#define STATUS_LED_STATE1 STATUS_LED_ON
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* #define STATUS_LED_BIT2 GPIO_PF4 */
#endif
/* define to enable splash screen support */
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index cf40d06..39bbb41 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -132,7 +132,6 @@
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY PF12
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
@@ -141,13 +140,7 @@
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
- do { \
- bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
- bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
- bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
- } while (0)
+#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
/*
@@ -155,8 +148,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 92ceb38..96704d7 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -137,8 +137,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
@@ -157,7 +155,6 @@
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY PF3
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
@@ -166,13 +163,7 @@
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTFIO() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
- do { \
- bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \
- bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \
- bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \
- } while (0)
+#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
/*
@@ -268,8 +259,6 @@
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
-
/* Define if want to do post memory test */
#undef CONFIG_POST
#ifdef CONFIG_POST
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 59e0565..1c14b6b 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -134,8 +134,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index f9c9711..60cca0c 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -140,8 +140,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index 0be170c..0c0204f 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -131,7 +131,6 @@
#define CONFIG_ENV_SECT_SIZE (1056 * 8)
#define CONFIG_ENV_OFFSET ((16 + 256) * 1056)
#define CONFIG_ENV_SIZE (8 * 1056)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
/*
@@ -145,7 +144,6 @@
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
-#define BFIN_NAND_READY PF10
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
@@ -154,12 +152,7 @@
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
- do { \
- bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \
- bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \
- } while (0)
+#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
/*
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 1e3fdef..036bfe4 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -151,8 +151,6 @@
} while (0)
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
#endif
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 1896cf5..901a32f 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -83,6 +83,7 @@
# define CONFIG_CMD_CPLBINFO
# define CONFIG_CMD_ELF
# define CONFIG_ELF_SIMPLE_LOAD
+# define CONFIG_CMD_GPIO
# define CONFIG_CMD_KGDB
# define CONFIG_CMD_REGINFO
# define CONFIG_CMD_STRINGS
@@ -247,12 +248,26 @@
# define CONFIG_SYS_AUTOLOAD "no"
# endif
# endif
+# define CONFIG_IP_DEFRAG
# define CONFIG_NET_RETRY_COUNT 20
#endif
/*
+ * I2C Settings
+ */
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+# ifndef CONFIG_SYS_I2C_SPEED
+# define CONFIG_SYS_I2C_SPEED 50000
+# endif
+# ifndef CONFIG_SYS_I2C_SLAVE
+# define CONFIG_SYS_I2C_SLAVE 0
+# endif
+#endif
+
+/*
* Misc Settings
*/
+#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
#define CONFIG_LZMA
#endif
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index ac9b3c5..6fe7639 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -77,6 +77,13 @@
#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
+/*
+ * BCSR bits as defined in the Canyonlands board user manual.
+ */
+#define BCSR_USBCTRL_OTG_RST 0x32
+#define BCSR_USBCTRL_HOST_RST 0x01
+#define BCSR_SELECT_PCIE 0x10
+
#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
/* base address of inbound PCIe window */
@@ -417,6 +424,7 @@
#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
#endif
/*
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index ad1dd12..e0c6d53 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -117,8 +117,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 8d0bc12..742df9c 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -119,8 +119,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index bbea3ab..9def99f 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -120,8 +120,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index 93c4c8d..63b9399 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -107,8 +107,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
new file mode 100644
index 0000000..277ff67
--- /dev/null
+++ b/include/configs/colibri_pxa270.h
@@ -0,0 +1,278 @@
+/*
+ * Toradex Colibri PXA270 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_VPAC270 1 /* Toradex Colibri PXA270 board */
+
+#undef BOARD_LATE_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_SIZE 0x4000
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_ENV_OVERWRITE /* override default environment */
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \
+ "bootm 0xa0000000; " \
+ "fi; " \
+ "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
+ "bootm 0xa0000000; " \
+ "fi; " \
+ "bootm 0x80000;"
+#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FLASH
+
+/*
+ * Networking Configuration
+ * chip on the Voipac PXA270 board
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x08000000
+#define DM9000_IO (CONFIG_DM9000_BASE)
+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
+#define CONFIG_NET_RETRY_COUNT 10
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x290 /* 520 MHz */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR (0xa1000000)
+
+/*
+ * NOR FLASH
+ */
+#ifdef CONFIG_CMD_FLASH
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+
+#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_PROTECTION 1
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+#else /* No flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE 0x000000
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPSR0_VAL 0x00000000
+#define CONFIG_SYS_GPSR1_VAL 0x00020000
+#define CONFIG_SYS_GPSR2_VAL 0x0002C000
+#define CONFIG_SYS_GPSR3_VAL 0x00000000
+
+#define CONFIG_SYS_GPCR0_VAL 0x00000000
+#define CONFIG_SYS_GPCR1_VAL 0x00000000
+#define CONFIG_SYS_GPCR2_VAL 0x00000000
+#define CONFIG_SYS_GPCR3_VAL 0x00000000
+
+#define CONFIG_SYS_GPDR0_VAL 0x08000000
+#define CONFIG_SYS_GPDR1_VAL 0x0002A981
+#define CONFIG_SYS_GPDR2_VAL 0x0202FC00
+#define CONFIG_SYS_GPDR3_VAL 0x00000000
+
+#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
+#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010
+#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A
+#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008
+#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
+#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000
+#define CONFIG_SYS_GAFR3_L_VAL 0x54000300
+#define CONFIG_SYS_GAFR3_U_VAL 0x00024001
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x00500240
+#define CONFIG_SYS_CCCR 0x02000290
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x000095f2
+#define CONFIG_SYS_MSC1_VAL 0x00007ff4
+#define CONFIG_SYS_MSC2_VAL 0x00000000
+#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9
+#define CONFIG_SYS_MDREFR_VAL 0x2013e01e
+#define CONFIG_SYS_MDMRS_VAL 0x00320032
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000001
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001c787
+#define CONFIG_SYS_MCATT1_VAL 0x0001c787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430f
+#define CONFIG_SYS_MCIO1_VAL 0x0001430f
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "tdex270"
+#define CONFIG_USB_STORAGE
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index b4fda76..049298c 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -131,15 +131,12 @@
(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024)
#define CONFIG_NET_MULTI 1
-#ifdef CONFIG_NET_MULTI
#define CONFIG_DRIVER_AT91EMAC 1
#define CONFIG_SYS_RX_ETH_BUFFER 8
-#else
-#define CONFIG_DRIVER_ETHER 1
-#endif
+#define CONFIG_RMII 1
+#define CONFIG_MII 1
+#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1
#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_AT91C_USE_RMII 1
-#define CONFIG_PHY_ADDRESS (1 << 5)
#define CONFIG_KS8721_PHY 1
#define CONFIG_SYS_FLASH_CFI 1
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 1076de6..2815771 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -32,7 +32,7 @@
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index c3d95a0..055931c 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -131,12 +131,23 @@
* Commands configuration - using default command set for now
*/
#include <config_cmd_default.h>
+
/*
- * Disabling some default commands for staggered bring-up
+ * Network
*/
-#undef CONFIG_CMD_BOOTD /* no bootd since no net */
-#undef CONFIG_CMD_NET /* no net since no eth */
-#undef CONFIG_CMD_NFS /* no NFS since no net */
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
+#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
+#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
+#define CONFIG_PHY_BASE_ADR 0x8
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#endif
/*
* Environment variables configurations
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index 2fbc6ad..eb3fa57 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -172,9 +172,9 @@
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_CMD_MII
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
+#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
index 2eef5ef..2c0a263 100644
--- a/include/configs/ibf-dsp561.h
+++ b/include/configs/ibf-dsp561.h
@@ -58,6 +58,18 @@
/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AX88180 1
+#define AX88180_BASE 0x2c000000
+#define CONFIG_HOSTNAME ibf-dsp561
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+
+
+/*
* Flash Settings
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
@@ -126,8 +138,6 @@
} while (0)
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
#endif
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index 425a745..c024d78 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -116,7 +116,6 @@
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY PF10
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
@@ -125,14 +124,7 @@
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
- do { \
- bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \
- bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \
- bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \
- bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \
- } while (0)
+#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
/*
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index fb8ccae..76e9a76 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -202,6 +202,7 @@
*/
#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECCTEST
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_PCI
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index a928c2c..6519c90 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -127,9 +127,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */
diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h
index 96b4d1c..9ef03a6 100644
--- a/include/configs/mv88f6281gtw_ge.h
+++ b/include/configs/mv88f6281gtw_ge.h
@@ -172,9 +172,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif /* CONFIG_CMD_NET */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index e018b21..ae5a791 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -31,7 +31,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index af7c65a..c4aa220 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -36,7 +36,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index b441831..3a3b389 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -23,7 +23,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 9eba003..3308ace 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -26,7 +26,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index d4482d3..5439aa3 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -36,7 +36,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 1e88dc0..f612e0f 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -32,7 +32,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index be9daf4..aaf929e 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -33,7 +33,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
new file mode 100644
index 0000000..b1e40a3
--- /dev/null
+++ b/include/configs/omap4_panda.h
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * Configuration settings for the TI OMAP4 Panda board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP44XX 1 /* which is a 44XX */
+#define CONFIG_OMAP4430 1 /* which is in a 4430 */
+#define CONFIG_PANDA 1 /* working with Panda */
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap4.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF 1
+
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 256k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
+ /* initial data */
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/* I2C */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* MMC */
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_SYS_MMC_SET_DEV 1
+#define CONFIG_DOS_PARTITION 1
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * Enabling relocation of u-boot by default
+ * Relocation can be skipped if u-boot is copied to the TEXT_BASE
+ */
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Environment setup
+ */
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "mmcdev=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "Panda # "
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE GPT1_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
new file mode 100644
index 0000000..8121554
--- /dev/null
+++ b/include/configs/omap4_sdp4430.h
@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * Configuration settings for the TI SDP4430 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP44XX 1 /* which is a 44XX */
+#define CONFIG_OMAP4430 1 /* which is in a 4430 */
+#define CONFIG_4430SDP 1 /* working with SDP */
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap4.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF 1
+
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 256k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
+ /* initial data */
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/* I2C */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* MMC */
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_SYS_MMC_SET_DEV 1
+#define CONFIG_DOS_PARTITION 1
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * Enabling relocation of u-boot by default
+ * Relocation can be skipped if u-boot is copied to the TEXT_BASE
+ */
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Environment setup
+ */
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "mmcdev=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE GPT1_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h
index d2f4502..52fa73d 100644
--- a/include/configs/openrd_base.h
+++ b/include/configs/openrd_base.h
@@ -183,9 +183,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0x8
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h
index 3d8e25c..5857301 100644
--- a/include/configs/rd6281a.h
+++ b/include/configs/rd6281a.h
@@ -171,8 +171,8 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
+#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
+#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index b2bf96a..c8ea8fd 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -28,7 +28,7 @@
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index aeac2de..c8b8d0d 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -109,10 +109,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-
/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
@@ -487,6 +483,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index dab4f80..53d06ed 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -382,6 +382,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 315eebe..618513a 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -56,8 +56,8 @@
#define CONFIG_SYS_SCRATCH_VA 0xe8000000
#define CONFIG_PCI 1 /* Enable PCIE */
-#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
-#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
@@ -108,9 +108,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-
/*
* DDR Setup
*/
@@ -307,23 +304,23 @@
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BUS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
-#define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS
-#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
+#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
+#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
-#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
-#define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BUS 0xe3000000
-#define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS
-#define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS
-#define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
+#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
+#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI)
@@ -409,10 +406,10 @@
* 0xa000_0000 512M PCI-Express 2 Memory
* Changed it for operating from 0xd0000000
*/
-#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
+#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
/*
@@ -452,10 +449,10 @@
* 0xe300_0000 16M PCI-Express 2 I/0
* Note that this is at 0xe0000000
*/
-#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
+#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
/*
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index e9edc44..c5de86e 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -174,9 +174,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 09bce6d..76a47c4 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -32,7 +32,7 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */
#define CONFIG_S5PC100 1 /* which is in a S5PC100 */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 89f7cc4..ad70109 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -355,6 +355,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 86b231c..891d2bf 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -321,6 +321,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_SAVEENV
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 2783f9e..363f7b4 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -353,6 +353,7 @@
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h
index 0ecc5b1..b38886b 100644
--- a/include/configs/t3corp.h
+++ b/include/configs/t3corp.h
@@ -74,8 +74,8 @@
#define CONFIG_SYS_FLASH_SIZE (64 << 20)
#define CONFIG_SYS_FPGA1_BASE 0xe0000000
-#define CONFIG_SYS_FPGA2_BASE 0xe0100000
-#define CONFIG_SYS_FPGA3_BASE 0xe0200000
+#define CONFIG_SYS_FPGA2_BASE 0xe2000000
+#define CONFIG_SYS_FPGA3_BASE 0xe4000000
#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
@@ -84,14 +84,12 @@
(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
+#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */
#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */
-#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */
-
/*
* Initial RAM & stack pointer (placed in OCM)
*/
@@ -121,6 +119,7 @@
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
@@ -144,10 +143,13 @@
/*
* DDR2 SDRAM
*/
+#define CONFIG_SYS_MBYTES_SDRAM 256
+#define CONFIG_DDR_ECC
#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
+#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */
/* DDR1/2 SDRAM Device Control Register Data Values */
/* Memory Queue */
@@ -162,9 +164,6 @@
#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
-#define CONFIG_DDR_ECC
-#define CONFIG_SYS_MBYTES_SDRAM 256
-
#define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK
/* DDR1/2 SDRAM Device Control Register Data Values */
@@ -360,6 +359,7 @@
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_ECCTEST
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
@@ -417,7 +417,7 @@
#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
EBC_BXAP_TWT_ENCODE(5) | \
EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(4) | \
+ EBC_BXAP_OEN_ENCODE(3) | \
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
@@ -426,7 +426,7 @@
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
- EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BS_32MB | \
EBC_BXCR_BU_RW | \
EBC_BXCR_BW_32BIT)
@@ -434,7 +434,7 @@
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
EBC_BXAP_TWT_ENCODE(5) | \
EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(4) | \
+ EBC_BXAP_OEN_ENCODE(3) | \
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
@@ -443,7 +443,7 @@
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
- EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BS_16MB | \
EBC_BXCR_BU_RW | \
EBC_BXCR_BW_32BIT)
@@ -451,7 +451,7 @@
#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \
EBC_BXAP_TWT_ENCODE(5) | \
EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(4) | \
+ EBC_BXAP_OEN_ENCODE(3) | \
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
@@ -460,7 +460,7 @@
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
- EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BS_16MB | \
EBC_BXCR_BU_RW | \
EBC_BXCR_BW_32BIT)
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index 9c04d8a..52055e8 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -106,8 +106,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 409a042..24ce8f8 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -120,8 +120,6 @@
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
new file mode 100644
index 0000000..1589913
--- /dev/null
+++ b/include/configs/ve8313.h
@@ -0,0 +1,511 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * ve8313 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1
+#define CONFIG_MPC83xx 1
+#define CONFIG_MPC831x 1
+#define CONFIG_MPC8313 1
+#define CONFIG_VE8313 1
+
+#define CONFIG_PCI 1
+
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+/*
+ * On-board devices
+ *
+ */
+#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
+
+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
+
+#define CONFIG_SYS_IMMR 0xE0000000
+
+#define CONFIG_SYS_MEMTEST_START 0x00001000
+#define CONFIG_SYS_MEMTEST_END 0x07000000
+
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
+
+/*
+ * Device configurations
+ */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
+ | CSCONFIG_AP \
+ | 0x00040000 /* TODO */ \
+ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+ /* 0x80840102 */
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+ | ( 3 << TIMING_CFG0_RRT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_WWT_SHIFT ) \
+ | ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+ | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+ /* 0x0e720802 */
+#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
+ | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+ | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
+ | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+ | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
+ | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
+ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+ /* 0x26256222 */
+#define CONFIG_SYS_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+ | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
+ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+ | ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+ | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+ | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+ /* 0x029028c7 */
+#define CONFIG_SYS_DDR_INTERVAL ( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+ | ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+ /* 0x03202000 */
+#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_32_BE )
+ /* 0x43080000 */
+#define CONFIG_SYS_SDRAM_CFG2 0x00401000
+#define CONFIG_SYS_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
+ | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+ /* 0x44400232 */
+#define CONFIG_SYS_DDR_MODE_2 0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+ /*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
+ | DDRCDR_PZ_NOMZ \
+ | DDRCDR_NZ_NOMZ \
+ | DDRCDR_M_ODR )
+ /* 0x73000002 */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000
+#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
+
+#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ (2 << BR_PS_SHIFT) | /* 16 bit */ \
+ BR_V) /* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV4 \
+ | OR_GPCM_SCY_5 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EAD)
+ /* 0xfe000c55 */
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
+
+#define CONFIG_SYS_LBC_LBCR 0x00040000
+
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
+
+/*
+ * NAND settings
+ */
+#define CONFIG_SYS_NAND_BASE 0x61000000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+
+#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
+ | BR_PS_8 \
+ | BR_DECC_CHK_GEN \
+ | BR_MS_FCM \
+ | BR_V ) /* valid */
+ /* 0x61000c21 */
+#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \
+ | OR_FCM_BCTLD \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_2 \
+ | OR_FCM_RST \
+ | OR_FCM_TRLX)
+ /* 0xffff90ac */
+
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+/* CS2 NvRAM */
+#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
+ | BR_PS_8 \
+ | BR_V)
+ /* 0x60000801 */
+#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_3 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
+ /* 0xfffe0937 */
+/* local bus read write buffer mapping SRAM@0x64000000 */
+#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
+ | BR_PS_16 \
+ | BR_V)
+ /* 0x62001001 */
+
+#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
+ /* 0xfe0009f7 */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+#endif
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_TSEC1
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC1"
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define TSEC1_PHY_ADDR 0x01
+#define TSEC1_FLAGS 0
+#define TSEC1_PHYIDX 0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC1"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE 0x4000
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
+#define CONFIG_SYS_HZ 1000 /* 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* 0x64050000 */
+#define CONFIG_SYS_HRCW_LOW (\
+ 0x20000000 /* reserved, must be set */ |\
+ HRCWL_DDRCM |\
+ HRCWL_CSB_TO_CLKIN_4X1 | \
+ HRCWL_CORE_TO_CSB_2_5X1)
+
+/* 0xa0600004 */
+#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
+ HRCWH_PCI_ARBITER_ENABLE | \
+ HRCWH_CORE_ENABLE | \
+ HRCWH_FROM_0X00000100 | \
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT | \
+ HRCWH_TSEC1M_IN_MII | \
+ HRCWH_BIG_ENDIAN | \
+ HRCWH_LALE_EARLY)
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH (0x01000000 | \
+ SICRH_ETSEC2_B | \
+ SICRH_ETSEC2_C | \
+ SICRH_ETSEC2_D | \
+ SICRH_ETSEC2_E | \
+ SICRH_ETSEC2_F | \
+ SICRH_ETSEC2_G | \
+ SICRH_TSOBI1 | \
+ SICRH_TSOBI2)
+ /* 0x010fff03 */
+#define CONFIG_SYS_SICRL (SICRL_LBC | \
+ SICRL_SPI_A | \
+ SICRL_SPI_B | \
+ SICRL_SPI_C | \
+ SICRL_SPI_D | \
+ SICRL_ETSEC2_A)
+ /* 0x33fc0003) */
+
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
+
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+
+#if defined(CONFIG_PCI)
+/* PCI @ 0x80000000 */
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT1L (0)
+#define CONFIG_SYS_IBAT1U (0)
+#define CONFIG_SYS_IBAT2L (0)
+#define CONFIG_SYS_IBAT2U (0)
+#endif
+
+/* PCI2 not supported on 8313 */
+#define CONFIG_SYS_IBAT3L (0)
+#define CONFIG_SYS_IBAT3U (0)
+#define CONFIG_SYS_IBAT4L (0)
+#define CONFIG_SYS_IBAT4U (0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \
+ BATU_VP)
+
+/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* FPGA, SRAM, NAND @ 0x60000000 */
+#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CONFIG_NETDEV eth0
+
+#define CONFIG_HOSTNAME ve8313
+#define CONFIG_UBOOTPATH ve8313/u-boot.bin
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#define CONFIG_BAUDRATE 115200
+
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0" \
+ "u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "u-boot_addr_r=100000\0" \
+ "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
+ "update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
+ " ${filesize};" \
+ "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
new file mode 100644
index 0000000..6d02995
--- /dev/null
+++ b/include/configs/vpac270.h
@@ -0,0 +1,323 @@
+/*
+ * Voipac PXA270 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
+
+#undef BOARD_LATE_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_SIZE 0x4000
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_ENV_OVERWRITE /* override default environment */
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
+ "bootm 0xa4000000; " \
+ "fi; " \
+ "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
+ "bootm 0xa4000000; " \
+ "fi; " \
+ "bootm 0x40000;"
+#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_USB
+#undef CONFIG_LCD
+#define CONFIG_CMD_IDE
+
+#ifdef CONFIG_ONENAND_U_BOOT
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_ONENAND
+#else
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_ONENAND
+#endif
+
+/*
+ * Networking Configuration
+ * chip on the Voipac PXA270 board
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
+#define DM9000_IO (CONFIG_DM9000_BASE)
+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
+#define CONFIG_NET_RETRY_COUNT 10
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR (0x5c000000)
+
+/*
+ * NOR FLASH
+ */
+#if defined(CONFIG_CMD_FLASH) /* NOR */
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+
+#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_PROTECTION 1
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ONENAND_BASE 0x00000000
+#define CONFIG_ENV_IS_IN_ONENAND 1
+
+#else /* No flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE 0x000000
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+/*
+ * IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define CONFIG_LBA48
+#undef CONFIG_IDE_LED
+#undef CONFIG_IDE_RESET
+
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+
+#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
+
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
+#define CONFIG_SYS_ATA_REG_OFFSET 0x120
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
+
+#define CONFIG_SYS_ATA_STRIDE 2
+#endif
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPSR0_VAL 0x01308800
+#define CONFIG_SYS_GPSR1_VAL 0x00cf0000
+#define CONFIG_SYS_GPSR2_VAL 0x922ac000
+#define CONFIG_SYS_GPSR3_VAL 0x0161e800
+
+#define CONFIG_SYS_GPCR0_VAL 0x00010000
+#define CONFIG_SYS_GPCR1_VAL 0x0
+#define CONFIG_SYS_GPCR2_VAL 0x0
+#define CONFIG_SYS_GPCR3_VAL 0x0
+
+#define CONFIG_SYS_GPDR0_VAL 0xcbb18800
+#define CONFIG_SYS_GPDR1_VAL 0xfccfa981
+#define CONFIG_SYS_GPDR2_VAL 0x922affff
+#define CONFIG_SYS_GPDR3_VAL 0x0161e904
+
+#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510
+#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa
+#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401
+#define CONFIG_SYS_GAFR3_L_VAL 0x54010310
+#define CONFIG_SYS_GAFR3_U_VAL 0x00025401
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x00500240
+#define CONFIG_SYS_CCCR 0x02000290
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa
+#define CONFIG_SYS_MSC1_VAL 0x02ccf974
+#define CONFIG_SYS_MSC2_VAL 0x00000000
+#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3
+#define CONFIG_SYS_MDREFR_VAL 0x201fe01e
+#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+#define CONFIG_SYS_MEM_BUF_IMP 0x0f
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000001
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001c787
+#define CONFIG_SYS_MCATT1_VAL 0x0001c787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430f
+#define CONFIG_SYS_MCIO1_VAL 0x0001430f
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_VOIPAC_LCD
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270"
+#define CONFIG_USB_STORAGE
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
new file mode 100644
index 0000000..a5a873b
--- /dev/null
+++ b/include/configs/zipitz2.h
@@ -0,0 +1,259 @@
+/*
+ * Aeronix Zipit Z2 configuration file
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
+
+#undef BOARD_LATE_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_SIZE 0x20000
+
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_STACKSIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE 512
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
+ "source 0xa0000000; " \
+ "else " \
+ "bootm 0x60000; " \
+ "fi; "
+#define CONFIG_BOOTARGS \
+ "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ * STUART - the lower serial port on Colibri board
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_STUART 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SPI
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * SPI and LCD
+ */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_SOFT_SPI
+#define CONFIG_LCD
+#define CONFIG_LMS283GF05
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
+#undef SPI_INIT
+
+#define SPI_DELAY udelay(10)
+#define SPI_SDA(val) zipitz2_spi_sda(val)
+#define SPI_SCL(val) zipitz2_spi_scl(val)
+#define SPI_READ zipitz2_spi_read()
+#ifndef __ASSEMBLY__
+void zipitz2_spi_sda(int);
+void zipitz2_spi_scl(int);
+unsigned char zipitz2_spi_read(void);
+#endif
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+
+/*
+ * NOR FLASH
+ */
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
+#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
+#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
+#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
+#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
+#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
+#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
+#define CONFIG_SYS_GPCR0_VAL 0x00000000
+#define CONFIG_SYS_GPCR1_VAL 0x00000020
+#define CONFIG_SYS_GPCR2_VAL 0x00000000
+#define CONFIG_SYS_GPCR3_VAL 0x00000000
+#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
+#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
+#define CONFIG_SYS_GPDR2_VAL 0x8fe1ffff
+#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
+#define CONFIG_SYS_GPSR0_VAL 0x06080400
+#define CONFIG_SYS_GPSR1_VAL 0x007f0000
+#define CONFIG_SYS_GPSR2_VAL 0x032a0000
+#define CONFIG_SYS_GPSR3_VAL 0x00000180
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x00511220
+#define CONFIG_SYS_CCCR 0x00000190
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
+#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
+#define CONFIG_SYS_MSC2_VAL 0x0000b884
+#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
+#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
+#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000001
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001c787
+#define CONFIG_SYS_MCATT1_VAL 0x0001c787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430f
+#define CONFIG_SYS_MCIO1_VAL 0x0001430f
+
+#endif /* __CONFIG_H */
diff --git a/include/environment.h b/include/environment.h
index 203f731..fbccf6a 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -74,15 +74,24 @@
#endif /* CONFIG_ENV_IS_IN_FLASH */
#if defined(CONFIG_ENV_IS_IN_NAND)
-# ifndef CONFIG_ENV_OFFSET
-# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND"
-# endif
+# if defined(CONFIG_ENV_OFFSET_OOB)
+# ifdef CONFIG_ENV_OFFSET_REDUND
+# error "CONFIG_ENV_OFFSET_REDUND is not supported when CONFIG_ENV_OFFSET_OOB"
+# error "is set"
+# endif
+extern unsigned long nand_env_oob_offset;
+# define CONFIG_ENV_OFFSET nand_env_oob_offset
+# else
+# ifndef CONFIG_ENV_OFFSET
+# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND"
+# endif
+# ifdef CONFIG_ENV_OFFSET_REDUND
+# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+# endif /* CONFIG_ENV_OFFSET_OOB */
# ifndef CONFIG_ENV_SIZE
# error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND"
# endif
-# ifdef CONFIG_ENV_OFFSET_REDUND
-# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-# endif
#endif /* CONFIG_ENV_IS_IN_NAND */
#if defined(CONFIG_ENV_IS_IN_MG_DISK)
diff --git a/include/fat.h b/include/fat.h
index c8b9493..de48afd 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -33,7 +33,7 @@
#define SECTOR_SIZE FS_BLOCK_SIZE
-#define FS_BLOCK_SIZE 512
+#define FS_BLOCK_SIZE 512
#if FS_BLOCK_SIZE != SECTOR_SIZE
#error FS_BLOCK_SIZE != SECTOR_SIZE - This code needs to be fixed!
@@ -57,37 +57,31 @@
#define SIGNLEN 8
/* File attributes */
-#define ATTR_RO 1
-#define ATTR_HIDDEN 2
-#define ATTR_SYS 4
-#define ATTR_VOLUME 8
-#define ATTR_DIR 16
-#define ATTR_ARCH 32
+#define ATTR_RO 1
+#define ATTR_HIDDEN 2
+#define ATTR_SYS 4
+#define ATTR_VOLUME 8
+#define ATTR_DIR 16
+#define ATTR_ARCH 32
-#define ATTR_VFAT (ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME)
+#define ATTR_VFAT (ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME)
#define DELETED_FLAG ((char)0xe5) /* Marks deleted files when in name[0] */
#define aRING 0x05 /* Used as special character in name[0] */
-/* Indicates that the entry is the last long entry in a set of long
+/*
+ * Indicates that the entry is the last long entry in a set of long
* dir entries
*/
#define LAST_LONG_ENTRY_MASK 0x40
/* Flags telling whether we should read a file or list a directory */
-#define LS_NO 0
-#define LS_YES 1
-#define LS_DIR 1
-#define LS_ROOT 2
+#define LS_NO 0
+#define LS_YES 1
+#define LS_DIR 1
+#define LS_ROOT 2
-#ifdef DEBUG
-#define FAT_DPRINT(args...) printf(args)
-#else
-#define FAT_DPRINT(args...)
-#endif
-#define FAT_ERROR(arg) printf(arg)
-
-#define ISDIRDELIM(c) ((c) == '/' || (c) == '\\')
+#define ISDIRDELIM(c) ((c) == '/' || (c) == '\\')
#define FSTYPE_NONE (-1)
@@ -166,17 +160,18 @@
} dir_entry;
typedef struct dir_slot {
- __u8 id; /* Sequence number for slot */
- __u8 name0_4[10]; /* First 5 characters in name */
- __u8 attr; /* Attribute byte */
- __u8 reserved; /* Unused */
- __u8 alias_checksum;/* Checksum for 8.3 alias */
- __u8 name5_10[12]; /* 6 more characters in name */
- __u16 start; /* Unused */
- __u8 name11_12[4]; /* Last 2 characters in name */
+ __u8 id; /* Sequence number for slot */
+ __u8 name0_4[10]; /* First 5 characters in name */
+ __u8 attr; /* Attribute byte */
+ __u8 reserved; /* Unused */
+ __u8 alias_checksum;/* Checksum for 8.3 alias */
+ __u8 name5_10[12]; /* 6 more characters in name */
+ __u16 start; /* Unused */
+ __u8 name11_12[4]; /* Last 2 characters in name */
} dir_slot;
-/* Private filesystem parameters
+/*
+ * Private filesystem parameters
*
* Note: FAT buffer has to be 32 bit aligned
* (see FAT32 accesses)
@@ -198,10 +193,10 @@
unsigned long maxsize);
struct filesystem {
- file_detectfs_func *detect;
- file_ls_func *ls;
- file_read_func *read;
- const char name[12];
+ file_detectfs_func *detect;
+ file_ls_func *ls;
+ file_read_func *read;
+ const char name[12];
};
/* FAT tables */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 9a453af..54af9fe 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -59,7 +59,7 @@
static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
#endif /* CONFIG_HAS_FSL_DR_USB */
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
+#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
void fdt_fixup_crypto_node(void *blob, int sec_rev);
#else
static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
@@ -83,6 +83,9 @@
void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
void fdt_del_node_and_alias(void *blob, const char *alias);
+u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr);
+int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
+ phys_addr_t compat_off);
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */
diff --git a/include/lcd.h b/include/lcd.h
index 1f85daa..cd9d49d 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -87,7 +87,7 @@
u_char vl_wbf; /* Wait between frames */
} vidinfo_t;
-#elif defined CONFIG_PXA250
+#elif defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
/*
* PXA LCD DMA descriptor
*/
diff --git a/include/mmc.h b/include/mmc.h
index 8973bc7..fcb237e 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -271,6 +271,7 @@
int mmc_init(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
struct mmc *find_mmc_device(int dev_num);
+int mmc_set_dev(int dev_num);
void print_mmc_devices(char separator);
int board_mmc_getcd(u8 *cd, struct mmc *mmc);
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 5214911..ba6cdf1 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -65,6 +65,7 @@
#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
+#define SPR_8308 0x8100
#define SPR_831X_FAMILY 0x80B
#define SPR_8311 0x80B2
#define SPR_8313 0x80B0
@@ -115,8 +116,9 @@
#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
#define SPCR_TSEC2EP_SHIFT (31-31)
-#elif defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
-/* SPCR bits - MPC831x and MPC837x specific */
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC837x)
+/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
#define SPCR_TSECDP 0x00003000 /* TSEC data priority */
#define SPCR_TSECDP_SHIFT (31-19)
#define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */
@@ -473,7 +475,7 @@
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_2 0x00000000
@@ -541,7 +543,8 @@
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC837x)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
@@ -592,7 +595,8 @@
/* RSR - Reset Status Register
*/
-#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC837x)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
#else
@@ -734,8 +738,8 @@
#define SCCR_USBDRCM_2 0x00200000
#define SCCR_USBDRCM_3 0x00300000
-#elif defined(CONFIG_MPC8315)
-/* SCCR bits - MPC8315 specific */
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+/* SCCR bits - MPC8315/MPC8308 specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
@@ -750,6 +754,13 @@
#define SCCR_TSEC2CM_2 0x20000000
#define SCCR_TSEC2CM_3 0x30000000
+#define SCCR_SDHCCM 0x0c000000
+#define SCCR_SDHCCM_SHIFT 26
+#define SCCR_SDHCCM_0 0x00000000
+#define SCCR_SDHCCM_1 0x04000000
+#define SCCR_SDHCCM_2 0x08000000
+#define SCCR_SDHCCM_3 0x0c000000
+
#define SCCR_USBDRCM 0x00c00000
#define SCCR_USBDRCM_SHIFT 22
#define SCCR_USBDRCM_0 0x00000000
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index a4d4d65..2495b99 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -6,8 +6,6 @@
#ifndef __MPC85xx_H__
#define __MPC85xx_H__
-#include <asm/fsl_lbc.h>
-
/* define for common ppc_asm.tmpl */
#define EXC_OFF_SYS_RESET 0x100 /* System reset */
#define _START_OFFSET 0
diff --git a/include/nand.h b/include/nand.h
index 2a81597..8bdf419 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -130,3 +130,12 @@
__attribute__((noreturn)) void nand_boot(void);
#endif
+
+#ifdef CONFIG_ENV_OFFSET_OOB
+#define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored
+ as block number*/
+#define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is
+ stored as byte number */
+#define ENV_OFFSET_SIZE 8
+int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
+#endif
diff --git a/include/netdev.h b/include/netdev.h
index 882642a..94eedfe 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -43,12 +43,14 @@
/* Driver initialization prototypes */
int altera_tse_initialize(u8 dev_num, int mac_base,
int sgdma_rx_base, int sgdma_tx_base);
+int ax88180_initialize(bd_t *bis);
int au1x00_enet_initialize(bd_t*);
int at91emac_register(bd_t *bis, unsigned long iobase);
int bfin_EMAC_initialize(bd_t *bis);
int cs8900_initialize(u8 dev_num, int base_addr);
int dc21x4x_initialize(bd_t *bis);
int davinci_emac_initialize(void);
+int designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
@@ -61,7 +63,6 @@
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
-int kirkwood_egiga_initialize(bd_t *bis);
int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
int mcdmafec_initialize(bd_t *bis);
@@ -70,6 +71,7 @@
int mpc5xxx_fec_initialize(bd_t *bis);
int mpc8220_fec_initialize(bd_t *bis);
int mpc82xx_scc_enet_initialize(bd_t *bis);
+int mvgbe_initialize(bd_t *bis);
int natsemi_initialize(bd_t *bis);
int npe_initialize(bd_t *bis);
int ns8382x_initialize(bd_t *bis);
diff --git a/include/status_led.h b/include/status_led.h
index 9dbf01f..f213595 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -346,9 +346,6 @@
#elif defined(CONFIG_NIOS2)
/* XXX empty just to avoid the error */
/************************************************************************/
-#elif defined(CONFIG_BLACKFIN)
-/* XXX empty just to avoid the error */
-/************************************************************************/
#elif defined(CONFIG_V38B)
# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
diff --git a/include/video_fb.h b/include/video_fb.h
index 9825f0c..f649c54 100644
--- a/include/video_fb.h
+++ b/include/video_fb.h
@@ -1,4 +1,4 @@
- /*
+/*
* (C) Copyright 1997-2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
diff --git a/nand_spl/board/freescale/mpc8536ds/nand_boot.c b/nand_spl/board/freescale/mpc8536ds/nand_boot.c
index af29dc2..5a0a0c7 100644
--- a/nand_spl/board/freescale/mpc8536ds/nand_boot.c
+++ b/nand_spl/board/freescale/mpc8536ds/nand_boot.c
@@ -34,12 +34,11 @@
int px_spd;
u32 plat_ratio, bus_clk, sys_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- ccsr_lbc_t *lbc = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
/* for FPGA */
- out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
- out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
+ set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+ set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
#else
#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
#endif
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index ff47d55..9547d44 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -32,7 +32,7 @@
static void nand_wait(void)
{
- fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+ fsl_lbc_t *regs = LBC_BASE_ADDR;
for (;;) {
uint32_t status = in_be32(®s->ltesr);
@@ -49,7 +49,7 @@
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
{
- fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+ fsl_lbc_t *regs = LBC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
int large = in_be32(®s->bank[0].or) & OR_FCM_PGS;
int block_shift = large ? 17 : 14;
diff --git a/net/eth.c b/net/eth.c
index 83d559c..de6d5c6 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -234,6 +234,9 @@
puts (" [PRIME]");
}
+ if (strchr(dev->name, ' '))
+ puts("\nWarning: eth device name has a space!\n");
+
eth_getenv_enetaddr_by_index(eth_number, env_enetaddr);
if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
diff --git a/onenand_ipl/board/vpac270/Makefile b/onenand_ipl/board/vpac270/Makefile
new file mode 100644
index 0000000..22d0410
--- /dev/null
+++ b/onenand_ipl/board/vpac270/Makefile
@@ -0,0 +1,83 @@
+IPL =onenand_ipl
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
+LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
+CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
+OBJCFLAGS += --gap-fill=0x00
+
+SOBJS := lowlevel_init.o
+SOBJS += start.o
+COBJS := vpac270.o
+COBJS += onenand_read.o
+COBJS += onenand_boot.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
+
+onenandobj := $(OBJTREE)/onenand_ipl/
+
+ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin
+
+all: $(obj).depend $(ALL)
+
+$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x5c040400 -O binary $< $@
+
+$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(onenandobj)onenand-ipl: $(OBJS) $(onenandobj)u-boot.lds
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $@.map -o $@
+
+$(onenandobj)u-boot.lds: $(LDSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+# create symbolic links from common files
+
+# from cpu directory
+$(obj)start.S:
+ @rm -f $@
+ ln -s $(SRCTREE)/$(CPUDIR)/start.S $@
+
+# from onenand_ipl directory
+$(obj)onenand_ipl.h:
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@
+
+$(obj)onenand_boot.c: $(obj)onenand_ipl.h
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@
+
+$(obj)onenand_read.c: $(obj)onenand_ipl.h
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)vpac270.c:
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/vpac270.c $@
+
+$(obj)lowlevel_init.S:
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/lowlevel_init.S $@
+endif
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)$.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/onenand_ipl/board/vpac270/config.mk b/onenand_ipl/board/vpac270/config.mk
new file mode 100644
index 0000000..f071dea
--- /dev/null
+++ b/onenand_ipl/board/vpac270/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x5c03fc00
diff --git a/board/altera/ep1s40/ep1s40.c b/onenand_ipl/board/vpac270/lowlevel_init.S
similarity index 64%
copy from board/altera/ep1s40/ep1s40.c
copy to onenand_ipl/board/vpac270/lowlevel_init.S
index 6395de7..e79d8dd 100644
--- a/board/altera/ep1s40/ep1s40.c
+++ b/onenand_ipl/board/vpac270/lowlevel_init.S
@@ -1,6 +1,8 @@
/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
+ * Voipac PXA270 Lowlevel Hardware Initialization
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -21,27 +23,12 @@
* MA 02111-1307 USA
*/
-#include <common.h>
-#include <netdev.h>
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/macro.h>
-int checkboard (void)
-{
- puts ("BOARD : Altera EP-1S40\n");
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
+.globl lowlevel_init
+lowlevel_init:
+ pxa_clock_setup
+ mov pc, lr
diff --git a/arch/arm/cpu/arm_cortexa8/u-boot.lds b/onenand_ipl/board/vpac270/u-boot.onenand.lds
similarity index 72%
copy from arch/arm/cpu/arm_cortexa8/u-boot.lds
copy to onenand_ipl/board/vpac270/u-boot.onenand.lds
index 820e3a1..b2e7557 100644
--- a/arch/arm/cpu/arm_cortexa8/u-boot.lds
+++ b/onenand_ipl/board/vpac270/u-boot.onenand.lds
@@ -1,9 +1,6 @@
/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -15,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -32,10 +29,10 @@
. = 0x00000000;
. = ALIGN(4);
- .text :
+ .text :
{
- arch/arm/cpu/arm_cortexa8/start.o (.text)
- *(.text)
+ start.o (.text)
+ *(.text)
}
. = ALIGN(4);
@@ -47,12 +44,8 @@
. = ALIGN(4);
.got : { *(.got) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
. = ALIGN(4);
__bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss) . = ALIGN(4); }
_end = .;
}
diff --git a/board/altera/ep1s40/ep1s40.c b/onenand_ipl/board/vpac270/vpac270.c
similarity index 67%
rename from board/altera/ep1s40/ep1s40.c
rename to onenand_ipl/board/vpac270/vpac270.c
index 6395de7..a1eb331 100644
--- a/board/altera/ep1s40/ep1s40.c
+++ b/onenand_ipl/board/vpac270/vpac270.c
@@ -1,6 +1,13 @@
/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -22,26 +29,14 @@
*/
#include <common.h>
-#include <netdev.h>
+#include <asm/arch/hardware.h>
-int checkboard (void)
+int board_init (void)
{
- puts ("BOARD : Altera EP-1S40\n");
return 0;
}
-phys_size_t initdram (int board_type)
+int s_init(int skip)
{
- return (0);
+ return 0;
}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/tools/updater/cmd_flash.c b/tools/updater/cmd_flash.c
index 5ce45ba..957a7c4 100644
--- a/tools/updater/cmd_flash.c
+++ b/tools/updater/cmd_flash.c
@@ -121,10 +121,8 @@
int n, sect_first, sect_last;
int rcode = 0;
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 2)
+ return cmd_usage(cmdtp);
if (strcmp(argv[1], "all") == 0) {
for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
@@ -146,10 +144,8 @@
return rcode;
}
- if (argc != 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 3)
+ return cmd_usage(cmdtp);
if (strcmp(argv[1], "bank") == 0) {
bank = simple_strtoul(argv[2], NULL, 16);
@@ -167,10 +163,8 @@
addr_first = simple_strtoul(argv[1], NULL, 16);
addr_last = simple_strtoul(argv[2], NULL, 16);
- if (addr_first >= addr_last) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (addr_first >= addr_last)
+ return cmd_usage(cmdtp);
printf ("Erase Flash from 0x%08lx to 0x%08lx ", addr_first, addr_last);
rcode = flash_sect_erase(addr_first, addr_last);
@@ -243,19 +237,15 @@
int i, p, n, sect_first, sect_last;
int rcode = 0;
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc < 3)
+ return cmd_usage(cmdtp);
if (strcmp(argv[1], "off") == 0)
p = 0;
else if (strcmp(argv[1], "on") == 0)
p = 1;
- else {
- cmd_usage(cmdtp);
- return 1;
- }
+ else
+ return cmd_usage(cmdtp);
if (strcmp(argv[2], "all") == 0) {
for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
@@ -309,10 +299,8 @@
return rcode;
}
- if (argc != 4) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (argc != 4)
+ return cmd_usage(cmdtp);
if (strcmp(argv[2], "bank") == 0) {
bank = simple_strtoul(argv[3], NULL, 16);
@@ -340,7 +328,8 @@
}
#if defined(CONFIG_SYS_FLASH_PROTECTION)
- if (!rcode) puts (" done\n");
+ if (!rcode)
+ puts(" done\n");
#endif /* CONFIG_SYS_FLASH_PROTECTION */
return rcode;
@@ -349,12 +338,10 @@
addr_first = simple_strtoul(argv[2], NULL, 16);
addr_last = simple_strtoul(argv[3], NULL, 16);
- if (addr_first >= addr_last) {
- cmd_usage(cmdtp);
- return 1;
- }
- rcode = flash_sect_protect (p, addr_first, addr_last);
- return rcode;
+ if (addr_first >= addr_last)
+ return cmd_usage(cmdtp);
+
+ return flash_sect_protect (p, addr_first, addr_last);
}
int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
{
