powerpc/boot: Change the macro of Boot from SRIO and PCIE master module Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
diff --git a/README b/README index 2dd0bc0..983d55e 100644 --- a/README +++ b/README
@@ -3975,6 +3975,9 @@ - CONFIG_SRIO2: Board has SRIO 2 port available +- CONFIG_SRIO_PCIE_BOOT_MASTER + Board can support master function for Boot from SRIO and PCIE + - CONFIG_SYS_SRIOn_MEM_VIRT: Virtual Address of SRIO port 'n' memory region
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4067f05..0990141 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -564,7 +564,7 @@ #ifdef CONFIG_SYS_SRIO srio_init(); -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER char *s = getenv("bootmaster"); if (s) { if (!strcmp(s, "SRIO1")) {
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 6e6f7dc..90d1065 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -24,7 +24,7 @@ #include <asm/fsl_srio.h> #include <asm/errno.h> -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER #define SRIO_PORT_ACCEPT_ALL 0x10000001 #define SRIO_IB_ATMU_AR 0x80f55000 #define SRIO_OB_ATMU_AR_MAINT 0x80077000 @@ -299,7 +299,7 @@ } } -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER void srio_boot_master(int port) { struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index f1b3c35..86035d9 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -337,7 +337,6 @@ #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -371,7 +370,6 @@ #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -413,7 +411,6 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -449,7 +446,6 @@ #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 77ac1f7..621c899 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c
@@ -211,7 +211,7 @@ return 1; } -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER static void fsl_pcie_boot_master(pit_t *pi) { /* configure inbound window for slave's u-boot image */ @@ -388,7 +388,7 @@ /* see if we are a PCIe or PCI controller */ pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER /* boot from PCIE --master */ char *s = getenv("bootmaster"); char pcie[6]; @@ -624,7 +624,7 @@ if (fsl_is_pci_agent(hose)) { fsl_pci_config_unlock(hose); hose->last_busno = hose->first_busno; -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER } else { /* boot from PCIE --master releases slave's core 0 */ char *s = getenv("bootmaster");
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 9cd3a7c..4ea8717 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h
@@ -77,6 +77,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_DPAA_RMAN /* RMan */ #define CONFIG_FSL_LAW /* Use common FSL init code */
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index ce8f9b0..dd2b9c3 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h
@@ -40,7 +40,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ - +#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #include "corenet_ds.h"
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 53979dd..48acee4 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h
@@ -36,7 +36,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ - +#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ #include "corenet_ds.h"
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 778230d..d1e27c4 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h
@@ -41,7 +41,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ - +#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #include "corenet_ds.h"