Merge with http://www.jdl.com/software/u-boot-86xx.git
diff --git a/CHANGELOG b/CHANGELOG index da785f4..727a7b6 100644 --- a/CHANGELOG +++ b/CHANGELOG
@@ -1,7 +1,21 @@ ====================================================================== -Changes since U-Boot 1.1.4: +Changes for U-Boot 1.1.5: ====================================================================== +* Cleanup compile warnings. Prepare for release 1.1.5 + +* Fix compile problem in include/configs/ep82xxm.h + (must have never been tested before!) + +* MCC200: Fix uninitialized variable problem in LCD driver + +* Add board/cpu specific NAND chip select function to 440 NDFC + Based on idea and implementation from Jeff Mann + Patch by Stefan Roese, 20 Oct 2006 + +* Make 4xx bootup message shorter on 440EPx/GRx platforms + Patch by Stefan Roese, 18 Oct 2006 + * Add (preliminary) support for V38B board * PPC405EP: Add support for board configuration of CPC0_PCI register
diff --git a/Makefile b/Makefile index d8ca1f6..94d518f 100644 --- a/Makefile +++ b/Makefile
@@ -23,7 +23,7 @@ VERSION = 1 PATCHLEVEL = 1 -SUBLEVEL = 4 +SUBLEVEL = 5 EXTRAVERSION = U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) VERSION_FILE = $(obj)include/version_autogenerated.h
diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c index 35e644d..fe3f78e 100644 --- a/board/ep82xxm/ep82xxm.c +++ b/board/ep82xxm/ep82xxm.c
@@ -227,8 +227,6 @@ #ifndef CFG_RAMBOOT volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; - uchar c = 0xFF; uint psdmr = CFG_PSDMR; int i;
diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 7042a9c..4fb3b65 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c
@@ -178,6 +178,14 @@ printf("Device %d: %s", dev, nand_info[dev].name); puts("... is now current device\n"); nand_curr_device = dev; + +#ifdef CFG_NAND_SELECT_DEVICE + /* + * Select the chip in the board/cpu specific driver + */ + board_nand_select_device(nand_info[dev].priv, dev); +#endif + return 0; }
diff --git a/common/lcd.c b/common/lcd.c index df31ca9..eaed2ab 100644 --- a/common/lcd.c +++ b/common/lcd.c
@@ -578,7 +578,9 @@ */ int lcd_display_bitmap(ulong bmp_image, int x, int y) { +#if !defined(CONFIG_MCC200) ushort *cmap; +#endif ushort i, j; uchar *fb; bmp_image_t *bmp=(bmp_image_t *)bmp_image; @@ -624,13 +626,13 @@ debug ("Display-bmp: %d x %d with %d colors\n", (int)width, (int)height, (int)colors); +#if !defined(CONFIG_MCC200) + /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ if (bpix==8) { #if defined(CONFIG_PXA250) cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); -#elif defined(CONFIG_MCC200) - /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ #else # error "Don't know location of color map" #endif @@ -654,6 +656,7 @@ #endif } } +#endif /* * BMP format for Monochrome assumes that the state of a
diff --git a/common/miiphybb.c b/common/miiphybb.c index adb697c..537c15d 100644 --- a/common/miiphybb.c +++ b/common/miiphybb.c
@@ -41,7 +41,7 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg) { int j; /* counter */ -#ifndef CONFIG_EP8248 +#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif @@ -126,7 +126,7 @@ { short rdreg; /* register working value */ int j; /* counter */ -#ifndef CONFIG_EP8248 +#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif @@ -193,7 +193,7 @@ unsigned char reg, unsigned short value) { int j; /* counter */ -#ifndef CONFIG_EP8248 +#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif
diff --git a/common/usb_storage.c b/common/usb_storage.c index 69ecf18..06ea99b 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c
@@ -932,8 +932,8 @@ const unsigned char max_vendor_len = 40; const unsigned char max_product_len = 20; if (descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a) { - strncpy(vendor, "SMSC", max_vendor_len); - strncpy(product, "Flash Media Cntrller", max_product_len); + strncpy ((char *)vendor, "SMSC", max_vendor_len); + strncpy ((char *)product, "Flash Media Cntrller", max_product_len); } } #endif /* CONFIG_USB_BIN_FIXUP */
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 94478db..f4a7208 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c
@@ -192,6 +192,7 @@ char buf[32]; #if !defined(CONFIG_IOP480) + char addstr[64] = ""; sys_info_t sys_info; puts ("CPU: "); @@ -308,19 +309,23 @@ #endif /* CONFIG_440 */ case PVR_440EPX1_RA: - puts("EPx Rev. A - Security/Kasumi support"); + puts("EPx Rev. A"); + strcpy(addstr, "Security/Kasumi support"); break; case PVR_440EPX2_RA: - puts("EPx Rev. A - No Security/Kasumi support"); + puts("EPx Rev. A"); + strcpy(addstr, "No Security/Kasumi support"); break; case PVR_440GRX1_RA: - puts("GRx Rev. A - Security/Kasumi support"); + puts("GRx Rev. A"); + strcpy(addstr, "Security/Kasumi support"); break; case PVR_440GRX2_RA: - puts("GRx Rev. A - No Security/Kasumi support"); + puts("GRx Rev. A"); + strcpy(addstr, "No Security/Kasumi support"); break; case PVR_440SP_RA: @@ -349,13 +354,16 @@ sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, FREQ_EBC / 1000000); + if (addstr[0] != 0) + printf(" %s\n", addstr); + #if defined(I2C_BOOTROM) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); #if defined(SDR0_PINSTP_SHIFT) printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A'); printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); -#endif -#endif +#endif /* SDR0_PINSTP_SHIFT */ +#endif /* I2C_BOOTROM */ #if defined(CONFIG_PCI) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index 183ab5e..2c44111 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c
@@ -66,7 +66,7 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; if (hwctl & 0x1) out8(base + NDFC_CMD, byte); @@ -79,7 +79,7 @@ static u_char ndfc_read_byte(struct mtd_info *mtdinfo) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; return (in8(base + NDFC_DATA)); } @@ -87,7 +87,7 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY)) ; @@ -111,30 +111,30 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(;len > 0; len -= 4) + for (;len > 0; len -= 4) *p++ = in32(base + NDFC_DATA); } static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(; len > 0; len -= 4) + for (; len > 0; len -= 4) out32(base + NDFC_DATA, *p++); } static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(; len > 0; len -= 4) + for (; len > 0; len -= 4) if (*p++ != in32(base + NDFC_DATA)) return -1; @@ -142,8 +142,20 @@ } #endif /* #ifndef CONFIG_NAND_SPL */ +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; + + /* Set NandFlash Core Configuration Register */ + /* 1col x 2 rows */ + out32(base + NDFC_CCR, 0x00000000 | (chip << 24)); +} + void board_nand_init(struct nand_chip *nand) { + int chip = (ulong)nand->IO_ADDR_W & 0x00000003; + ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; + nand->eccmode = NAND_ECC_SOFT; nand->hwcontrol = ndfc_hwcontrol; @@ -166,10 +178,11 @@ mtebc(pb0ap, CFG_EBC_PB0AP); #endif - /* Set NandFlash Core Configuration Register */ - /* Chip select 3, 1col x 2 rows */ - out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24)); - out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222); + /* + * Select required NAND chip in NDFC + */ + board_nand_select_device(nand, chip); + out32(base + NDFC_BCFG0 + (chip << 2), 0x80002222); } #endif
diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c index e1781fc..3899045 100644 --- a/drivers/nand/nand.c +++ b/drivers/nand/nand.c
@@ -66,8 +66,15 @@ size += nand_info[i].size; if (nand_curr_device == -1) nand_curr_device = i; -} + } printf("%lu MiB\n", size / (1024 * 1024)); + +#ifdef CFG_NAND_SELECT_DEVICE + /* + * Select the chip in the board/cpu specific driver + */ + board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device); +#endif } #endif
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 5d7bed6..372b10c 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h
@@ -28,7 +28,7 @@ #define CONFIG_MPC8260 #define CPU_ID_STR "MPC8270" -#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board /* +#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ /* 256MB SDRAM / 64MB FLASH */ #undef DEBUG
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index f67fd91..3a76315 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h
@@ -134,13 +134,6 @@ #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif -/*----------------------------------------------------------------------- - * NAND FLASH - *----------------------------------------------------------------------*/ -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE CFG_NAND_ADDR - /* * IPL (Initial Program Loader, integrated inside CPU) * Will load first 4k from NAND (SPL) into cache and execute it from there. @@ -406,6 +399,14 @@ #define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) /*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + +/*----------------------------------------------------------------------- * Cache Configuration *----------------------------------------------------------------------*/ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
diff --git a/include/nand.h b/include/nand.h index 5c7311f..23493f7 100644 --- a/include/nand.h +++ b/include/nand.h
@@ -117,4 +117,8 @@ int nand_unlock( nand_info_t *meminfo, ulong start, ulong length ); int nand_get_lock_status(nand_info_t *meminfo, ulong offset); +#ifdef CFG_NAND_SELECT_DEVICE +void board_nand_select_device(struct nand_chip *nand, int chip); +#endif + #endif