PPC: Use r2 instead of r29 as global data pointer
R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc
will refuse to use load/store multiple insns; instead, it issues a
list of simple load/store instructions upon function entry and exit,
resulting in bigger code size, which in turn makes the build for a
few boards fail.
Use r2 instead.
Signed-off-by: Wolfgang Denk <wd@denx.de>
diff --git a/examples/stubs.c b/examples/stubs.c
index 571c4d5..9b3cadd 100644
--- a/examples/stubs.c
+++ b/examples/stubs.c
@@ -25,14 +25,14 @@
: : "i"(XF_ ## x * sizeof(void *)) : "eax", "ecx");
#elif defined(CONFIG_PPC)
/*
- * r29 holds the pointer to the global_data, r11 is a call-clobbered
+ * r2 holds the pointer to the global_data, r11 is a call-clobbered
* register
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
-" lwz %%r11, %0(%%r29)\n" \
+" lwz %%r11, %0(%%r2)\n" \
" lwz %%r11, %1(%%r11)\n" \
" mtctr %%r11\n" \
" bctr\n" \
diff --git a/examples/test_burst_lib.S b/examples/test_burst_lib.S
index 5bb4981..aef4e32 100644
--- a/examples/test_burst_lib.S
+++ b/examples/test_burst_lib.S
@@ -70,7 +70,7 @@
* we can load the instruction and data TLB registers with the
* same values.
*/
- lwz r9,20(r29) /* gd->ram_size */
+ lwz r9,20(r2) /* gd->ram_size */
addis r9,r9,-0x80
mr r8, r9 /* Higher 8 Meg in SDRAM */
diff --git a/examples/x86-testapp.c b/examples/x86-testapp.c
index a1ab319..e8603d9 100644
--- a/examples/x86-testapp.c
+++ b/examples/x86-testapp.c
@@ -30,11 +30,11 @@
asm volatile ( \
" .globl mon_" #x "\n" \
"mon_" #x ":\n" \
-" lwz %%r11, %0(%%r29)\n" \
+" lwz %%r11, %0(%%r2)\n" \
" lwz %%r11, %1(%%r11)\n" \
" mtctr %%r11\n" \
" bctr\n" \
- : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "r11", "r29");
+ : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "r11", "r2");
#elif defined(__arm__)
#define EXPORT_FUNC(x) \
asm volatile ( \
@@ -67,7 +67,7 @@
#if defined(__i386__)
xxx_t *pq;
#elif defined(__powerpc__)
- register volatile xxx_t *pq asm("r29");
+ register volatile xxx_t *pq asm("r2");
#elif defined(__arm__)
register volatile xxx_t *pq asm("r8");
#elif defined(__mips__)
