| /* |
| * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. |
| * |
| * This software is available to you under a choice of one of two |
| * licenses. You may choose to be licensed under the terms of the GNU |
| * General Public License (GPL) Version 2, available from the file |
| * COPYING in the main directory of this source tree, or the |
| * OpenIB.org BSD license below: |
| * |
| * Redistribution and use in source and binary forms, with or |
| * without modification, are permitted provided that the following |
| * conditions are met: |
| * |
| * - Redistributions of source code must retain the above |
| * copyright notice, this list of conditions and the following |
| * disclaimer. |
| * |
| * - Redistributions in binary form must reproduce the above |
| * copyright notice, this list of conditions and the following |
| * disclaimer in the documentation and/or other materials |
| * provided with the distribution. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| * SOFTWARE. |
| */ |
| |
| #ifndef _DR_STE_V1_ |
| #define _DR_STE_V1_ |
| |
| #include "dr_ste.h" |
| |
| #define DR_STE_DECAP_L3_ACTION_NUM 8 |
| #define DR_STE_L2_HDR_MAX_SZ 20 |
| #define DR_STE_CALC_DFNR_TYPE(lookup_type, inner) \ |
| ((inner) ? DR_STE_V1_LU_TYPE_##lookup_type##_I : \ |
| DR_STE_V1_LU_TYPE_##lookup_type##_O) |
| |
| enum dr_ste_v1_entry_format { |
| DR_STE_V1_TYPE_BWC_BYTE = 0x0, |
| DR_STE_V1_TYPE_BWC_DW = 0x1, |
| DR_STE_V1_TYPE_MATCH_AND_MASK_BYTE = 0x2, |
| DR_STE_V1_TYPE_MATCH_AND_MASK_DW = 0x3, |
| DR_STE_V1_TYPE_MATCH = 0x4, |
| }; |
| |
| /* |
| * Lookup type is built from 2B: [ Definer mode 1B ][ Definer index 1B ] |
| */ |
| enum dr_ste_v1_lu_type { |
| DR_STE_V1_LU_TYPE_NOP = 0x0000, |
| DR_STE_V1_LU_TYPE_ETHL2_TNL = 0x0002, |
| DR_STE_V1_LU_TYPE_IBL3_EXT = 0x0102, |
| DR_STE_V1_LU_TYPE_ETHL2_O = 0x0003, |
| DR_STE_V1_LU_TYPE_IBL4 = 0x0103, |
| DR_STE_V1_LU_TYPE_ETHL2_I = 0x0004, |
| DR_STE_V1_LU_TYPE_SRC_QP_GVMI = 0x0104, |
| DR_STE_V1_LU_TYPE_ETHL2_SRC_O = 0x0005, |
| DR_STE_V1_LU_TYPE_ETHL2_HEADERS_O = 0x0105, |
| DR_STE_V1_LU_TYPE_ETHL2_SRC_I = 0x0006, |
| DR_STE_V1_LU_TYPE_ETHL2_HEADERS_I = 0x0106, |
| DR_STE_V1_LU_TYPE_ETHL3_IPV4_5_TUPLE_O = 0x0007, |
| DR_STE_V1_LU_TYPE_IPV6_DES_O = 0x0107, |
| DR_STE_V1_LU_TYPE_ETHL3_IPV4_5_TUPLE_I = 0x0008, |
| DR_STE_V1_LU_TYPE_IPV6_DES_I = 0x0108, |
| DR_STE_V1_LU_TYPE_ETHL4_O = 0x0009, |
| DR_STE_V1_LU_TYPE_IPV6_SRC_O = 0x0109, |
| DR_STE_V1_LU_TYPE_ETHL4_I = 0x000a, |
| DR_STE_V1_LU_TYPE_IPV6_SRC_I = 0x010a, |
| DR_STE_V1_LU_TYPE_ETHL2_SRC_DST_O = 0x000b, |
| DR_STE_V1_LU_TYPE_MPLS_O = 0x010b, |
| DR_STE_V1_LU_TYPE_ETHL2_SRC_DST_I = 0x000c, |
| DR_STE_V1_LU_TYPE_MPLS_I = 0x010c, |
| DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_O = 0x000d, |
| DR_STE_V1_LU_TYPE_GRE = 0x010d, |
| DR_STE_V1_LU_TYPE_FLEX_PARSER_TNL_HEADER = 0x000e, |
| DR_STE_V1_LU_TYPE_GENERAL_PURPOSE = 0x010e, |
| DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_I = 0x000f, |
| DR_STE_V1_LU_TYPE_STEERING_REGISTERS_0 = 0x010f, |
| DR_STE_V1_LU_TYPE_STEERING_REGISTERS_1 = 0x0110, |
| DR_STE_V1_LU_TYPE_FLEX_PARSER_OK = 0x0011, |
| DR_STE_V1_LU_TYPE_FLEX_PARSER_0 = 0x0111, |
| DR_STE_V1_LU_TYPE_FLEX_PARSER_1 = 0x0112, |
| DR_STE_V1_LU_TYPE_ETHL4_MISC_O = 0x0113, |
| DR_STE_V1_LU_TYPE_ETHL4_MISC_I = 0x0114, |
| DR_STE_V1_LU_TYPE_TNL_HEADER = 0x0117, |
| DR_STE_V1_LU_TYPE_MATCH = 0x0400, |
| DR_STE_V1_LU_TYPE_INVALID = 0x00ff, |
| DR_STE_V1_LU_TYPE_DONT_CARE = DR_STE_LU_TYPE_DONT_CARE, |
| }; |
| |
| enum dr_ste_v1_header_anchors { |
| DR_STE_HEADER_ANCHOR_START_OUTER = 0x00, |
| DR_STE_HEADER_ANCHOR_1ST_VLAN = 0x02, |
| DR_STE_HEADER_ANCHOR_IPV6_IPV4 = 0x07, |
| DR_STE_HEADER_ANCHOR_INNER_MAC = 0x13, |
| DR_STE_HEADER_ANCHOR_INNER_IPV6_IPV4 = 0x19, |
| }; |
| |
| enum dr_ste_v1_action_size { |
| DR_STE_ACTION_SINGLE_SZ = 4, |
| DR_STE_ACTION_DOUBLE_SZ = 8, |
| DR_STE_ACTION_TRIPLE_SZ = 12, |
| }; |
| |
| enum dr_ste_v1_action_insert_ptr_attr { |
| DR_STE_V1_ACTION_INSERT_PTR_ATTR_NONE = 0, /* Regular push header (e.g. push vlan) */ |
| DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP = 1, /* Encapsulation / Tunneling */ |
| DR_STE_V1_ACTION_INSERT_PTR_ATTR_ESP = 2, /* IPsec */ |
| }; |
| |
| enum dr_ste_v1_action_id { |
| DR_STE_V1_ACTION_ID_NOP = 0x00, |
| DR_STE_V1_ACTION_ID_COPY = 0x05, |
| DR_STE_V1_ACTION_ID_SET = 0x06, |
| DR_STE_V1_ACTION_ID_ADD = 0x07, |
| DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE = 0x08, |
| DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER = 0x09, |
| DR_STE_V1_ACTION_ID_INSERT_INLINE = 0x0a, |
| DR_STE_V1_ACTION_ID_INSERT_POINTER = 0x0b, |
| DR_STE_V1_ACTION_ID_FLOW_TAG = 0x0c, |
| DR_STE_V1_ACTION_ID_QUEUE_ID_SEL = 0x0d, |
| DR_STE_V1_ACTION_ID_ACCELERATED_LIST = 0x0e, |
| DR_STE_V1_ACTION_ID_MODIFY_LIST = 0x0f, |
| DR_STE_V1_ACTION_ID_ASO = 0x12, |
| DR_STE_V1_ACTION_ID_TRAILER = 0x13, |
| DR_STE_V1_ACTION_ID_COUNTER_ID = 0x14, |
| DR_STE_V1_ACTION_ID_MAX = 0x21, |
| /* use for special cases */ |
| DR_STE_V1_ACTION_ID_SPECIAL_ENCAP_L3 = 0x22, |
| }; |
| |
| enum { |
| DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_0 = 0x00, |
| DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_1 = 0x01, |
| DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_2 = 0x02, |
| DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_0 = 0x08, |
| DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_1 = 0x09, |
| DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0 = 0x0e, |
| DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0 = 0x18, |
| DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_1 = 0x19, |
| DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_0 = 0x40, |
| DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_1 = 0x41, |
| DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_0 = 0x44, |
| DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_1 = 0x45, |
| DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_2 = 0x46, |
| DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_3 = 0x47, |
| DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_0 = 0x4c, |
| DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_1 = 0x4d, |
| DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_2 = 0x4e, |
| DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_3 = 0x4f, |
| DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_0 = 0x5e, |
| DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_1 = 0x5f, |
| DR_STE_V1_ACTION_MDFY_FLD_METADATA_2_CQE = 0x7b, |
| DR_STE_V1_ACTION_MDFY_FLD_GNRL_PURPOSE = 0x7c, |
| DR_STE_V1_ACTION_MDFY_FLD_FLEX_PARSER_7 = 0x82, |
| DR_STE_V1_ACTION_MDFY_FLD_FLEX_PARSER_6 = 0x83, |
| DR_STE_V1_ACTION_MDFY_FLD_FLEX_PARSER_5 = 0x84, |
| DR_STE_V1_ACTION_MDFY_FLD_FLEX_PARSER_4 = 0x85, |
| DR_STE_V1_ACTION_MDFY_FLD_FLEX_PARSER_3 = 0x86, |
| DR_STE_V1_ACTION_MDFY_FLD_FLEX_PARSER_2 = 0x87, |
| DR_STE_V1_ACTION_MDFY_FLD_FLEX_PARSER_1 = 0x88, |
| DR_STE_V1_ACTION_MDFY_FLD_FLEX_PARSER_0 = 0x89, |
| DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2_0 = 0x8c, |
| DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2_1 = 0x8d, |
| DR_STE_V1_ACTION_MDFY_FLD_REGISTER_1_0 = 0x8e, |
| DR_STE_V1_ACTION_MDFY_FLD_REGISTER_1_1 = 0x8f, |
| DR_STE_V1_ACTION_MDFY_FLD_REGISTER_0_0 = 0x90, |
| DR_STE_V1_ACTION_MDFY_FLD_REGISTER_0_1 = 0x91, |
| }; |
| |
| enum dr_ste_v1_aso_ctx_type { |
| DR_STE_V1_ASO_CTX_TYPE_CT = 0x1, |
| DR_STE_V1_ASO_CTX_TYPE_POLICERS = 0x2, |
| DR_STE_V1_ASO_CTX_TYPE_FIRST_HIT = 0x4, |
| }; |
| |
| void dr_ste_v1_set_reparse(uint8_t *hw_ste_p); |
| |
| #endif |
