src/hotspot/cpu/ppc/vmreg_ppc.hpp

/*
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#ifndef CPU_PPC_VMREG_PPC_HPP
#define CPU_PPC_VMREG_PPC_HPP

inline bool is_Register() {
  return (unsigned int)value() < (unsigned int)ConcreteRegisterImpl::max_gpr;
}

inline bool is_FloatRegister() {
  return value() >= ConcreteRegisterImpl::max_gpr &&
         value() < ConcreteRegisterImpl::max_fpr;
}

inline bool is_VectorSRegister() {
  return value() >= ConcreteRegisterImpl::max_fpr &&
         value() < ConcreteRegisterImpl::max_vsr;
}

inline bool is_ConditionRegister() {
  return value() >= ConcreteRegisterImpl::max_vsr &&
         value() < ConcreteRegisterImpl::max_cnd;
}

inline bool is_SpecialRegister() {
  return value() >= ConcreteRegisterImpl::max_cnd &&
         value() < ConcreteRegisterImpl::max_spr;
}

inline Register as_Register() {
  assert(is_Register() && is_even(value()), "even-aligned GPR name");
  return ::as_Register(value()>>1);
}

inline FloatRegister as_FloatRegister() {
  assert(is_FloatRegister() && is_even(value()), "must be");
  return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1);
}

inline VectorSRegister as_VectorSRegister() {
  assert(is_VectorSRegister(), "must be");
  return ::as_VectorSRegister((value() - ConcreteRegisterImpl::max_fpr) >> 2);
}

inline bool is_concrete() {
  assert(is_reg(), "must be");
  if (is_Register() || is_FloatRegister()) return is_even(value());
  if (is_VectorSRegister()) {
    int base = value() - ConcreteRegisterImpl::max_fpr;
    return (base & 3) == 0;
  }
  return true;
}

#endif // CPU_PPC_VMREG_PPC_HPP