Initial commit of seabios/acpi for OVSS VM open source license compliance Change-Id: I186679c02ccdf895390ea86f65a45b82f8344a60
diff --git a/acpi/LICENSE b/acpi/LICENSE new file mode 100644 index 0000000..a42a477 --- /dev/null +++ b/acpi/LICENSE
@@ -0,0 +1,406 @@ +The files in this version are derived from seabios/src/fw/acpi-dsdt.dsl which +has the following license header: + +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +The full text of the referenced license is as follows: + +The licenses for most software are designed to take away your freedom to share +and change it. By contrast, the GNU General Public Licenses are intended to +guarantee your freedom to share and change free software--to make sure the +software is free for all its users. + +This license, the Library General Public License, applies to some specially +designated Free Software Foundation software, and to any other libraries whose +authors decide to use it. You can use it for your libraries, too. + +When we speak of free software, we are referring to freedom, not price. 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diff --git a/acpi/README.md b/acpi/README.md new file mode 100644 index 0000000..05a0ea6 --- /dev/null +++ b/acpi/README.md
@@ -0,0 +1,18 @@ +# GCE ACPI Templates + +This is a collection of ASL-language ACPI table templates used by GCE virtual +machines. They are derived from DSL files in the +[Seabios](https://github.com/coreboot/seabios) project and modified for GCE's +purposes. + +The contents do not comprise a usable version of the Seabios system firmware. +They are provided here to clarify ACPI table provenance. They make explicit the +nature of the relationship to GCE proprietary source code and maintain +separation from the private codebase. + +These cannot and should not be used without correctly-calibrated text template +processing and ASL interpretation. + +Corresponding source code for interpreting these files is not +provided—**the scope of this folder is merely license clarification and +compliance.**
diff --git a/acpi/dsdt_x86 b/acpi/dsdt_x86 new file mode 100644 index 0000000..2a9743f --- /dev/null +++ b/acpi/dsdt_x86
@@ -0,0 +1,1202 @@ +DefinitionBlock ("", "DSDT", 2, "Google", "GOOGDSDT", 0x00000001) +{ + External (_SB_.CPON, PkgObj) + External (_SB_.MNOT, MethodObj) // 2 Arguments + External (_SB_.NTFY, MethodObj) // 2 Arguments + External (_SB_.PCI0.PCNT, MethodObj) // 2 Arguments + Scope (\) + { + // Debug method - use this method to send output to the BIOS debug port. + // This method handles strings, integers, and buffers. + // For example: DBUG("abc") DBUG(0x123) + OperationRegion (DBG, SystemIO, {{ u16max }}, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + DBGB = 0x0A + } + } + Scope (_SB) + { + // Boolean value representing whether to add the _OSC method. + Name (POSC, {{ posc }}) + // Boolean value representing whether to use zero-based regions. + Name (ZBR, {{ zbr }}) + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_PXM, Zero) // _PXM: Device Proximity + // The templates modified and returned by the _CRS method. + Name (CRES, ResourceTemplate () + { + // PCI bus numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x0000, // Translation Offset + 0x0000, // Length + ,, PCBN) + // PCI config + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x01, // Alignment + 0x00, // Length + PCFG) + // 16-bit low chunk before PCI config + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x0000, // Translation Offset + 0x0000, // Length + ,, PLOW, TypeStatic, DenseTranslation) + // 16-bit next chunk after PCI config + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0FFF, // Range Maximum + 0x0000, // Translation Offset + 0x1000, // Length + ,, PCHK, TypeStatic, DenseTranslation) + // 16-bit PCI I/O + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x0000, // Translation Offset + 0x0000, // Length + ,, PC16, TypeStatic, DenseTranslation) + // Hotplug and power management legacy region + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0xA000, // Range Minimum + 0xBFFF, // Range Maximum + 0x0000, // Translation Offset + 0x2000, // Length + ,, , TypeStatic, DenseTranslation) + // VGA framebuffer + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x00000000, // Range Maximum + 0x00000000, // Translation Offset + 0x00000000, // Length + ,, VGAF, AddressRangeMemory, TypeStatic) + // 32-bit PCI memory + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x00000000, // Range Maximum + 0x00000000, // Translation Offset + 0x00000000, // Length + ,, PM32, AddressRangeMemory, TypeStatic) + }) + // Template to be concatenated for each active CRS allowlist entry + Name (CRWM, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x00000000, // Range Maximum + 0x00000000, // Translation Offset + 0x00000000, // Length + ,, PC32, AddressRangeMemory, TypeStatic) + }) + // 64-bit PCI memory + Name (CR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0x0000000000000000, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000000000000, // Length + ,, PC64, AddressRangeMemory, TypeStatic) + }) + // The address values patched before sending the table to the VM. + Name (PBBS, {{ u16max }}) + Name (PBBE, {{ u16max }}) + Name (PBIS, {{ u16max }}) + Name (PBIE, {{ u16max }}) + Name (PB0S, {{ u32max }}) + Name (PB0E, {{ u32max }}) +## for hole_index in range(11) + Name (PWS{{ hex(hole_index) }}, {{ u32max }}) + Name (PWE{{ hex(hole_index) }}, {{ u32max }}) +## endfor + Name (PB1V, {{ u8max }}) + Name (PB1S, {{ u64max }}) + Name (PB1E, {{ u64max }}) + Name (PB1L, {{ u64max }}) + Name (PPCI, {{ u16max }}) + Name (VGAS, {{ u32max }}) + Name (VGAL, {{ u32max }}) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + // Fix PCI bus numbers + CreateWordField (CRES, ^PCBN._MIN, BS32) // _MIN: Minimum Base Address + CreateWordField (CRES, ^PCBN._MAX, BE32) // _MAX: Maximum Base Address + CreateWordField (CRES, ^PCBN._LEN, BL32) // _LEN: Length + BS32 = PBBS /* \_SB_.PCI0.PBBS */ + BE32 = PBBE /* \_SB_.PCI0.PBBE */ + BL32 = ((PBBE - PBBS) + One) + // Lowest chunk of 16-bit addresses + CreateWordField (CRES, ^PLOW._MIN, LMIN) // _MIN: Minimum Base Address + CreateWordField (CRES, ^PLOW._MAX, LMAX) // _MAX: Maximum Base Address + CreateWordField (CRES, ^PLOW._LEN, LLEN) // _LEN: Length + LMIN = Zero + LMAX = PPCI - One + LLEN = PPCI + // PCI config range + CreateWordField (CRES, ^PCFG._MIN, PMIN) // _MIN: Minimum Base Address + CreateWordField (CRES, ^PCFG._MAX, PMAX) // _MAX: Maximum Base Address + CreateByteField (CRES, ^PCFG._LEN, PLEN) // _LEN: Length + PMIN = PPCI + PMAX = PPCI + PLEN = 0x8 + // Remaining 16-bit memory below 0x1000 + CreateWordField (CRES, ^PCHK._MIN, CMIN) // _MIN: Minimum Base Address + CreateWordField (CRES, ^PCHK._MAX, CMAX) // _MAX: Maximum Base Address + CreateWordField (CRES, ^PCHK._LEN, CLEN) // _LEN: Length + CMIN = PMIN + PLEN + CLEN = ((CMAX - CMIN) + One) + // PCI 16-bit I/O range + CreateWordField (CRES, ^PC16._MIN, IS32) // _MIN: Minimum Base Address + CreateWordField (CRES, ^PC16._MAX, IE32) // _MAX: Maximum Base Address + CreateWordField (CRES, ^PC16._LEN, IL32) // _LEN: Length + IS32 = PBIS /* \_SB_.PCI0.PBIS */ + IE32 = PBIE /* \_SB_.PCI0.PBIE */ + IL32 = ((PBIE - PBIS) + One) + If ((!ZBR && ((IS32 == Zero) && (IE32 == Zero)))) + { + IL32 = Zero + } + // VGA framebuffer + CreateDWordField (CRES, ^VGAF._MIN, FMIN) // _MIN: Minimum Base Address + CreateDWordField (CRES, ^VGAF._MAX, FMAX) // _MAX: Maximum Base Address + CreateDWordField (CRES, ^VGAF._LEN, FLEN) // _LEN: Length + FMIN = VGAS + FMAX = ((VGAS + VGAL) - One) + FLEN = VGAL + // PCI 32-bit range + CreateDWordField (CRES, ^PM32._MIN, PS32) // _MIN: Minimum Base Address + CreateDWordField (CRES, ^PM32._MAX, PE32) // _MAX: Maximum Base Address + CreateDWordField (CRES, ^PM32._LEN, PL32) // _LEN: Length + If ((PWS0 != Zero)) + { + PS32 = PWS0 /* \_SB_.PCI0.PWS0 */ + PE32 = PWE0 /* \_SB_.PCI0.PWE0 */ + PL32 = ((PWE0 - PWS0) + One) + } + Else + { + PS32 = PB0S /* \_SB_.PCI0.PB0S */ + PE32 = PB0E /* \_SB_.PCI0.PB0E */ + PL32 = ((PB0E - PB0S) + One) + } + If ((!ZBR && ((PS32 == Zero) && (PE32 == Zero)))) + { + PL32 = Zero + } + // Concatenate all active PCI CRS allowlist entries + Local0 = CRES /* \_SB_.PCI0.CRES */ + CreateDWordField (CRWM, ^PC32._MIN, RS32) // _MIN: Minimum Base Address + CreateDWordField (CRWM, ^PC32._MAX, RE32) // _MAX: Maximum Base Address + CreateDWordField (CRWM, ^PC32._LEN, RL32) // _LEN: Length +## for hole in pci_crs_holes + If (({{ hole.start }} != Zero)) + { + RS32 = {{ hole.start }} + RE32 = {{ hole.end }} + RL32 = (({{ hole.end }} - {{ hole.start }}) + One) + ConcatenateResTemplate (Local0, CRWM, Local0) + } +## endfor + // PCI 64-bit range + If ((PB1V == Zero)) + { + Return (Local0) + } + CreateQWordField (CR64, ^PC64._MIN, PS64) // _MIN: Minimum Base Address + CreateQWordField (CR64, ^PC64._MAX, PE64) // _MAX: Maximum Base Address + CreateQWordField (CR64, ^PC64._LEN, PL64) // _LEN: Length + PS64 = PB1S /* \_SB_.PCI0.PB1S */ + PE64 = PB1E /* \_SB_.PCI0.PB1E */ + PL64 = PB1L /* \_SB_.PCI0.PB1L */ + ConcatenateResTemplate (Local0, CR64, Local0) + Return (Local0) + } + // Report PCI host bridge capabilities to allow PCI hotplug + If (POSC) + { + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, Serialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + } + // Provides mapping from PCI interrupt pins to interrupt inputs of + // interrupt controllers. NOTE: Same mapping as PCI routing table + // from Bochs BIOS. + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { +## for link in pci_links + Package (0x04) + { + {{ link.address }}, + {{ link.pin }}, + // First device is power management and can only use IRQ 9 from LNKS + {% if link.pin == "0" and link.address == "0x0001FFFF" %}LNKS{% else %}{{ link.name }}{% endif %}, + Zero + }{% if not loop.is_last %},{% endif %} +## endfor + }) + } + } + Scope (_SB.PCI0) + { + Device (VGA) + { + Name (_ADR, 0x00020000) // _ADR: Address + OperationRegion (PCIC, PCI_Config, Zero, 0x04) + Field (PCIC, DWordAcc, NoLock, Preserve) + { + VEND, 32 + } + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + If ((VEND == 0x01001B36)) + { + Return (0x03) + } + Else + { + Return (Zero) + } + } + } + } + Scope (_SB.PCI0) + { + // PIIX4 PM + Device (PX13) + { + Name (_ADR, 0x00010003) // _ADR: Address + OperationRegion (P13C, PCI_Config, Zero, 0xFF) + } + } + Scope (_SB.PCI0) + { + // PIIX3 ISA bridge + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + // PIIX PCI to ISA IRQ remapping + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + // Enable bits + Field (^PX13.P13C, AnyAcc, NoLock, Preserve) + { + Offset (0x5F), + , 7, + LPEN, 1, + Offset (0x67), + , 3, + CAEN, 1, + , 3, + CBEN, 1 + } + Name (FDEN, Zero) + } + } + // Common legacy ISA style devices + Scope (_SB.PCI0.ISA) + { + OperationRegion (ISAE, SystemIO, {{ u16max }}, One) + Field (ISAE, ByteAcc, NoLock, WriteAsZeros) + { + SERA, 1, + SERB, 1, + KBDC, 1, + WPEN, 1, + SERC, 1, + SERD, 1, + , 1, + LGCY, 1 + } + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x10, // Alignment + 0x02, // Length + ) + IRQNoFlags () + {8} + IO (Decode16, + 0x0072, // Range Minimum + 0x0072, // Range Maximum + 0x02, // Alignment + 0x06, // Length + ) + }) + } + // IBM Enhanced Keyboard + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = LGCY /* \_SB_.PCI0.ISA_.LGCY */ + If ((Local0 == Zero)) + { + Local1 = KBDC /* \_SB_.PCI0.ISA_.KBDC */ + If ((Local1 == Zero)) + { + Return (Zero) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + // PS/2 Mouse + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = LGCY /* \_SB_.PCI0.ISA_.LGCY */ + If ((Local0 == Zero)) + { + Local1 = KBDC /* \_SB_.PCI0.ISA_.KBDC */ + If ((Local1 == Zero)) + { + Return (Zero) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + // Enhanced floppy controller + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (Zero) + } + } + // Standard LPT Parallel Port + Device (LPT) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (Zero) + } + } + // Serial ports + Name (C1AD, {{ u16max }}) + Name (C2AD, {{ u16max }}) + Name (C3AD, {{ u16max }}) + Name (C4AD, {{ u16max }}) + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = LGCY /* \_SB_.PCI0.ISA_.LGCY */ + If ((Local0 == Zero)) + { + Local1 = SERA /* \_SB_.PCI0.ISA_.SERA */ + If ((Local1 == Zero)) + { + Return (Zero) + } + Else + { + Return (0x0F) + } + } + Else + { + Local1 = CAEN /* \_SB_.PCI0.ISA_.CAEN */ + If ((Local1 == Zero)) + { + Return (Zero) + } + Else + { + Return (0x0F) + } + } + } + Name (CRES, ResourceTemplate () + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x00, // Alignment + 0x00, // Length + COIO) + IRQNoFlags () + {4} + }) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + CreateWordField (CRES, ^COIO._MIN, CMIN) // _MIN: Minimum Base Address + CreateWordField (CRES, ^COIO._MAX, CMAX) // _MAX: Maximum Base Address + CreateByteField (CRES, ^COIO._LEN, CLEN) // _LEN: Length + CMIN = C1AD + CMAX = C1AD + CLEN = 0x8 + Return (CRES) + } + } + Device (COM2) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = LGCY /* \_SB_.PCI0.ISA_.LGCY */ + If ((Local0 == Zero)) + { + Local1 = SERB /* \_SB_.PCI0.ISA_.SERB */ + If ((Local1 == Zero)) + { + Return (Zero) + } + Else + { + Return (0x0F) + } + } + Else + { + Local1 = CBEN /* \_SB_.PCI0.ISA_.CBEN */ + If ((Local1 == Zero)) + { + Return (Zero) + } + Else + { + Return (0x0F) + } + } + } + Name (CRES, ResourceTemplate () + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x00, // Alignment + 0x00, // Length + COIO) + IRQNoFlags () + {3} + }) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + CreateWordField (CRES, ^COIO._MIN, CMIN) // _MIN: Minimum Base Address + CreateWordField (CRES, ^COIO._MAX, CMAX) // _MAX: Maximum Base Address + CreateByteField (CRES, ^COIO._LEN, CLEN) // _LEN: Length + CMIN = C2AD + CMAX = C2AD + CLEN = 0x8 + Return (CRES) + } + } + Device (COM3) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = LGCY /* \_SB_.PCI0.ISA_.LGCY */ + If ((Local0 == Zero)) + { + Local1 = SERC /* \_SB_.PCI0.ISA_.SERC */ + If ((Local1 == One)) + { + Return (0x0F) + } + } + Return (Zero) + } + Name (CRES, ResourceTemplate () + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x00, // Alignment + 0x00, // Length + COIO) + IRQNoFlags () + {6} + }) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + CreateWordField (CRES, ^COIO._MIN, CMIN) // _MIN: Minimum Base Address + CreateWordField (CRES, ^COIO._MAX, CMAX) // _MAX: Maximum Base Address + CreateByteField (CRES, ^COIO._LEN, CLEN) // _LEN: Length + CMIN = C3AD + CMAX = C3AD + CLEN = 0x8 + Return (CRES) + } + } + Device (COM4) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = LGCY /* \_SB_.PCI0.ISA_.LGCY */ + If ((Local0 == Zero)) + { + Local1 = SERD /* \_SB_.PCI0.ISA_.SERD */ + If ((Local1 == One)) + { + Return (0x0F) + } + } + Return (Zero) + } + Name (CRES, ResourceTemplate () + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x00, // Alignment + 0x00, // Length + COIO) + IRQNoFlags () + {7} + }) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + CreateWordField (CRES, ^COIO._MIN, CMIN) // _MIN: Minimum Base Address + CreateWordField (CRES, ^COIO._MAX, CMAX) // _MAX: Maximum Base Address + CreateByteField (CRES, ^COIO._LEN, CLEN) // _LEN: Length + CMIN = C4AD + CMAX = C4AD + CLEN = 0x8 + Return (CRES) + } + } + // Serial tablet + Device (PEN) + { + Name (_HID, EisaId ("WACF004")) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = LGCY /* \_SB_.PCI0.ISA_.LGCY */ + If ((Local0 == Zero)) + { + Local1 = WPEN /* \_SB_.PCI0.ISA_.WPEN */ + If ((Local1 == Zero)) + { + Return (Zero) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (Zero) + } + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0200, // Range Minimum + 0x0208, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + } + // PCI hotplug definitions + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + OperationRegion (SEJ, SystemIO, {{ u16max }}, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + // Methods called by hotplug devices + Method (PCEJ, 1, NotSerialized) + { + B0EJ = (One << Arg0) + } + // PCI hotplug notify method + Method (PCNF, 0, NotSerialized) + { + // Local0 = iterator + Local0 = Zero + While ((Local0 < 0x1F)) + { + Local0++ + // PCNT is hotplug notification method supplied by SSDT + If ((PCIU & (One << Local0))) + { + PCNT (Local0, One) + } + If ((PCID & (One << Local0))) + { + PCNT (Local0, 0x03) + } + } + } + } + Scope (_SB) + { +## for int in pci_interrupts + Device ({{ int.name }}) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, {{ int.uid }}) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST ({{ int.reg }})) + } + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + {{ int.reg }} |= 0x80 + } + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR ({{ int.reg }})) + } + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + {{ int.reg }} = PRRI + } + } +## endfor + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + Return (0x0B) + } + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, PR0I) + { + 0x00000000, + } + }) + Method (IQCR, 1, Serialized) + { + CreateDWordField (PRR0, ^PR0I._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + // The SCI cannot be disabled and is always attached to GSI 9, so + // these are no-ops. We only need this link to override the polarity + // to active high and match the content of the MADT. + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + Scope (_SB) + { + // Boolean value which allows CPMA to always return x2APIC entries. + Name (MDX2, {{ madt_x2apic }}) + // Methods called by runtime generated SSDT Processor objects + Method (CPMA, 1, NotSerialized) + { + // Arg0 = Processor ID = Local APIC ID + // Local0 = CPON flag for this CPU + Local0 = DerefOf (CPON [Arg0]) + If ((MDX2) || (Arg0 >= 255)) + { + // Local1 = Buffer (in MADT x2APIC form) to return + Local1 = Buffer (0x10) + { + /* 0000 */ 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // ........ + } + // Update the processor ID, LAPIC ID, and enable/disable status + Local1 [0x04] = (Arg0) & 0xFF + Local1 [0x05] = (Arg0 >> 8) & 0xFF + Local1 [0x06] = (Arg0 >> 16) & 0xFF + Local1 [0x07] = (Arg0 >> 24) & 0xFF + Local1 [0x08] = Local0 + Local1 [0x0C] = (Arg0) & 0xFF + Local1 [0x0D] = (Arg0 >> 8) & 0xFF + Local1 [0x0E] = (Arg0 >> 16) & 0xFF + Local1 [0x0F] = (Arg0 >> 24) & 0xFF + Return (Local1) + } + // Local1 = Buffer (in MADT APIC form) to return + Local1 = Buffer (0x08) + { + 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // ........ + } + // Update the processor ID, LAPIC ID, and enable/disable status + Local1 [0x02] = Arg0 + Local1 [0x03] = Arg0 + Local1 [0x04] = Local0 + Return (Local1) + } + Method (CPST, 1, NotSerialized) + { + // Arg0 = Processor ID = Local APIC ID + // Local0 = CPON flag for this CPU + Local0 = DerefOf (CPON [Arg0]) + If (Local0) + { + Return (0x0F) + } + Else + { + Return (Zero) + } + } + Method (CPEJ, 2, NotSerialized) + { + // Arg0 = processor index + // Arg1 = _EJ0 argument + DBUG ("CPEJ") + DBUG (Arg0) + DBUG (Arg1) + // Check if hot-eject is requested + If ((Arg1 == One)) + { + // Local0 = local processor bitmap + // Must have same bit count as PRST field and highest CPU count + Local0 = Buffer (0x80){} + // Local1 = byte index + Local1 = (Arg0 >> 0x03) + // Local2 = bit index + Local2 = (Arg0 & 0x07) + // Local3 = bit mask + Local3 = (One << Local2) + // Write mask to local processor bitmap + Local0 [Local1] = Local3 + // Write mask to operation region to request processor eject + PRS = Local0 + } + Sleep (0xC8) + } + OperationRegion (PRST, SystemIO, {{ u16max }}, 0x80) + // CPU hotplug notify method + Field (PRST, ByteAcc, NoLock, Preserve) + { + PRS, 1024 + } + Method (PRSC, 0, NotSerialized) + { + // Local5 = active CPU bitmap + Local5 = PRS /* \_SB_.PRS_ */ + // Local2 = last read byte from bitmap + Local2 = Zero + // Local0 = Processor ID / APIC ID iterator + Local0 = Zero + While ((Local0 < SizeOf (CPON))) + { + // Local1 = CPON flag for this CPU + Local1 = DerefOf (CPON [Local0]) + If ((Local0 & 0x07)) + { + // Shift down previously read bitmap byte + Local2 >>= One + } + Else + { + // Read next byte from CPU bitmap + Local2 = DerefOf (Local5 [(Local0 >> 0x03)]) + } + // Local3 = active state for this CPU + Local3 = (Local2 & One) + If ((Local1 != Local3)) + { + // State change - update CPON with new state + CPON [Local0] = Local3 + // Do CPU notify + If ((Local3 == One)) + { + // Device check + NTFY (Local0, One) + } + Else + { + // Eject Request + NTFY (Local0, 0x03) + } + } + Local0++ + } + } + } + Scope (_SB) + { + Mutex (MMTX, 0x00) + OperationRegion (MOR, SystemIO, 0xAF80, 0x80) + Field (MOR, DWordAcc, NoLock, Preserve) + { + MHPE, 32, // Memory hotplug enable (R) + MCNT, 32, // Memory count (R) + MSEL, 32, // Memory select (RW) + MFLG, 32, // Memory flags (RW) + MBL, 32, // Memory base low (R) + MBH, 32, // Memory base high (R) + MLL, 32, // Memory length low (R) + MLH, 32, // Memory length high (R) + MPDI, 32, // Memory proximity domain ID (R) + MOSE, 32, // Memory OSPM source event (RW) + MOSC, 32 // Memory OSPM status code (RW) + } + // MFLG: + // 0x00000001 : Present (R) + // 0x00000002 : Insert pending (RW) + // 0x00000004 : Remove pending (RW) + Method (MSTA, 1, NotSerialized) + { + // Input: + // Arg0 : Memory device index + // Output: + // Bit0 : Set if the device is present + // Bit1 : Set if the device is enabled and decoding its resources + // Bit2 : Set if the device should be shown in the UI + // Bit3 : Set if the device is functioning properly + // Bit4 : Set if the battery is present + Local0 = Zero + Acquire (MMTX, 0xFFFF) + MSEL = Arg0 + If ((((MFLG & One) != Zero) && ((MFLG & + 0x04) == Zero))) + { + Local0 = 0x0F + } + Release (MMTX) + Return (Local0) + } + Method (MCRS, 1, NotSerialized) + { + // Input: + // Arg0 : Memory device index + // Output: + // Resource template + Local0 = ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, , AddressRangeMemory, TypeStatic) + } + CreateDWordField (Local0, 0x0E, MINL) + CreateDWordField (Local0, 0x12, MINH) + CreateDWordField (Local0, 0x16, MAXL) + CreateDWordField (Local0, 0x1A, MAXH) + CreateDWordField (Local0, 0x26, LENL) + CreateDWordField (Local0, 0x2A, LENH) + Acquire (MMTX, 0xFFFF) + MSEL = Arg0 + MINL = MBL /* \_SB_.MBL_ */ + MINH = MBH /* \_SB_.MBH_ */ + LENL = MLL /* \_SB_.MLL_ */ + LENH = MLH /* \_SB_.MLH_ */ + MAXL = (MINL + LENL) /* \_SB_.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MCRS.LENH */ + If (((MAXL < MINL) | (MAXL < LENL))) + { + MAXH += One + } + MAXL -= One + If ((MAXL == Ones)) + { + MAXH -= One + } + DBUG ("MCRS") + DBUG (Arg0) + DBUG (MINL) + DBUG (MINH) + DBUG (MAXL) + DBUG (MAXH) + DBUG (LENL) + DBUG (LENH) + Release (MMTX) + Return (Local0) + } + Method (MPXM, 1, NotSerialized) + { + // Input: + // Arg0 : Memory device index + // Output: + // Proximity domain ID + Acquire (MMTX, 0xFFFF) + MSEL = Arg0 + Local0 = MPDI /* \_SB_.MPDI */ + DBUG ("MPXM") + DBUG (Arg0) + DBUG (Local0) + Release (MMTX) + Return (Local0) + } + Method (MOST, 4, NotSerialized) + { + // Input: + // Arg0 : Memory device index + // Arg1 : OSPM source event + // Arg2 : OSPM status code + // Arg3 : OSPM status information + Acquire (MMTX, 0xFFFF) + MSEL = Arg0 + MOSE = Arg1 + MOSC = Arg2 + DBUG ("MOST") + DBUG (Arg0) + DBUG (Arg1) + DBUG (Arg2) + DBUG (Arg3) + Release (MMTX) + } + Method (MEJ0, 2, NotSerialized) + { + // Input: + // Arg0 : Memory device index + // Arg1 : _EJ0 argument + Acquire (MMTX, 0xFFFF) + DBUG ("MEJ0") + DBUG (Arg0) + DBUG (Arg1) + If ((Arg1 == One)) + { + MSEL = Arg0 + MFLG = 0x04 + } + Release (MMTX) + Sleep (0xC8) + } + Method (MSCA, 0, NotSerialized) + { + Acquire (MMTX, 0xFFFF) + DBUG ("MSCA") + Local0 = MCNT /* \_SB_.MCNT */ + Local1 = Zero + While ((Local1 < Local0)) + { + MSEL = Local1 + Local2 = MFLG /* \_SB_.MFLG */ + If (((Local2 & 0x02) != Zero)) + { + DBUG ("MSCA --> MNOT") + DBUG (Local1) + MNOT (Local1, One) + MFLG = 0x02 + } + Local1 += One + } + Release (MMTX) + } + } + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_L00, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + // PCI hotplug event + \_SB.PCI0.PCNF () + } + Method (_E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + // CPU hotplug event + \_SB.PRSC () + } + Method (_E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + // Memory hotplug event + \_SB.MSCA () + } + Method (_L04, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L05, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L06, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L07, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L08, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L09, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L0A, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L0B, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L0C, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L0D, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L0E, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + Method (_L0F, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + } + } +}
diff --git a/acpi/dsdt_x86_pci_root b/acpi/dsdt_x86_pci_root new file mode 100644 index 0000000..200990d --- /dev/null +++ b/acpi/dsdt_x86_pci_root
@@ -0,0 +1,199 @@ +DefinitionBlock ("", "DSPC", 2, "Google", "GOOGDSPC", 0x00000001) +{ + External (LNKA, DeviceObj) + External (LNKB, DeviceObj) + External (LNKC, DeviceObj) + External (LNKD, DeviceObj) + External (POSC, IntObj) + External (ZBR, IntObj) + // PCI root bus device definition + Scope (_SB) + { + Device (PR{{ bus_id }}) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_UID, {{ u8max }}) // _UID: Unique ID + Name (_BBN, {{ u8max }}) // _BBN: BIOS Bus Number + Name (_PXM, {{ u8max }}) // _PXM: Device Proximity + Name (CRES, ResourceTemplate () + { + // PCI bus numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x0000, // Translation Offset + 0x0000, // Length + ,, PCBN) + // 16-bit PCI memory + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x0000, // Translation Offset + 0x0000, // Length + ,, PC16, TypeStatic, DenseTranslation) + // 32-bit PCI memory + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x00000000, // Range Maximum + 0x00000000, // Translation Offset + 0x00000000, // Length + ,, PM32, AddressRangeMemory, TypeStatic) + }) + // Template to be concatenated for each active CRS allowlist entry + Name (CRWM, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x00000000, // Range Maximum + 0x00000000, // Translation Offset + 0x00000000, // Length + ,, PC32, AddressRangeMemory, TypeStatic) + }) + // 64-bit PCI memory + Name (CR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0x0000000000000000, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000000000000, // Length + ,, PC64, AddressRangeMemory, TypeStatic) + }) + Name (PBBS, {{ u16max }}) + Name (PBBE, {{ u16max }}) + Name (PBIS, {{ u16max }}) + Name (PBIE, {{ u16max }}) + Name (PB0S, {{ u32max }}) + Name (PB0E, {{ u32max }}) +## for hole_index in range(11) + Name (PWS{{ hex(hole_index) }}, {{ u32max }}) + Name (PWE{{ hex(hole_index) }}, {{ u32max }}) +## endfor + Name (PB1V, {{ u8max }}) + Name (PB1S, {{ u64max }}) + Name (PB1E, {{ u64max }}) + Name (PB1L, {{ u64max }}) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + // Fix PCI bus numbers + CreateWordField (CRES, ^PCBN._MIN, BS32) // _MIN: Minimum Base Address + CreateWordField (CRES, ^PCBN._MAX, BE32) // _MAX: Maximum Base Address + CreateWordField (CRES, ^PCBN._LEN, BL32) // _LEN: Length + BS32 = PBBS + BE32 = PBBE + BL32 = ((PBBE - PBBS) + One) + // PCI 16-bit I/O range + CreateWordField (CRES, ^PC16._MIN, IS32) // _MIN: Minimum Base Address + CreateWordField (CRES, ^PC16._MAX, IE32) // _MAX: Maximum Base Address + CreateWordField (CRES, ^PC16._LEN, IL32) // _LEN: Length + IS32 = PBIS + IE32 = PBIE + IL32 = ((PBIE - PBIS) + One) + If ((!ZBR && ((IS32 == Zero) && (IE32 == Zero)))) + { + IL32 = Zero + } + // PCI 32-bit range + CreateDWordField (CRES, ^PM32._MIN, PS32) // _MIN: Minimum Base Address + CreateDWordField (CRES, ^PM32._MAX, PE32) // _MAX: Maximum Base Address + CreateDWordField (CRES, ^PM32._LEN, PL32) // _LEN: Length + If ((PWS0 != Zero)) + { + PS32 = PWS0 + PE32 = PWE0 + PL32 = ((PWE0 - PWS0) + One) + } + Else + { + PS32 = PB0S + PE32 = PB0E + PL32 = ((PB0E - PB0S) + One) + } + If ((!ZBR && ((PS32 == Zero) && (PE32 == Zero)))) + { + PL32 = Zero + } + // Concatenate all active PCI CRS allowlist entries + Local0 = CRES + CreateDWordField (CRWM, ^PC32._MIN, RS32) // _MIN: Minimum Base Address + CreateDWordField (CRWM, ^PC32._MAX, RE32) // _MAX: Maximum Base Address + CreateDWordField (CRWM, ^PC32._LEN, RL32) // _LEN: Length +## for hole in pci_crs_holes + If (({{ hole.start }} != Zero)) + { + RS32 = {{ hole.start }} + RE32 = {{ hole.end }} + RL32 = (({{ hole.end }} - {{ hole.start }}) + One) + ConcatenateResTemplate (Local0, CRWM, Local0) + } +## endfor + // PCI 64-bit range + If ((PB1V == Zero)) + { + Return (Local0) + } + CreateQWordField (CR64, ^PC64._MIN, PS64) // _MIN: Minimum Base Address + CreateQWordField (CR64, ^PC64._MAX, PE64) // _MAX: Maximum Base Address + CreateQWordField (CR64, ^PC64._LEN, PL64) // _LEN: Length + PS64 = PB1S + PE64 = PB1E + PL64 = PB1L + ConcatenateResTemplate (Local0, CR64, Local0) + Return (Local0) + } + // Report PCI host bridge capabilities to allow PCI hotplug + If (POSC) + { + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, Serialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 + CTRL = CDW3 + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + CDW3 = CTRL + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + } + // Provides mapping from PCI interrupt pins to interrupt inputs + // of interrupt controllers. NOTE: Same mapping as PCI routing + // table from Bochs BIOS. + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { +## for link in pci_links + Package (0x04) + { + {{ link.address }}, + {{ link.pin }}, + {{ link.name }}, + Zero + }{% if not loop.is_last %},{% endif %} +## endfor + }) + } + } +}
diff --git a/acpi/ssdt b/acpi/ssdt new file mode 100644 index 0000000..d522392 --- /dev/null +++ b/acpi/ssdt
@@ -0,0 +1,155 @@ +DefinitionBlock ("", "SSDT", 1, "Google", "GOOGSSDT", 0x00000001) +{ + External (_SB_.PCI0, DeviceObj) + External (_SB_.PCI0.ISA_, DeviceObj) + External (_SB_.PCI0.PCEJ, MethodObj) // 1 Arguments + Scope (\) + { + // S3 (suspend-to-ram), S4 (suspend-to-disk) and S5 (power-off) type + // codes. Must match PIIX4 emulation. + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x00, + 0x00, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + Scope (\_SB.PCI0.ISA) + { + Device (PEVT) + { + Name (_HID, "QEMU0001") // _HID: Hardware ID + Name (PEST, {{ pvpanic_port }}) + OperationRegion (PEOR, SystemIO, PEST, One) + Field (PEOR, ByteAcc, NoLock, Preserve) + { + PEPT, 8 + } + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = PEST /* \_SB_.PCI0.ISA_.PEVT.PEST */ + If ((Local0 == Zero)) + { + Return (Zero) + } + Else + { + Return (0x0F) + } + } + Method (RDPT, 0, NotSerialized) + { + Local0 = PEPT /* \_SB_.PCI0.ISA_.PEVT.PEPT */ + Return (Local0) + } + Method (WRPT, 1, NotSerialized) + { + PEPT = Arg0 + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x01, // Alignment + 0x01, // Length + _Y06) + }) + CreateWordField (_CRS, \_SB.PCI0.ISA.PEVT._Y06._MIN, IOMN) // _MIN: Minimum Base Address + CreateWordField (_CRS, \_SB.PCI0.ISA.PEVT._Y06._MAX, IOMX) // _MAX: Maximum Base Address + Method (_INI, 0, NotSerialized) // _INI: Initialize + { + IOMN = PEST /* \_SB_.PCI0.ISA_.PEVT.PEST */ + IOMX = PEST /* \_SB_.PCI0.ISA_.PEVT.PEST */ + } + } + } + Scope (_SB) + { +## for memory in memory_devices + Device (M{{ memory.id }}) + { + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Name (_UID, 0x{{ memory.id }}) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MSTA (_UID)) + } + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + Return (MOST (_UID, Arg0, Arg1, Arg2)) + } + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + Return (MEJ0 (_UID, Arg0)) + } + } +## endfor + // Memory device notifier called by DSDT + Method (MNOT, 2, NotSerialized) + { +## for memory in memory_devices + If ((Arg0 == 0x{{ memory.id }})) + { + Notify (M{{ memory.id }}, Arg1) + } +## endfor + } + // Boolean value representing whether to define PCI hotplug Devices. + Name (PCHP, {{ pchp }}) + If (PCHP) + { + Scope (PCI0) + { +## for device in devices + Device (S{{ device.id }}) + { + Name (_SUN, 0x{{ device.id }}) // _SUN: Slot User Number + Name (_ADR, 0x00{{ device.id }}0000) // _ADR: Address + Method (NOEJ, 1, NotSerialized) + { + // Device should only eject if Arg0 is 1. + // See ACPI spec v6.5: 6.3.3. _EJx (Eject) + If (Arg0 == 1) + { + PCEJ (_SUN) + } + } + } +## endfor + Method (PCNT, 2, NotSerialized) + { +## for device in devices + If ((Arg0 == 0x{{ device.id }})) + { + Notify (S{{ device.id }}, Arg1) + } +## endfor + } + } + } + } +}
diff --git a/acpi/ssdt_cpu b/acpi/ssdt_cpu new file mode 100644 index 0000000..aac8969 --- /dev/null +++ b/acpi/ssdt_cpu
@@ -0,0 +1,26 @@ +DefinitionBlock ("", "SCPU", 1, "Google", "GOOGSCPU", 0x00000001) +{ + External (_SB_.CPEJ, MethodObj) // 2 Arguments + External (_SB_.CPMA, MethodObj) // 1 Arguments + External (_SB_.CPST, MethodObj) // 1 Arguments + Scope (_SB) + { + Device (C000) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, {{ u16max }}) // _UID: Unique ID + Method (_MAT, 0, NotSerialized) // _MAT: Multiple APIC Table Entry + { + Return (CPMA (_UID)) + } + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (CPST (_UID)) + } + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CPEJ (_UID, Arg0) + } + } + } +}
diff --git a/acpi/ssdt_cpu_cst b/acpi/ssdt_cpu_cst new file mode 100644 index 0000000..ba1a63b --- /dev/null +++ b/acpi/ssdt_cpu_cst
@@ -0,0 +1,22 @@ +DefinitionBlock ("", "SCST", 1, "Google", "GOOGSCST", 0x00000001) +{ + Name (_CST, Package () + { + 1, + Package () + { + ResourceTemplate () + { + Register (FFixedHW, + 0x00, + {{ u8max }}, + {{ u64max }}, + ,) + }, + + {{ u8max }}, + {{ u16max }}, + 0 + }, + }) +} \ No newline at end of file
diff --git a/acpi/ssdt_cpu_ntfy b/acpi/ssdt_cpu_ntfy new file mode 100644 index 0000000..20b59cf --- /dev/null +++ b/acpi/ssdt_cpu_ntfy
@@ -0,0 +1,14 @@ +DefinitionBlock ("", "SNTF", 1, "Google", "GOOGSNTF", 0x00000001) +{ + External (_SB.C000, DeviceObj) + Scope (_SB) + { + Method (NTFY, 2, NotSerialized) + { + If ((Arg0 == {{ u16max }})) + { + Notify (C000, Arg1) + } + } + } +}
diff --git a/acpi/ssdt_cpu_on b/acpi/ssdt_cpu_on new file mode 100644 index 0000000..5627bab --- /dev/null +++ b/acpi/ssdt_cpu_on
@@ -0,0 +1,9 @@ +DefinitionBlock ("", "SCPO", 1, "Google", "GOOGSCPO", 0x00000001) +{ + Scope (_SB) + { + Name (CPON, Package ({{ u8max }}) + { + }) + } +}