Merge with git://git.kernel.org/pub/scm/boot/u-boot/galak/u-boot.git#mpc8349emds
diff --git a/CHANGELOG b/CHANGELOG index f8bba74..ef3b807 100644 --- a/CHANGELOG +++ b/CHANGELOG
@@ -8,6 +8,26 @@ - reworked memory map to allow mapping of all regions with BATs Patch by Kumar Gala 20 Apr 2006 +* Coding Style cleanup + +* Write RTC seconds first to maintain settings integrity per + Maxim/Dallas DS1306 data sheet. + Patch by Alan J. Luse, 02 May 2006 + +* Scheduled for removal: strnicmp() which is unused + +* Update for Intel Monahans boards: + - support for magic key detection and handling on delta board + - NAND support for zylonite board + some minor cleanup + +* Declare load_serial_ymodem() when using CFG_CMD_LOADB. + Patch by Jon Loeliger, 01 May 2006 + +* Fixed handling of bad checksums with "mkimage -l" + +* Added support for BC3450 board + Patch by Stefan Strobl, 21 Oct 2005 + * Update for NC650 board: - Support rev1 and rev2 hardware - adapt to new NAND layer
diff --git a/MAKEALL b/MAKEALL index 23868ae..0d81844 100755 --- a/MAKEALL +++ b/MAKEALL
@@ -25,10 +25,10 @@ ######################################################################### LIST_5xxx=" \ - cpci5200 EVAL5200 icecube_5100 icecube_5200 \ - lite5200b mcc200 o2dnt pf5200 \ - PM520 Total5100 Total5200 Total5200_Rev2 \ - TQM5200_auto \ + BC3450 cpci5200 EVAL5200 icecube_5100 \ + icecube_5200 lite5200b mcc200 o2dnt \ + pf5200 PM520 Total5100 Total5200 \ + Total5200_Rev2 TQM5200_auto \ " #########################################################################
diff --git a/Makefile b/Makefile index 249c9f0..74e9474 100644 --- a/Makefile +++ b/Makefile
@@ -259,6 +259,9 @@ aev_config: unconfig @./mkconfig -a aev ppc mpc5xxx tqm5200 +BC3450_config: unconfig + @./mkconfig -a BC3450 ppc mpc5xxx bc3450 + cpci5200_config: unconfig @./mkconfig -a cpci5200 ppc mpc5xxx cpci5200 esd
diff --git a/README b/README index 3ae9cfc..3ffef62 100644 --- a/README +++ b/README
@@ -262,12 +262,13 @@ PowerPC based boards: --------------------- - CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCI405 - CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC2 - CONFIG_AMX860 CONFIG_GTH CONFIG_PCIPPC6 - CONFIG_AP1000 CONFIG_gw8260 CONFIG_pcu_e - CONFIG_AR405 CONFIG_hermes CONFIG_PIP405 - CONFIG_BAB7xx CONFIG_hymod CONFIG_PM826 + CONFIG_ADCIOP CONFIG_FPS860L CONFIG_OXC + CONFIG_ADS860 CONFIG_GEN860T CONFIG_PCI405 + CONFIG_AMX860 CONFIG_GENIETV CONFIG_PCIPPC2 + CONFIG_AP1000 CONFIG_GTH CONFIG_PCIPPC6 + CONFIG_AR405 CONFIG_gw8260 CONFIG_pcu_e + CONFIG_BAB7xx CONFIG_hermes CONFIG_PIP405 + CONFIG_BC3450 CONFIG_hymod CONFIG_PM826 CONFIG_c2mon CONFIG_IAD210 CONFIG_ppmc8260 CONFIG_CANBT CONFIG_ICU862 CONFIG_QS823 CONFIG_CCM CONFIG_IP860 CONFIG_QS850 @@ -299,7 +300,6 @@ CONFIG_FADS860T CONFIG_NX823 CONFIG_WALNUT CONFIG_FLAGADM CONFIG_OCRTC CONFIG_ZPC1900 CONFIG_FPS850L CONFIG_ORSG CONFIG_ZUMA - CONFIG_FPS860L CONFIG_OXC ARM based boards: -----------------
diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile new file mode 100644 index 0000000..4dec44f --- /dev/null +++ b/board/bc3450/Makefile
@@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o cmd_bc3450.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +#########################################################################
diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c new file mode 100644 index 0000000..0d86518 --- /dev/null +++ b/board/bc3450/bc3450.c
@@ -0,0 +1,672 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * (C) Copyright 2006 + * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> + +#ifdef CONFIG_VIDEO_SM501 +#include <sm501.h> +#endif + +#if defined(CONFIG_MPC5200_DDR) +#include "mt46v16m16-75.h" +#else +#include "mt48lc16m16a2-75.h" +#endif + +#ifdef CONFIG_RTC_MPC5200 +#include <rtc.h> +#endif + +#ifdef CONFIG_PS2MULT +void ps2mult_early_init(void); +#endif + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +#if defined(CONFIG_MPC5200) +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ + + /* find RAM size using SDRAM CS1 only */ + sdram_start(0); + test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + + return dramsize; +} + +#elif defined(CONFIG_MGT5100) + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup and enable SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + + /* address select register */ + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; + __asm__ volatile ("sync"); + + /* find RAM size */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* set SDRAM end address according to size */ + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); + +#else /* CFG_RAMBOOT */ + + /* Retrieve amount of SDRAM available */ + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); + +#endif /* CFG_RAMBOOT */ + + return dramsize; +} + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif + +int checkboard (void) +{ +#if defined (CONFIG_TQM5200) + puts ("Board: TQM5200 (TQ-Components GmbH)\n"); +#endif + +#if defined (CONFIG_BC3450) + puts ("Dev: GERSYS BC3450\n"); +#endif + + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ +#if defined(CONFIG_MGT5100) + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ +#endif + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) +#define GPIO_PSC1_4 0x01000000UL + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + } +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#ifdef CONFIG_POST +/* + * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 + * is left open, no keypress is detected. + */ +int post_hotkeys_pressed(void) +{ + struct mpc5xxx_gpio *gpio; + + gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; + + /* + * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in + * CODEC or UART mode. Consumer IrDA should still be possible. + */ + gpio->port_config &= ~(0x07000000); + gpio->port_config |= 0x03000000; + + /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ + gpio->simple_gpioe |= 0x20000000; + + /* Configure GPIO_IRDA_1 as input */ + gpio->simple_ddr &= ~(0x20000000); + + return ((gpio->simple_ival & 0x20000000) ? 0 : 1); +} +#endif + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + +void post_word_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + + *save_addr = a; +} + +ulong post_word_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + + return *save_addr; +} +#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ + + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ +#ifdef CONFIG_RTC_MPC5200 + struct rtc_time t; + + /* set to Wed Dec 31 19:00:00 1969 */ + t.tm_sec = t.tm_min = 0; + t.tm_hour = 19; + t.tm_mday = 31; + t.tm_mon = 12; + t.tm_year = 1969; + t.tm_wday = 3; + + rtc_set(&t); +#endif /* CONFIG_RTC_MPC5200 */ + +#ifdef CONFIG_PS2MULT + ps2mult_early_init(); +#endif /* CONFIG_PS2MULT */ + return (0); +} +#endif /* CONFIG_BOARD_EARLY_INIT_R */ + + +int last_stage_init (void) +{ + /* + * auto scan for really existing devices and re-set chip select + * configuration. + */ + u16 save, tmp; + int restore; + + /* + * Check for SRAM and SRAM size + */ + + /* save original SRAM content */ + save = *(volatile u16 *)CFG_CS2_START; + restore = 1; + + /* write test pattern to SRAM */ + *(volatile u16 *)CFG_CS2_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in SRAM detection\n"); + + if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) { + /* no SRAM at all, disable cs */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); + *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; + *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; + restore = 0; + __asm__ volatile ("sync"); + } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) { + /* make sure that we access a mirrored address */ + *(volatile u16 *)CFG_CS2_START = 0x1111; + __asm__ volatile ("sync"); + if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) { + /* SRAM size = 512 kByte */ + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, + 0x80000); + __asm__ volatile ("sync"); + puts ("SRAM: 512 kB\n"); + } + else + puts ("!! possible error in SRAM detection\n"); + } else { + puts ("SRAM: 1 MB\n"); + } + /* restore origianl SRAM content */ + if (restore) { + *(volatile u16 *)CFG_CS2_START = save; + __asm__ volatile ("sync"); + } + + /* + * Check for Grafic Controller + */ + + /* save origianl FB content */ + save = *(volatile u16 *)CFG_CS1_START; + restore = 1; + + /* write test pattern to FB memory */ + *(volatile u16 *)CFG_CS1_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in grafic controller detection\n"); + + if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + /* no grafic controller at all, disable cs */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); + *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; + *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; + restore = 0; + __asm__ volatile ("sync"); + } else { + puts ("VGA: SMI501 (Voyager) with 8 MB\n"); + } + /* restore origianl FB content */ + if (restore) { + *(volatile u16 *)CFG_CS1_START = save; + __asm__ volatile ("sync"); + } + + return 0; +} + +#ifdef CONFIG_VIDEO_SM501 + +#define DISPLAY_WIDTH 640 +#define DISPLAY_HEIGHT 480 + +#ifdef CONFIG_VIDEO_SM501_8BPP +#error CONFIG_VIDEO_SM501_8BPP not supported. +#endif /* CONFIG_VIDEO_SM501_8BPP */ + +#ifdef CONFIG_VIDEO_SM501_16BPP +#error CONFIG_VIDEO_SM501_16BPP not supported. +#endif /* CONFIG_VIDEO_SM501_16BPP */ + +#ifdef CONFIG_VIDEO_SM501_32BPP +static const SMI_REGS init_regs [] = +{ +#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT) + /* FP only */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x091a0a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x091a0a01}, + {0x00054, 0x0}, + {0x80000, 0x01013106}, + {0x80004, 0xc428bb17}, + {0x80000, 0x03013106}, + {0x8000C, 0x00000000}, + {0x80010, 0x0a000a00}, + {0x80014, 0x02800000}, + {0x80018, 0x01e00000}, + {0x8001C, 0x00000000}, + {0x80020, 0x01e00280}, + {0x80024, 0x02fa027f}, + {0x80028, 0x004a028b}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201e9}, + {0x80200, 0x00010200}, + {0x80000, 0x0f013106}, +#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP) + /* CRT only */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x10090a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x10090a01}, + {0x00054, 0x0}, + {0x80200, 0x00010000}, + {0x80204, 0x0}, + {0x80208, 0x0A000A00}, + {0x8020C, 0x02fa027f}, + {0x80210, 0x004a028b}, + {0x80214, 0x020c01df}, + {0x80218, 0x000201e9}, + {0x80200, 0x00013306}, +#else /* panel + CRT */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x091a0a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x091a0a01}, + {0x00054, 0x0}, + {0x80000, 0x0f013106}, + {0x80004, 0xc428bb17}, + {0x8000C, 0x00000000}, + {0x80010, 0x0a000a00}, + {0x80014, 0x02800000}, + {0x80018, 0x01e00000}, + {0x8001C, 0x00000000}, + {0x80020, 0x01e00280}, + {0x80024, 0x02fa027f}, + {0x80028, 0x004a028b}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201e9}, + {0x80200, 0x00010000}, +#endif + {0, 0} +}; +#endif /* CONFIG_VIDEO_SM501_32BPP */ + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +/* + * Return text to be printed besides the logo. + */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { +#if defined (CONFIG_TQM5200) + strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); +#else +#error No supported board selected +#endif /* CONFIG_TQM5200 */ + +#if defined (CONFIG_BC3450) + } else if (line_number == 2) { + strcpy (info, " Dev: GERSYS BC3450"); +#endif /* CONFIG_BC3450 */ + } + else { + info [0] = '\0'; + } +} +#endif + +/* + * Returns SM501 register base address. First thing called in the + * driver. Checks if SM501 is physically present. + */ +unsigned int board_video_init (void) +{ + u16 save, tmp; + int restore, ret; + + /* + * Check for Grafic Controller + */ + + /* save origianl FB content */ + save = *(volatile u16 *)CFG_CS1_START; + restore = 1; + + /* write test pattern to FB memory */ + *(volatile u16 *)CFG_CS1_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in grafic controller detection\n"); + + if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + /* no grafic controller found */ + restore = 0; + ret = 0; + } else { + ret = SM501_MMIO_BASE; + } + + if (restore) { + *(volatile u16 *)CFG_CS1_START = save; + __asm__ volatile ("sync"); + } + return ret; +} + +/* + * Returns SM501 framebuffer address + */ +unsigned int board_video_get_fb (void) +{ + return SM501_FB_BASE; +} + +/* + * Called after initializing the SM501 and before clearing the screen. + */ +void board_validate_screen (unsigned int base) +{ +} + +/* + * Return a pointer to the initialization sequence. + */ +const SMI_REGS *board_get_regs (void) +{ + return init_regs; +} + +int board_get_width (void) +{ + return DISPLAY_WIDTH; +} + +int board_get_height (void) +{ + return DISPLAY_HEIGHT; +} + +#endif /* CONFIG_VIDEO_SM501 */
diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c new file mode 100644 index 0000000..6bbe4e6 --- /dev/null +++ b/board/bc3450/cmd_bc3450.c
@@ -0,0 +1,827 @@ +/* + * (C) Copyright 2005 + * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de + * + * (C) Copyright 2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +/* + * BC3450 specific commands + */ +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +#undef DEBUG +#ifdef DEBUG +# define dprintf(fmt,args...) printf(fmt, ##args) +#else +# define dprintf(fmt,args...) +#endif + +/* + * Definitions for DS1620 chip + */ +#define THERM_START_CONVERT 0xee +#define THERM_RESET 0xaf +#define THERM_READ_CONFIG 0xac +#define THERM_READ_TEMP 0xaa +#define THERM_READ_TL 0xa2 +#define THERM_READ_TH 0xa1 +#define THERM_WRITE_CONFIG 0x0c +#define THERM_WRITE_TL 0x02 +#define THERM_WRITE_TH 0x01 + +#define CFG_CPU 2 +#define CFG_1SHOT 1 +#define CFG_STANDALONE 0 + +struct therm { + int hi; + int lo; +}; + +/* + * SM501 Register + */ +#define SM501_GPIO_CTRL_LOW 0x00000008UL /* gpio pins 0..31 */ +#define SM501_GPIO_CTRL_HIGH 0x0000000CUL /* gpio pins 32..63 */ +#define SM501_POWER_MODE0_GATE 0x00000040UL +#define SM501_POWER_MODE1_GATE 0x00000048UL +#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL +#define SM501_GPIO_DATA_LOW 0x00010000UL +#define SM501_GPIO_DATA_HIGH 0x00010004UL +#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL +#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL +#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL +#define SM501_CRT_DISPLAY_CONTROL 0x00080200UL + +/* SM501 CRT Display Control Bits */ +#define SM501_CDC_SEL (1 << 9) +#define SM501_CDC_TE (1 << 8) +#define SM501_CDC_E (1 << 2) + +/* SM501 Panel Display Control Bits */ +#define SM501_PDC_FPEN (1 << 27) +#define SM501_PDC_BIAS (1 << 26) +#define SM501_PDC_DATA (1 << 25) +#define SM501_PDC_VDDEN (1 << 24) + +/* SM501 GPIO Data LOW Bits */ +#define SM501_GPIO24 0x01000000 +#define SM501_GPIO25 0x02000000 +#define SM501_GPIO26 0x04000000 +#define SM501_GPIO27 0x08000000 +#define SM501_GPIO28 0x10000000 +#define SM501_GPIO29 0x20000000 +#define SM501_GPIO30 0x40000000 +#define SM501_GPIO31 0x80000000 + +/* SM501 GPIO Data HIGH Bits */ +#define SM501_GPIO46 0x00004000 +#define SM501_GPIO47 0x00008000 +#define SM501_GPIO48 0x00010000 +#define SM501_GPIO49 0x00020000 +#define SM501_GPIO50 0x00040000 +#define SM501_GPIO51 0x00080000 + +/* BC3450 GPIOs @ SM501 Data LOW */ +#define DIP (SM501_GPIO24 | SM501_GPIO25 | SM501_GPIO26 | SM501_GPIO27) +#define DS1620_DQ SM501_GPIO29 /* I/O */ +#define DS1620_CLK SM501_GPIO30 /* High active O/P */ +#define DS1620_RES SM501_GPIO31 /* Low active O/P */ +/* BC3450 GPIOs @ SM501 Data HIGH */ +#define BUZZER SM501_GPIO47 /* Low active O/P */ +#define DS1620_TLOW SM501_GPIO48 /* High active I/P */ +#define PWR_OFF SM501_GPIO49 /* Low active O/P */ +#define FP_DATA_TRI SM501_GPIO50 /* High active O/P */ + + +/* + * Initialise GPIO on SM501 + * + * This function may be called from several other functions. + * Yet, the initialisation sequence is executed only the first + * time the function is called. + */ +int sm501_gpio_init (void) +{ + static int init_done = 0; + + if (init_done) { +/* dprintf("sm501_gpio_init: nothing to be done.\n"); */ + return 1; + } + + /* enable SM501 GPIO control (in both power modes) */ + *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + + /* set up default O/Ps */ + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= + ~(DS1620_RES | DS1620_CLK); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ; + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= + ~(FP_DATA_TRI); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= + (BUZZER | PWR_OFF); + + /* configure directions for SM501 GPIO pins */ + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &= + ~(0x3F << 14); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= + ~(DIP | DS1620_DQ); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= + (DS1620_RES | DS1620_CLK); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &= + ~DS1620_TLOW; + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |= + (PWR_OFF | BUZZER | FP_DATA_TRI); + + init_done = 1; +/* dprintf("sm501_gpio_init: done.\n"); */ + return 0; +} + + +/* + * dip - read Config Inputs + * + * read and prints the dip switch + * and/or external config inputs (4bits) 0...0x0F + */ +int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + vu_long rc = 0; + + sm501_gpio_init (); + + /* read dip switch */ + rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW); + rc = ~rc; + rc &= DIP; + rc = (int) (rc >> 24); + + /* plausibility check */ + if (rc > 0x0F) + return -1; + + printf ("0x%x\n", rc); + return 0; +} + +U_BOOT_CMD (dip, 1, 1, cmd_dip, + "dip - read dip switch and config inputs\n", + "\n" + " - prints the state of the dip switch and/or\n" + " external configuration inputs as hex value.\n" + " - \"Config 1\" is the LSB\n"); + + +/* + * buz - turns Buzzer on/off + */ +#ifdef CONFIG_BC3450_BUZZER +static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + if (argc != 2) { + printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n"); + return 1; + } + + sm501_gpio_init (); + + if (strncmp (argv[1], "on", 2) == 0) { + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= + ~(BUZZER); + return 0; + } else if (strncmp (argv[1], "off", 3) == 0) { + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= + BUZZER; + return 0; + } + printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n"); + return 1; +} + +U_BOOT_CMD (buz, 2, 1, cmd_buz, + "buz - turns buzzer on/off\n", + "\n" "buz <on/off>\n" " - turns the buzzer on or off\n"); +#endif /* CONFIG_BC3450_BUZZER */ + + +/* + * fp - front panel commands + */ +static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + sm501_gpio_init (); + + if (strncmp (argv[1], "on", 2) == 0) { + /* turn on VDD first */ + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN; + udelay (1000); + /* then put data on */ + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA; + /* wait some time and enable backlight */ + udelay (1000); + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS; + udelay (1000); + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN; + return 0; + } else if (strncmp (argv[1], "off", 3) == 0) { + /* turn off the backlight first */ + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN; + udelay (1000); + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS; + udelay (200000); + /* wait some time, then remove data */ + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA; + udelay (1000); + /* and remove VDD last */ + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= + ~SM501_PDC_VDDEN; + return 0; + } else if (strncmp (argv[1], "bl", 2) == 0) { + /* turn on/off backlight only */ + if (strncmp (argv[2], "on", 2) == 0) { + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= + SM501_PDC_BIAS; + udelay (1000); + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) |= + SM501_PDC_FPEN; + return 0; + } else if (strncmp (argv[2], "off", 3) == 0) { + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= + ~SM501_PDC_FPEN; + udelay (1000); + *(vu_long *) (SM501_MMIO_BASE + + SM501_PANEL_DISPLAY_CONTROL) &= + ~SM501_PDC_BIAS; + return 0; + } + } +#ifdef CONFIG_BC3450_CRT + else if (strncmp (argv[1], "crt", 3) == 0) { + /* enables/disables the crt output (debug only) */ + if (strncmp (argv[2], "on", 2) == 0) { + *(vu_long *) (SM501_MMIO_BASE + + SM501_CRT_DISPLAY_CONTROL) |= + (SM501_CDC_TE | SM501_CDC_E); + *(vu_long *) (SM501_MMIO_BASE + + SM501_CRT_DISPLAY_CONTROL) &= + ~SM501_CDC_SEL; + return 0; + } else if (strncmp (argv[2], "off", 3) == 0) { + *(vu_long *) (SM501_MMIO_BASE + + SM501_CRT_DISPLAY_CONTROL) &= + ~(SM501_CDC_TE | SM501_CDC_E); + *(vu_long *) (SM501_MMIO_BASE + + SM501_CRT_DISPLAY_CONTROL) |= + SM501_CDC_SEL; + return 0; + } + } +#endif /* CONFIG_BC3450_CRT */ + printf ("Usage:%s\n", cmdtp->help); + return 1; +} + +U_BOOT_CMD (fp, 3, 1, cmd_fp, + "fp - front panes access functions\n", + "\n" + "fp bl <on/off>\n" + " - turns the CCFL backlight of the display on/off\n" + "fp <on/off>\n" " - turns the whole display on/off\n" +#ifdef CONFIG_BC3450_CRT + "fp crt <on/off>\n" + " - enables/disables the crt output (debug only)\n" +#endif /* CONFIG_BC3450_CRT */ + ); + + +/* + * temp - DS1620 thermometer + */ +/* GERSYS BC3450 specific functions */ +static inline void bc_ds1620_set_clk (int clk) +{ + if (clk) + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= + DS1620_CLK; + else + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= + ~DS1620_CLK; +} + +static inline void bc_ds1620_set_data (int dat) +{ + if (dat) + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= + DS1620_DQ; + else + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= + ~DS1620_DQ; +} + +static inline int bc_ds1620_get_data (void) +{ + vu_long rc; + + rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW); + rc &= DS1620_DQ; + if (rc != 0) + rc = 1; + return (int) rc; +} + +static inline void bc_ds1620_set_data_dir (int dir) +{ + if (dir) /* in */ + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ; + else /* out */ + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ; +} + +static inline void bc_ds1620_set_reset (int res) +{ + if (res) + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES; + else + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES; +} + +/* hardware independent functions */ +static void ds1620_send_bits (int nr, int value) +{ + int i; + + for (i = 0; i < nr; i++) { + bc_ds1620_set_data (value & 1); + bc_ds1620_set_clk (0); + udelay (1); + bc_ds1620_set_clk (1); + udelay (1); + + value >>= 1; + } +} + +static unsigned int ds1620_recv_bits (int nr) +{ + unsigned int value = 0, mask = 1; + int i; + + bc_ds1620_set_data (0); + + for (i = 0; i < nr; i++) { + bc_ds1620_set_clk (0); + udelay (1); + + if (bc_ds1620_get_data ()) + value |= mask; + + mask <<= 1; + + bc_ds1620_set_clk (1); + udelay (1); + } + + return value; +} + +static void ds1620_out (int cmd, int bits, int value) +{ + bc_ds1620_set_clk (1); + bc_ds1620_set_data_dir (0); + + bc_ds1620_set_reset (0); + udelay (1); + bc_ds1620_set_reset (1); + + udelay (1); + + ds1620_send_bits (8, cmd); + if (bits) + ds1620_send_bits (bits, value); + + udelay (1); + + /* go stand alone */ + bc_ds1620_set_data_dir (1); + bc_ds1620_set_reset (0); + bc_ds1620_set_clk (0); + + udelay (10000); +} + +static unsigned int ds1620_in (int cmd, int bits) +{ + unsigned int value; + + bc_ds1620_set_clk (1); + bc_ds1620_set_data_dir (0); + + bc_ds1620_set_reset (0); + udelay (1); + bc_ds1620_set_reset (1); + + udelay (1); + + ds1620_send_bits (8, cmd); + + bc_ds1620_set_data_dir (1); + value = ds1620_recv_bits (bits); + + /* go stand alone */ + bc_ds1620_set_data_dir (1); + bc_ds1620_set_reset (0); + bc_ds1620_set_clk (0); + + return value; +} + +static int cvt_9_to_int (unsigned int val) +{ + if (val & 0x100) + val |= 0xfffffe00; + + return val; +} + +/* set thermostate thresholds */ +static void ds1620_write_state (struct therm *therm) +{ + ds1620_out (THERM_WRITE_TL, 9, therm->lo); + ds1620_out (THERM_WRITE_TH, 9, therm->hi); + ds1620_out (THERM_START_CONVERT, 0, 0); +} + +static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i; + struct therm therm; + + sm501_gpio_init (); + + /* print temperature */ + if (argc == 1) { + i = cvt_9_to_int (ds1620_in (THERM_READ_TEMP, 9)); + printf ("%d.%d C\n", i >> 1, i & 1 ? 5 : 0); + return 0; + } + + /* set to default operation */ + if (strncmp (argv[1], "set", 3) == 0) { + if (strncmp (argv[2], "default", 3) == 0) { + therm.hi = +88; + therm.lo = -20; + therm.hi <<= 1; + therm.lo <<= 1; + ds1620_write_state (&therm); + ds1620_out (THERM_WRITE_CONFIG, 8, CFG_STANDALONE); + return 0; + } + } + + printf ("Usage:%s\n", cmdtp->help); + return 1; +} + +U_BOOT_CMD (temp, 3, 1, cmd_temp, + "temp - print current temperature\n", + "\n" "temp\n" " - print current temperature\n"); + +#ifdef CONFIG_BC3450_CAN +/* + * Initialise CAN interface + * + * return 1 on CAN initialization failure + * return 0 if no failure + */ +int can_init (void) +{ + static int init_done = 0; + int i; + struct mpc5xxx_mscan *can1 = + (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0900); + struct mpc5xxx_mscan *can2 = + (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0980); + + /* GPIO configuration of the CAN pins is done in BC3450.h */ + + if (!init_done) { + /* init CAN 1 */ + can1->canctl1 |= 0x80; /* CAN enable */ + udelay (100); + + i = 0; + can1->canctl0 |= 0x02; /* sleep mode */ + /* wait until sleep mode reached */ + while (!(can1->canctl1 & 0x02)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not enter sleep mode!\n", + __FUNCTION__); + return 1; + } + } + i = 0; + can1->canctl0 = 0x01; /* enter init mode */ + /* wait until init mode reached */ + while (!(can1->canctl1 & 0x01)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not enter init mode!\n", + __FUNCTION__); + return 1; + } + } + can1->canctl1 = 0x80; + can1->canctl1 |= 0x40; + can1->canbtr0 = 0x0F; + can1->canbtr1 = 0x7F; + can1->canidac &= ~(0x30); + can1->canidar1 = 0x00; + can1->canidar3 = 0x00; + can1->canidar5 = 0x00; + can1->canidar7 = 0x00; + can1->canidmr0 = 0xFF; + can1->canidmr1 = 0xFF; + can1->canidmr2 = 0xFF; + can1->canidmr3 = 0xFF; + can1->canidmr4 = 0xFF; + can1->canidmr5 = 0xFF; + can1->canidmr6 = 0xFF; + can1->canidmr7 = 0xFF; + + i = 0; + can1->canctl0 &= ~(0x01); /* leave init mode */ + can1->canctl0 &= ~(0x02); + /* wait until init and sleep mode left */ + while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not leave init/sleep mode!\n", + __FUNCTION__); + return 1; + } + } + + /* init CAN 2 */ + can2->canctl1 |= 0x80; /* CAN enable */ + udelay (100); + + i = 0; + can2->canctl0 |= 0x02; /* sleep mode */ + /* wait until sleep mode reached */ + while (!(can2->canctl1 & 0x02)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not enter sleep mode!\n", + __FUNCTION__); + return 1; + } + } + i = 0; + can2->canctl0 = 0x01; /* enter init mode */ + /* wait until init mode reached */ + while (!(can2->canctl1 & 0x01)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not enter init mode!\n", + __FUNCTION__); + return 1; + } + } + can2->canctl1 = 0x80; + can2->canctl1 |= 0x40; + can2->canbtr0 = 0x0F; + can2->canbtr1 = 0x7F; + can2->canidac &= ~(0x30); + can2->canidar1 = 0x00; + can2->canidar3 = 0x00; + can2->canidar5 = 0x00; + can2->canidar7 = 0x00; + can2->canidmr0 = 0xFF; + can2->canidmr1 = 0xFF; + can2->canidmr2 = 0xFF; + can2->canidmr3 = 0xFF; + can2->canidmr4 = 0xFF; + can2->canidmr5 = 0xFF; + can2->canidmr6 = 0xFF; + can2->canidmr7 = 0xFF; + can2->canctl0 &= ~(0x01); /* leave init mode */ + can2->canctl0 &= ~(0x02); + + i = 0; + /* wait until init mode left */ + while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) { + udelay (10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not leave init/sleep mode!\n", + __FUNCTION__); + return 1; + } + } + init_done = 1; + } + return 0; +} + +/* + * Do CAN test + * by sending message between CAN1 and CAN2 + * + * return 1 on CAN failure + * return 0 if no failure + */ +int do_can (char *argv[]) +{ + int i; + struct mpc5xxx_mscan *can1 = + (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0900); + struct mpc5xxx_mscan *can2 = + (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0980); + + /* send a message on CAN1 */ + can1->cantbsel = 0x01; + can1->cantxfg.idr[0] = 0x55; + can1->cantxfg.idr[1] = 0x00; + can1->cantxfg.idr[1] &= ~0x8; + can1->cantxfg.idr[1] &= ~0x10; + can1->cantxfg.dsr[0] = 0xCC; + can1->cantxfg.dlr = 1; + can1->cantxfg.tbpr = 0; + can1->cantflg = 0x01; + + i = 0; + while ((can1->cantflg & 0x01) == 0) { + i++; + if (i == 10) { + printf ("%s: CAN1 send timeout, " + "can not send message!\n", __FUNCTION__); + return 1; + } + udelay (1000); + } + udelay (1000); + + i = 0; + while (!(can2->canrflg & 0x01)) { + i++; + if (i == 10) { + printf ("%s: CAN2 receive timeout, " + "no message received!\n", __FUNCTION__); + return 1; + } + udelay (1000); + } + + if (can2->canrxfg.dsr[0] != 0xCC) { + printf ("%s: CAN2 receive error, " + "data mismatch!\n", __FUNCTION__); + return 1; + } + + /* send a message on CAN2 */ + can2->cantbsel = 0x01; + can2->cantxfg.idr[0] = 0x55; + can2->cantxfg.idr[1] = 0x00; + can2->cantxfg.idr[1] &= ~0x8; + can2->cantxfg.idr[1] &= ~0x10; + can2->cantxfg.dsr[0] = 0xCC; + can2->cantxfg.dlr = 1; + can2->cantxfg.tbpr = 0; + can2->cantflg = 0x01; + + i = 0; + while ((can2->cantflg & 0x01) == 0) { + i++; + if (i == 10) { + printf ("%s: CAN2 send error, " + "can not send message!\n", __FUNCTION__); + return 1; + } + udelay (1000); + } + udelay (1000); + + i = 0; + while (!(can1->canrflg & 0x01)) { + i++; + if (i == 10) { + printf ("%s: CAN1 receive timeout, " + "no message received!\n", __FUNCTION__); + return 1; + } + udelay (1000); + } + + if (can1->canrxfg.dsr[0] != 0xCC) { + printf ("%s: CAN1 receive error 0x%02x\n", + __FUNCTION__, (can1->canrxfg.dsr[0])); + return 1; + } + + return 0; +} +#endif /* CONFIG_BC3450_CAN */ + +/* + * test - BC3450 HW test routines + */ +int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ +#ifdef CONFIG_BC3450_CAN + int rcode; + + can_init (); +#endif /* CONFIG_BC3450_CAN */ + + sm501_gpio_init (); + + if (argc != 2) { + printf ("Usage:%s\n", cmdtp->help); + return 1; + } + + if (strncmp (argv[1], "unit-off", 8) == 0) { + printf ("waiting 2 seconds...\n"); + udelay (2000000); + *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= + ~PWR_OFF; + return 0; + } +#ifdef CONFIG_BC3450_CAN + else if (strncmp (argv[1], "can", 2) == 0) { + rcode = do_can (argv); + if (simple_strtoul (argv[2], NULL, 10) == 2) { + if (rcode == 0) + printf ("OK\n"); + else + printf ("Error\n"); + } + return rcode; + } +#endif /* CONFIG_BC3450_CAN */ + + printf ("Usage:%s\n", cmdtp->help); + return 1; +} + +U_BOOT_CMD (test, 2, 1, cmd_test, "test - unit test routines\n", "\n" +#ifdef CONFIG_BC3450_CAN + "test can\n" + " - connect CAN1 (X8) with CAN2 (X9) for this test\n" +#endif /* CONFIG_BC3450_CAN */ + "test unit-off\n" + " - turns off the BC3450 unit\n" + " WARNING: Unsaved environment variables will be lost!\n"); +#endif /* CFG_CMD_BSP */
diff --git a/board/bc3450/config.mk b/board/bc3450/config.mk new file mode 100644 index 0000000..47e9955 --- /dev/null +++ b/board/bc3450/config.mk
@@ -0,0 +1,41 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# BC3450 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFC000000 boot low (standard configuration with room for max 64 MByte +# Flash ROM) +# 0x00100000 boot from RAM (for testing only) +# + +ifndef TEXT_BASE +## Standard: boot low +TEXT_BASE = 0xFC000000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h new file mode 100644 index 0000000..3f1e169 --- /dev/null +++ b/board/bc3450/mt48lc16m16a2-75.h
@@ -0,0 +1,47 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ +/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ +#define SDRAM_CONFIG2 0x8AD70000 +/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif
diff --git a/board/bc3450/u-boot.lds b/board/bc3450/u-boot.lds new file mode 100644 index 0000000..93b98a8 --- /dev/null +++ b/board/bc3450/u-boot.lds
@@ -0,0 +1,124 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +}
diff --git a/board/delta/delta.c b/board/delta/delta.c index b7671dd..b127ac8 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c
@@ -28,6 +28,8 @@ #include <common.h> #include <i2c.h> #include <da9030.h> +#include <malloc.h> +#include <command.h> #include <asm/arch/pxa-regs.h> DECLARE_GLOBAL_DATA_PTR; @@ -35,6 +37,9 @@ /* ------------------------------------------------------------------------- */ static void init_DA9030(void); +static void keys_init(void); +static void get_pressed_keys(uchar *s); +static uchar *key_match(uchar *kbd_data); /* * Miscelaneous platform dependent initialisations @@ -56,13 +61,216 @@ int board_late_init(void) { +#ifdef DELTA_CHECK_KEYBD + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + char *str; + int i; +#endif /* DELTA_CHECK_KEYBD */ + setenv("stdout", "serial"); setenv("stderr", "serial"); + +#ifdef DELTA_CHECK_KEYBD + keys_init(); + + memset(kbd_data, '\0', KEYBD_DATALEN); + + /* check for pressed keys and setup keybd_env */ + get_pressed_keys(kbd_data); + + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + } + setenv ("keybd", keybd_env); + + str = strdup ((char *)key_match (kbd_data)); /* decode keys */ + +# ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ + setenv ("preboot", str); /* set or delete definition */ +# endif /* CONFIG_PREBOOT */ + if (str != NULL) { + free (str); + } +#endif /* DELTA_CHECK_KEYBD */ + init_DA9030(); return 0; } +/* + * Magic Key Handling, mainly copied from board/lwmon/lwmon.c + */ +#ifdef DELTA_CHECK_KEYBD + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +/* + * Get pressed keys + * s is a buffer of size KEYBD_DATALEN-1 + */ +static void get_pressed_keys(uchar *s) +{ + unsigned long val; + val = GPLR3; + + if(val & (1<<31)) + *s++ = KEYBD_KP_DKIN0; + if(val & (1<<18)) + *s++ = KEYBD_KP_DKIN1; + if(val & (1<<29)) + *s++ = KEYBD_KP_DKIN2; + if(val & (1<<22)) + *s++ = KEYBD_KP_DKIN5; +} + +static void keys_init() +{ + CKENB |= CKENB_7_GPIO; + udelay(100); + + /* Configure GPIOs */ + GPIO127 = 0xa840; /* KP_DKIN0 */ + GPIO114 = 0xa840; /* KP_DKIN1 */ + GPIO125 = 0xa840; /* KP_DKIN2 */ + GPIO118 = 0xa840; /* KP_DKIN5 */ + + /* Configure GPIOs as inputs */ + GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22); + GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22); + + udelay(100); +} + +static int compare_magic (uchar *kbd_data, uchar *str) +{ + /* uchar compare[KEYBD_DATALEN-1]; */ + uchar compare[KEYBD_DATALEN]; + char *nxt; + int i; + + /* Don't include modifier byte */ + /* memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); */ + memcpy (compare, kbd_data, KEYBD_DATALEN); + + for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { + uchar c; + int k; + + c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); + + if (str == (uchar *)nxt) { /* invalid character */ + break; + } + + /* + * Check if this key matches the input. + * Set matches to zero, so they match only once + * and we can find duplicates or extra keys + */ + for (k = 0; k < sizeof(compare); ++k) { + if (compare[k] == '\0') /* only non-zero entries */ + continue; + if (c == compare[k]) { /* found matching key */ + compare[k] = '\0'; + break; + } + } + if (k == sizeof(compare)) { + return -1; /* unmatched key */ + } + } + + /* + * A full match leaves no keys in the `compare' array, + */ + for (i = 0; i < sizeof(compare); ++i) { + if (compare[i]) + { + return -1; + } + } + + return 0; +} + + +static uchar *key_match (uchar *kbd_data) +{ + char magic[sizeof (kbd_magic_prefix) + 1]; + uchar *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can pe appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); +#if 0 + printf ("### Check magic \"%s\"\n", magic); +#endif + if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { + char cmd_name[sizeof (kbd_command_prefix) + 1]; + char *cmd; + + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + + cmd = getenv (cmd_name); +#if 0 + printf ("### Set PREBOOT to $(%s): \"%s\"\n", + cmd_name, cmd ? cmd : "<<NULL>>"); +#endif + *kbd_data = *suffix; + return ((uchar *)cmd); + } + } +#if 0 + printf ("### Delete PREBOOT\n"); +#endif + *kbd_data = '\0'; + return (NULL); +} + +int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + int i; + + /* Read keys */ + get_pressed_keys(kbd_data); + puts ("Keys:"); + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + printf (" %02x", kbd_data[i]); + } + putc ('\n'); + setenv ("keybd", keybd_env); + return 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "kbd - read keyboard status\n", + NULL +); + +#endif /* DELTA_CHECK_KEYBD */ + + int dram_init (void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
diff --git a/board/nc650/nand.c b/board/nc650/nand.c index f27e536..de54386 100644 --- a/board/nc650/nand.c +++ b/board/nc650/nand.c
@@ -37,22 +37,22 @@ struct nand_chip *this = mtd->priv; switch(cmd) { - case NAND_CTL_SETCLE: - this->IO_ADDR_W += 2; - break; - case NAND_CTL_CLRCLE: - this->IO_ADDR_W -= 2; - break; - case NAND_CTL_SETALE: - this->IO_ADDR_W += 1; - break; - case NAND_CTL_CLRALE: - this->IO_ADDR_W -= 1; - break; - case NAND_CTL_SETNCE: - case NAND_CTL_CLRNCE: - /* nop */ - break; + case NAND_CTL_SETCLE: + this->IO_ADDR_W += 2; + break; + case NAND_CTL_CLRCLE: + this->IO_ADDR_W -= 2; + break; + case NAND_CTL_SETALE: + this->IO_ADDR_W += 1; + break; + case NAND_CTL_CLRALE: + this->IO_ADDR_W -= 1; + break; + case NAND_CTL_SETNCE: + case NAND_CTL_CLRNCE: + /* nop */ + break; } } #elif defined(CONFIG_IDS852_REV2) @@ -64,24 +64,24 @@ struct nand_chip *this = mtd->priv; switch(cmd) { - case NAND_CTL_SETCLE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0; - break; - case NAND_CTL_CLRCLE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; - break; - case NAND_CTL_SETALE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0; - break; - case NAND_CTL_CLRALE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; - break; - case NAND_CTL_SETNCE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; - break; - case NAND_CTL_CLRNCE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0; - break; + case NAND_CTL_SETCLE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0; + break; + case NAND_CTL_CLRCLE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; + break; + case NAND_CTL_SETALE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0; + break; + case NAND_CTL_CLRALE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; + break; + case NAND_CTL_SETNCE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; + break; + case NAND_CTL_CLRNCE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0; + break; } } #else
diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c index c90ac9c..8a6b5b0 100644 --- a/board/nc650/nc650.c +++ b/board/nc650/nc650.c
@@ -265,8 +265,8 @@ int iCompatMode = 0; char *pParam = NULL; char *envlb; - - /* + + /* First byte in CPLD read address space signals compatibility mode 0 - cp850 1 - kp852 @@ -274,9 +274,9 @@ pParam = (char*)(CFG_CPLD_BASE); if( *pParam != 0) iCompatMode = 1; - + if ( iCompatMode != 0) { - /* + /* In KP852 compatibility mode we have to write to DPRAM as early as possible the binary coded line config and board name. @@ -288,7 +288,7 @@ setenv( DPRAM_VARNAME, DEFAULT_LB); envlb = DEFAULT_LB; } - + /* Status string */ printf("Mode: KP852(LB=%s)\n", envlb); @@ -305,7 +305,7 @@ } else { puts("Mode: CP850\n"); } - + return 0; } #endif
diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile index 999647f..f3ad674 100644 --- a/board/zylonite/Makefile +++ b/board/zylonite/Makefile
@@ -1,4 +1,3 @@ - # # (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,12 +20,11 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := zylonite.o flash.o +OBJS := zylonite.o nand.o SOBJS := lowlevel_init.o $(LIB): $(OBJS) $(SOBJS)
diff --git a/board/zylonite/config.mk b/board/zylonite/config.mk index 09b0f71..b5d5955 100644 --- a/board/zylonite/config.mk +++ b/board/zylonite/config.mk
@@ -2,3 +2,5 @@ #TEXT_BASE = 0xa1700000 #TEXT_BASE = 0xa3080000 TEXT_BASE = 0xa3008000 + +BOARDLIBS = drivers/nand/libnand.a
diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S index c3bb4eb..da01765 100644 --- a/board/zylonite/lowlevel_init.S +++ b/board/zylonite/lowlevel_init.S
@@ -235,6 +235,7 @@ orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access str r1, [r0] +#ifndef CFG_SKIP_DRAM_SCRUB /* scrub/init SDRAM if enabled/present */ /* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */ /* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */ @@ -254,6 +255,7 @@ stmia r8!, {r0-r7} beq 15f b 10b +#endif /* CFG_SKIP_DRAM_SCRUB */ 15: /* Mask all interrupts */
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c new file mode 100644 index 0000000..5d2cd65 --- /dev/null +++ b/board/zylonite/nand.c
@@ -0,0 +1,584 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#ifdef CONFIG_NEW_NAND_CODE + +#include <nand.h> +#include <asm/arch/pxa-regs.h> + +#ifdef CFG_DFC_DEBUG1 +# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG1(fmt, args...) +#endif + +#ifdef CFG_DFC_DEBUG2 +# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG2(fmt, args...) +#endif + +#ifdef CFG_DFC_DEBUG3 +# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG3(fmt, args...) +#endif + +#define MIN(x, y) ((x < y) ? x : y) + +/* These really don't belong here, as they are specific to the NAND Model */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr delta_bbt_descr = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct nand_oobinfo delta_oob = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 6, + .eccpos = {2, 3, 4, 5, 6, 7}, + .oobfree = { {8, 2}, {12, 4} } +}; + + +/* + * not required for Monahans DFC + */ +static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + return; +} + +#if 0 +/* read device ready pin */ +static int dfc_device_ready(struct mtd_info *mtdinfo) +{ + if(NDSR & NDSR_RDY) + return 1; + else + return 0; + return 0; +} +#endif + +/* + * Write buf to the DFC Controller Data Buffer + */ +static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + unsigned long bytes_multi = len & 0xfffffffc; + unsigned long rest = len & 0x3; + unsigned long *long_buf; + int i; + + DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf)); + if(bytes_multi) { + for(i=0; i<bytes_multi; i+=4) { + long_buf = (unsigned long*) &buf[i]; + NDDB = *long_buf; + } + } + if(rest) { + printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n"); + } + return; +} + + +/* + * These functions are quite problematic for the DFC. Luckily they are + * not used in the current nand code, except for nand_command, which + * we've defined our own anyway. The problem is, that we always need + * to write 4 bytes to the DFC Data Buffer, but in these functions we + * don't know if to buffer the bytes/half words until we've gathered 4 + * bytes or if to send them straight away. + * + * Solution: Don't use these with Mona's DFC and complain loudly. + */ +static void dfc_write_word(struct mtd_info *mtd, u16 word) +{ + printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n"); +} +static void dfc_write_byte(struct mtd_info *mtd, u_char byte) +{ + printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n"); +} + +/* The original: + * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len) + * + * Shouldn't this be "u_char * const buf" ? + */ +static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) +{ + int i=0, j; + + /* we have to be carefull not to overflow the buffer if len is + * not a multiple of 4 */ + unsigned long bytes_multi = len & 0xfffffffc; + unsigned long rest = len & 0x3; + unsigned long *long_buf; + + DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len); + /* if there are any, first copy multiple of 4 bytes */ + if(bytes_multi) { + for(i=0; i<bytes_multi; i+=4) { + long_buf = (unsigned long*) &buf[i]; + *long_buf = NDDB; + } + } + + /* ...then the rest */ + if(rest) { + unsigned long rest_data = NDDB; + for(j=0;j<rest; j++) + buf[i+j] = (u_char) ((rest_data>>j) & 0xff); + } + + return; +} + +/* + * read a word. Not implemented as not used in NAND code. + */ +static u16 dfc_read_word(struct mtd_info *mtd) +{ + printf("dfc_write_byte: UNIMPLEMENTED.\n"); + return 0; +} + +/* global var, too bad: mk@tbd: move to ->priv pointer */ +static unsigned long read_buf = 0; +static int bytes_read = -1; + +/* + * read a byte from NDDB Because we can only read 4 bytes from NDDB at + * a time, we buffer the remaining bytes. The buffer is reset when a + * new command is sent to the chip. + * + * WARNING: + * This function is currently only used to read status and id + * bytes. For these commands always 8 bytes need to be read from + * NDDB. So we read and discard these bytes right now. In case this + * function is used for anything else in the future, we must check + * what was the last command issued and read the appropriate amount of + * bytes respectively. + */ +static u_char dfc_read_byte(struct mtd_info *mtd) +{ + unsigned char byte; + unsigned long dummy; + + if(bytes_read < 0) { + read_buf = NDDB; + dummy = NDDB; + bytes_read = 0; + } + byte = (unsigned char) (read_buf>>(8 * bytes_read++)); + if(bytes_read >= 4) + bytes_read = -1; + + DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf); + return byte; +} + +/* calculate delta between OSCR values start and now */ +static unsigned long get_delta(unsigned long start) +{ + unsigned long cur = OSCR; + + if(cur < start) /* OSCR overflowed */ + return (cur + (start^0xffffffff)); + else + return (cur - start); +} + +/* delay function, this doesn't belong here */ +static void wait_us(unsigned long us) +{ + unsigned long start = OSCR; + us *= OSCR_CLK_FREQ; + + while (get_delta(start) < us) { + /* do nothing */ + } +} + +static void dfc_clear_nddb(void) +{ + NDCR &= ~NDCR_ND_RUN; + wait_us(CFG_NAND_OTHER_TO); +} + +/* wait_event with timeout */ +static unsigned long dfc_wait_event(unsigned long event) +{ + unsigned long ndsr, timeout, start = OSCR; + + if(!event) + return 0xff000000; + else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) + timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; + else + timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; + + while(1) { + ndsr = NDSR; + if(ndsr & event) { + NDSR |= event; + break; + } + if(get_delta(start) > timeout) { + DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event); + return 0xff000000; + } + + } + return ndsr; +} + +/* we don't always wan't to do this */ +static void dfc_new_cmd(void) +{ + int retry = 0; + unsigned long status; + + while(retry++ <= CFG_NAND_SENDCMD_RETRY) { + /* Clear NDSR */ + NDSR = 0xFFF; + + /* set NDCR[NDRUN] */ + if(!(NDCR & NDCR_ND_RUN)) + NDCR |= NDCR_ND_RUN; + + status = dfc_wait_event(NDSR_WRCMDREQ); + + if(status & NDSR_WRCMDREQ) + return; + + DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry); + dfc_clear_nddb(); + } + DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry); +} + +/* this function is called after Programm and Erase Operations to + * check for success or failure */ +static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long ndsr=0, event=0; + + if(state == FL_WRITING) { + event = NDSR_CS0_CMDD | NDSR_CS0_BBD; + } else if(state == FL_ERASING) { + event = NDSR_CS0_CMDD | NDSR_CS0_BBD; + } + + ndsr = dfc_wait_event(event); + + if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000)) + return(0x1); /* Status Read error */ + return 0; +} + +/* cmdfunc send commands to the DFC */ +static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + /* register struct nand_chip *this = mtd->priv; */ + unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0; + + /* clear the ugly byte read buffer */ + bytes_read = -1; + read_buf = 0; + + switch (command) { + case NAND_CMD_READ0: + DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + dfc_new_cmd(); + ndcb0 = (NAND_CMD_READ0 | (4<<16)); + column >>= 1; /* adjust for 16 bit bus */ + ndcb1 = (((column>>1) & 0xff) | + ((page_addr<<8) & 0xff00) | + ((page_addr<<8) & 0xff0000) | + ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_READ1: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n"); + goto end; + case NAND_CMD_READOOB: + DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n"); + goto end; + case NAND_CMD_READID: + dfc_new_cmd(); + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n"); + ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/ + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_PAGEPROG: + /* sent as a multicommand in NAND_CMD_SEQIN */ + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n"); + goto end; + case NAND_CMD_ERASE1: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + dfc_new_cmd(); + ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16)); + ndcb1 = (page_addr & 0x00ffffff); + goto write_cmd; + case NAND_CMD_ERASE2: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n"); + goto end; + case NAND_CMD_SEQIN: + /* send PAGE_PROG command(0x1080) */ + dfc_new_cmd(); + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16)); + column >>= 1; /* adjust for 16 bit bus */ + ndcb1 = (((column>>1) & 0xff) | + ((page_addr<<8) & 0xff00) | + ((page_addr<<8) & 0xff0000) | + ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ + event = NDSR_WRDREQ; + goto write_cmd; + case NAND_CMD_STATUS: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n"); + dfc_new_cmd(); + ndcb0 = NAND_CMD_STATUS | (4<<21); + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_RESET: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n"); + ndcb0 = NAND_CMD_RESET | (5<<21); + event = NDSR_CS0_CMDD; + goto write_cmd; + default: + printk("dfc_cmdfunc: error, unsupported command.\n"); + goto end; + } + + write_cmd: + NDCB0 = ndcb0; + NDCB0 = ndcb1; + NDCB0 = ndcb2; + + /* wait_event: */ + dfc_wait_event(event); + end: + return; +} + +static void dfc_gpio_init(void) +{ + DFC_DEBUG2("Setting up DFC GPIO's.\n"); + + /* no idea what is done here, see zylonite.c */ + GPIO4 = 0x1; + + DF_ALE_WE1 = 0x00000001; + DF_ALE_WE2 = 0x00000001; + DF_nCS0 = 0x00000001; + DF_nCS1 = 0x00000001; + DF_nWE = 0x00000001; + DF_nRE = 0x00000001; + DF_IO0 = 0x00000001; + DF_IO8 = 0x00000001; + DF_IO1 = 0x00000001; + DF_IO9 = 0x00000001; + DF_IO2 = 0x00000001; + DF_IO10 = 0x00000001; + DF_IO3 = 0x00000001; + DF_IO11 = 0x00000001; + DF_IO4 = 0x00000001; + DF_IO12 = 0x00000001; + DF_IO5 = 0x00000001; + DF_IO13 = 0x00000001; + DF_IO6 = 0x00000001; + DF_IO14 = 0x00000001; + DF_IO7 = 0x00000001; + DF_IO15 = 0x00000001; + + DF_nWE = 0x1901; + DF_nRE = 0x1901; + DF_CLE_NOE = 0x1900; + DF_ALE_WE1 = 0x1901; + DF_INT_RnB = 0x1900; +} + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand_new.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; + + /* set up GPIO Control Registers */ + dfc_gpio_init(); + + /* turn on the NAND Controller Clock (104 MHz @ D0) */ + CKENA |= (CKENA_4_NAND | CKENA_9_SMC); + +#undef CFG_TIMING_TIGHT +#ifndef CFG_TIMING_TIGHT + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), + DFC_MAX_tCH); + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), + DFC_MAX_tCS); + tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1), + DFC_MAX_tWH); + tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1), + DFC_MAX_tWP); + tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1), + DFC_MAX_tRH); + tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1), + DFC_MAX_tRP); + tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1), + DFC_MAX_tR); + tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1), + DFC_MAX_tWHR); + tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1), + DFC_MAX_tAR); +#else /* this is the tight timing */ + + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), + DFC_MAX_tCH); + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), + DFC_MAX_tCS); + tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)), + DFC_MAX_tWH); + tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)), + DFC_MAX_tWP); + tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)), + DFC_MAX_tRH); + tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)), + DFC_MAX_tRP); + tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2), + DFC_MAX_tR); + tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2), + DFC_MAX_tWHR); + tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2), + DFC_MAX_tAR); +#endif /* CFG_TIMING_TIGHT */ + + + DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR); + + /* tRP value is split in the register */ + if(tRP & (1 << 4)) { + tRP_high = 1; + tRP &= ~(1 << 4); + } else { + tRP_high = 0; + } + + NDTR0CS0 = (tCH << 19) | + (tCS << 16) | + (tWH << 11) | + (tWP << 8) | + (tRP_high << 6) | + (tRH << 3) | + (tRP << 0); + + NDTR1CS0 = (tR << 16) | + (tWHR << 4) | + (tAR << 0); + + /* If it doesn't work (unlikely) think about: + * - ecc enable + * - chip select don't care + * - read id byte count + * + * Intentionally enabled by not setting bits: + * - dma (DMA_EN) + * - page size = 512 + * - cs don't care, see if we can enable later! + * - row address start position (after second cycle) + * - pages per block = 32 + * - ND_RDY : clears command buffer + */ + /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ + + NDCR = (NDCR_SPARE_EN | /* use the spare area */ + NDCR_DWIDTH_C | /* 16bit DFC data bus width */ + NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ + (2 << 16) | /* read id count = 7 ???? mk@tbd */ + NDCR_ND_ARB_EN | /* enable bus arbiter */ + NDCR_RDYM | /* flash device ready ir masked */ + NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */ + NDCR_CS1_PAGEDM | + NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */ + NDCR_CS1_CMDDM | + NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */ + NDCR_CS1_BBDM | + NDCR_DBERRM | /* double bit error ir masked */ + NDCR_SBERRM | /* single bit error ir masked */ + NDCR_WRDREQM | /* write data request ir masked */ + NDCR_RDDREQM | /* read data request ir masked */ + NDCR_WRCMDREQM); /* write command request ir masked */ + + + /* wait 10 us due to cmd buffer clear reset */ + /* wait(10); */ + + + nand->hwcontrol = dfc_hwcontrol; +/* nand->dev_ready = dfc_device_ready; */ + nand->eccmode = NAND_ECC_SOFT; + nand->options = NAND_BUSWIDTH_16; + nand->waitfunc = dfc_wait; + nand->read_byte = dfc_read_byte; + nand->write_byte = dfc_write_byte; + nand->read_word = dfc_read_word; + nand->write_word = dfc_write_word; + nand->read_buf = dfc_read_buf; + nand->write_buf = dfc_write_buf; + + nand->cmdfunc = dfc_cmdfunc; + nand->autooob = &delta_oob; + nand->badblock_pattern = &delta_bbt_descr; +} + +#else + #error "U-Boot legacy NAND support not available for Monahans DFC." +#endif +#endif
diff --git a/common/cmd_load.c b/common/cmd_load.c index 2432ee2..f63b8e8 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c
@@ -33,9 +33,12 @@ DECLARE_GLOBAL_DATA_PTR; +#if (CONFIG_COMMANDS & CFG_CMD_LOADB) +static ulong load_serial_ymodem (ulong offset); +#endif + #if (CONFIG_COMMANDS & CFG_CMD_LOADS) static ulong load_serial (ulong offset); -static ulong load_serial_ymodem (ulong offset); static int read_record (char *buf, ulong len); # if (CONFIG_COMMANDS & CFG_CMD_SAVES) static int save_serial (ulong offset, ulong size);
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h new file mode 100644 index 0000000..5b54f30 --- /dev/null +++ b/include/configs/BC3450.h
@@ -0,0 +1,568 @@ +/* + * -- Version 1.1 -- + * + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * (C) Copyright 2005 + * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de. + * + * History: + * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ +#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */ + +#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */ +#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */ +#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */ +#define CONFIG_BC3450_USB 1 /* + USB support */ +# define CONFIG_FAT 1 /* + FAT support */ +# define CONFIG_EXT2 1 /* + EXT2 support */ +#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */ +#undef CONFIG_BC3450_CAN /* + CAN transceiver */ +#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */ +#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */ +#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */ +#define CONFIG_BC3450_FP 1 /* + enable FP O/P */ +#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * AT-PS/2 Multiplexer + */ +#ifdef CONFIG_BC3450_PS2 +# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ +# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ +# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ +# define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ +# define CONFIG_BOARD_EARLY_INIT_R +#endif /* CONFIG_BC3450_PS2 */ + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +# define CONFIG_PCI 1 +# define CONFIG_PCI_PNP 1 +/* #define CONFIG_PCI_SCAN_SHOW 1 */ + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_NET_MULTI 1 +/*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */ +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 + +#ifdef CONFIG_PCI +# define ADD_PCI_CMD CFG_CMD_PCI +#else +# define ADD_PCI_CMD 0 +#endif + +/* + * Video console + */ +# define CONFIG_VIDEO +# define CONFIG_VIDEO_SM501 +# define CONFIG_VIDEO_SM501_32BPP +# define CONFIG_CFB_CONSOLE +# define CONFIG_VIDEO_LOGO +# define CONFIG_VGA_AS_SINGLE_DEVICE +# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */ +# define CONFIG_VIDEO_SW_CURSOR +# define CONFIG_SPLASH_SCREEN +# define CFG_CONSOLE_IS_IN_ENV + +#ifdef CONFIG_VIDEO +# define ADD_BMP_CMD CFG_CMD_BMP +#else +# define ADD_BMP_CMD 0 +#endif + +/* + * Partitions + */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* + * USB + */ +#ifdef CONFIG_BC3450_USB +# define CONFIG_USB_OHCI +# define ADD_USB_CMD CFG_CMD_USB +# define CONFIG_USB_STORAGE +#else /* !CONFIG_BC3450_USB */ +# define ADD_USB_CMD 0 +#endif /* CONFIG_BC3450_USB */ + +/* + * POST support + */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_I2C) + +#ifdef CONFIG_POST +# define CFG_CMD_POST_DIAG CFG_CMD_DIAG +/* preserve space for the post_word at end of on-chip SRAM */ +# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 +#else +# define CFG_CMD_POST_DIAG 0 +#endif /* CONFIG_POST */ + +/* + * IDE + */ +#ifdef CONFIG_BC3450_IDE +# define ADD_IDE_CMD CFG_CMD_IDE +#else +# define ADD_IDE_CMD 0 +#endif /* CONFIG_BC3450_IDE */ + +/* + * Filesystem support + */ +#if defined (CONFIG_BC3450_IDE) || defined (CONFIG_BC3450_USB) +#ifdef CONFIG_FAT +# define ADD_FAT_CMD CFG_CMD_FAT +#else +# define ADD_FAT_CMD 0 +#endif /* CONFIG_FAT */ + +#ifdef CONFIG_EXT2 +# define ADD_EXT2_CMD CFG_CMD_EXT2 +#else +# define ADD_EXT2_CMD 0 +#endif /* CONFIG_EXT2 */ +#endif /* CONFIG_BC3450_IDE / _USB */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_BMP_CMD | \ + ADD_IDE_CMD | \ + ADD_FAT_CMD | \ + ADD_EXT2_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP | \ + CFG_CMD_BSP) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_TIMESTAMP /* display image timestamps */ + +#if (TEXT_BASE == 0xFC000000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo;" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ipaddr=192.168.1.10\0" \ + "serverip=192.168.1.3\0" \ + "netmask=255.255.255.0\0" \ + "hostname=bc3450\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "kernel_addr=fc0a0000\0" \ + "ramdisk_addr=fc1c0000\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ideargs=setenv bootargs root=/dev/hda2 ro\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off panic=1\0" \ + "addcons=setenv bootargs $(bootargs) " \ + "console=ttyS0,$(baudrate) console=tty0\0" \ + "flash_self=run ramargs addip addcons;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile); " \ + "run nfsargs addip addcons; bootm\0" \ + "ide_nfs=run nfsargs addip addcons; " \ + "disk 200000 0:1; bootm\0" \ + "ide_ide=run ideargs addip addcons; " \ + "disk 200000 0:1; bootm\0" \ + "usb_self=run usbload; run ramargs addip addcons; " \ + "bootm 200000 400000\0" \ + "usbload=usb reset; usb scan; usbboot 200000 0:1; " \ + "usbboot 400000 0:2\0" \ + "bootfile=uImage\0" \ + "load=tftp 200000 $(u-boot)\0" \ + "u-boot=u-boot.bin\0" \ + "update=protect off FC000000 FC05FFFF;" \ + "erase FC000000 FC05FFFF;" \ + "cp.b 200000 FC000000 $(filesize);" \ + "protect on FC000000 FC05FFFF\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +/* + * PCI Bus clocking configuration + * + * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet + * hasn't been tested with a IPB Bus Clock of 66 MHz. + */ +#if defined(CFG_IPBSPEED_133) +# define CFG_PCISPEED_66 /* define for 66MHz speed */ +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #2 */ + +/* + * I2C clock frequency + * + * Please notice, that the resulting clock frequency could differ from the + * configured value. This is because the I2C clock is derived from system + * clock over a frequency divider with only a few divider values. U-boot + * calculates the best approximation for CFG_I2C_SPEED. However the calculated + * approximation allways lies below the configured value, never above. + */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration for I²C EEPROM M24C32 + * M24C64 should work also. For other EEPROMs config should be verified. + * + * The TQM5200 module may hold an EEPROM at address 0x50. + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 + +/* + * RTC configuration + */ +#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231) +# define CONFIG_RTC_M41T11 1 +# define CFG_I2C_RTC_ADDR 0x68 +#else +# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */ +# define CONFIG_BOARD_EARLY_INIT_R +#endif + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ + +/* use CFI flash driver if no module variant is spezified */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ + +#if !defined(CFG_LOWBOOT) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) +#else /* CFG_LOWBOOT */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) +#endif /* CFG_LOWBOOT */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* Dynamic MTD partition support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM5200-0" +#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ + "1408k(kernel)," \ + "2m(initrd)," \ + "4m(small-fs)," \ + "16m(big-fs)," \ + "8m(misc)" + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +# define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +# define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif /*CONFIG_POST*/ + +#define CFG_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + * + * Define CONFIG_FEC10MBIT to force FEC at 10MBIT + */ +#define CONFIG_MPC5xxx_FEC 1 +#undef CONFIG_FEC_10MBIT +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration on BC3450 + * + * PSC1: UART1 (Service-UART) [0x xxxxxxx4] + * PSC2: UART2 [0x xxxxxx4x] + * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x] + * PSC3: USB2 [0x xxxxx1xx] + * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx] + * (this has to match + * CONFIG_USB_CONFIG which is + * used by usb_ohci.c to set + * the USB ports) + * Eth: 10/100Mbit Ethernet [0x xxx0xxxx] + * (this is reset to '5' + * in FEC driver: fec.c) + * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx] + * ATA/CS: ??? [0x x1xxxxxx] + * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx] + * CS1: Use Pin gpio_wkup_6 as second + * SDRAM chip select (mem_cs1) + * Timer: CAN2 / SPI + * I2C: CAN1 / I²C2 [0x bxxxxxxx] + */ +#ifdef CONFIG_BC3450_AC97 +# define CFG_GPS_PORT_CONFIG 0xb1502124 +#else /* PSC2=UART2 */ +# define CFG_GPS_PORT_CONFIG 0xb1502144 +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max no of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg. Buffer Size */ + +#define CFG_ALT_MEMTEST /* Enable an alternative, */ + /* more extensive mem test */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* dec freq: 1ms ticks */ + +/* + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +# define CFG_HID0_INIT HID0_ICE | HID0_ICFI +# define CFG_HID0_FINAL HID0_ICE +#else +# define CFG_HID0_INIT 0 +# define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#ifdef CFG_PCISPEED_66 +# define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ +#else +# define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ +#endif +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* automatic configuration of chip selects */ +#ifdef CONFIG_TQM5200 +# define CONFIG_LAST_STAGE_INIT +#endif /* CONFIG_TQM5200 */ + +/* + * SRAM - Do not map below 2 GB in address space, because this area is used + * for SDRAM autosizing. + */ +#ifdef CONFIG_TQM5200 +# define CFG_CS2_START 0xE5000000 +# define CFG_CS2_SIZE 0x100000 /* 1 MByte */ +# define CFG_CS2_CFG 0x0004D930 +#endif /* CONFIG_TQM5200 */ + +/* + * Grafic controller - Do not map below 2 GB in address space, because this + * area is used for SDRAM autosizing. + */ +#ifdef CONFIG_TQM5200 +# define SM501_FB_BASE 0xE0000000 +# define CFG_CS1_START (SM501_FB_BASE) +# define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ +# define CFG_CS1_CFG 0x8F48FF70 +# define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 +#endif /* CONFIG_TQM5200 */ + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */ + /* flash and SM501 */ + +#define CFG_RESET_ADDRESS 0xff000000 + +/* + * USB stuff + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */ + +/* + * IDE/ATA stuff Supports IDE harddisk + */ +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#endif /* __CONFIG_H */
diff --git a/include/configs/delta.h b/include/configs/delta.h index e4c8cca..91284fd 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h
@@ -66,6 +66,17 @@ #define CFG_I2C_INIT_BOARD 1 /* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */ +#define DELTA_CHECK_KEYBD 1 /* check for keys pressed during boot */ +#define CONFIG_PREBOOT "\0" + +#ifdef DELTA_CHECK_KEYBD +# define KEYBD_DATALEN 4 /* we have four keys */ +# define KEYBD_KP_DKIN0 0x1 /* vol+ */ +# define KEYBD_KP_DKIN1 0x2 /* vol- */ +# define KEYBD_KP_DKIN2 0x3 /* multi */ +# define KEYBD_KP_DKIN5 0x4 /* SWKEY_GN */ +#endif /* DELTA_CHECK_KEYBD */ + /* * select serial console configuration */
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 4232d50..c6aa8ec 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h
@@ -76,14 +76,17 @@ #define CONFIG_BAUDRATE 115200 -/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */ #ifdef TURN_ON_ETHERNET # define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) #else -# define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) +# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_ENV \ + | CFG_CMD_NAND) \ + & ~(CFG_CMD_NET \ + | CFG_CMD_FLASH \ + | CFG_CMD_IMLS)) #endif - /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -127,8 +130,11 @@ #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ +#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */ + +/* Monahans Core Frequency */ +#define CFG_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ +#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */ /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -159,98 +165,64 @@ #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ +#define CFG_DRAM_BASE 0x80000000 /* at CS0 */ +#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */ -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -#define FPGA_REGS_BASE_PHYSICAL 0x08000000 - -/* - * GPIO settings - */ -#define CFG_GPSR0_VAL 0x00008000 -#define CFG_GPSR1_VAL 0x00FC0382 -#define CFG_GPSR2_VAL 0x0001FFFF -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -#define CFG_GPDR0_VAL 0x0060A800 -#define CFG_GPDR1_VAL 0x00FF0382 -#define CFG_GPDR2_VAL 0x0001C000 -#define CFG_GAFR0_L_VAL 0x98400000 -#define CFG_GAFR0_U_VAL 0x00002950 -#define CFG_GAFR1_L_VAL 0x000A9558 -#define CFG_GAFR1_U_VAL 0x0005AAAA -#define CFG_GAFR2_L_VAL 0xA0000000 -#define CFG_GAFR2_U_VAL 0x00000002 - -#define CFG_PSSR_VAL 0x20 - -/* - * Memory settings - */ -#define CFG_MSC0_VAL 0x23F223F2 -#define CFG_MSC1_VAL 0x3FF1A441 -#define CFG_MSC2_VAL 0x7FF97FF1 -#define CFG_MDCNFG_VAL 0x00001AC9 -#define CFG_MDREFR_VAL 0x00018018 -#define CFG_MDMRS_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 - -#define _LED 0x08000010 -#define LED_BLANK 0x08000040 - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -/* NOTE: many default partitioning schemes assume the kernel starts at the - * second sector, not an environment. You have been warned! - */ -#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) +#undef CFG_SKIP_DRAM_SCRUB /* - * FPGA Offsets + * NAND Flash */ -#define WHOAMI_OFFSET 0x00 -#define HEXLED_OFFSET 0x10 -#define BLANKLED_OFFSET 0x40 -#define DISCRETELED_OFFSET 0x40 -#define CNFG_SWITCHES_OFFSET 0x50 -#define USER_SWITCHES_OFFSET 0x60 -#define MISC_WR_OFFSET 0x80 -#define MISC_RD_OFFSET 0x90 -#define INT_MASK_OFFSET 0xC0 -#define INT_CLEAR_OFFSET 0xD0 -#define GP_OFFSET 0x100 +/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ +#define CONFIG_NEW_NAND_CODE +#define CFG_NAND0_BASE 0x0 +#undef CFG_NAND1_BASE + +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ + +/* nand timeout values */ +#define CFG_NAND_PROG_ERASE_TO 3000 +#define CFG_NAND_OTHER_TO 100 +#define CFG_NAND_SENDCMD_RETRY 3 +#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ + +/* NAND Timing Parameters (in ns) */ +#define NAND_TIMING_tCH 10 +#define NAND_TIMING_tCS 0 +#define NAND_TIMING_tWH 20 +#define NAND_TIMING_tWP 40 + +#define NAND_TIMING_tRH 20 +#define NAND_TIMING_tRP 40 + +#define NAND_TIMING_tR 11123 +#define NAND_TIMING_tWHR 100 +#define NAND_TIMING_tAR 10 + +/* NAND debugging */ +#define CFG_DFC_DEBUG1 /* usefull */ +#undef CFG_DFC_DEBUG2 /* noisy */ +#undef CFG_DFC_DEBUG3 /* extremly noisy */ + +#define CONFIG_MTD_DEBUG +#define CONFIG_MTD_DEBUG_VERBOSE 1 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NO_FLASH 1 + +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x40000 +#define CFG_ENV_OFFSET_REDUND 0x44000 +#define CFG_ENV_SIZE 0x4000 + #endif /* __CONFIG_H */
diff --git a/include/linux/string.h b/include/linux/string.h index 1a45fd3..6239039 100644 --- a/include/linux/string.h +++ b/include/linux/string.h
@@ -38,7 +38,7 @@ #ifndef __HAVE_ARCH_STRNCMP extern int strncmp(const char *,const char *,__kernel_size_t); #endif -#ifndef __HAVE_ARCH_STRNICMP +#if 0 /* not used - was: #ifndef __HAVE_ARCH_STRNICMP */ extern int strnicmp(const char *, const char *, __kernel_size_t); #endif #ifndef __HAVE_ARCH_STRCHR
diff --git a/lib_arm/board.c b/lib_arm/board.c index 1028b04..babc254 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c
@@ -297,7 +297,7 @@ mem_malloc_init (_armboot_start - CFG_MALLOC_LEN); #if (CONFIG_COMMANDS & CFG_CMD_NAND) - puts ("NAND:"); + puts ("NAND: "); nand_init(); /* go init the NAND */ #endif
diff --git a/lib_generic/string.c b/lib_generic/string.c index 0e99d1b..e0b793a 100644 --- a/lib_generic/string.c +++ b/lib_generic/string.c
@@ -21,7 +21,7 @@ #include <malloc.h> -#ifndef __HAVE_ARCH_STRNICMP +#if 0 /* not used - was: #ifndef __HAVE_ARCH_STRNICMP */ /** * strnicmp - Case insensitive, length-limited string comparison * @s1: One string
diff --git a/lib_m68k/board.c b/lib_m68k/board.c index e25833b..80c41a6 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c
@@ -631,7 +631,7 @@ #if (CONFIG_COMMANDS & CFG_CMD_NAND) WATCHDOG_RESET (); - puts ("NAND:"); + puts ("NAND: "); nand_init(); /* go init the NAND */ #endif
diff --git a/rtc/ds1306.c b/rtc/ds1306.c index e143bf7..e01e1ce 100644 --- a/rtc/ds1306.c +++ b/rtc/ds1306.c
@@ -360,13 +360,13 @@ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000)); - rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon)); - rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday)); - rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1)); - rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour)); - rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min)); rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec)); + rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min)); + rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour)); + rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1)); + rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday)); + rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon)); + rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000)); } /* ------------------------------------------------------------------------- */
diff --git a/tools/mkimage.c b/tools/mkimage.c index 5222bb2..fea3e5b 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c
@@ -277,7 +277,8 @@ */ if (xflag) { if (ep != addr + sizeof(image_header_t)) { - fprintf (stderr, "%s: For XIP, the entry point must be the load addr + %lu\n", + fprintf (stderr, + "%s: For XIP, the entry point must be the load addr + %lu\n", cmdname, (unsigned long)sizeof(image_header_t)); exit (EXIT_FAILURE); @@ -347,8 +348,9 @@ if (crc32 (0, data, len) != checksum) { fprintf (stderr, - "*** Warning: \"%s\" has bad header checksum!\n", - imagefile); + "%s: ERROR: \"%s\" has bad header checksum!\n", + cmdname, imagefile); + exit (EXIT_FAILURE); } data = (char *)(ptr + sizeof(image_header_t)); @@ -356,8 +358,9 @@ if (crc32 (0, data, len) != ntohl(hdr->ih_dcrc)) { fprintf (stderr, - "*** Warning: \"%s\" has corrupted data!\n", - imagefile); + "%s: ERROR: \"%s\" has corrupted data!\n", + cmdname, imagefile); + exit (EXIT_FAILURE); } /* for multi-file images we need the data part, too */