blob: 2655b42cfce2de4971d9ae1da02cab41aebad1b6 [file] [log] [blame]
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 BayLibre SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
&apb {
mali: gpu@40000 {
compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
reg = <0x0 0x40000 0x0 0x40000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp", "gpmmu", "pp", "pmu",
"pp0", "ppmmu0", "pp1", "ppmmu1",
"pp2", "ppmmu2";
/*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/
clock-names = "bus", "core";
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
/*
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; *//* Glitch free mux */
/*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, *//* Do Nothing */
//<&clkc CLKID_MALI_0>;
/*assigned-clock-rates = <0>,*/ /* Do Nothing */
/* <666666666>,
<0>;*/ /* Do Nothing */
};
};