| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree Source for the r8a77965 SoC |
| * |
| * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> |
| * |
| * Based on r8a7796.dtsi |
| * Copyright (C) 2016 Renesas Electronics Corp. |
| */ |
| |
| #include <dt-bindings/clock/renesas-cpg-mssr.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| #define CPG_AUDIO_CLK_I 10 |
| |
| / { |
| compatible = "renesas,r8a77965"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| psci { |
| compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| a57_0: cpu@0 { |
| compatible = "arm,cortex-a57", "arm,armv8"; |
| reg = <0x0>; |
| device_type = "cpu"; |
| power-domains = <&sysc 0>; |
| next-level-cache = <&L2_CA57>; |
| enable-method = "psci"; |
| }; |
| |
| a57_1: cpu@1 { |
| compatible = "arm,cortex-a57","arm,armv8"; |
| reg = <0x1>; |
| device_type = "cpu"; |
| power-domains = <&sysc 1>; |
| next-level-cache = <&L2_CA57>; |
| enable-method = "psci"; |
| }; |
| |
| L2_CA57: cache-controller-0 { |
| compatible = "cache"; |
| reg = <0>; |
| power-domains = <&sysc 12>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| }; |
| |
| extal_clk: extal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| extalr_clk: extalr { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| /* |
| * The external audio clocks are configured as 0 Hz fixed frequency |
| * clocks by default. |
| * Boards that provide audio clocks should override them. |
| */ |
| audio_clk_a: audio_clk_a { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| audio_clk_b: audio_clk_b { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| audio_clk_c: audio_clk_c { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| /* External CAN clock - to be overridden by boards that provide it */ |
| can_clk: can { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| /* External SCIF clock - to be overridden by boards that provide it */ |
| scif_clk: scif { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| /* External PCIe clock - can be overridden by the board */ |
| pcie_bus_clk: pcie_bus { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| /* External USB clocks - can be overridden by the board */ |
| usb3s0_clk: usb3s0 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| usb_extal_clk: usb_extal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| pmu_a57 { |
| compatible = "arm,cortex-a57-pmu"; |
| interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&a57_0>, |
| <&a57_1>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gic: interrupt-controller@f1010000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0xf1010000 0 0x1000>, |
| <0x0 0xf1020000 0 0x20000>, |
| <0x0 0xf1040000 0 0x20000>, |
| <0x0 0xf1060000 0 0x20000>; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| clocks = <&cpg CPG_MOD 408>; |
| clock-names = "clk"; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 408>; |
| }; |
| |
| pfc: pin-controller@e6060000 { |
| compatible = "renesas,pfc-r8a77965"; |
| reg = <0 0xe6060000 0 0x50c>; |
| }; |
| |
| cpg: clock-controller@e6150000 { |
| compatible = "renesas,r8a77965-cpg-mssr"; |
| reg = <0 0xe6150000 0 0x1000>; |
| clocks = <&extal_clk>, <&extalr_clk>; |
| clock-names = "extal", "extalr"; |
| #clock-cells = <2>; |
| #power-domain-cells = <0>; |
| #reset-cells = <1>; |
| }; |
| |
| rst: reset-controller@e6160000 { |
| compatible = "renesas,r8a77965-rst"; |
| reg = <0 0xe6160000 0 0x0200>; |
| }; |
| |
| prr: chipid@fff00044 { |
| compatible = "renesas,prr"; |
| reg = <0 0xfff00044 0 4>; |
| }; |
| |
| sysc: system-controller@e6180000 { |
| compatible = "renesas,r8a77965-sysc"; |
| reg = <0 0xe6180000 0 0x0400>; |
| #power-domain-cells = <1>; |
| }; |
| |
| gpio0: gpio@e6050000 { |
| compatible = "renesas,gpio-r8a77965", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6050000 0 0x50>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 0 16>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 912>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 912>; |
| }; |
| |
| gpio1: gpio@e6051000 { |
| compatible = "renesas,gpio-r8a77965", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6051000 0 0x50>; |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 32 29>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 911>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 911>; |
| }; |
| |
| gpio2: gpio@e6052000 { |
| compatible = "renesas,gpio-r8a77965", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6052000 0 0x50>; |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 64 15>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 910>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 910>; |
| }; |
| |
| gpio3: gpio@e6053000 { |
| compatible = "renesas,gpio-r8a77965", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6053000 0 0x50>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 96 16>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 909>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 909>; |
| }; |
| |
| gpio4: gpio@e6054000 { |
| compatible = "renesas,gpio-r8a77965", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6054000 0 0x50>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 128 18>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 908>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 908>; |
| }; |
| |
| gpio5: gpio@e6055000 { |
| compatible = "renesas,gpio-r8a77965", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6055000 0 0x50>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 160 26>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 907>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 907>; |
| }; |
| |
| gpio6: gpio@e6055400 { |
| compatible = "renesas,gpio-r8a77965", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6055400 0 0x50>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 192 32>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 906>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 906>; |
| }; |
| |
| gpio7: gpio@e6055800 { |
| compatible = "renesas,gpio-r8a77965", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6055800 0 0x50>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 224 4>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 905>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 905>; |
| }; |
| |
| intc_ex: interrupt-controller@e61c0000 { |
| /* placeholder */ |
| }; |
| |
| dmac0: dma-controller@e6700000 { |
| compatible = "renesas,dmac-r8a77965", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe6700000 0 0x10000>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 219>; |
| clock-names = "fck"; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 219>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| dmac1: dma-controller@e7300000 { |
| compatible = "renesas,dmac-r8a77965", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe7300000 0 0x10000>; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 218>; |
| clock-names = "fck"; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 218>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| dmac2: dma-controller@e7310000 { |
| compatible = "renesas,dmac-r8a77965", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe7310000 0 0x10000>; |
| interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 217>; |
| clock-names = "fck"; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 217>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| scif0: serial@e6e60000 { |
| compatible = "renesas,scif-r8a77965", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6e60000 0 64>; |
| interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 207>, |
| <&cpg CPG_CORE 20>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x51>, <&dmac1 0x50>, |
| <&dmac2 0x51>, <&dmac2 0x50>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 207>; |
| status = "disabled"; |
| }; |
| |
| scif1: serial@e6e68000 { |
| compatible = "renesas,scif-r8a77965", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6e68000 0 64>; |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 206>, |
| <&cpg CPG_CORE 20>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x53>, <&dmac1 0x52>, |
| <&dmac2 0x53>, <&dmac2 0x52>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 206>; |
| status = "disabled"; |
| }; |
| |
| scif2: serial@e6e88000 { |
| compatible = "renesas,scif-r8a77965", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6e88000 0 64>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 310>, |
| <&cpg CPG_CORE 20>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 310>; |
| status = "disabled"; |
| }; |
| |
| scif3: serial@e6c50000 { |
| compatible = "renesas,scif-r8a77965", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6c50000 0 64>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 204>, |
| <&cpg CPG_CORE 20>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x57>, <&dmac0 0x56>; |
| dma-names = "tx", "rx"; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 204>; |
| status = "disabled"; |
| }; |
| |
| scif4: serial@e6c40000 { |
| compatible = "renesas,scif-r8a77965", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6c40000 0 64>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 203>, |
| <&cpg CPG_CORE 20>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x59>, <&dmac0 0x58>; |
| dma-names = "tx", "rx"; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 203>; |
| status = "disabled"; |
| }; |
| |
| scif5: serial@e6f30000 { |
| compatible = "renesas,scif-r8a77965", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6f30000 0 64>; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 202>, |
| <&cpg CPG_CORE 20>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, |
| <&dmac2 0x5b>, <&dmac2 0x5a>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 202>; |
| status = "disabled"; |
| }; |
| |
| avb: ethernet@e6800000 { |
| compatible = "renesas,etheravb-r8a77965", |
| "renesas,etheravb-rcar-gen3"; |
| reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; |
| clocks = <&cpg CPG_MOD 812>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 812>; |
| phy-mode = "rgmii-txid"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| csi20: csi2@fea80000 { |
| /* placeholder */ |
| }; |
| |
| csi40: csi2@feaa0000 { |
| /* placeholder */ |
| }; |
| |
| vin0: video@e6ef0000 { |
| /* placeholder */ |
| }; |
| |
| vin1: video@e6ef1000 { |
| /* placeholder */ |
| }; |
| |
| vin2: video@e6ef2000 { |
| /* placeholder */ |
| }; |
| |
| vin3: video@e6ef3000 { |
| /* placeholder */ |
| }; |
| |
| vin4: video@e6ef4000 { |
| /* placeholder */ |
| }; |
| |
| vin5: video@e6ef5000 { |
| /* placeholder */ |
| }; |
| |
| vin6: video@e6ef6000 { |
| /* placeholder */ |
| }; |
| |
| vin7: video@e6ef7000 { |
| /* placeholder */ |
| }; |
| |
| ohci0: usb@ee080000 { |
| /* placeholder */ |
| }; |
| |
| ehci0: usb@ee080100 { |
| compatible = "generic-ehci"; |
| reg = <0 0xee080100 0 0x100>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 703>; |
| phys = <&usb2_phy0>; |
| phy-names = "usb"; |
| companion= <&ohci0>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 703>; |
| status = "disabled"; |
| }; |
| |
| usb2_phy0: usb-phy@ee080200 { |
| compatible = "renesas,usb2-phy-r8a77965", |
| "renesas,rcar-gen3-usb2-phy"; |
| reg = <0 0xee080200 0 0x700>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 703>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 703>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| ohci1: usb@ee0a0000 { |
| /* placeholder */ |
| }; |
| |
| ehci1: usb@ee0a0100 { |
| compatible = "generic-ehci"; |
| reg = <0 0xee0a0100 0 0x100>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 702>; |
| phys = <&usb2_phy1>; |
| phy-names = "usb"; |
| companion= <&ohci1>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 702>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@e6500000 { |
| /* placeholder */ |
| }; |
| |
| i2c1: i2c@e6508000 { |
| /* placeholder */ |
| }; |
| |
| i2c2: i2c@e6510000 { |
| /* placeholder */ |
| }; |
| |
| i2c3: i2c@e66d0000 { |
| /* placeholder */ |
| }; |
| |
| i2c4: i2c@e66d8000 { |
| /* placeholder */ |
| }; |
| |
| i2c5: i2c@e66e0000 { |
| /* placeholder */ |
| }; |
| |
| i2c6: i2c@e66e8000 { |
| /* placeholder */ |
| }; |
| |
| i2c_dvfs: i2c@e60b0000 { |
| /* placeholder */ |
| }; |
| |
| pwm0: pwm@e6e30000 { |
| /* placeholder */ |
| }; |
| |
| pwm1: pwm@e6e31000 { |
| /* placeholder */ |
| }; |
| |
| pwm2: pwm@e6e32000 { |
| /* placeholder */ |
| }; |
| |
| pwm3: pwm@e6e33000 { |
| /* placeholder */ |
| }; |
| |
| pwm4: pwm@e6e34000 { |
| /* placeholder */ |
| }; |
| |
| pwm5: pwm@e6e35000 { |
| /* placeholder */ |
| }; |
| |
| pwm6: pwm@e6e36000 { |
| /* placeholder */ |
| }; |
| |
| du: display@feb00000 { |
| /* placeholder */ |
| |
| ports { |
| port@0 { |
| reg = <0>; |
| du_out_rgb: endpoint { |
| }; |
| }; |
| port@1 { |
| reg = <1>; |
| du_out_hdmi0: endpoint { |
| }; |
| }; |
| port@2 { |
| reg = <2>; |
| du_out_lvds0: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| hsusb: usb@e6590000 { |
| /* placeholder */ |
| }; |
| |
| pciec0: pcie@fe000000 { |
| /* placeholder */ |
| }; |
| |
| pciec1: pcie@ee800000 { |
| /* placeholder */ |
| }; |
| |
| rcar_sound: sound@ec500000 { |
| /* placeholder */ |
| |
| rcar_sound,dvc { |
| dvc0: dvc-0 { |
| }; |
| dvc1: dvc-1 { |
| }; |
| }; |
| |
| rcar_sound,src { |
| src0: src-0 { |
| }; |
| src1: src-1 { |
| }; |
| }; |
| |
| rcar_sound,ssi { |
| ssi0: ssi-0 { |
| }; |
| ssi1: ssi-1 { |
| }; |
| }; |
| }; |
| |
| usb2_phy1: usb-phy@ee0a0200 { |
| compatible = "renesas,usb2-phy-r8a77965", |
| "renesas,rcar-gen3-usb2-phy"; |
| reg = <0 0xee0a0200 0 0x700>; |
| clocks = <&cpg CPG_MOD 702>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 702>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| rpc: rpc@0xee200000 { |
| compatible = "renesas,rpc-r8a77965", "renesas,rpc"; |
| reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; |
| clocks = <&cpg CPG_MOD 917>; |
| bank-width = <2>; |
| status = "disabled"; |
| }; |
| |
| sdhi0: sd@ee100000 { |
| compatible = "renesas,sdhi-r8a77965"; |
| reg = <0 0xee100000 0 0x2000>; |
| interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 314>; |
| max-frequency = <200000000>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 314>; |
| status = "disabled"; |
| }; |
| |
| sdhi1: sd@ee120000 { |
| compatible = "renesas,sdhi-r8a77965"; |
| reg = <0 0xee120000 0 0x2000>; |
| interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 313>; |
| max-frequency = <200000000>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 313>; |
| status = "disabled"; |
| }; |
| |
| sdhi2: sd@ee140000 { |
| compatible = "renesas,sdhi-r8a77965"; |
| reg = <0 0xee140000 0 0x2000>; |
| interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 312>; |
| max-frequency = <200000000>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 312>; |
| status = "disabled"; |
| }; |
| |
| sdhi3: sd@ee160000 { |
| compatible = "renesas,sdhi-r8a77965"; |
| reg = <0 0xee160000 0 0x2000>; |
| interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 311>; |
| max-frequency = <200000000>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 311>; |
| status = "disabled"; |
| }; |
| |
| usb3_phy0: usb-phy@e65ee000 { |
| /* placeholder */ |
| }; |
| |
| usb3_peri0: usb@ee020000 { |
| /* placeholder */ |
| }; |
| |
| xhci0: usb@ee000000 { |
| compatible = "renesas,xhci-r8a77965", |
| "renesas,rcar-gen3-xhci"; |
| reg = <0 0xee000000 0 0xc00>; |
| interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 328>; |
| power-domains = <&sysc 32>; |
| resets = <&cpg 328>; |
| status = "disabled"; |
| }; |
| |
| wdt0: watchdog@e6020000 { |
| /* placeholder */ |
| }; |
| }; |
| }; |
