| // ---------------------------------------------------------------------- |
| // regs.h header |
| // |
| // bus base define, update manually |
| // |
| // ---------------------------------------------------------------------- |
| // |
| #ifndef _BASE_REGISTER |
| #define _BASE_REGISTER |
| #define REG_BASE_AOBUS (0xFF800000L) |
| #define REG_BASE_PERIPHS (0xFF634000L) |
| #define REG_BASE_CBUS (0xFFD00000L) |
| #define REG_BASE_HIU (0xFF63C000L) |
| #define REG_BASE_VCBUS (0xFF900000L) |
| #define DMC_REG_BASE (0xFF638000L) |
| #define REG_BASE_DSI_HOST (0xFFD00000L)/* 0xFFD07000L*/ |
| |
| #endif /*_BASE_REGISTER*/ |
| |
| #ifndef REG_OTHERS |
| #define REG_OTHERS |
| /* other regs */ |
| #define SPI_START_ADDR 0xFB000000 |
| #define P_SPI_START_ADDR (volatile unsigned int *)0xFB000000 |
| |
| #endif /*REG_OTHERS*/ |
| |
| // ---------------------------------------------------------------------- |
| // This file is automatically generated from the script: |
| // |
| // ./create_headers_from_register_map_h.pl |
| // |
| // and was applied to the file |
| // |
| // ./register_map.h |
| // |
| // DO NOT EDIT!!!!! |
| // ---------------------------------------------------------------------- |
| // |
| #ifdef REGISTER_H |
| #else |
| #define REGISTER_H |
| #endif |
| |
| // ---------------------------------------------------------------------- |
| // This file is automatically generated from the script: |
| // |
| // ./create_headers_from_dos_params_h.pl |
| // |
| // and was applied to the file |
| // |
| // ./dos_param.h |
| // |
| // DO NOT EDIT!!!!! |
| // ---------------------------------------------------------------------- |
| // |
| #ifdef DOS_REGISTER_H |
| #else |
| #define DOS_REGISTER_H |
| |
| |
| // |
| // Reading file: ./dos_param.h |
| // |
| //------------------------------------------------------------------------------ |
| // Define all modules' base address under DOS |
| // APB allocation from 32'hd0050000 |
| //------------------------------------------------------------------------------ |
| // Define base address for VDEC module under DOS: |
| // DOS_VDEC_ASSIST_BASE_ADDR 14'h0000 |
| // DOS_VDEC_MDEC_BASE_ADDR 14'h0900 |
| // DOS_VDEC_VLD_BASE_ADDR 14'h0c00 |
| // DOS_VDEC_IQIDCT_BASE_ADDR 14'h0e00 |
| // DOS_VDEC_VCPU_BASE_ADDR 14'h0300 |
| // DOS_VDEC_RESERVED_BASE_ADDR 14'h0f00 // Do not use this offset |
| // Define base address for DOS top-level register module: |
| // DOS_TOP_BASE_ADDR 14'h3f00 |
| //------------------------------------------------------------------------------ |
| // VDEC_ASSIST module level register offset |
| //------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: DOS_VDEC_ASSIST_CBUS_BASE = 0x00 |
| // ----------------------------------------------- |
| #define VDEC_ASSIST_MMC_CTRL0 (0x0001) |
| #define P_VDEC_ASSIST_MMC_CTRL0 (volatile unsigned int *)((0x0001 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MMC_CTRL1 (0x0002) |
| #define P_VDEC_ASSIST_MMC_CTRL1 (volatile unsigned int *)((0x0002 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MMC_CTRL2 (0x0003) |
| #define P_VDEC_ASSIST_MMC_CTRL2 (volatile unsigned int *)((0x0003 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MMC_CTRL3 (0x0004) |
| #define P_VDEC_ASSIST_MMC_CTRL3 (volatile unsigned int *)((0x0004 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INT0 (0x0025) |
| #define P_VDEC_ASSIST_AMR1_INT0 (volatile unsigned int *)((0x0025 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INT1 (0x0026) |
| #define P_VDEC_ASSIST_AMR1_INT1 (volatile unsigned int *)((0x0026 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INT2 (0x0027) |
| #define P_VDEC_ASSIST_AMR1_INT2 (volatile unsigned int *)((0x0027 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INT3 (0x0028) |
| #define P_VDEC_ASSIST_AMR1_INT3 (volatile unsigned int *)((0x0028 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INT4 (0x0029) |
| #define P_VDEC_ASSIST_AMR1_INT4 (volatile unsigned int *)((0x0029 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INT5 (0x002a) |
| #define P_VDEC_ASSIST_AMR1_INT5 (volatile unsigned int *)((0x002a << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INT6 (0x002b) |
| #define P_VDEC_ASSIST_AMR1_INT6 (volatile unsigned int *)((0x002b << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INT7 (0x002c) |
| #define P_VDEC_ASSIST_AMR1_INT7 (volatile unsigned int *)((0x002c << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INT8 (0x002d) |
| #define P_VDEC_ASSIST_AMR1_INT8 (volatile unsigned int *)((0x002d << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INT9 (0x002e) |
| #define P_VDEC_ASSIST_AMR1_INT9 (volatile unsigned int *)((0x002e << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INTA (0x002f) |
| #define P_VDEC_ASSIST_AMR1_INTA (volatile unsigned int *)((0x002f << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INTB (0x0030) |
| #define P_VDEC_ASSIST_AMR1_INTB (volatile unsigned int *)((0x0030 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INTC (0x0031) |
| #define P_VDEC_ASSIST_AMR1_INTC (volatile unsigned int *)((0x0031 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INTD (0x0032) |
| #define P_VDEC_ASSIST_AMR1_INTD (volatile unsigned int *)((0x0032 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INTE (0x0033) |
| #define P_VDEC_ASSIST_AMR1_INTE (volatile unsigned int *)((0x0033 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR1_INTF (0x0034) |
| #define P_VDEC_ASSIST_AMR1_INTF (volatile unsigned int *)((0x0034 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INT0 (0x0035) |
| #define P_VDEC_ASSIST_AMR2_INT0 (volatile unsigned int *)((0x0035 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INT1 (0x0036) |
| #define P_VDEC_ASSIST_AMR2_INT1 (volatile unsigned int *)((0x0036 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INT2 (0x0037) |
| #define P_VDEC_ASSIST_AMR2_INT2 (volatile unsigned int *)((0x0037 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INT3 (0x0038) |
| #define P_VDEC_ASSIST_AMR2_INT3 (volatile unsigned int *)((0x0038 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INT4 (0x0039) |
| #define P_VDEC_ASSIST_AMR2_INT4 (volatile unsigned int *)((0x0039 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INT5 (0x003a) |
| #define P_VDEC_ASSIST_AMR2_INT5 (volatile unsigned int *)((0x003a << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INT6 (0x003b) |
| #define P_VDEC_ASSIST_AMR2_INT6 (volatile unsigned int *)((0x003b << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INT7 (0x003c) |
| #define P_VDEC_ASSIST_AMR2_INT7 (volatile unsigned int *)((0x003c << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INT8 (0x003d) |
| #define P_VDEC_ASSIST_AMR2_INT8 (volatile unsigned int *)((0x003d << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INT9 (0x003e) |
| #define P_VDEC_ASSIST_AMR2_INT9 (volatile unsigned int *)((0x003e << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INTA (0x003f) |
| #define P_VDEC_ASSIST_AMR2_INTA (volatile unsigned int *)((0x003f << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INTB (0x0040) |
| #define P_VDEC_ASSIST_AMR2_INTB (volatile unsigned int *)((0x0040 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INTC (0x0041) |
| #define P_VDEC_ASSIST_AMR2_INTC (volatile unsigned int *)((0x0041 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INTD (0x0042) |
| #define P_VDEC_ASSIST_AMR2_INTD (volatile unsigned int *)((0x0042 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INTE (0x0043) |
| #define P_VDEC_ASSIST_AMR2_INTE (volatile unsigned int *)((0x0043 << 2) + 0xff620000) |
| #define VDEC_ASSIST_AMR2_INTF (0x0044) |
| #define P_VDEC_ASSIST_AMR2_INTF (volatile unsigned int *)((0x0044 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBX_SSEL (0x0045) |
| #define P_VDEC_ASSIST_MBX_SSEL (volatile unsigned int *)((0x0045 << 2) + 0xff620000) |
| #define VDEC_ASSIST_TIMER0_LO (0x0060) |
| #define P_VDEC_ASSIST_TIMER0_LO (volatile unsigned int *)((0x0060 << 2) + 0xff620000) |
| #define VDEC_ASSIST_TIMER0_HI (0x0061) |
| #define P_VDEC_ASSIST_TIMER0_HI (volatile unsigned int *)((0x0061 << 2) + 0xff620000) |
| #define VDEC_ASSIST_TIMER1_LO (0x0062) |
| #define P_VDEC_ASSIST_TIMER1_LO (volatile unsigned int *)((0x0062 << 2) + 0xff620000) |
| #define VDEC_ASSIST_TIMER1_HI (0x0063) |
| #define P_VDEC_ASSIST_TIMER1_HI (volatile unsigned int *)((0x0063 << 2) + 0xff620000) |
| #define VDEC_ASSIST_DMA_INT (0x0064) |
| #define P_VDEC_ASSIST_DMA_INT (volatile unsigned int *)((0x0064 << 2) + 0xff620000) |
| #define VDEC_ASSIST_DMA_INT_MSK (0x0065) |
| #define P_VDEC_ASSIST_DMA_INT_MSK (volatile unsigned int *)((0x0065 << 2) + 0xff620000) |
| #define VDEC_ASSIST_DMA_INT2 (0x0066) |
| #define P_VDEC_ASSIST_DMA_INT2 (volatile unsigned int *)((0x0066 << 2) + 0xff620000) |
| #define VDEC_ASSIST_DMA_INT_MSK2 (0x0067) |
| #define P_VDEC_ASSIST_DMA_INT_MSK2 (volatile unsigned int *)((0x0067 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX0_IRQ_REG (0x0070) |
| #define P_VDEC_ASSIST_MBOX0_IRQ_REG (volatile unsigned int *)((0x0070 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX0_CLR_REG (0x0071) |
| #define P_VDEC_ASSIST_MBOX0_CLR_REG (volatile unsigned int *)((0x0071 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX0_MASK (0x0072) |
| #define P_VDEC_ASSIST_MBOX0_MASK (volatile unsigned int *)((0x0072 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX0_FIQ_SEL (0x0073) |
| #define P_VDEC_ASSIST_MBOX0_FIQ_SEL (volatile unsigned int *)((0x0073 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX1_IRQ_REG (0x0074) |
| #define P_VDEC_ASSIST_MBOX1_IRQ_REG (volatile unsigned int *)((0x0074 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX1_CLR_REG (0x0075) |
| #define P_VDEC_ASSIST_MBOX1_CLR_REG (volatile unsigned int *)((0x0075 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX1_MASK (0x0076) |
| #define P_VDEC_ASSIST_MBOX1_MASK (volatile unsigned int *)((0x0076 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX1_FIQ_SEL (0x0077) |
| #define P_VDEC_ASSIST_MBOX1_FIQ_SEL (volatile unsigned int *)((0x0077 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX2_IRQ_REG (0x0078) |
| #define P_VDEC_ASSIST_MBOX2_IRQ_REG (volatile unsigned int *)((0x0078 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX2_CLR_REG (0x0079) |
| #define P_VDEC_ASSIST_MBOX2_CLR_REG (volatile unsigned int *)((0x0079 << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX2_MASK (0x007a) |
| #define P_VDEC_ASSIST_MBOX2_MASK (volatile unsigned int *)((0x007a << 2) + 0xff620000) |
| #define VDEC_ASSIST_MBOX2_FIQ_SEL (0x007b) |
| #define P_VDEC_ASSIST_MBOX2_FIQ_SEL (volatile unsigned int *)((0x007b << 2) + 0xff620000) |
| //------------------------------------------------------------------------------ |
| // VDEC2_ASSIST module level register offset |
| //------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: DOS_VDEC2_ASSIST_CBUS_BASE = 0x00 |
| // ----------------------------------------------- |
| #define VDEC2_ASSIST_MMC_CTRL0 (0x2001) |
| #define P_VDEC2_ASSIST_MMC_CTRL0 (volatile unsigned int *)((0x2001 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MMC_CTRL1 (0x2002) |
| #define P_VDEC2_ASSIST_MMC_CTRL1 (volatile unsigned int *)((0x2002 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INT0 (0x2025) |
| #define P_VDEC2_ASSIST_AMR1_INT0 (volatile unsigned int *)((0x2025 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INT1 (0x2026) |
| #define P_VDEC2_ASSIST_AMR1_INT1 (volatile unsigned int *)((0x2026 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INT2 (0x2027) |
| #define P_VDEC2_ASSIST_AMR1_INT2 (volatile unsigned int *)((0x2027 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INT3 (0x2028) |
| #define P_VDEC2_ASSIST_AMR1_INT3 (volatile unsigned int *)((0x2028 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INT4 (0x2029) |
| #define P_VDEC2_ASSIST_AMR1_INT4 (volatile unsigned int *)((0x2029 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INT5 (0x202a) |
| #define P_VDEC2_ASSIST_AMR1_INT5 (volatile unsigned int *)((0x202a << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INT6 (0x202b) |
| #define P_VDEC2_ASSIST_AMR1_INT6 (volatile unsigned int *)((0x202b << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INT7 (0x202c) |
| #define P_VDEC2_ASSIST_AMR1_INT7 (volatile unsigned int *)((0x202c << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INT8 (0x202d) |
| #define P_VDEC2_ASSIST_AMR1_INT8 (volatile unsigned int *)((0x202d << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INT9 (0x202e) |
| #define P_VDEC2_ASSIST_AMR1_INT9 (volatile unsigned int *)((0x202e << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INTA (0x202f) |
| #define P_VDEC2_ASSIST_AMR1_INTA (volatile unsigned int *)((0x202f << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INTB (0x2030) |
| #define P_VDEC2_ASSIST_AMR1_INTB (volatile unsigned int *)((0x2030 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INTC (0x2031) |
| #define P_VDEC2_ASSIST_AMR1_INTC (volatile unsigned int *)((0x2031 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INTD (0x2032) |
| #define P_VDEC2_ASSIST_AMR1_INTD (volatile unsigned int *)((0x2032 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INTE (0x2033) |
| #define P_VDEC2_ASSIST_AMR1_INTE (volatile unsigned int *)((0x2033 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR1_INTF (0x2034) |
| #define P_VDEC2_ASSIST_AMR1_INTF (volatile unsigned int *)((0x2034 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INT0 (0x2035) |
| #define P_VDEC2_ASSIST_AMR2_INT0 (volatile unsigned int *)((0x2035 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INT1 (0x2036) |
| #define P_VDEC2_ASSIST_AMR2_INT1 (volatile unsigned int *)((0x2036 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INT2 (0x2037) |
| #define P_VDEC2_ASSIST_AMR2_INT2 (volatile unsigned int *)((0x2037 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INT3 (0x2038) |
| #define P_VDEC2_ASSIST_AMR2_INT3 (volatile unsigned int *)((0x2038 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INT4 (0x2039) |
| #define P_VDEC2_ASSIST_AMR2_INT4 (volatile unsigned int *)((0x2039 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INT5 (0x203a) |
| #define P_VDEC2_ASSIST_AMR2_INT5 (volatile unsigned int *)((0x203a << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INT6 (0x203b) |
| #define P_VDEC2_ASSIST_AMR2_INT6 (volatile unsigned int *)((0x203b << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INT7 (0x203c) |
| #define P_VDEC2_ASSIST_AMR2_INT7 (volatile unsigned int *)((0x203c << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INT8 (0x203d) |
| #define P_VDEC2_ASSIST_AMR2_INT8 (volatile unsigned int *)((0x203d << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INT9 (0x203e) |
| #define P_VDEC2_ASSIST_AMR2_INT9 (volatile unsigned int *)((0x203e << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INTA (0x203f) |
| #define P_VDEC2_ASSIST_AMR2_INTA (volatile unsigned int *)((0x203f << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INTB (0x2040) |
| #define P_VDEC2_ASSIST_AMR2_INTB (volatile unsigned int *)((0x2040 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INTC (0x2041) |
| #define P_VDEC2_ASSIST_AMR2_INTC (volatile unsigned int *)((0x2041 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INTD (0x2042) |
| #define P_VDEC2_ASSIST_AMR2_INTD (volatile unsigned int *)((0x2042 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INTE (0x2043) |
| #define P_VDEC2_ASSIST_AMR2_INTE (volatile unsigned int *)((0x2043 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_AMR2_INTF (0x2044) |
| #define P_VDEC2_ASSIST_AMR2_INTF (volatile unsigned int *)((0x2044 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBX_SSEL (0x2045) |
| #define P_VDEC2_ASSIST_MBX_SSEL (volatile unsigned int *)((0x2045 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_TIMER0_LO (0x2060) |
| #define P_VDEC2_ASSIST_TIMER0_LO (volatile unsigned int *)((0x2060 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_TIMER0_HI (0x2061) |
| #define P_VDEC2_ASSIST_TIMER0_HI (volatile unsigned int *)((0x2061 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_TIMER1_LO (0x2062) |
| #define P_VDEC2_ASSIST_TIMER1_LO (volatile unsigned int *)((0x2062 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_TIMER1_HI (0x2063) |
| #define P_VDEC2_ASSIST_TIMER1_HI (volatile unsigned int *)((0x2063 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_DMA_INT (0x2064) |
| #define P_VDEC2_ASSIST_DMA_INT (volatile unsigned int *)((0x2064 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_DMA_INT_MSK (0x2065) |
| #define P_VDEC2_ASSIST_DMA_INT_MSK (volatile unsigned int *)((0x2065 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_DMA_INT2 (0x2066) |
| #define P_VDEC2_ASSIST_DMA_INT2 (volatile unsigned int *)((0x2066 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_DMA_INT_MSK2 (0x2067) |
| #define P_VDEC2_ASSIST_DMA_INT_MSK2 (volatile unsigned int *)((0x2067 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX0_IRQ_REG (0x2070) |
| #define P_VDEC2_ASSIST_MBOX0_IRQ_REG (volatile unsigned int *)((0x2070 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX0_CLR_REG (0x2071) |
| #define P_VDEC2_ASSIST_MBOX0_CLR_REG (volatile unsigned int *)((0x2071 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX0_MASK (0x2072) |
| #define P_VDEC2_ASSIST_MBOX0_MASK (volatile unsigned int *)((0x2072 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX0_FIQ_SEL (0x2073) |
| #define P_VDEC2_ASSIST_MBOX0_FIQ_SEL (volatile unsigned int *)((0x2073 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX1_IRQ_REG (0x2074) |
| #define P_VDEC2_ASSIST_MBOX1_IRQ_REG (volatile unsigned int *)((0x2074 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX1_CLR_REG (0x2075) |
| #define P_VDEC2_ASSIST_MBOX1_CLR_REG (volatile unsigned int *)((0x2075 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX1_MASK (0x2076) |
| #define P_VDEC2_ASSIST_MBOX1_MASK (volatile unsigned int *)((0x2076 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX1_FIQ_SEL (0x2077) |
| #define P_VDEC2_ASSIST_MBOX1_FIQ_SEL (volatile unsigned int *)((0x2077 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX2_IRQ_REG (0x2078) |
| #define P_VDEC2_ASSIST_MBOX2_IRQ_REG (volatile unsigned int *)((0x2078 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX2_CLR_REG (0x2079) |
| #define P_VDEC2_ASSIST_MBOX2_CLR_REG (volatile unsigned int *)((0x2079 << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX2_MASK (0x207a) |
| #define P_VDEC2_ASSIST_MBOX2_MASK (volatile unsigned int *)((0x207a << 2) + 0xff620000) |
| #define VDEC2_ASSIST_MBOX2_FIQ_SEL (0x207b) |
| #define P_VDEC2_ASSIST_MBOX2_FIQ_SEL (volatile unsigned int *)((0x207b << 2) + 0xff620000) |
| //------------------------------------------------------------------------------ |
| // HCODEC_ASSIST module level register offset |
| //------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: DOS_HCODEC_ASSIST_CBUS_BASE = 0x00 |
| // ----------------------------------------------- |
| #define HCODEC_ASSIST_MMC_CTRL0 (0x1001) |
| #define P_HCODEC_ASSIST_MMC_CTRL0 (volatile unsigned int *)((0x1001 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MMC_CTRL1 (0x1002) |
| #define P_HCODEC_ASSIST_MMC_CTRL1 (volatile unsigned int *)((0x1002 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MMC_CTRL2 (0x1003) |
| #define P_HCODEC_ASSIST_MMC_CTRL2 (volatile unsigned int *)((0x1003 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MMC_CTRL3 (0x1004) |
| #define P_HCODEC_ASSIST_MMC_CTRL3 (volatile unsigned int *)((0x1004 << 2) + 0xff620000) |
| //cfg_soft_rst = mfdin_reg0_crst[0]; // Soft Reset |
| //cfg_cg_cfe = mfdin_reg0_crst[1]; // Clock Gating Forcing Enable |
| //cfg_dbuf_rst = mfdin_reg0_crst[2]; // Reset DBUF information |
| #define HCODEC_MFDIN_REG0_CRST (0x1008) |
| #define P_HCODEC_MFDIN_REG0_CRST (volatile unsigned int *)((0x1008 << 2) + 0xff620000) |
| //cfg_iformat = mfdin_reg1_ctrl[3:0]; // Data In Format: 0 :CANVAS 422 YCbCr<-one canvas, |
| // 1 :CANVAS 444 YCbCr(or RGB)<-one canvas, |
| // 2 :CANVAS 420 Y<-one CrCb<-one (NV21) |
| // 3 :CANVAS 420 Y<-one CbCr<-one (NV12) |
| // 4 :CANVAS 420 Y<-one Cb<-one Cr<-one |
| // 5 :CANVAS 444 Y<-one Cb<-one Cr<-one |
| // 6 : Reserved for other canvas mode |
| // 7 : should combine with cfg_ifmt_extra, for 10-12bits |
| // 8 :LINEAR RGB888 (24bit) |
| // 9 :LINEAR RGB565 (16bit) |
| // 10:LINEAR YUV422 |
| // 11:LINEAR YUV420 (Note:Legacy mode not supported) |
| // 12~15: Reserved for other linear mode |
| //cfg_oformat = mfdin_reg1_ctrl[5:4]; // Data Out Format: 0:420 1:422 2:444 3:reserved |
| //cfg_dsample_enable= mfdin_reg1_ctrl[6]; // Downsample Enable |
| //cfg_dsample_trunc = mfdin_reg1_ctrl[7]; // Downsample Addition Option: 0:Round 1:Truncated |
| //cfg_block_ysize = mfdin_reg1_ctrl[8]; // 0:block-y-size=16, 1:block-y-size=8(for JPEG's efficiency) |
| //cfg_interp_enable = mfdin_reg1_ctrl[9]; // Chroma Interpolation Enable |
| //cfg_interp_mode = mfdin_reg1_ctrl[11:10];// 0:average round 1:average truncated 2:repeat left 3:repeat right |
| //cfg_r2y_enable = mfdin_reg1_ctrl[12]; // RGb->YUV Enable |
| //cfg_r2y_mode = mfdin_reg1_ctrl[14:13];// RGb->YUV Mode |
| //cfg_rgb565_mode = mfdin_reg1_ctrl[15]; // RGB565 mode: 0:fill zero in tail 1:fill zero in head |
| //cfg_ifmt_extra = mfdin_reg1_ctrl[17:16];// when cfg_iformat==7, |
| // 0: CANVAS 12bit 422, YCbCr<-one canvas{...Y1[11:0],C1[11:0],Y0[11:0],C0[11:0]} |
| // 1: CANVAS 10bit 444, YCbCr<-one canvas{...2'b0,Y0[9:0],U0[9:0],V0[9:0]} |
| // 2: CANVAS 10bit 422, YCbCr<-one canvas{...Y1[9:0],C1[9:0],Y0[9:0],C0[9:0]} |
| //cfg_reserved1 = mfdin_reg1_ctrl[18]; // Reserved |
| //cfg_nr_enable = mfdin_reg1_ctrl[19]; // Noise Reduction Enable |
| //cfg_outofpic = mfdin_reg1_ctrl[28:20];// Out Of Picture Control: [8]mode:0:extend 1:fixed, [7:0]fixed value |
| //cfg_rd_blktype = mfdin_reg1_ctrl[30:29];// Block Type: 0:H264_I_PIC_ALL_4x4, 1:H264_P_PIC_Y_16x16_C_8x8, 2:JPEG_ALL_8x8, 3:Reserved |
| //cfg_rd_nonycintl = mfdin_reg1_ctrl[31]; // 0:YC interleaved 1:YC non-interleaved(for JPEG) |
| #define HCODEC_MFDIN_REG1_CTRL (0x1009) |
| #define P_HCODEC_MFDIN_REG1_CTRL (volatile unsigned int *)((0x1009 << 2) + 0xff620000) |
| //mfdin_reg2: DEBUG Only Status |
| #define HCODEC_MFDIN_REG2_STAT (0x100a) |
| #define P_HCODEC_MFDIN_REG2_STAT (volatile unsigned int *)((0x100a << 2) + 0xff620000) |
| //cfg_canvas_index0 = mfdin_reg3_canv[7:0]; //canvas index 0 |
| //cfg_canvas_index1 = mfdin_reg3_canv[15:8]; //canvas index 1 |
| //cfg_canvas_index2 = mfdin_reg3_canv[23:16];//canvas index 2 |
| //cfg_canv_idx0_bppx = mfdin_reg3_canv[25:24];//canvas bytes per pixel in x direction for index0, 0:half 1:1 2:2 3:3 |
| //cfg_canv_idx1_bppx = mfdin_reg3_canv[27:26];//canvas bytes per pixel in x direction for index1, 0:half 1:1 2:2 3:3 |
| //cfg_canv_idx0_bppy = mfdin_reg3_canv[29:28];//canvas bytes per pixel in y direction for index0, 0:half 1:1 2:2 3:3 |
| //cfg_canv_idx1_bppy = mfdin_reg3_canv[31:30];//canvas bytes per pixel in y direction for index1, 0:half 1:1 2:2 3:3 |
| #define HCODEC_MFDIN_REG3_CANV (0x100b) |
| #define P_HCODEC_MFDIN_REG3_CANV (volatile unsigned int *)((0x100b << 2) + 0xff620000) |
| //cfg_bytes_per_line = mfdin_reg4_lnr0[15:0]; //linear Bytes per line |
| //cfg_linear_bytes4p = mfdin_reg4_lnr0[17:16]; //linear (Bytes per pixel) - 1 |
| //cfg_linear_dbl2line = mfdin_reg4_lnr0[18]; //linear double size for odd line |
| #define HCODEC_MFDIN_REG4_LNR0 (0x100c) |
| #define P_HCODEC_MFDIN_REG4_LNR0 (volatile unsigned int *)((0x100c << 2) + 0xff620000) |
| //cfg_base_address = mfdin_reg5_lnr1[31:0]; //linear base address |
| #define HCODEC_MFDIN_REG5_LNR1 (0x100d) |
| #define P_HCODEC_MFDIN_REG5_LNR1 (volatile unsigned int *)((0x100d << 2) + 0xff620000) |
| //assign cfg_r2y_trunc = mfdin_reg6_dcfg[9]; //RGb->YUV Addition Option: 0:Round 1:Truncated |
| //assign cfg_dma_ugt = mfdin_reg6_dcfg[8]; //DMA Urgent |
| //assign cfg_dma_thread_id = mfdin_reg6_dcfg[7:6]; //DMA Thread ID |
| //assign cfg_dma_burst_num = mfdin_reg6_dcfg[5:0]; //DMA Burst Number |
| #define HCODEC_MFDIN_REG6_DCFG (0x100e) |
| #define P_HCODEC_MFDIN_REG6_DCFG (volatile unsigned int *)((0x100e << 2) + 0xff620000) |
| //cfg_soft_cmd = mfdin_reg7_scmd; // Soft Command [28]selfcleared start,[27:14]dmb_x,[13:0]dmb_y |
| #define HCODEC_MFDIN_REG7_SCMD (0x100f) |
| #define P_HCODEC_MFDIN_REG7_SCMD (volatile unsigned int *)((0x100f << 2) + 0xff620000) |
| //cfg_pic_xsize = mfdin_reg8_dmbl[23:12]; //pixel (x,y) at the begining of last dmb in the picturem, picture x size |
| //cfg_pic_ysize = mfdin_reg8_dmbl[11:0]; //picture y size |
| #define HCODEC_MFDIN_REG8_DMBL (0x1010) |
| #define P_HCODEC_MFDIN_REG8_DMBL (volatile unsigned int *)((0x1010 << 2) + 0xff620000) |
| //cfg_endian = mfdin_reg9_endn; //Endian Control |
| #define HCODEC_MFDIN_REG9_ENDN (0x1011) |
| #define P_HCODEC_MFDIN_REG9_ENDN (volatile unsigned int *)((0x1011 << 2) + 0xff620000) |
| //cfg_canv_biasx = mfdin_rega_cav1[23:12]; //canvas bias address x |
| //cfg_canv_biasy = mfdin_rega_cav1[11:0]; //canvas bias address y |
| #define HCODEC_MFDIN_REGA_CAV1 (0x1012) |
| #define P_HCODEC_MFDIN_REGA_CAV1 (volatile unsigned int *)((0x1012 << 2) + 0xff620000) |
| //cfg_amp_en = mfdin_regb_ampc[24]; //Amplitude Enable |
| //cfg_amp_cy = mfdin_regb_ampc[23:16]; //Amplitude Coeff Y |
| //cfg_amp_cu = mfdin_regb_ampc[15:8]; //Amplitude Coeff U |
| //cfg_amp_cv = mfdin_regb_ampc[7:0]; //Amplitude Coeff V |
| #define HCODEC_MFDIN_REGB_AMPC (0x1013) |
| #define P_HCODEC_MFDIN_REGB_AMPC (volatile unsigned int *)((0x1013 << 2) + 0xff620000) |
| //cfg_mb_end = mfdin_regc_mblp; // Soft Command [28]mb end enable,[27:14]dmb_x,[13:0]dmb_y |
| #define HCODEC_MFDIN_REGC_MBLP (0x1014) |
| #define P_HCODEC_MFDIN_REGC_MBLP (volatile unsigned int *)((0x1014 << 2) + 0xff620000) |
| // cfg_y_snr_en = mfdin_reg0d[0]; |
| // cfg_y_snr_err_norm = mfdin_reg0d[1]; |
| // [3:0] cfg_y_snr_gau_bld_core = mfdin_reg0d[5:2]; |
| // [7:0] cfg_y_snr_gau_bld_ofst = mfdin_reg0d[13:6]; |
| // [5:0] cfg_y_snr_gau_bld_rate = mfdin_reg0d[19:14]; |
| // [5:0] cfg_y_snr_gau_alp0_min = mfdin_reg0d[25:20]; |
| // [5:0] cfg_y_snr_gau_alp0_max = mfdin_reg0d[31:26]; |
| #define HCODEC_MFDIN_REG0D (0x1015) |
| #define P_HCODEC_MFDIN_REG0D (volatile unsigned int *)((0x1015 << 2) + 0xff620000) |
| // cfg_y_tnr_en = mfdin_reg0e[0]; |
| // cfg_y_tnr_mc_en = mfdin_reg0e[1]; |
| // cfg_y_tnr_txt_mode = mfdin_reg0e[2]; |
| // [3:0] cfg_y_tnr_mot_sad_margin = mfdin_reg0e[6:3]; |
| // [5:0] cfg_y_tnr_alpha_min = mfdin_reg0e[12:7]; |
| // [5:0] cfg_y_tnr_alpha_max = mfdin_reg0e[18:13]; |
| // [5:0] cfg_y_tnr_deghost_os = mfdin_reg0e[24:19]; |
| #define HCODEC_MFDIN_REG0E (0x1016) |
| #define P_HCODEC_MFDIN_REG0E (volatile unsigned int *)((0x1016 << 2) + 0xff620000) |
| // [3:0] cfg_y_tnr_mot_cortxt_rate = mfdin_reg0f[3:0]; |
| // [7:0] cfg_y_tnr_mot_distxt_ofst = mfdin_reg0f[15:8]; |
| // [3:0] cfg_y_tnr_mot_distxt_rate = mfdin_reg0f[7:4]; |
| // [7:0] cfg_y_tnr_mot_dismot_ofst = mfdin_reg0f[23:16]; |
| // [7:0] cfg_y_tnr_mot_frcsad_lock = mfdin_reg0f[31:24]; |
| #define HCODEC_MFDIN_REG0F (0x1017) |
| #define P_HCODEC_MFDIN_REG0F (volatile unsigned int *)((0x1017 << 2) + 0xff620000) |
| // [7:0] cfg_y_tnr_mot2alp_frc_gain = mfdin_reg10[7:0]; |
| // [7:0] cfg_y_tnr_mot2alp_nrm_gain = mfdin_reg10[15:8]; |
| // [7:0] cfg_y_tnr_mot2alp_dis_gain = mfdin_reg10[23:16]; |
| // [5:0] cfg_y_tnr_mot2alp_dis_ofst = mfdin_reg10[29:24]; |
| #define HCODEC_MFDIN_REG10 (0x1018) |
| #define P_HCODEC_MFDIN_REG10 (volatile unsigned int *)((0x1018 << 2) + 0xff620000) |
| // [7:0] cfg_y_bld_beta2alp_rate = mfdin_reg11[7:0]; |
| // [5:0] cfg_y_bld_beta_min = mfdin_reg11[13:8]; |
| // [5:0] cfg_y_bld_beta_max = mfdin_reg11[19:14]; |
| #define HCODEC_MFDIN_REG11 (0x1019) |
| #define P_HCODEC_MFDIN_REG11 (volatile unsigned int *)((0x1019 << 2) + 0xff620000) |
| // REG12~16 for Chroma, same as Luma |
| #define HCODEC_MFDIN_REG12 (0x101a) |
| #define P_HCODEC_MFDIN_REG12 (volatile unsigned int *)((0x101a << 2) + 0xff620000) |
| #define HCODEC_MFDIN_REG13 (0x101b) |
| #define P_HCODEC_MFDIN_REG13 (volatile unsigned int *)((0x101b << 2) + 0xff620000) |
| #define HCODEC_MFDIN_REG14 (0x101c) |
| #define P_HCODEC_MFDIN_REG14 (volatile unsigned int *)((0x101c << 2) + 0xff620000) |
| #define HCODEC_MFDIN_REG15 (0x101d) |
| #define P_HCODEC_MFDIN_REG15 (volatile unsigned int *)((0x101d << 2) + 0xff620000) |
| #define HCODEC_MFDIN_REG16 (0x101e) |
| #define P_HCODEC_MFDIN_REG16 (volatile unsigned int *)((0x101e << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INT0 (0x1025) |
| #define P_HCODEC_ASSIST_AMR1_INT0 (volatile unsigned int *)((0x1025 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INT1 (0x1026) |
| #define P_HCODEC_ASSIST_AMR1_INT1 (volatile unsigned int *)((0x1026 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INT2 (0x1027) |
| #define P_HCODEC_ASSIST_AMR1_INT2 (volatile unsigned int *)((0x1027 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INT3 (0x1028) |
| #define P_HCODEC_ASSIST_AMR1_INT3 (volatile unsigned int *)((0x1028 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INT4 (0x1029) |
| #define P_HCODEC_ASSIST_AMR1_INT4 (volatile unsigned int *)((0x1029 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INT5 (0x102a) |
| #define P_HCODEC_ASSIST_AMR1_INT5 (volatile unsigned int *)((0x102a << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INT6 (0x102b) |
| #define P_HCODEC_ASSIST_AMR1_INT6 (volatile unsigned int *)((0x102b << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INT7 (0x102c) |
| #define P_HCODEC_ASSIST_AMR1_INT7 (volatile unsigned int *)((0x102c << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INT8 (0x102d) |
| #define P_HCODEC_ASSIST_AMR1_INT8 (volatile unsigned int *)((0x102d << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INT9 (0x102e) |
| #define P_HCODEC_ASSIST_AMR1_INT9 (volatile unsigned int *)((0x102e << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INTA (0x102f) |
| #define P_HCODEC_ASSIST_AMR1_INTA (volatile unsigned int *)((0x102f << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INTB (0x1030) |
| #define P_HCODEC_ASSIST_AMR1_INTB (volatile unsigned int *)((0x1030 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INTC (0x1031) |
| #define P_HCODEC_ASSIST_AMR1_INTC (volatile unsigned int *)((0x1031 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INTD (0x1032) |
| #define P_HCODEC_ASSIST_AMR1_INTD (volatile unsigned int *)((0x1032 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INTE (0x1033) |
| #define P_HCODEC_ASSIST_AMR1_INTE (volatile unsigned int *)((0x1033 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR1_INTF (0x1034) |
| #define P_HCODEC_ASSIST_AMR1_INTF (volatile unsigned int *)((0x1034 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INT0 (0x1035) |
| #define P_HCODEC_ASSIST_AMR2_INT0 (volatile unsigned int *)((0x1035 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INT1 (0x1036) |
| #define P_HCODEC_ASSIST_AMR2_INT1 (volatile unsigned int *)((0x1036 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INT2 (0x1037) |
| #define P_HCODEC_ASSIST_AMR2_INT2 (volatile unsigned int *)((0x1037 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INT3 (0x1038) |
| #define P_HCODEC_ASSIST_AMR2_INT3 (volatile unsigned int *)((0x1038 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INT4 (0x1039) |
| #define P_HCODEC_ASSIST_AMR2_INT4 (volatile unsigned int *)((0x1039 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INT5 (0x103a) |
| #define P_HCODEC_ASSIST_AMR2_INT5 (volatile unsigned int *)((0x103a << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INT6 (0x103b) |
| #define P_HCODEC_ASSIST_AMR2_INT6 (volatile unsigned int *)((0x103b << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INT7 (0x103c) |
| #define P_HCODEC_ASSIST_AMR2_INT7 (volatile unsigned int *)((0x103c << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INT8 (0x103d) |
| #define P_HCODEC_ASSIST_AMR2_INT8 (volatile unsigned int *)((0x103d << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INT9 (0x103e) |
| #define P_HCODEC_ASSIST_AMR2_INT9 (volatile unsigned int *)((0x103e << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INTA (0x103f) |
| #define P_HCODEC_ASSIST_AMR2_INTA (volatile unsigned int *)((0x103f << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INTB (0x1040) |
| #define P_HCODEC_ASSIST_AMR2_INTB (volatile unsigned int *)((0x1040 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INTC (0x1041) |
| #define P_HCODEC_ASSIST_AMR2_INTC (volatile unsigned int *)((0x1041 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INTD (0x1042) |
| #define P_HCODEC_ASSIST_AMR2_INTD (volatile unsigned int *)((0x1042 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INTE (0x1043) |
| #define P_HCODEC_ASSIST_AMR2_INTE (volatile unsigned int *)((0x1043 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_AMR2_INTF (0x1044) |
| #define P_HCODEC_ASSIST_AMR2_INTF (volatile unsigned int *)((0x1044 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBX_SSEL (0x1045) |
| #define P_HCODEC_ASSIST_MBX_SSEL (volatile unsigned int *)((0x1045 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_TIMER0_LO (0x1060) |
| #define P_HCODEC_ASSIST_TIMER0_LO (volatile unsigned int *)((0x1060 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_TIMER0_HI (0x1061) |
| #define P_HCODEC_ASSIST_TIMER0_HI (volatile unsigned int *)((0x1061 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_TIMER1_LO (0x1062) |
| #define P_HCODEC_ASSIST_TIMER1_LO (volatile unsigned int *)((0x1062 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_TIMER1_HI (0x1063) |
| #define P_HCODEC_ASSIST_TIMER1_HI (volatile unsigned int *)((0x1063 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_DMA_INT (0x1064) |
| #define P_HCODEC_ASSIST_DMA_INT (volatile unsigned int *)((0x1064 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_DMA_INT_MSK (0x1065) |
| #define P_HCODEC_ASSIST_DMA_INT_MSK (volatile unsigned int *)((0x1065 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_DMA_INT2 (0x1066) |
| #define P_HCODEC_ASSIST_DMA_INT2 (volatile unsigned int *)((0x1066 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_DMA_INT_MSK2 (0x1067) |
| #define P_HCODEC_ASSIST_DMA_INT_MSK2 (volatile unsigned int *)((0x1067 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX0_IRQ_REG (0x1070) |
| #define P_HCODEC_ASSIST_MBOX0_IRQ_REG (volatile unsigned int *)((0x1070 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX0_CLR_REG (0x1071) |
| #define P_HCODEC_ASSIST_MBOX0_CLR_REG (volatile unsigned int *)((0x1071 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX0_MASK (0x1072) |
| #define P_HCODEC_ASSIST_MBOX0_MASK (volatile unsigned int *)((0x1072 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX0_FIQ_SEL (0x1073) |
| #define P_HCODEC_ASSIST_MBOX0_FIQ_SEL (volatile unsigned int *)((0x1073 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX1_IRQ_REG (0x1074) |
| #define P_HCODEC_ASSIST_MBOX1_IRQ_REG (volatile unsigned int *)((0x1074 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX1_CLR_REG (0x1075) |
| #define P_HCODEC_ASSIST_MBOX1_CLR_REG (volatile unsigned int *)((0x1075 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX1_MASK (0x1076) |
| #define P_HCODEC_ASSIST_MBOX1_MASK (volatile unsigned int *)((0x1076 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX1_FIQ_SEL (0x1077) |
| #define P_HCODEC_ASSIST_MBOX1_FIQ_SEL (volatile unsigned int *)((0x1077 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX2_IRQ_REG (0x1078) |
| #define P_HCODEC_ASSIST_MBOX2_IRQ_REG (volatile unsigned int *)((0x1078 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX2_CLR_REG (0x1079) |
| #define P_HCODEC_ASSIST_MBOX2_CLR_REG (volatile unsigned int *)((0x1079 << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX2_MASK (0x107a) |
| #define P_HCODEC_ASSIST_MBOX2_MASK (volatile unsigned int *)((0x107a << 2) + 0xff620000) |
| #define HCODEC_ASSIST_MBOX2_FIQ_SEL (0x107b) |
| #define P_HCODEC_ASSIST_MBOX2_FIQ_SEL (volatile unsigned int *)((0x107b << 2) + 0xff620000) |
| //------------------------------------------------------------------------------ |
| // MDEC module level register offset |
| //------------------------------------------------------------------------------ |
| // |
| // Reading file: mdec_regs.h |
| // |
| //======================================================================== |
| // MDEC module level register offset |
| //======================================================================== |
| // ----------------------------------------------- |
| // CBUS_BASE: DOS_VDEC_MDEC_CBUS_BASE = 0x09 |
| // ----------------------------------------------- |
| #define MC_CTRL_REG (0x0900) |
| #define P_MC_CTRL_REG (volatile unsigned int *)((0x0900 << 2) + 0xff620000) |
| #define MC_MB_INFO (0x0901) |
| #define P_MC_MB_INFO (volatile unsigned int *)((0x0901 << 2) + 0xff620000) |
| #define MC_PIC_INFO (0x0902) |
| #define P_MC_PIC_INFO (volatile unsigned int *)((0x0902 << 2) + 0xff620000) |
| #define MC_HALF_PEL_ONE (0x0903) |
| #define P_MC_HALF_PEL_ONE (volatile unsigned int *)((0x0903 << 2) + 0xff620000) |
| #define MC_HALF_PEL_TWO (0x0904) |
| #define P_MC_HALF_PEL_TWO (volatile unsigned int *)((0x0904 << 2) + 0xff620000) |
| #define POWER_CTL_MC (0x0905) |
| #define P_POWER_CTL_MC (volatile unsigned int *)((0x0905 << 2) + 0xff620000) |
| #define MC_CMD (0x0906) |
| #define P_MC_CMD (volatile unsigned int *)((0x0906 << 2) + 0xff620000) |
| #define MC_CTRL0 (0x0907) |
| #define P_MC_CTRL0 (volatile unsigned int *)((0x0907 << 2) + 0xff620000) |
| #define MC_PIC_W_H (0x0908) |
| #define P_MC_PIC_W_H (volatile unsigned int *)((0x0908 << 2) + 0xff620000) |
| #define MC_STATUS0 (0x0909) |
| #define P_MC_STATUS0 (volatile unsigned int *)((0x0909 << 2) + 0xff620000) |
| #define MC_STATUS1 (0x090a) |
| #define P_MC_STATUS1 (volatile unsigned int *)((0x090a << 2) + 0xff620000) |
| #define MC_CTRL1 (0x090b) |
| #define P_MC_CTRL1 (volatile unsigned int *)((0x090b << 2) + 0xff620000) |
| #define MC_MIX_RATIO0 (0x090c) |
| #define P_MC_MIX_RATIO0 (volatile unsigned int *)((0x090c << 2) + 0xff620000) |
| #define MC_MIX_RATIO1 (0x090d) |
| #define P_MC_MIX_RATIO1 (volatile unsigned int *)((0x090d << 2) + 0xff620000) |
| #define MC_DP_MB_XY (0x090e) |
| #define P_MC_DP_MB_XY (volatile unsigned int *)((0x090e << 2) + 0xff620000) |
| #define MC_OM_MB_XY (0x090f) |
| #define P_MC_OM_MB_XY (volatile unsigned int *)((0x090f << 2) + 0xff620000) |
| #define PSCALE_RST (0x0910) |
| #define P_PSCALE_RST (volatile unsigned int *)((0x0910 << 2) + 0xff620000) |
| #define PSCALE_CTRL (0x0911) |
| #define P_PSCALE_CTRL (volatile unsigned int *)((0x0911 << 2) + 0xff620000) |
| #define PSCALE_PICI_W (0x0912) |
| #define P_PSCALE_PICI_W (volatile unsigned int *)((0x0912 << 2) + 0xff620000) |
| #define PSCALE_PICI_H (0x0913) |
| #define P_PSCALE_PICI_H (volatile unsigned int *)((0x0913 << 2) + 0xff620000) |
| #define PSCALE_PICO_W (0x0914) |
| #define P_PSCALE_PICO_W (volatile unsigned int *)((0x0914 << 2) + 0xff620000) |
| #define PSCALE_PICO_H (0x0915) |
| #define P_PSCALE_PICO_H (volatile unsigned int *)((0x0915 << 2) + 0xff620000) |
| #define PSCALE_PICO_START_X (0x0916) |
| #define P_PSCALE_PICO_START_X (volatile unsigned int *)((0x0916 << 2) + 0xff620000) |
| #define PSCALE_PICO_START_Y (0x0917) |
| #define P_PSCALE_PICO_START_Y (volatile unsigned int *)((0x0917 << 2) + 0xff620000) |
| #define PSCALE_DUMMY (0x0918) |
| #define P_PSCALE_DUMMY (volatile unsigned int *)((0x0918 << 2) + 0xff620000) |
| #define PSCALE_FILT0_COEF0 (0x0919) |
| #define P_PSCALE_FILT0_COEF0 (volatile unsigned int *)((0x0919 << 2) + 0xff620000) |
| #define PSCALE_FILT0_COEF1 (0x091a) |
| #define P_PSCALE_FILT0_COEF1 (volatile unsigned int *)((0x091a << 2) + 0xff620000) |
| #define PSCALE_CMD_CTRL (0x091b) |
| #define P_PSCALE_CMD_CTRL (volatile unsigned int *)((0x091b << 2) + 0xff620000) |
| #define PSCALE_CMD_BLK_X (0x091c) |
| #define P_PSCALE_CMD_BLK_X (volatile unsigned int *)((0x091c << 2) + 0xff620000) |
| #define PSCALE_CMD_BLK_Y (0x091d) |
| #define P_PSCALE_CMD_BLK_Y (volatile unsigned int *)((0x091d << 2) + 0xff620000) |
| #define PSCALE_STATUS (0x091e) |
| #define P_PSCALE_STATUS (volatile unsigned int *)((0x091e << 2) + 0xff620000) |
| #define PSCALE_BMEM_ADDR (0x091f) |
| #define P_PSCALE_BMEM_ADDR (volatile unsigned int *)((0x091f << 2) + 0xff620000) |
| #define PSCALE_BMEM_DAT (0x0920) |
| #define P_PSCALE_BMEM_DAT (volatile unsigned int *)((0x0920 << 2) + 0xff620000) |
| #define PSCALE_DRAM_BUF_CTRL (0x0921) |
| #define P_PSCALE_DRAM_BUF_CTRL (volatile unsigned int *)((0x0921 << 2) + 0xff620000) |
| #define PSCALE_MCMD_CTRL (0x0922) |
| #define P_PSCALE_MCMD_CTRL (volatile unsigned int *)((0x0922 << 2) + 0xff620000) |
| #define PSCALE_MCMD_XSIZE (0x0923) |
| #define P_PSCALE_MCMD_XSIZE (volatile unsigned int *)((0x0923 << 2) + 0xff620000) |
| #define PSCALE_MCMD_YSIZE (0x0924) |
| #define P_PSCALE_MCMD_YSIZE (volatile unsigned int *)((0x0924 << 2) + 0xff620000) |
| #define PSCALE_RBUF_START_BLKX (0x0925) |
| #define P_PSCALE_RBUF_START_BLKX (volatile unsigned int *)((0x0925 << 2) + 0xff620000) |
| #define PSCALE_RBUF_START_BLKY (0x0926) |
| #define P_PSCALE_RBUF_START_BLKY (volatile unsigned int *)((0x0926 << 2) + 0xff620000) |
| //`define PSCALE_RBUF_MB_WIDTH 8'h27 |
| #define PSCALE_PICO_SHIFT_XY (0x0928) |
| #define P_PSCALE_PICO_SHIFT_XY (volatile unsigned int *)((0x0928 << 2) + 0xff620000) |
| #define PSCALE_CTRL1 (0x0929) |
| #define P_PSCALE_CTRL1 (volatile unsigned int *)((0x0929 << 2) + 0xff620000) |
| //Bit 15, wmask enable |
| //Bit 14:13, filt0 srckey_less, |
| //Bit 12:11, filt1 srckey_less, in the case of the interpolated data is equal distance to |
| //key data and normal data, 00: select normal data, 01: select right data, 10: select key data |
| //Bit 10:9, srckey mode, 00: equal, 01: less than or equal, 10: great than or equal |
| //Bit 8, src key enable |
| //Bit 7:0, y src key |
| #define PSCALE_SRCKEY_CTRL0 (0x092a) |
| #define P_PSCALE_SRCKEY_CTRL0 (volatile unsigned int *)((0x092a << 2) + 0xff620000) |
| //Bit 15:8, cb src key |
| //Bit 7:0, cr src key |
| #define PSCALE_SRCKEY_CTRL1 (0x092b) |
| #define P_PSCALE_SRCKEY_CTRL1 (volatile unsigned int *)((0x092b << 2) + 0xff620000) |
| //Bit 22:16 canvas_rd_addr2 |
| //Bit 14:8 canvas_rd_addr1 |
| //Bit 6:0 canvas_rd_addr1 |
| #define PSCALE_CANVAS_RD_ADDR (0x092c) |
| #define P_PSCALE_CANVAS_RD_ADDR (volatile unsigned int *)((0x092c << 2) + 0xff620000) |
| //Bit 22:16 canvas_wr_addr2 |
| //Bit 14:8 canvas_wr_addr1 |
| //Bit 6:0 canvas_wr_addr1 |
| #define PSCALE_CANVAS_WR_ADDR (0x092d) |
| #define P_PSCALE_CANVAS_WR_ADDR (volatile unsigned int *)((0x092d << 2) + 0xff620000) |
| //bit 13:8 pscale thread ID and token |
| //bit 7 disable write response count adding to busy bit |
| //bit 5:0 pscale prearbitor burst num |
| #define PSCALE_CTRL2 (0x092e) |
| #define P_PSCALE_CTRL2 (volatile unsigned int *)((0x092e << 2) + 0xff620000) |
| // 31 - use_omem_mb_xy_auto |
| //23:16 - omem_max_mb_x |
| //15:8 - omem_mb_y_auto |
| // 7:0 - omem_mb_x_auto |
| #define HDEC_MC_OMEM_AUTO (0x0930) |
| #define P_HDEC_MC_OMEM_AUTO (volatile unsigned int *)((0x0930 << 2) + 0xff620000) |
| #define HDEC_MC_MBRIGHT_IDX (0x0931) |
| #define P_HDEC_MC_MBRIGHT_IDX (volatile unsigned int *)((0x0931 << 2) + 0xff620000) |
| #define HDEC_MC_MBRIGHT_RD (0x0932) |
| #define P_HDEC_MC_MBRIGHT_RD (volatile unsigned int *)((0x0932 << 2) + 0xff620000) |
| #define MC_MPORT_CTRL (0x0940) |
| #define P_MC_MPORT_CTRL (volatile unsigned int *)((0x0940 << 2) + 0xff620000) |
| #define MC_MPORT_DAT (0x0941) |
| #define P_MC_MPORT_DAT (volatile unsigned int *)((0x0941 << 2) + 0xff620000) |
| #define MC_WT_PRED_CTRL (0x0942) |
| #define P_MC_WT_PRED_CTRL (volatile unsigned int *)((0x0942 << 2) + 0xff620000) |
| #define MC_MBBOT_ST_EVEN_ADDR (0x0944) |
| #define P_MC_MBBOT_ST_EVEN_ADDR (volatile unsigned int *)((0x0944 << 2) + 0xff620000) |
| #define MC_MBBOT_ST_ODD_ADDR (0x0945) |
| #define P_MC_MBBOT_ST_ODD_ADDR (volatile unsigned int *)((0x0945 << 2) + 0xff620000) |
| #define MC_DPDN_MB_XY (0x0946) |
| #define P_MC_DPDN_MB_XY (volatile unsigned int *)((0x0946 << 2) + 0xff620000) |
| #define MC_OMDN_MB_XY (0x0947) |
| #define P_MC_OMDN_MB_XY (volatile unsigned int *)((0x0947 << 2) + 0xff620000) |
| #define MC_HCMDBUF_H (0x0948) |
| #define P_MC_HCMDBUF_H (volatile unsigned int *)((0x0948 << 2) + 0xff620000) |
| #define MC_HCMDBUF_L (0x0949) |
| #define P_MC_HCMDBUF_L (volatile unsigned int *)((0x0949 << 2) + 0xff620000) |
| #define MC_HCMD_H (0x094a) |
| #define P_MC_HCMD_H (volatile unsigned int *)((0x094a << 2) + 0xff620000) |
| #define MC_HCMD_L (0x094b) |
| #define P_MC_HCMD_L (volatile unsigned int *)((0x094b << 2) + 0xff620000) |
| #define MC_IDCT_DAT (0x094c) |
| #define P_MC_IDCT_DAT (volatile unsigned int *)((0x094c << 2) + 0xff620000) |
| #define MC_CTRL_GCLK_CTRL (0x094d) |
| #define P_MC_CTRL_GCLK_CTRL (volatile unsigned int *)((0x094d << 2) + 0xff620000) |
| #define MC_OTHER_GCLK_CTRL (0x094e) |
| #define P_MC_OTHER_GCLK_CTRL (volatile unsigned int *)((0x094e << 2) + 0xff620000) |
| //Bit 29:24, mbbot thread ID and token |
| //Bit 21:16, mc read/write thread ID and token |
| //Bit 13:8, mbbot pre-arbitor burst number |
| //Bit 5:0, mc pre-arbitor burst number |
| #define MC_CTRL2 (0x094f) |
| #define P_MC_CTRL2 (volatile unsigned int *)((0x094f << 2) + 0xff620000) |
| // `define DBLK_QUANT 8'h76 // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo |
| //`define ANC1_CANVAS_ADDR 8'h80 |
| //`define ANC2_CANVAS_ADDR 8'h81 |
| //`define REC_CANVAS_ADDR 8'h89 |
| //`define MDEC_PIC_W 8'h8c |
| //`define MDEC_PIC_H 8'h8d |
| // mdec_pic_dc_mux_ctrl[31] -- mcr_hevc_mode |
| #define MDEC_PIC_DC_MUX_CTRL (0x098d) |
| #define P_MDEC_PIC_DC_MUX_CTRL (volatile unsigned int *)((0x098d << 2) + 0xff620000) |
| #define MDEC_PIC_DC_CTRL (0x098e) |
| #define P_MDEC_PIC_DC_CTRL (volatile unsigned int *)((0x098e << 2) + 0xff620000) |
| #define MDEC_PIC_DC_STATUS (0x098f) |
| #define P_MDEC_PIC_DC_STATUS (volatile unsigned int *)((0x098f << 2) + 0xff620000) |
| #define ANC0_CANVAS_ADDR (0x0990) |
| #define P_ANC0_CANVAS_ADDR (volatile unsigned int *)((0x0990 << 2) + 0xff620000) |
| #define ANC1_CANVAS_ADDR (0x0991) |
| #define P_ANC1_CANVAS_ADDR (volatile unsigned int *)((0x0991 << 2) + 0xff620000) |
| #define ANC2_CANVAS_ADDR (0x0992) |
| #define P_ANC2_CANVAS_ADDR (volatile unsigned int *)((0x0992 << 2) + 0xff620000) |
| #define ANC3_CANVAS_ADDR (0x0993) |
| #define P_ANC3_CANVAS_ADDR (volatile unsigned int *)((0x0993 << 2) + 0xff620000) |
| #define ANC4_CANVAS_ADDR (0x0994) |
| #define P_ANC4_CANVAS_ADDR (volatile unsigned int *)((0x0994 << 2) + 0xff620000) |
| #define ANC5_CANVAS_ADDR (0x0995) |
| #define P_ANC5_CANVAS_ADDR (volatile unsigned int *)((0x0995 << 2) + 0xff620000) |
| #define ANC6_CANVAS_ADDR (0x0996) |
| #define P_ANC6_CANVAS_ADDR (volatile unsigned int *)((0x0996 << 2) + 0xff620000) |
| #define ANC7_CANVAS_ADDR (0x0997) |
| #define P_ANC7_CANVAS_ADDR (volatile unsigned int *)((0x0997 << 2) + 0xff620000) |
| #define ANC8_CANVAS_ADDR (0x0998) |
| #define P_ANC8_CANVAS_ADDR (volatile unsigned int *)((0x0998 << 2) + 0xff620000) |
| #define ANC9_CANVAS_ADDR (0x0999) |
| #define P_ANC9_CANVAS_ADDR (volatile unsigned int *)((0x0999 << 2) + 0xff620000) |
| #define ANC10_CANVAS_ADDR (0x099a) |
| #define P_ANC10_CANVAS_ADDR (volatile unsigned int *)((0x099a << 2) + 0xff620000) |
| #define ANC11_CANVAS_ADDR (0x099b) |
| #define P_ANC11_CANVAS_ADDR (volatile unsigned int *)((0x099b << 2) + 0xff620000) |
| #define ANC12_CANVAS_ADDR (0x099c) |
| #define P_ANC12_CANVAS_ADDR (volatile unsigned int *)((0x099c << 2) + 0xff620000) |
| #define ANC13_CANVAS_ADDR (0x099d) |
| #define P_ANC13_CANVAS_ADDR (volatile unsigned int *)((0x099d << 2) + 0xff620000) |
| #define ANC14_CANVAS_ADDR (0x099e) |
| #define P_ANC14_CANVAS_ADDR (volatile unsigned int *)((0x099e << 2) + 0xff620000) |
| #define ANC15_CANVAS_ADDR (0x099f) |
| #define P_ANC15_CANVAS_ADDR (volatile unsigned int *)((0x099f << 2) + 0xff620000) |
| #define ANC16_CANVAS_ADDR (0x09a0) |
| #define P_ANC16_CANVAS_ADDR (volatile unsigned int *)((0x09a0 << 2) + 0xff620000) |
| #define ANC17_CANVAS_ADDR (0x09a1) |
| #define P_ANC17_CANVAS_ADDR (volatile unsigned int *)((0x09a1 << 2) + 0xff620000) |
| #define ANC18_CANVAS_ADDR (0x09a2) |
| #define P_ANC18_CANVAS_ADDR (volatile unsigned int *)((0x09a2 << 2) + 0xff620000) |
| #define ANC19_CANVAS_ADDR (0x09a3) |
| #define P_ANC19_CANVAS_ADDR (volatile unsigned int *)((0x09a3 << 2) + 0xff620000) |
| #define ANC20_CANVAS_ADDR (0x09a4) |
| #define P_ANC20_CANVAS_ADDR (volatile unsigned int *)((0x09a4 << 2) + 0xff620000) |
| #define ANC21_CANVAS_ADDR (0x09a5) |
| #define P_ANC21_CANVAS_ADDR (volatile unsigned int *)((0x09a5 << 2) + 0xff620000) |
| #define ANC22_CANVAS_ADDR (0x09a6) |
| #define P_ANC22_CANVAS_ADDR (volatile unsigned int *)((0x09a6 << 2) + 0xff620000) |
| #define ANC23_CANVAS_ADDR (0x09a7) |
| #define P_ANC23_CANVAS_ADDR (volatile unsigned int *)((0x09a7 << 2) + 0xff620000) |
| #define ANC24_CANVAS_ADDR (0x09a8) |
| #define P_ANC24_CANVAS_ADDR (volatile unsigned int *)((0x09a8 << 2) + 0xff620000) |
| #define ANC25_CANVAS_ADDR (0x09a9) |
| #define P_ANC25_CANVAS_ADDR (volatile unsigned int *)((0x09a9 << 2) + 0xff620000) |
| #define ANC26_CANVAS_ADDR (0x09aa) |
| #define P_ANC26_CANVAS_ADDR (volatile unsigned int *)((0x09aa << 2) + 0xff620000) |
| #define ANC27_CANVAS_ADDR (0x09ab) |
| #define P_ANC27_CANVAS_ADDR (volatile unsigned int *)((0x09ab << 2) + 0xff620000) |
| #define ANC28_CANVAS_ADDR (0x09ac) |
| #define P_ANC28_CANVAS_ADDR (volatile unsigned int *)((0x09ac << 2) + 0xff620000) |
| #define ANC29_CANVAS_ADDR (0x09ad) |
| #define P_ANC29_CANVAS_ADDR (volatile unsigned int *)((0x09ad << 2) + 0xff620000) |
| #define ANC30_CANVAS_ADDR (0x09ae) |
| #define P_ANC30_CANVAS_ADDR (volatile unsigned int *)((0x09ae << 2) + 0xff620000) |
| #define ANC31_CANVAS_ADDR (0x09af) |
| #define P_ANC31_CANVAS_ADDR (volatile unsigned int *)((0x09af << 2) + 0xff620000) |
| #define DBKR_CANVAS_ADDR (0x09b0) |
| #define P_DBKR_CANVAS_ADDR (volatile unsigned int *)((0x09b0 << 2) + 0xff620000) |
| #define DBKW_CANVAS_ADDR (0x09b1) |
| #define P_DBKW_CANVAS_ADDR (volatile unsigned int *)((0x09b1 << 2) + 0xff620000) |
| #define REC_CANVAS_ADDR (0x09b2) |
| #define P_REC_CANVAS_ADDR (volatile unsigned int *)((0x09b2 << 2) + 0xff620000) |
| //28:24, read/write, current canvas idx, used in h264 only now |
| //23:0, read only, current canvas address, 23:16, Cr canvas addr, 15:8, Cb canvas addr, 7:0, Y canvas addr |
| #define CURR_CANVAS_CTRL (0x09b3) |
| #define P_CURR_CANVAS_CTRL (volatile unsigned int *)((0x09b3 << 2) + 0xff620000) |
| #define MDEC_PIC_DC_THRESH (0x09b8) |
| #define P_MDEC_PIC_DC_THRESH (volatile unsigned int *)((0x09b8 << 2) + 0xff620000) |
| #define MDEC_PICR_BUF_STATUS (0x09b9) |
| #define P_MDEC_PICR_BUF_STATUS (volatile unsigned int *)((0x09b9 << 2) + 0xff620000) |
| #define MDEC_PICW_BUF_STATUS (0x09ba) |
| #define P_MDEC_PICW_BUF_STATUS (volatile unsigned int *)((0x09ba << 2) + 0xff620000) |
| #define MCW_DBLK_WRRSP_CNT (0x09bb) |
| #define P_MCW_DBLK_WRRSP_CNT (volatile unsigned int *)((0x09bb << 2) + 0xff620000) |
| #define MC_MBBOT_WRRSP_CNT (0x09bc) |
| #define P_MC_MBBOT_WRRSP_CNT (volatile unsigned int *)((0x09bc << 2) + 0xff620000) |
| #define MDEC_PICW_BUF2_STATUS (0x09bd) |
| #define P_MDEC_PICW_BUF2_STATUS (volatile unsigned int *)((0x09bd << 2) + 0xff620000) |
| #define WRRSP_FIFO_PICW_DBK (0x09be) |
| #define P_WRRSP_FIFO_PICW_DBK (volatile unsigned int *)((0x09be << 2) + 0xff620000) |
| #define WRRSP_FIFO_PICW_MC (0x09bf) |
| #define P_WRRSP_FIFO_PICW_MC (volatile unsigned int *)((0x09bf << 2) + 0xff620000) |
| #define AV_SCRATCH_0 (0x09c0) |
| #define P_AV_SCRATCH_0 (volatile unsigned int *)((0x09c0 << 2) + 0xff620000) |
| #define AV_SCRATCH_1 (0x09c1) |
| #define P_AV_SCRATCH_1 (volatile unsigned int *)((0x09c1 << 2) + 0xff620000) |
| #define AV_SCRATCH_2 (0x09c2) |
| #define P_AV_SCRATCH_2 (volatile unsigned int *)((0x09c2 << 2) + 0xff620000) |
| #define AV_SCRATCH_3 (0x09c3) |
| #define P_AV_SCRATCH_3 (volatile unsigned int *)((0x09c3 << 2) + 0xff620000) |
| #define AV_SCRATCH_4 (0x09c4) |
| #define P_AV_SCRATCH_4 (volatile unsigned int *)((0x09c4 << 2) + 0xff620000) |
| #define AV_SCRATCH_5 (0x09c5) |
| #define P_AV_SCRATCH_5 (volatile unsigned int *)((0x09c5 << 2) + 0xff620000) |
| #define AV_SCRATCH_6 (0x09c6) |
| #define P_AV_SCRATCH_6 (volatile unsigned int *)((0x09c6 << 2) + 0xff620000) |
| #define AV_SCRATCH_7 (0x09c7) |
| #define P_AV_SCRATCH_7 (volatile unsigned int *)((0x09c7 << 2) + 0xff620000) |
| #define AV_SCRATCH_8 (0x09c8) |
| #define P_AV_SCRATCH_8 (volatile unsigned int *)((0x09c8 << 2) + 0xff620000) |
| #define AV_SCRATCH_9 (0x09c9) |
| #define P_AV_SCRATCH_9 (volatile unsigned int *)((0x09c9 << 2) + 0xff620000) |
| #define AV_SCRATCH_A (0x09ca) |
| #define P_AV_SCRATCH_A (volatile unsigned int *)((0x09ca << 2) + 0xff620000) |
| #define AV_SCRATCH_B (0x09cb) |
| #define P_AV_SCRATCH_B (volatile unsigned int *)((0x09cb << 2) + 0xff620000) |
| #define AV_SCRATCH_C (0x09cc) |
| #define P_AV_SCRATCH_C (volatile unsigned int *)((0x09cc << 2) + 0xff620000) |
| #define AV_SCRATCH_D (0x09cd) |
| #define P_AV_SCRATCH_D (volatile unsigned int *)((0x09cd << 2) + 0xff620000) |
| #define AV_SCRATCH_E (0x09ce) |
| #define P_AV_SCRATCH_E (volatile unsigned int *)((0x09ce << 2) + 0xff620000) |
| #define AV_SCRATCH_F (0x09cf) |
| #define P_AV_SCRATCH_F (volatile unsigned int *)((0x09cf << 2) + 0xff620000) |
| #define AV_SCRATCH_G (0x09d0) |
| #define P_AV_SCRATCH_G (volatile unsigned int *)((0x09d0 << 2) + 0xff620000) |
| #define AV_SCRATCH_H (0x09d1) |
| #define P_AV_SCRATCH_H (volatile unsigned int *)((0x09d1 << 2) + 0xff620000) |
| #define AV_SCRATCH_I (0x09d2) |
| #define P_AV_SCRATCH_I (volatile unsigned int *)((0x09d2 << 2) + 0xff620000) |
| #define AV_SCRATCH_J (0x09d3) |
| #define P_AV_SCRATCH_J (volatile unsigned int *)((0x09d3 << 2) + 0xff620000) |
| #define AV_SCRATCH_K (0x09d4) |
| #define P_AV_SCRATCH_K (volatile unsigned int *)((0x09d4 << 2) + 0xff620000) |
| #define AV_SCRATCH_L (0x09d5) |
| #define P_AV_SCRATCH_L (volatile unsigned int *)((0x09d5 << 2) + 0xff620000) |
| #define AV_SCRATCH_M (0x09d6) |
| #define P_AV_SCRATCH_M (volatile unsigned int *)((0x09d6 << 2) + 0xff620000) |
| #define AV_SCRATCH_N (0x09d7) |
| #define P_AV_SCRATCH_N (volatile unsigned int *)((0x09d7 << 2) + 0xff620000) |
| // bit[29:24] A_brst_num_co_mb |
| // bit[21:16] A_id_co_mb |
| // bit[11:0] wrrsp_count_co_mb |
| #define WRRSP_CO_MB (0x09d8) |
| #define P_WRRSP_CO_MB (volatile unsigned int *)((0x09d8 << 2) + 0xff620000) |
| // bit[29:24] A_brst_num_dcac |
| // bit[21:16] A_id_dcac |
| // bit[11:0] wrrsp_count_dcac |
| #define WRRSP_DCAC (0x09d9) |
| #define P_WRRSP_DCAC (volatile unsigned int *)((0x09d9 << 2) + 0xff620000) |
| // bit[11:0] wrrsp_count_vld |
| #define WRRSP_VLD (0x09da) |
| #define P_WRRSP_VLD (volatile unsigned int *)((0x09da << 2) + 0xff620000) |
| // doublew_cfg0[0]; // Second Channel Enable, 1:Enable 0:Disable |
| // doublew_cfg0[3:1]; // [2:0] Endian Control for Luma |
| // doublew_cfg0[5:4]; // [1:0] Pixel sel by horizontal, 0x:1/2 10:left 11:right |
| // doublew_cfg0[7:6]; // [1:0] Pixel sel by vertical, 0x:1/2 10:up 11:down |
| // doublew_cfg0[8]; // Size by horizontal, 0:original size 1: 1/2 shrunken size |
| // doublew_cfg0[9]; // Size by vertical, 0:original size 1: 1/2 shrunken size |
| // doublew_cfg0[10]; // 1:Round 0:Truncation |
| // doublew_cfg0[11]; // DMA Urgent |
| // doublew_cfg0[17:12]; // [5:0] DMA Burst Number |
| // doublew_cfg0[23:18]; // [5:0] DMA ID |
| // doublew_cfg0[26:24]; // [2:0] Endian Control for Chroma |
| // doublew_cfg0[27]; // Source from, 1:MCW 0:DBLK |
| // doublew_cfg0[29:28]; // [1:0] 0x:select both top and bottom 10:select top 11:select bottom |
| // doublew_cfg0[30]; // 0:no merge 1:automatic merge |
| // doublew_cfg0[31]; // 0:Y addr no change 1:Y addr divided to half |
| #define MDEC_DOUBLEW_CFG0 (0x09db) |
| #define P_MDEC_DOUBLEW_CFG0 (volatile unsigned int *)((0x09db << 2) + 0xff620000) |
| // doublew_cfg1[7:0]; // [7:0] DMA Canvas Address for Luma |
| // doublew_cfg1[15:8]; // [7:0] DMA Canvas Address for Chroma |
| // doublew_cfg1[16]; // Disable 1st Write - |
| // doublew_cfg1[17]; // Reverse to original version - |
| // doublew_cfg1[18]; // DMA Address Mode - 0:Canvas Mode 1:Non-Canvas Mode |
| #define MDEC_DOUBLEW_CFG1 (0x09dc) |
| #define P_MDEC_DOUBLEW_CFG1 (volatile unsigned int *)((0x09dc << 2) + 0xff620000) |
| // doublew_cfg2[11:0]; //[11:0] vertical flip initial value |
| // doublew_cfg2[15]; // vertical flip enable |
| // doublew_cfg2[24:16]; // [8:0] horizontal flip initial value |
| // doublew_cfg2[31]; // horizontal flip enable |
| #define MDEC_DOUBLEW_CFG2 (0x09dd) |
| #define P_MDEC_DOUBLEW_CFG2 (volatile unsigned int *)((0x09dd << 2) + 0xff620000) |
| // doublew_cfg3[31:0]; //[31:0] non-canvas start address for Luma - |
| #define MDEC_DOUBLEW_CFG3 (0x09de) |
| #define P_MDEC_DOUBLEW_CFG3 (volatile unsigned int *)((0x09de << 2) + 0xff620000) |
| // doublew_cfg4[31:0]; //[31:0] non-canvas start address for Chroma - |
| #define MDEC_DOUBLEW_CFG4 (0x09df) |
| #define P_MDEC_DOUBLEW_CFG4 (volatile unsigned int *)((0x09df << 2) + 0xff620000) |
| // doublew_cfg5[12:0]; //[12:0] non-canvas picture width for Luma - |
| // doublew_cfg5[28:16]; //[12:0] non-canvas picture width for Chroma - |
| #define MDEC_DOUBLEW_CFG5 (0x09e0) |
| #define P_MDEC_DOUBLEW_CFG5 (volatile unsigned int *)((0x09e0 << 2) + 0xff620000) |
| // doublew_cfg6: reserved |
| #define MDEC_DOUBLEW_CFG6 (0x09e1) |
| #define P_MDEC_DOUBLEW_CFG6 (volatile unsigned int *)((0x09e1 << 2) + 0xff620000) |
| // doublew_cfg7: reserved |
| #define MDEC_DOUBLEW_CFG7 (0x09e2) |
| #define P_MDEC_DOUBLEW_CFG7 (volatile unsigned int *)((0x09e2 << 2) + 0xff620000) |
| // doublew_status[11:0];//[11:0] wrrsp_count_doublew |
| // doublew_status[12]; // doublew_status_busy |
| // doublew_status[13]; // doublew_status_error |
| #define MDEC_DOUBLEW_STATUS (0x09e3) |
| #define P_MDEC_DOUBLEW_STATUS (volatile unsigned int *)((0x09e3 << 2) + 0xff620000) |
| #define MDEC_EXTIF_CFG0 (0x09e4) |
| #define P_MDEC_EXTIF_CFG0 (volatile unsigned int *)((0x09e4 << 2) + 0xff620000) |
| #define MDEC_EXTIF_CFG1 (0x09e5) |
| #define P_MDEC_EXTIF_CFG1 (volatile unsigned int *)((0x09e5 << 2) + 0xff620000) |
| #define MDEC_EXTIF_STS0 (0x09e6) |
| #define P_MDEC_EXTIF_STS0 (volatile unsigned int *)((0x09e6 << 2) + 0xff620000) |
| //====================================== |
| // MC Control Register Bits |
| // |
| //====================================== |
| // For bits, just copy the defines...don't translate to addresses |
| #define MC_ENABLE 0x0001 |
| //`define MC_RESET 16'h0002 |
| #define SKIP_MB 0x0004 |
| |
| //====================================== |
| // MB Info Register Bits |
| // |
| //====================================== |
| #define INTRA_MB 0x0001 |
| |
| #define BWD_PRED 0x0004 |
| #define FWD_PRED 0x0008 |
| |
| #define FLD_MOT 0x0100 |
| #define FRM_16x8_MOT 0x0200 |
| #define DUAL_PRM_MOT 0x0300 |
| |
| #define FRM_DCT 0x0000 // Bit 10 |
| #define FLD_DCT 0x0400 |
| |
| //====================================== |
| // MB Info Register Bits |
| // |
| //====================================== |
| #define I_PIC 0x0001 |
| #define P_PIC 0x0002 |
| #define B_PIC 0x0003 |
| |
| #define FLD_PIC 0x0000 // Bit 8 |
| #define FRM_PIC 0x0100 |
| //======================================================================== |
| // DBLK Register: 12'h950 - 12'h97f |
| //======================================================================== |
| #define DBLK_RST (0x0950) |
| #define P_DBLK_RST (volatile unsigned int *)((0x0950 << 2) + 0xff620000) |
| #define DBLK_CTRL (0x0951) |
| #define P_DBLK_CTRL (volatile unsigned int *)((0x0951 << 2) + 0xff620000) |
| #define DBLK_MB_WID_HEIGHT (0x0952) |
| #define P_DBLK_MB_WID_HEIGHT (volatile unsigned int *)((0x0952 << 2) + 0xff620000) |
| #define DBLK_STATUS (0x0953) |
| #define P_DBLK_STATUS (volatile unsigned int *)((0x0953 << 2) + 0xff620000) |
| #define DBLK_CMD_CTRL (0x0954) |
| #define P_DBLK_CMD_CTRL (volatile unsigned int *)((0x0954 << 2) + 0xff620000) |
| #define DBLK_MB_XY (0x0955) |
| #define P_DBLK_MB_XY (volatile unsigned int *)((0x0955 << 2) + 0xff620000) |
| #define DBLK_QP (0x0956) |
| #define P_DBLK_QP (volatile unsigned int *)((0x0956 << 2) + 0xff620000) |
| #define DBLK_Y_BHFILT (0x0957) |
| #define P_DBLK_Y_BHFILT (volatile unsigned int *)((0x0957 << 2) + 0xff620000) |
| #define DBLK_Y_BHFILT_HIGH (0x0958) |
| #define P_DBLK_Y_BHFILT_HIGH (volatile unsigned int *)((0x0958 << 2) + 0xff620000) |
| #define DBLK_Y_BVFILT (0x0959) |
| #define P_DBLK_Y_BVFILT (volatile unsigned int *)((0x0959 << 2) + 0xff620000) |
| #define DBLK_CB_BFILT (0x095a) |
| #define P_DBLK_CB_BFILT (volatile unsigned int *)((0x095a << 2) + 0xff620000) |
| #define DBLK_CR_BFILT (0x095b) |
| #define P_DBLK_CR_BFILT (volatile unsigned int *)((0x095b << 2) + 0xff620000) |
| #define DBLK_Y_HFILT (0x095c) |
| #define P_DBLK_Y_HFILT (volatile unsigned int *)((0x095c << 2) + 0xff620000) |
| #define DBLK_Y_HFILT_HIGH (0x095d) |
| #define P_DBLK_Y_HFILT_HIGH (volatile unsigned int *)((0x095d << 2) + 0xff620000) |
| #define DBLK_Y_VFILT (0x095e) |
| #define P_DBLK_Y_VFILT (volatile unsigned int *)((0x095e << 2) + 0xff620000) |
| #define DBLK_CB_FILT (0x095f) |
| #define P_DBLK_CB_FILT (volatile unsigned int *)((0x095f << 2) + 0xff620000) |
| #define DBLK_CR_FILT (0x0960) |
| #define P_DBLK_CR_FILT (volatile unsigned int *)((0x0960 << 2) + 0xff620000) |
| #define DBLK_BETAX_QP_SEL (0x0961) |
| #define P_DBLK_BETAX_QP_SEL (volatile unsigned int *)((0x0961 << 2) + 0xff620000) |
| #define DBLK_CLIP_CTRL0 (0x0962) |
| #define P_DBLK_CLIP_CTRL0 (volatile unsigned int *)((0x0962 << 2) + 0xff620000) |
| #define DBLK_CLIP_CTRL1 (0x0963) |
| #define P_DBLK_CLIP_CTRL1 (volatile unsigned int *)((0x0963 << 2) + 0xff620000) |
| #define DBLK_CLIP_CTRL2 (0x0964) |
| #define P_DBLK_CLIP_CTRL2 (volatile unsigned int *)((0x0964 << 2) + 0xff620000) |
| #define DBLK_CLIP_CTRL3 (0x0965) |
| #define P_DBLK_CLIP_CTRL3 (volatile unsigned int *)((0x0965 << 2) + 0xff620000) |
| #define DBLK_CLIP_CTRL4 (0x0966) |
| #define P_DBLK_CLIP_CTRL4 (volatile unsigned int *)((0x0966 << 2) + 0xff620000) |
| #define DBLK_CLIP_CTRL5 (0x0967) |
| #define P_DBLK_CLIP_CTRL5 (volatile unsigned int *)((0x0967 << 2) + 0xff620000) |
| #define DBLK_CLIP_CTRL6 (0x0968) |
| #define P_DBLK_CLIP_CTRL6 (volatile unsigned int *)((0x0968 << 2) + 0xff620000) |
| #define DBLK_CLIP_CTRL7 (0x0969) |
| #define P_DBLK_CLIP_CTRL7 (volatile unsigned int *)((0x0969 << 2) + 0xff620000) |
| #define DBLK_CLIP_CTRL8 (0x096a) |
| #define P_DBLK_CLIP_CTRL8 (volatile unsigned int *)((0x096a << 2) + 0xff620000) |
| #define DBLK_STATUS1 (0x096b) |
| #define P_DBLK_STATUS1 (volatile unsigned int *)((0x096b << 2) + 0xff620000) |
| #define DBLK_GCLK_FREE (0x096c) |
| #define P_DBLK_GCLK_FREE (volatile unsigned int *)((0x096c << 2) + 0xff620000) |
| #define DBLK_GCLK_OFF (0x096d) |
| #define P_DBLK_GCLK_OFF (volatile unsigned int *)((0x096d << 2) + 0xff620000) |
| #define DBLK_AVSFLAGS (0x096e) |
| #define P_DBLK_AVSFLAGS (volatile unsigned int *)((0x096e << 2) + 0xff620000) |
| // bit 15:0 |
| #define DBLK_CBPY (0x0970) |
| #define P_DBLK_CBPY (volatile unsigned int *)((0x0970 << 2) + 0xff620000) |
| // bit 11:8 -- deblk_cbpy_bottom |
| // bit 7:4 -- deblk_cbpy_left |
| // bit 3:0 -- deblk_cbpy_top |
| #define DBLK_CBPY_ADJ (0x0971) |
| #define P_DBLK_CBPY_ADJ (volatile unsigned int *)((0x0971 << 2) + 0xff620000) |
| // bit 7:0 -- deblk_cbpc |
| #define DBLK_CBPC (0x0972) |
| #define P_DBLK_CBPC (volatile unsigned int *)((0x0972 << 2) + 0xff620000) |
| // bit 15 -- bottom_mb |
| // bit 14 -- left_mb |
| // bit 13 -- top_mb |
| // bit 12 -- reserved |
| // bit 11:8 -- deblk_cbpc_bottom |
| // bit 7:4 -- deblk_cbpc_left |
| // bit 3:0 -- deblk_cbpc_top |
| #define DBLK_CBPC_ADJ (0x0973) |
| #define P_DBLK_CBPC_ADJ (volatile unsigned int *)((0x0973 << 2) + 0xff620000) |
| // bit 15:8 -- deblk_hmvd -- {left_1, left_0, below_1, below_0, block3-0} |
| // bit 7:0 -- deblk_vmvd -- {top_1, top_0, below_1, below_0, block3-0} |
| #define DBLK_VHMVD (0x0974) |
| #define P_DBLK_VHMVD (volatile unsigned int *)((0x0974 << 2) + 0xff620000) |
| // bit 13:12 -- right_vmvd |
| // bit 11 -- right_above_vmvd |
| // bit 10 -- left_below_hmvd |
| // bit 9 -- disable_dblk_luma |
| // bit 8 -- disable_dblk_chroma |
| // bit 7 -- bBelowRefDiff |
| // bit 6 -- bLeftRefDiff |
| // bit 5 -- bAboveRefDiff |
| // bit 4 -- reserved |
| // bit 3 -- s_below |
| // bit 2 -- s_left |
| // bit 1 -- s_above |
| // bit 0 -- s |
| #define DBLK_STRONG (0x0975) |
| #define P_DBLK_STRONG (volatile unsigned int *)((0x0975 << 2) + 0xff620000) |
| // bit 14:10 -- PQUANT |
| // bit 9:5 -- left_PQUANT |
| // bit 4:0 -- top_PQUANT |
| #define DBLK_RV8_QUANT (0x0976) |
| #define P_DBLK_RV8_QUANT (volatile unsigned int *)((0x0976 << 2) + 0xff620000) |
| #define DBLK_CBUS_HCMD2 (0x0977) |
| #define P_DBLK_CBUS_HCMD2 (volatile unsigned int *)((0x0977 << 2) + 0xff620000) |
| #define DBLK_CBUS_HCMD1 (0x0978) |
| #define P_DBLK_CBUS_HCMD1 (volatile unsigned int *)((0x0978 << 2) + 0xff620000) |
| #define DBLK_CBUS_HCMD0 (0x0979) |
| #define P_DBLK_CBUS_HCMD0 (volatile unsigned int *)((0x0979 << 2) + 0xff620000) |
| #define DBLK_VLD_HCMD2 (0x097a) |
| #define P_DBLK_VLD_HCMD2 (volatile unsigned int *)((0x097a << 2) + 0xff620000) |
| #define DBLK_VLD_HCMD1 (0x097b) |
| #define P_DBLK_VLD_HCMD1 (volatile unsigned int *)((0x097b << 2) + 0xff620000) |
| #define DBLK_VLD_HCMD0 (0x097c) |
| #define P_DBLK_VLD_HCMD0 (volatile unsigned int *)((0x097c << 2) + 0xff620000) |
| #define DBLK_OST_YBASE (0x097d) |
| #define P_DBLK_OST_YBASE (volatile unsigned int *)((0x097d << 2) + 0xff620000) |
| #define DBLK_OST_CBCRDIFF (0x097e) |
| #define P_DBLK_OST_CBCRDIFF (volatile unsigned int *)((0x097e << 2) + 0xff620000) |
| //13:8 dblk thread ID and token |
| //5:0 dblk prearbitor burst num |
| #define DBLK_CTRL1 (0x097f) |
| #define P_DBLK_CTRL1 (volatile unsigned int *)((0x097f << 2) + 0xff620000) |
| // MCRCC_CTL1 |
| // 31:3 <reserved[23:0]> |
| // 2 <cfg_field_pic> |
| // 1 <sw_rst> |
| // 0 <bypass_en> |
| #define MCRCC_CTL1 (0x0980) |
| #define P_MCRCC_CTL1 (volatile unsigned int *)((0x0980 << 2) + 0xff620000) |
| // MCRCC_CTL2 |
| // 31:24 <cfg_cache_anc01_c[7:0]> |
| // 23:16 <cfg_cache_anc01_y[7:0]> |
| // 15:8 <cfg_cache_anc00_c[7:0]> |
| // 7:0 <cfg_cache_anc00_y[7:0]> |
| #define MCRCC_CTL2 (0x0981) |
| #define P_MCRCC_CTL2 (volatile unsigned int *)((0x0981 << 2) + 0xff620000) |
| // MCRCC_CTL3 |
| // 31:24 <cfg_cache_anc11_c[7:0]> |
| // 23:16 <cfg_cache_anc11_y[7:0]> |
| // 15:8 <cfg_cache_anc10_c[7:0]> |
| // 7:0 <cfg_cache_anc10_y[7:0]> |
| #define MCRCC_CTL3 (0x0982) |
| #define P_MCRCC_CTL3 (volatile unsigned int *)((0x0982 << 2) + 0xff620000) |
| // bit[31:10] reserved |
| // bit[9:0] sw_clock_gating control |
| // [9] vdec clk_en for assist and cbus. |
| // [8] vdec clk_en for ddr |
| // [7] vdec clk_en for vcpu |
| // [6] vdec clk_en for assist |
| // [5] vdec clk_en for dblk |
| // [4] vdec clk_en for iqidct |
| // [3] vdec clk_en for mc |
| // [2] vdec clk_en for pic_dc |
| // [1] vdec clk_en for psc |
| // [0] vdec clk_en for vld |
| #define GCLK_EN (0x0983) |
| #define P_GCLK_EN (volatile unsigned int *)((0x0983 << 2) + 0xff620000) |
| // [0] Reserved |
| // [1] Reserved |
| // [2] Reset assist, mdec's CBUS |
| // [3] Reset mdec's VLD |
| // [4] Reset mdec's VLD |
| // [5] Reset mdec's VLD |
| // [6] Reset mdec's IQIDCT |
| // [7] Reset mdec's MC |
| // [8] Reset mdec's DBLK |
| // [9] Reset mdec's PIC_DC |
| // [10] Reset mdec's Pscale |
| // [11] Reset vcpu's MCPU |
| // [12] Reset vcpu's CCPU |
| // [13] Reset mmc_pre_arb |
| #define MDEC_SW_RESET (0x0984) |
| #define P_MDEC_SW_RESET (volatile unsigned int *)((0x0984 << 2) + 0xff620000) |
| //DBLK last address 12'h97f |
| // |
| // Closing file: mdec_regs.h |
| // |
| //------------------------------------------------------------------------------ |
| // VLD module level register offset |
| //------------------------------------------------------------------------------ |
| // |
| // Reading file: vld_regs.h |
| // |
| //======================================================================== |
| // VLD module level register offset |
| //======================================================================== |
| // ----------------------------------------------- |
| // CBUS_BASE: DOS_VDEC_VLD_CBUS_BASE = 0x0c |
| // ----------------------------------------------- |
| #define VLD_STATUS_CTRL (0x0c00) |
| #define P_VLD_STATUS_CTRL (volatile unsigned int *)((0x0c00 << 2) + 0xff620000) |
| // |
| // bit 10 -- use_old_shift_en |
| // bit 9 -- output_mv_not_pmv |
| // bit 8:5 -- force_zigzag |
| // bit 4 -- force_zigzag_en |
| // bit 3 -- disable_viff_anempty_int |
| // bit 2 -- disable_m2_ac_coeff_one_cycle |
| // bit 1 -- forced_reset force reset pmv |
| // bit 0 -- mpeg_type 0:mpeg1 1: mpeg2 |
| #define MPEG1_2_REG (0x0c01) |
| #define P_MPEG1_2_REG (volatile unsigned int *)((0x0c01 << 2) + 0xff620000) |
| #define F_CODE_REG (0x0c02) |
| #define P_F_CODE_REG (volatile unsigned int *)((0x0c02 << 2) + 0xff620000) |
| #define PIC_HEAD_INFO (0x0c03) |
| #define P_PIC_HEAD_INFO (volatile unsigned int *)((0x0c03 << 2) + 0xff620000) |
| #define SLICE_VER_POS_PIC_TYPE (0x0c04) |
| #define P_SLICE_VER_POS_PIC_TYPE (volatile unsigned int *)((0x0c04 << 2) + 0xff620000) |
| #define QP_VALUE_REG (0x0c05) |
| #define P_QP_VALUE_REG (volatile unsigned int *)((0x0c05 << 2) + 0xff620000) |
| #define MBA_INC (0x0c06) |
| #define P_MBA_INC (volatile unsigned int *)((0x0c06 << 2) + 0xff620000) |
| #define MB_MOTION_MODE (0x0c07) |
| #define P_MB_MOTION_MODE (volatile unsigned int *)((0x0c07 << 2) + 0xff620000) |
| //`define PACKET_BYTE_COUNT 8'h08 |
| // bit 15 -- force_search_startcode_en |
| // bit 14 -- int_cpu_when_error (before do anything) |
| // bit 13 -- vld_error_reset |
| // bit 12 -- return_on_slice_header |
| // bit 6 -- jpeg_ff00_en |
| // bit 5:0 -- vld_power_ctl |
| #define POWER_CTL_VLD (0x0c08) |
| #define P_POWER_CTL_VLD (volatile unsigned int *)((0x0c08 << 2) + 0xff620000) |
| #define MB_WIDTH (0x0c09) |
| #define P_MB_WIDTH (volatile unsigned int *)((0x0c09 << 2) + 0xff620000) |
| #define SLICE_QP (0x0c0a) |
| #define P_SLICE_QP (volatile unsigned int *)((0x0c0a << 2) + 0xff620000) |
| // `define MB_X_MB_Y 8'h0b /* current MBX and MBY */ |
| #define PRE_START_CODE (0x0c0b) |
| #define P_PRE_START_CODE (volatile unsigned int *)((0x0c0b << 2) + 0xff620000) |
| #define SLICE_START_BYTE_01 (0x0c0c) |
| #define P_SLICE_START_BYTE_01 (volatile unsigned int *)((0x0c0c << 2) + 0xff620000) |
| #define SLICE_START_BYTE_23 (0x0c0d) |
| #define P_SLICE_START_BYTE_23 (volatile unsigned int *)((0x0c0d << 2) + 0xff620000) |
| #define RESYNC_MARKER_LENGTH (0x0c0e) |
| #define P_RESYNC_MARKER_LENGTH (volatile unsigned int *)((0x0c0e << 2) + 0xff620000) |
| // bit[6:5] - frame/field info, 01 - top, 10 - bottom, 11 - frame |
| // bit[4:0] - buffer ID |
| // L0_BUFF_ID_0, L0_BUFF_ID_1, L1_BUFF_ID_0, L1_BUFF_ID_1 |
| #define DECODER_BUFFER_INFO (0x0c0f) |
| #define P_DECODER_BUFFER_INFO (volatile unsigned int *)((0x0c0f << 2) + 0xff620000) |
| #define FST_FOR_MV_X (0x0c10) |
| #define P_FST_FOR_MV_X (volatile unsigned int *)((0x0c10 << 2) + 0xff620000) |
| #define FST_FOR_MV_Y (0x0c11) |
| #define P_FST_FOR_MV_Y (volatile unsigned int *)((0x0c11 << 2) + 0xff620000) |
| #define SCD_FOR_MV_X (0x0c12) |
| #define P_SCD_FOR_MV_X (volatile unsigned int *)((0x0c12 << 2) + 0xff620000) |
| #define SCD_FOR_MV_Y (0x0c13) |
| #define P_SCD_FOR_MV_Y (volatile unsigned int *)((0x0c13 << 2) + 0xff620000) |
| #define FST_BAK_MV_X (0x0c14) |
| #define P_FST_BAK_MV_X (volatile unsigned int *)((0x0c14 << 2) + 0xff620000) |
| #define FST_BAK_MV_Y (0x0c15) |
| #define P_FST_BAK_MV_Y (volatile unsigned int *)((0x0c15 << 2) + 0xff620000) |
| #define SCD_BAK_MV_X (0x0c16) |
| #define P_SCD_BAK_MV_X (volatile unsigned int *)((0x0c16 << 2) + 0xff620000) |
| #define SCD_BAK_MV_Y (0x0c17) |
| #define P_SCD_BAK_MV_Y (volatile unsigned int *)((0x0c17 << 2) + 0xff620000) |
| // Bit 7:4 -- read_buffer_interlace 0-progressive, 1-interlace, used in VC1 |
| // bit 3 -- disable_new_stcode_search_fix // From GXM |
| // bit 2 -- weighting_prediction |
| // bit 1 -- mb_weighting_flag |
| // bit 0 -- slice_weighting_flag |
| #define VLD_DECODE_CONTROL (0x0c18) |
| #define P_VLD_DECODE_CONTROL (volatile unsigned int *)((0x0c18 << 2) + 0xff620000) |
| #define VLD_REVERVED_19 (0x0c19) |
| #define P_VLD_REVERVED_19 (volatile unsigned int *)((0x0c19 << 2) + 0xff620000) |
| #define VIFF_BIT_CNT (0x0c1a) |
| #define P_VIFF_BIT_CNT (volatile unsigned int *)((0x0c1a << 2) + 0xff620000) |
| #define BYTE_ALIGN_PEAK_HI (0x0c1b) |
| #define P_BYTE_ALIGN_PEAK_HI (volatile unsigned int *)((0x0c1b << 2) + 0xff620000) |
| #define BYTE_ALIGN_PEAK_LO (0x0c1c) |
| #define P_BYTE_ALIGN_PEAK_LO (volatile unsigned int *)((0x0c1c << 2) + 0xff620000) |
| #define NEXT_ALIGN_PEAK (0x0c1d) |
| #define P_NEXT_ALIGN_PEAK (volatile unsigned int *)((0x0c1d << 2) + 0xff620000) |
| // bit 31 : byte_aligned_zero_23_from_org // From GXM |
| // bit 30 : force_shift_out_drop_flag_zero // From GXM |
| // bit 29 : en_st_protect_from_org // From GXM |
| // bit 28 : enable_halt_decode_start_voff |
| // bit 27 : disable_C_pred_check |
| // bit 26 : disable_I4_pred_check |
| // bit 25 : disable_I16_pred_check |
| // bit 24 : check_avs_1st_drop |
| // bit 23 : enable_cabac_protect // From GXM |
| // bit 22 : enable_avs_drop_more |
| // bit 21 : reset_avs_drop_ptr |
| // bit 20 : reset_cabac_use_next_at_end_req |
| // bit 19 : vc1_inv_intra_co_mb_ref_rd |
| // bit 18 : vc1_inv_co_mb_ref_rd |
| // bit 17 : vc1_inv_intra_co_mb_ref_wr |
| // bit 16 : vc1_inv_co_mb_ref_wr |
| // bit 15 : disable_mv_cal_begin_only |
| // bit 14 : avs_drop_enable |
| // bit 13:12 : avs_drop_ptr |
| // bit 11:8 : avs_demu_ctl_reg |
| // bit 7 : avs_enable |
| // bit 6 : disable_dblk_hcmd |
| // bit 5 : disable_mc_hcmd |
| // bit 4 : first_mode3_set enable |
| // bit 3 : first_mode3 |
| // bit 2:1 : vc1_profile 0-SP, 1-MP, 2-reserved, 3-AP |
| // bit 0 : vc1_enable |
| #define VC1_CONTROL_REG (0x0c1e) |
| #define P_VC1_CONTROL_REG (volatile unsigned int *)((0x0c1e << 2) + 0xff620000) |
| #define PMV1_X (0x0c20) |
| #define P_PMV1_X (volatile unsigned int *)((0x0c20 << 2) + 0xff620000) |
| #define PMV1_Y (0x0c21) |
| #define P_PMV1_Y (volatile unsigned int *)((0x0c21 << 2) + 0xff620000) |
| #define PMV2_X (0x0c22) |
| #define P_PMV2_X (volatile unsigned int *)((0x0c22 << 2) + 0xff620000) |
| #define PMV2_Y (0x0c23) |
| #define P_PMV2_Y (volatile unsigned int *)((0x0c23 << 2) + 0xff620000) |
| #define PMV3_X (0x0c24) |
| #define P_PMV3_X (volatile unsigned int *)((0x0c24 << 2) + 0xff620000) |
| #define PMV3_Y (0x0c25) |
| #define P_PMV3_Y (volatile unsigned int *)((0x0c25 << 2) + 0xff620000) |
| #define PMV4_X (0x0c26) |
| #define P_PMV4_X (volatile unsigned int *)((0x0c26 << 2) + 0xff620000) |
| #define PMV4_Y (0x0c27) |
| #define P_PMV4_Y (volatile unsigned int *)((0x0c27 << 2) + 0xff620000) |
| // Can't use the same address for different defines |
| // Therefore, create a single define that covers both |
| // Only appears to be used in micro-code since the VLD hardware is |
| // hard coded. |
| // `define M4_TABLE_SELECT 8'h28 // Does this exist in HW ? Added from register_mp2.h |
| // `define M4_TABLE_OUTPUT 8'h28 // Does this exist in HW ? Added from register_mp2.h |
| #define M4_TABLE_SELECT (0x0c28) |
| #define P_M4_TABLE_SELECT (volatile unsigned int *)((0x0c28 << 2) + 0xff620000) |
| #define M4_CONTROL_REG (0x0c29) |
| #define P_M4_CONTROL_REG (volatile unsigned int *)((0x0c29 << 2) + 0xff620000) |
| #define BLOCK_NUM (0x0c2a) |
| #define P_BLOCK_NUM (volatile unsigned int *)((0x0c2a << 2) + 0xff620000) |
| #define PATTERN_CODE (0x0c2b) |
| #define P_PATTERN_CODE (volatile unsigned int *)((0x0c2b << 2) + 0xff620000) |
| #define MB_INFO (0x0c2c) |
| #define P_MB_INFO (volatile unsigned int *)((0x0c2c << 2) + 0xff620000) |
| #define VLD_DC_PRED (0x0c2d) |
| #define P_VLD_DC_PRED (volatile unsigned int *)((0x0c2d << 2) + 0xff620000) |
| #define VLD_ERROR_MASK (0x0c2e) |
| #define P_VLD_ERROR_MASK (volatile unsigned int *)((0x0c2e << 2) + 0xff620000) |
| #define VLD_DC_PRED_C (0x0c2f) |
| #define P_VLD_DC_PRED_C (volatile unsigned int *)((0x0c2f << 2) + 0xff620000) |
| #define LAST_SLICE_MV_ADDR (0x0c30) |
| #define P_LAST_SLICE_MV_ADDR (volatile unsigned int *)((0x0c30 << 2) + 0xff620000) |
| #define LAST_MVX (0x0c31) |
| #define P_LAST_MVX (volatile unsigned int *)((0x0c31 << 2) + 0xff620000) |
| #define LAST_MVY (0x0c32) |
| #define P_LAST_MVY (volatile unsigned int *)((0x0c32 << 2) + 0xff620000) |
| #define VLD_C38 (0x0c38) |
| #define P_VLD_C38 (volatile unsigned int *)((0x0c38 << 2) + 0xff620000) |
| #define VLD_C39 (0x0c39) |
| #define P_VLD_C39 (volatile unsigned int *)((0x0c39 << 2) + 0xff620000) |
| #define VLD_STATUS (0x0c3a) |
| #define P_VLD_STATUS (volatile unsigned int *)((0x0c3a << 2) + 0xff620000) |
| #define VLD_SHIFT_STATUS (0x0c3b) |
| #define P_VLD_SHIFT_STATUS (volatile unsigned int *)((0x0c3b << 2) + 0xff620000) |
| // `define VLD_SHIFT_INFO 8'h3b // Does this exist in HW ? used in $ucode/mpeg4 |
| #define VOFF_STATUS (0x0c3c) |
| #define P_VOFF_STATUS (volatile unsigned int *)((0x0c3c << 2) + 0xff620000) |
| #define VLD_C3D (0x0c3d) |
| #define P_VLD_C3D (volatile unsigned int *)((0x0c3d << 2) + 0xff620000) |
| #define VLD_DBG_INDEX (0x0c3e) |
| #define P_VLD_DBG_INDEX (volatile unsigned int *)((0x0c3e << 2) + 0xff620000) |
| // vld_buff_info -- (index == 0) |
| // Bit11] halt_decode_start_voff |
| // Bit10] C_pred_error |
| // Bit[9] I4_pred_error |
| // Bit[8] I16_pred_error |
| // Bit[7:6] mv_UR_ready_cnt; |
| // Bit[5] vld_wr_idx |
| // Bit[4] iq_rd_idx |
| // Bit[3] vld_vi_block_rdy_1 |
| // Bit[2] vld_vi_block_rdy_2 |
| // Bit[1] voff_empty_1 |
| // Bit[0] voff_empty_2 |
| // cabac_buff_info_0 -- (index == 1) |
| // Bit[31] shift_data_ready |
| // Bit[30:29] Reserved |
| // Bit[28:24] cabac_buffer_ptr |
| // Bit[23:0] cabac_buffer |
| // cabac_buff_info_1 -- (index == 2) |
| // Bit[31:29] Reserved |
| // Bit[28:20] Drange |
| // Bit[19:16] bin_count_4 |
| // Bit[15:13] Reserved |
| // Bit[12:6] context_mem_do |
| // Bit[5:3] coeff_state |
| // Bit[2:0] mvd_state |
| // h264_mv_present -- (index == 3) |
| // Bit[31:16] mv_present_l0 |
| // Bit[15:0] mv_present_l1 |
| // h264_mv_cal_info_0 -- (index == 4) |
| // [31:28] mv_cal_state |
| // [27:24] direct_spatial_cnt |
| // Bit[23:21] Reserved |
| // Bit[20] mv_UR_ready_for_mv_cal |
| // Bit[19] co_mb_mem_ready_for_mv_cal |
| // Bit[18] mc_dblk_cmd_if_busy |
| // Bit[17] h264_co_mb_wr_busy |
| // Bit[16] H264_cbp_blk_ready |
| // Bit[15] mc_hcmd_rrdy |
| // Bit[14] mc_hcmd_srdy |
| // Bit[13] mc_cmd_if_ready |
| // Bit[12] mc_hcmd_mv_available |
| // Bit[11:8] mc_cmd_if_state |
| // Bit[7] dblk_hcmd_rrdy |
| // Bit[6] dblk_hcmd_srdy |
| // Bit[5] dblk_cmd_if_ready |
| // Bit[4] dblk_hcmd_mv_available |
| // Bit[3:0] dblk_cmd_if_state |
| // h264_mv_cal_info_1 -- (index == 5) |
| // Bit[31:29] Reserved |
| // Bit[28:24] total_mvd_num_l0 |
| // Bit[23:21] Reserved |
| // Bit[20:16] mv_cal_ptr_l0 |
| // Bit[15:13] Reserved |
| // Bit[12:8] mc_hcmd_ptr_l0 |
| // Bit[7:5] Reserved |
| // Bit[4:0] dblk_hcmd_ptr_l0 |
| // h264_mv_cal_info_2 -- (index == 6) |
| // Bit[31:29] Reserved |
| // Bit[28:24] total_mvd_num_l1 |
| // Bit[23:21] Reserved |
| // Bit[20:16] mv_cal_ptr_l1 |
| // Bit[15:13] Reserved |
| // Bit[12:8] mc_hcmd_ptr_l1 |
| // Bit[7:5] Reserved |
| // Bit[4:0] dblk_hcmd_ptr_l1 |
| // h264_co_mb_info -- (index == 7) |
| // Bit[31:26] Reserved |
| // Bit[25] mv_scale_cal_busy |
| // Bit[24:20] co_mv_count |
| // Bit[19:16] co_mv_process_state |
| // Bit[15] h264_co_mb_rd_busy |
| // Bit[15] h264_co_mb_rd_ready |
| // Bit[13:12] co_mv_transfer_block_cnt |
| // Bit[11:8] co_mv_transfer_ptr |
| // Bit[7] co_mv_POC_l1_busy |
| // Bit[6] h264_weight_scale_cal_en |
| // Bit[5] weight_cal_busy |
| // Bit[4] weight_cal_not_finished |
| // Bit[3:0] weight_process_state |
| #define VLD_DBG_DATA (0x0c3f) |
| #define P_VLD_DBG_DATA (volatile unsigned int *)((0x0c3f << 2) + 0xff620000) |
| // -------------------------------------------- |
| // VIFIFO DDR Interface |
| // -------------------------------------------- |
| // The VIFIFO start pointer into DDR memory is a 32-bit number |
| // The Start pointer will automatically be truncated to land on |
| // an 8-byte boundary. That is, bits [2:0] = 0; |
| #define VLD_MEM_VIFIFO_START_PTR (0x0c40) |
| #define P_VLD_MEM_VIFIFO_START_PTR (volatile unsigned int *)((0x0c40 << 2) + 0xff620000) |
| // The current pointer points so some location between the START and END |
| // pointers. The current pointer is a BYTE pointer. That is, you can |
| // point to any BYTE address within the START/END range |
| #define VLD_MEM_VIFIFO_CURR_PTR (0x0c41) |
| #define P_VLD_MEM_VIFIFO_CURR_PTR (volatile unsigned int *)((0x0c41 << 2) + 0xff620000) |
| #define VLD_MEM_VIFIFO_END_PTR (0x0c42) |
| #define P_VLD_MEM_VIFIFO_END_PTR (volatile unsigned int *)((0x0c42 << 2) + 0xff620000) |
| #define VLD_MEM_VIFIFO_BYTES_AVAIL (0x0c43) |
| #define P_VLD_MEM_VIFIFO_BYTES_AVAIL (volatile unsigned int *)((0x0c43 << 2) + 0xff620000) |
| // VIFIFO FIFO Control |
| // bit [31:24] viff_empty_int_enable_cpu[7:0] |
| // bit [23:16] viff_empty_int_enable_amrisc[7:0] |
| // -bit 23 Video BUFFER < 0x400 Bytes |
| // -bit 22 Video BUFFER < 0x200 Bytes |
| // -bit 21 Video BUFFER < 0x100 Bytes |
| // -bit 20 Video BUFFER < 0x80 Bytes |
| // -bit 19 Video BUFFER < 0x40 Bytes |
| // -bit 18 Video BUFFER < 0x20 Bytes |
| // -bit 17 vififo < 16 double words |
| // -bit 16 vififo < 8 double words |
| // bit [15:13] unused |
| // bit [12] A_urgent |
| // bit [11] transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request |
| // bit [10] use_level Set this bit to 1 to enable filling of the FIFO controlled by the buffer |
| // level control. If this bit is 0, then use bit[1] to control the enabling of filling |
| // bit [9] Data Ready. This bit is set when data can be popped |
| // bit [8] fill busy This bit will be high when we're fetching data from the DDR memory |
| // To reset this module, set cntl_enable = 0, and then wait for busy = 0. |
| // After that you can pulse cntl_init to start over |
| // bit [7] init_with_cntl_init |
| // bit [6] reserved |
| // bits [5:3] endian: see $lib/rtl/ddr_endian.v |
| // bit [2] cntl_empty_en Set to 1 to enable reading the DDR memory FIFO |
| // Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init |
| // bit [1] cntl_fill_en Set to 1 to enable reading data from DDR memory |
| // bit [0] cntl_init: After setting the read pointers, sizes, channel masks |
| // and read masks, set this bit to 1 and then to 0 |
| // NOTE: You don't need to pulse cntl_init if only the start address is |
| // being changed |
| #define VLD_MEM_VIFIFO_CONTROL (0x0c44) |
| #define P_VLD_MEM_VIFIFO_CONTROL (volatile unsigned int *)((0x0c44 << 2) + 0xff620000) |
| // -------------------------------------------- |
| // VIFIFO Buffer Level Manager |
| // -------------------------------------------- |
| #define VLD_MEM_VIFIFO_WP (0x0c45) |
| #define P_VLD_MEM_VIFIFO_WP (volatile unsigned int *)((0x0c45 << 2) + 0xff620000) |
| #define VLD_MEM_VIFIFO_RP (0x0c46) |
| #define P_VLD_MEM_VIFIFO_RP (volatile unsigned int *)((0x0c46 << 2) + 0xff620000) |
| #define VLD_MEM_VIFIFO_LEVEL (0x0c47) |
| #define P_VLD_MEM_VIFIFO_LEVEL (volatile unsigned int *)((0x0c47 << 2) + 0xff620000) |
| // |
| // bit [8] use_parser_video2_wp |
| // bit [7] vbuf2_out_manual |
| // bit [6] vbuf_out_manual |
| // bit [5] empty (ReadOnly) |
| // bit [4] full (ReadOnly) |
| // bit [3:2] reserved |
| // bit [1] manual mode Set to 1 for manual write pointer mode |
| // bit [0] Init Set high then low after everything has been initialized |
| #define VLD_MEM_VIFIFO_BUF_CNTL (0x0c48) |
| #define P_VLD_MEM_VIFIFO_BUF_CNTL (volatile unsigned int *)((0x0c48 << 2) + 0xff620000) |
| // bit 31:16 -- drop_bytes |
| // bit 15:14 -- drop_status (Read-Only) |
| // bit 13:12 -- sync_match_position (Read-Only) |
| // bit 11:6 -- reserved |
| // bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits |
| // bit 3 -- stamp_soft_reset |
| // bit 2 -- TIME_STAMP_length_enable |
| // bit 1 -- TIME_STAMP_sync64_enable |
| // bit 0 -- TIME_STAMP_enable |
| #define VLD_TIME_STAMP_CNTL (0x0c49) |
| #define P_VLD_TIME_STAMP_CNTL (volatile unsigned int *)((0x0c49 << 2) + 0xff620000) |
| // bit 31:0 -- TIME_STAMP_SYNC_CODE_0 |
| #define VLD_TIME_STAMP_SYNC_0 (0x0c4a) |
| #define P_VLD_TIME_STAMP_SYNC_0 (volatile unsigned int *)((0x0c4a << 2) + 0xff620000) |
| // bit 31:0 -- TIME_STAMP_SYNC_CODE_1 |
| #define VLD_TIME_STAMP_SYNC_1 (0x0c4b) |
| #define P_VLD_TIME_STAMP_SYNC_1 (volatile unsigned int *)((0x0c4b << 2) + 0xff620000) |
| // bit 31:0 TIME_STAMP_0 |
| #define VLD_TIME_STAMP_0 (0x0c4c) |
| #define P_VLD_TIME_STAMP_0 (volatile unsigned int *)((0x0c4c << 2) + 0xff620000) |
| // bit 31:0 TIME_STAMP_1 |
| #define VLD_TIME_STAMP_1 (0x0c4d) |
| #define P_VLD_TIME_STAMP_1 (volatile unsigned int *)((0x0c4d << 2) + 0xff620000) |
| // bit 31:0 TIME_STAMP_2 |
| #define VLD_TIME_STAMP_2 (0x0c4e) |
| #define P_VLD_TIME_STAMP_2 (volatile unsigned int *)((0x0c4e << 2) + 0xff620000) |
| // bit 31:0 TIME_STAMP_3 |
| #define VLD_TIME_STAMP_3 (0x0c4f) |
| #define P_VLD_TIME_STAMP_3 (volatile unsigned int *)((0x0c4f << 2) + 0xff620000) |
| // bit 31:0 TIME_STAMP_LENGTH |
| #define VLD_TIME_STAMP_LENGTH (0x0c50) |
| #define P_VLD_TIME_STAMP_LENGTH (volatile unsigned int *)((0x0c50 << 2) + 0xff620000) |
| // bit 15:0 vififo_rd_count |
| #define VLD_MEM_VIFIFO_WRAP_COUNT (0x0c51) |
| #define P_VLD_MEM_VIFIFO_WRAP_COUNT (volatile unsigned int *)((0x0c51 << 2) + 0xff620000) |
| // bit 29:24 A_brst_num |
| // bit 21:16 A_id |
| // bit 15:0 level_hold |
| #define VLD_MEM_VIFIFO_MEM_CTL (0x0c52) |
| #define P_VLD_MEM_VIFIFO_MEM_CTL (volatile unsigned int *)((0x0c52 << 2) + 0xff620000) |
| #define VLD_MEM_VBUF_RD_PTR (0x0c53) |
| #define P_VLD_MEM_VBUF_RD_PTR (volatile unsigned int *)((0x0c53 << 2) + 0xff620000) |
| #define VLD_MEM_VBUF2_RD_PTR (0x0c54) |
| #define P_VLD_MEM_VBUF2_RD_PTR (volatile unsigned int *)((0x0c54 << 2) + 0xff620000) |
| #define VLD_MEM_SWAP_ADDR (0x0c55) |
| #define P_VLD_MEM_SWAP_ADDR (volatile unsigned int *)((0x0c55 << 2) + 0xff620000) |
| // bit[23:16] - swap_d_count (Read Only) |
| // bit[15:8] - swap_a_count (Read Only) |
| // bit [7] - swap busy (Read Only) |
| // bit [6:2] - reserved |
| // bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory |
| // bit [0] - swap active |
| #define VLD_MEM_SWAP_CTL (0x0c56) |
| #define P_VLD_MEM_SWAP_CTL (volatile unsigned int *)((0x0c56 << 2) + 0xff620000) |
| // |
| // Closing file: vld_regs.h |
| // |
| //------------------------------------------------------------------------------ |
| // IQ/IDCT module level register offset |
| //------------------------------------------------------------------------------ |
| // |
| // Reading file: iqidct_regs.h |
| // |
| //======================================================================== |
| // IQ/IDCT module level register offset |
| //======================================================================== |
| // ----------------------------------------------- |
| // CBUS_BASE: DOS_VDEC_IQIDCT_CBUS_BASE = 0x0e |
| // ----------------------------------------------- |
| #define VCOP_CTRL_REG (0x0e00) |
| #define P_VCOP_CTRL_REG (volatile unsigned int *)((0x0e00 << 2) + 0xff620000) |
| #define QP_CTRL_REG (0x0e01) |
| #define P_QP_CTRL_REG (volatile unsigned int *)((0x0e01 << 2) + 0xff620000) |
| #define INTRA_QUANT_MATRIX (0x0e02) |
| #define P_INTRA_QUANT_MATRIX (volatile unsigned int *)((0x0e02 << 2) + 0xff620000) |
| #define NON_I_QUANT_MATRIX (0x0e03) |
| #define P_NON_I_QUANT_MATRIX (volatile unsigned int *)((0x0e03 << 2) + 0xff620000) |
| #define DC_SCALER (0x0e04) |
| #define P_DC_SCALER (volatile unsigned int *)((0x0e04 << 2) + 0xff620000) |
| #define DC_AC_CTRL (0x0e05) |
| #define P_DC_AC_CTRL (volatile unsigned int *)((0x0e05 << 2) + 0xff620000) |
| // `define RV_AI_CTRL 8'h05 // ONLY for $ucode/real/amrisc/rv.s reg value from apollo |
| #define DC_AC_SCALE_MUL (0x0e06) |
| #define P_DC_AC_SCALE_MUL (volatile unsigned int *)((0x0e06 << 2) + 0xff620000) |
| #define DC_AC_SCALE_DIV (0x0e07) |
| #define P_DC_AC_SCALE_DIV (volatile unsigned int *)((0x0e07 << 2) + 0xff620000) |
| // `define DC_AC_SCALE_RESULT 8'h06 |
| // `define RESERVED_E07 8'h07 |
| #define POWER_CTL_IQIDCT (0x0e08) |
| #define P_POWER_CTL_IQIDCT (volatile unsigned int *)((0x0e08 << 2) + 0xff620000) |
| #define RV_AI_Y_X (0x0e09) |
| #define P_RV_AI_Y_X (volatile unsigned int *)((0x0e09 << 2) + 0xff620000) |
| #define RV_AI_U_X (0x0e0a) |
| #define P_RV_AI_U_X (volatile unsigned int *)((0x0e0a << 2) + 0xff620000) |
| #define RV_AI_V_X (0x0e0b) |
| #define P_RV_AI_V_X (volatile unsigned int *)((0x0e0b << 2) + 0xff620000) |
| // bit 15:0 will count up when rv_ai_mb finished when non zero |
| // and rv_ai_mb_finished_int will be generate when this is not zero |
| #define RV_AI_MB_COUNT (0x0e0c) |
| #define P_RV_AI_MB_COUNT (volatile unsigned int *)((0x0e0c << 2) + 0xff620000) |
| // For H264 I in PB picture Use -- dma type : h264_next_intra_dma |
| #define NEXT_INTRA_DMA_ADDRESS (0x0e0d) |
| #define P_NEXT_INTRA_DMA_ADDRESS (volatile unsigned int *)((0x0e0d << 2) + 0xff620000) |
| // Bit 16 -- dcac_dma_read_cache_disable |
| // Bit 15 -- dcac_dma_urgent |
| // Bit 14 -- nv21_swap |
| // Bit 13 -- nv21_top_dma |
| // Bit 12 -- reset_rv_ai_wait_rd_data |
| // Bit 11 -- set_rv_ai_wait_rd_data [12:11] = 3 means only dec 1 (For Skipped MB of MBAFF) |
| // Bit 10 -- rv_ai_wait_rd_data (Read Only) |
| // Bit 9 -- enable_rv_ai_wait_rd_data |
| // Bit 8 -- disable_vc1_mv_update |
| // Bit 7 -- pred_dc_signed |
| // Bit 6 -- inc_vld_ready_count |
| // Bit 5 -- dec_vld_ready_count |
| // Bit 4 -- disable_ref_bidir_fix |
| // Bit 3 -- disable_MV_UL_l1_bot_fix |
| // Bit 2 -- disable_mb_aff_fix |
| // Bit 1 -- canvas_addr_7 |
| // Bit 0 -- constrained_intra_pred_flag for H264 |
| #define IQIDCT_CONTROL (0x0e0e) |
| #define P_IQIDCT_CONTROL (volatile unsigned int *)((0x0e0e << 2) + 0xff620000) |
| // Bit[31:19] Reserved |
| // Bit[18] iq_waiting |
| // Bit[17] iq_om_wr_idx |
| // Bit[16] iq_om_rd_idx |
| // Bit[15] iq_om_busy |
| // Bit[14] iq_om_2_busy |
| // Bit[13] idx_fifo_0 |
| // Bit[12] idx_fifo_1 |
| // Bit[11] idx_fifo_2 |
| // Bit[10] idx_fifo_3 |
| // Bit[9] idx_fifo_4 |
| // Bit[8] idx_fifo_5 |
| // Bit[7] idx_fifo_6 |
| // Bit[6] idx_fifo_7 |
| // Bit[5:3] idx_fifo_wp |
| // Bit[2:0] idx_fifo_rp |
| #define IQIDCT_DEBUG_INFO_0 (0x0e0f) |
| #define P_IQIDCT_DEBUG_INFO_0 (volatile unsigned int *)((0x0e0f << 2) + 0xff620000) |
| // For RTL Simulation Only |
| #define DEBLK_CMD (0x0e10) |
| #define P_DEBLK_CMD (volatile unsigned int *)((0x0e10 << 2) + 0xff620000) |
| // Bit[15+16] ds_mc_valid_2 |
| // Bit[14+16] new_idct1_rd_idx_2 |
| // Bit[13+16] new_idct1_wr_idx_2 |
| // Bit[12+16] idct1_buff0_busy_2 |
| // Bit[11+16] idct1_buff1_busy_2 |
| // Bit[10+16] new_idct1_busy_2 |
| // Bit[9+16] iq_om_8val_2 |
| // Bit[8+16] idct1_pipe_busy_2 |
| // Bit[7+16] wait_mb_left_finish_hold_2 |
| // Bit[6+16] new_idct2_rd_idx_2 |
| // Bit[5+16] new_idct2_wr_idx_2 |
| // Bit[4+16] idct2_buff0_busy_2 |
| // Bit[3+16] idct2_buff1_busy_2 |
| // Bit[2+16] idct2_en_2 |
| // Bit[1+16] new_idct2_busy_2 |
| // Bit[0+16] new_idct1_ready_2 |
| // Bit[15] ds_mc_valid_1 |
| // Bit[14] new_idct1_rd_idx_1 |
| // Bit[13] new_idct1_wr_idx_1 |
| // Bit[12] idct1_buff0_busy_1 |
| // Bit[11] idct1_buff1_busy_1 |
| // Bit[10] new_idct1_busy_1 |
| // Bit[9] iq_om_8val_1 |
| // Bit[8] idct1_pipe_busy_1 |
| // Bit[7] wait_mb_left_finish_hold_1 |
| // Bit[6] new_idct2_rd_idx_1 |
| // Bit[5] new_idct2_wr_idx_1 |
| // Bit[4] idct2_buff0_busy_1 |
| // Bit[3] idct2_buff1_busy_1 |
| // Bit[2] idct2_en_1 |
| // Bit[1] new_idct2_busy_1 |
| // Bit[0] new_idct1_ready_1 |
| #define IQIDCT_DEBUG_IDCT (0x0e11) |
| #define P_IQIDCT_DEBUG_IDCT (volatile unsigned int *)((0x0e11 << 2) + 0xff620000) |
| // bit 31 -- convas_enable |
| // bit 30:24 -- convas_x_count ( 8 pixels / 64 bits ) |
| // bit 23:16 -- convas_y_count |
| // bit 15 -- dcac_dma_busy |
| // bit 14 -- dcac_dma_read_cache_active |
| // bit 13:8 -- dcac_dma_count |
| // bit 7 -- dcac_dma_rw |
| // bit 6 -- dcac_skip_read_mode |
| // bit 5:0 -- dcac_dma_offset |
| #define DCAC_DMA_CTRL (0x0e12) |
| #define P_DCAC_DMA_CTRL (volatile unsigned int *)((0x0e12 << 2) + 0xff620000) |
| // when (convas_enable == 0 ) |
| // bit 31:0 dcac_dma_addr |
| // when (convas_enable == 1 ) |
| // bit 31:25 canvas_addr (7 bits) |
| // bit 24:12 convas_y_start ( 13 btis ) |
| // bit 11:0 convas_x_start ( 12 btis ) |
| #define DCAC_DMA_ADDRESS (0x0e13) |
| #define P_DCAC_DMA_ADDRESS (volatile unsigned int *)((0x0e13 << 2) + 0xff620000) |
| // bit 7:0 -- dcac_cpu_addr |
| #define DCAC_CPU_ADDRESS (0x0e14) |
| #define P_DCAC_CPU_ADDRESS (volatile unsigned int *)((0x0e14 << 2) + 0xff620000) |
| // bit 31:0 -- dcac_cpu_data |
| #define DCAC_CPU_DATA (0x0e15) |
| #define P_DCAC_CPU_DATA (volatile unsigned int *)((0x0e15 << 2) + 0xff620000) |
| // bit 31:19 -- reserved |
| // bit 18:16 -- block_num_reg -- Read-Only |
| // bit 15:0 -- dcac_mb_count |
| #define DCAC_MB_COUNT (0x0e16) |
| #define P_DCAC_MB_COUNT (volatile unsigned int *)((0x0e16 << 2) + 0xff620000) |
| // bit 31:18 -- reserved |
| // For H264 : |
| // bit 17:2 -- h264_quant |
| // bit 11:6 -- h264_quant_c |
| // bit 5:0 -- h264_quant_c |
| // For VC1 : |
| // bit 17 -- qindex_GT_8 |
| // bit 16 -- HalfQPStep |
| // bit 15:12 -- eQuantMode |
| // bit 11:6 -- AltPQuant |
| // bit 5:0 -- PQuant |
| // |
| #define IQ_QUANT (0x0e17) |
| #define P_IQ_QUANT (volatile unsigned int *)((0x0e17 << 2) + 0xff620000) |
| // bit 31:24 -- bitplane_width |
| // bit 23:16 -- bitplane_height |
| // bit 15:14 -- bitplane_start_x |
| // bit 13:12 -- bitplane_start_y |
| // bit 11:4 -- reserved |
| // bit 3:1 -- bitplane_type |
| // bit 0 -- bitplane_busy |
| #define VC1_BITPLANE_CTL (0x0e18) |
| #define P_VC1_BITPLANE_CTL (volatile unsigned int *)((0x0e18 << 2) + 0xff620000) |
| // bit 24:16 -- wq_param1 |
| // bit 8: 0 -- wq_param0 |
| #define AVSP_IQ_WQ_PARAM_01 (0x0e19) |
| #define P_AVSP_IQ_WQ_PARAM_01 (volatile unsigned int *)((0x0e19 << 2) + 0xff620000) |
| // bit 24:16 -- wq_param3 |
| // bit 8: 0 -- wq_param2 |
| #define AVSP_IQ_WQ_PARAM_23 (0x0e1a) |
| #define P_AVSP_IQ_WQ_PARAM_23 (volatile unsigned int *)((0x0e1a << 2) + 0xff620000) |
| // bit 24:16 -- wq_param5 |
| // bit 8: 0 -- wq_param4 |
| #define AVSP_IQ_WQ_PARAM_45 (0x0e1b) |
| #define P_AVSP_IQ_WQ_PARAM_45 (volatile unsigned int *)((0x0e1b << 2) + 0xff620000) |
| // bit 31 -- weight_quant_en |
| // bit 17:16 -- current_scene_model |
| // bit 12: 8 -- chroma_qp_delta_cr |
| // bit 4: 0 -- chroma_qp_delta_cb |
| #define AVSP_IQ_CTL (0x0e1c) |
| #define P_AVSP_IQ_CTL (volatile unsigned int *)((0x0e1c << 2) + 0xff620000) |
| #define RAM_TEST_CMD 0x002 |
| #define RAM_TEST_ADDR 0x003 |
| #define RAM_TEST_DATAH 0x004 |
| #define RAM_TEST_DATAL 0x005 |
| |
| #define RAM_TEST_RD_CMD 0x0000 |
| #define RAM_TEST_WR_CMD 0x8000 |
| #define IDCT_TM2_PT0 0x0001 |
| #define IDCT_TM2_PT1 0x0002 |
| #define IDCT_TM1_PT0 0x0004 |
| #define IDCT_TM1_PT1 0x0008 |
| #define IQ_OMEM_PT0 0x0010 |
| #define IQ_OMEM_PT1 0x0020 |
| #define MC_IMEM_PT0 0x0040 |
| #define ALL_RAM_PTS 0x007f |
| //====================================== |
| // VCOP Control Register Bits |
| // |
| //====================================== |
| //`define IQIDCT_RESET 16'h0001 // Bit 0 |
| #define QM_WEN 0x0002 // Bit 1 |
| #define IQIDCT_ENABLE 0x0004 // Bit 2 |
| #define INTRA_QM 0x0008 // Bit 3 0 = Use default; 1 = use loaded |
| #define NINTRA_QM 0x0010 // Bit 4 0 = Use default; 1 = use loaded |
| //====================================== |
| // QP Control Register Bits |
| // |
| //====================================== |
| #define INTRA_MODE 0x0080 // Bit 7 |
| // Duplicate Address: When actually used |
| // please move to a different address |
| // `define FLD_DCT_TYPE 16'h0100 // Bit 8 0 = Frame DCT; 1 = field DCT |
| // |
| // Closing file: iqidct_regs.h |
| // |
| //------------------------------------------------------------------------------ |
| // VCPU module level register offset |
| //------------------------------------------------------------------------------ |
| // |
| // Reading file: vcpu_regs.h |
| // |
| //======================================================================== |
| // VCPU module level register offset |
| //======================================================================== |
| // ----------------------------------------------- |
| // CBUS_BASE: DOS_VDEC_VCPU_CBUS_BASE = 0x03 |
| // ----------------------------------------------- |
| #define MSP (0x0300) |
| #define P_MSP (volatile unsigned int *)((0x0300 << 2) + 0xff620000) |
| #define MPSR (0x0301) |
| #define P_MPSR (volatile unsigned int *)((0x0301 << 2) + 0xff620000) |
| #define MINT_VEC_BASE (0x0302) |
| #define P_MINT_VEC_BASE (volatile unsigned int *)((0x0302 << 2) + 0xff620000) |
| #define MCPU_INTR_GRP (0x0303) |
| #define P_MCPU_INTR_GRP (volatile unsigned int *)((0x0303 << 2) + 0xff620000) |
| #define MCPU_INTR_MSK (0x0304) |
| #define P_MCPU_INTR_MSK (volatile unsigned int *)((0x0304 << 2) + 0xff620000) |
| #define MCPU_INTR_REQ (0x0305) |
| #define P_MCPU_INTR_REQ (volatile unsigned int *)((0x0305 << 2) + 0xff620000) |
| #define MPC_P (0x0306) |
| #define P_MPC_P (volatile unsigned int *)((0x0306 << 2) + 0xff620000) |
| #define MPC_D (0x0307) |
| #define P_MPC_D (volatile unsigned int *)((0x0307 << 2) + 0xff620000) |
| #define MPC_E (0x0308) |
| #define P_MPC_E (volatile unsigned int *)((0x0308 << 2) + 0xff620000) |
| #define MPC_W (0x0309) |
| #define P_MPC_W (volatile unsigned int *)((0x0309 << 2) + 0xff620000) |
| #define MINDEX0_REG (0x030a) |
| #define P_MINDEX0_REG (volatile unsigned int *)((0x030a << 2) + 0xff620000) |
| #define MINDEX1_REG (0x030b) |
| #define P_MINDEX1_REG (volatile unsigned int *)((0x030b << 2) + 0xff620000) |
| #define MINDEX2_REG (0x030c) |
| #define P_MINDEX2_REG (volatile unsigned int *)((0x030c << 2) + 0xff620000) |
| #define MINDEX3_REG (0x030d) |
| #define P_MINDEX3_REG (volatile unsigned int *)((0x030d << 2) + 0xff620000) |
| #define MINDEX4_REG (0x030e) |
| #define P_MINDEX4_REG (volatile unsigned int *)((0x030e << 2) + 0xff620000) |
| #define MINDEX5_REG (0x030f) |
| #define P_MINDEX5_REG (volatile unsigned int *)((0x030f << 2) + 0xff620000) |
| #define MINDEX6_REG (0x0310) |
| #define P_MINDEX6_REG (volatile unsigned int *)((0x0310 << 2) + 0xff620000) |
| #define MINDEX7_REG (0x0311) |
| #define P_MINDEX7_REG (volatile unsigned int *)((0x0311 << 2) + 0xff620000) |
| #define MMIN_REG (0x0312) |
| #define P_MMIN_REG (volatile unsigned int *)((0x0312 << 2) + 0xff620000) |
| #define MMAX_REG (0x0313) |
| #define P_MMAX_REG (volatile unsigned int *)((0x0313 << 2) + 0xff620000) |
| #define MBREAK0_REG (0x0314) |
| #define P_MBREAK0_REG (volatile unsigned int *)((0x0314 << 2) + 0xff620000) |
| #define MBREAK1_REG (0x0315) |
| #define P_MBREAK1_REG (volatile unsigned int *)((0x0315 << 2) + 0xff620000) |
| #define MBREAK2_REG (0x0316) |
| #define P_MBREAK2_REG (volatile unsigned int *)((0x0316 << 2) + 0xff620000) |
| #define MBREAK3_REG (0x0317) |
| #define P_MBREAK3_REG (volatile unsigned int *)((0x0317 << 2) + 0xff620000) |
| #define MBREAK_TYPE (0x0318) |
| #define P_MBREAK_TYPE (volatile unsigned int *)((0x0318 << 2) + 0xff620000) |
| #define MBREAK_CTRL (0x0319) |
| #define P_MBREAK_CTRL (volatile unsigned int *)((0x0319 << 2) + 0xff620000) |
| #define MBREAK_STAUTS (0x031a) |
| #define P_MBREAK_STAUTS (volatile unsigned int *)((0x031a << 2) + 0xff620000) |
| #define MDB_ADDR_REG (0x031b) |
| #define P_MDB_ADDR_REG (volatile unsigned int *)((0x031b << 2) + 0xff620000) |
| #define MDB_DATA_REG (0x031c) |
| #define P_MDB_DATA_REG (volatile unsigned int *)((0x031c << 2) + 0xff620000) |
| #define MDB_CTRL (0x031d) |
| #define P_MDB_CTRL (volatile unsigned int *)((0x031d << 2) + 0xff620000) |
| #define MSFTINT0 (0x031e) |
| #define P_MSFTINT0 (volatile unsigned int *)((0x031e << 2) + 0xff620000) |
| #define MSFTINT1 (0x031f) |
| #define P_MSFTINT1 (volatile unsigned int *)((0x031f << 2) + 0xff620000) |
| #define CSP (0x0320) |
| #define P_CSP (volatile unsigned int *)((0x0320 << 2) + 0xff620000) |
| #define CPSR (0x0321) |
| #define P_CPSR (volatile unsigned int *)((0x0321 << 2) + 0xff620000) |
| #define CINT_VEC_BASE (0x0322) |
| #define P_CINT_VEC_BASE (volatile unsigned int *)((0x0322 << 2) + 0xff620000) |
| #define CCPU_INTR_GRP (0x0323) |
| #define P_CCPU_INTR_GRP (volatile unsigned int *)((0x0323 << 2) + 0xff620000) |
| #define CCPU_INTR_MSK (0x0324) |
| #define P_CCPU_INTR_MSK (volatile unsigned int *)((0x0324 << 2) + 0xff620000) |
| #define CCPU_INTR_REQ (0x0325) |
| #define P_CCPU_INTR_REQ (volatile unsigned int *)((0x0325 << 2) + 0xff620000) |
| #define CPC_P (0x0326) |
| #define P_CPC_P (volatile unsigned int *)((0x0326 << 2) + 0xff620000) |
| #define CPC_D (0x0327) |
| #define P_CPC_D (volatile unsigned int *)((0x0327 << 2) + 0xff620000) |
| #define CPC_E (0x0328) |
| #define P_CPC_E (volatile unsigned int *)((0x0328 << 2) + 0xff620000) |
| #define CPC_W (0x0329) |
| #define P_CPC_W (volatile unsigned int *)((0x0329 << 2) + 0xff620000) |
| #define CINDEX0_REG (0x032a) |
| #define P_CINDEX0_REG (volatile unsigned int *)((0x032a << 2) + 0xff620000) |
| #define CINDEX1_REG (0x032b) |
| #define P_CINDEX1_REG (volatile unsigned int *)((0x032b << 2) + 0xff620000) |
| #define CINDEX2_REG (0x032c) |
| #define P_CINDEX2_REG (volatile unsigned int *)((0x032c << 2) + 0xff620000) |
| #define CINDEX3_REG (0x032d) |
| #define P_CINDEX3_REG (volatile unsigned int *)((0x032d << 2) + 0xff620000) |
| #define CINDEX4_REG (0x032e) |
| #define P_CINDEX4_REG (volatile unsigned int *)((0x032e << 2) + 0xff620000) |
| #define CINDEX5_REG (0x032f) |
| #define P_CINDEX5_REG (volatile unsigned int *)((0x032f << 2) + 0xff620000) |
| #define CINDEX6_REG (0x0330) |
| #define P_CINDEX6_REG (volatile unsigned int *)((0x0330 << 2) + 0xff620000) |
| #define CINDEX7_REG (0x0331) |
| #define P_CINDEX7_REG (volatile unsigned int *)((0x0331 << 2) + 0xff620000) |
| #define CMIN_REG (0x0332) |
| #define P_CMIN_REG (volatile unsigned int *)((0x0332 << 2) + 0xff620000) |
| #define CMAX_REG (0x0333) |
| #define P_CMAX_REG (volatile unsigned int *)((0x0333 << 2) + 0xff620000) |
| #define CBREAK0_REG (0x0334) |
| #define P_CBREAK0_REG (volatile unsigned int *)((0x0334 << 2) + 0xff620000) |
| #define CBREAK1_REG (0x0335) |
| #define P_CBREAK1_REG (volatile unsigned int *)((0x0335 << 2) + 0xff620000) |
| #define CBREAK2_REG (0x0336) |
| #define P_CBREAK2_REG (volatile unsigned int *)((0x0336 << 2) + 0xff620000) |
| #define CBREAK3_REG (0x0337) |
| #define P_CBREAK3_REG (volatile unsigned int *)((0x0337 << 2) + 0xff620000) |
| #define CBREAK_TYPE (0x0338) |
| #define P_CBREAK_TYPE (volatile unsigned int *)((0x0338 << 2) + 0xff620000) |
| #define CBREAK_CTRL (0x0339) |
| #define P_CBREAK_CTRL (volatile unsigned int *)((0x0339 << 2) + 0xff620000) |
| #define CBREAK_STAUTS (0x033a) |
| #define P_CBREAK_STAUTS (volatile unsigned int *)((0x033a << 2) + 0xff620000) |
| #define CDB_ADDR_REG (0x033b) |
| #define P_CDB_ADDR_REG (volatile unsigned int *)((0x033b << 2) + 0xff620000) |
| #define CDB_DATA_REG (0x033c) |
| #define P_CDB_DATA_REG (volatile unsigned int *)((0x033c << 2) + 0xff620000) |
| #define CDB_CTRL (0x033d) |
| #define P_CDB_CTRL (volatile unsigned int *)((0x033d << 2) + 0xff620000) |
| #define CSFTINT0 (0x033e) |
| #define P_CSFTINT0 (volatile unsigned int *)((0x033e << 2) + 0xff620000) |
| #define CSFTINT1 (0x033f) |
| #define P_CSFTINT1 (volatile unsigned int *)((0x033f << 2) + 0xff620000) |
| #define IMEM_DMA_CTRL (0x0340) |
| #define P_IMEM_DMA_CTRL (volatile unsigned int *)((0x0340 << 2) + 0xff620000) |
| #define IMEM_DMA_ADR (0x0341) |
| #define P_IMEM_DMA_ADR (volatile unsigned int *)((0x0341 << 2) + 0xff620000) |
| #define IMEM_DMA_COUNT (0x0342) |
| #define P_IMEM_DMA_COUNT (volatile unsigned int *)((0x0342 << 2) + 0xff620000) |
| // bit[29:24] A_brst_num_imem |
| // bit[21:16] A_id_imem |
| // bit[11:0] wrrsp_count_imem (reserved) |
| #define WRRSP_IMEM (0x0343) |
| #define P_WRRSP_IMEM (volatile unsigned int *)((0x0343 << 2) + 0xff620000) |
| #define LMEM_DMA_CTRL (0x0350) |
| #define P_LMEM_DMA_CTRL (volatile unsigned int *)((0x0350 << 2) + 0xff620000) |
| #define LMEM_DMA_ADR (0x0351) |
| #define P_LMEM_DMA_ADR (volatile unsigned int *)((0x0351 << 2) + 0xff620000) |
| #define LMEM_DMA_COUNT (0x0352) |
| #define P_LMEM_DMA_COUNT (volatile unsigned int *)((0x0352 << 2) + 0xff620000) |
| // bit[29:24] A_brst_num_lmem |
| // bit[21:16] A_id_lmem |
| // bit[11:0] wrrsp_count_lmem |
| #define WRRSP_LMEM (0x0353) |
| #define P_WRRSP_LMEM (volatile unsigned int *)((0x0353 << 2) + 0xff620000) |
| #define MAC_CTRL1 (0x0360) |
| #define P_MAC_CTRL1 (volatile unsigned int *)((0x0360 << 2) + 0xff620000) |
| #define ACC0REG1 (0x0361) |
| #define P_ACC0REG1 (volatile unsigned int *)((0x0361 << 2) + 0xff620000) |
| #define ACC1REG1 (0x0362) |
| #define P_ACC1REG1 (volatile unsigned int *)((0x0362 << 2) + 0xff620000) |
| #define MAC_CTRL2 (0x0370) |
| #define P_MAC_CTRL2 (volatile unsigned int *)((0x0370 << 2) + 0xff620000) |
| #define ACC0REG2 (0x0371) |
| #define P_ACC0REG2 (volatile unsigned int *)((0x0371 << 2) + 0xff620000) |
| #define ACC1REG2 (0x0372) |
| #define P_ACC1REG2 (volatile unsigned int *)((0x0372 << 2) + 0xff620000) |
| #define CPU_TRACE (0x0380) |
| #define P_CPU_TRACE (volatile unsigned int *)((0x0380 << 2) + 0xff620000) |
| // |
| // Closing file: vcpu_regs.h |
| // |
| //------------------------------------------------------------------------------ |
| // HENC module level register offset |
| //------------------------------------------------------------------------------ |
| // |
| // Reading file: henc_regs.h |
| // |
| //======================================================================== |
| // MDEC module level register offset |
| //======================================================================== |
| // ----------------------------------------------- |
| // CBUS_BASE: DOS_HCODEC_HENC_CBUS_BASE = 0x0a |
| // ----------------------------------------------- |
| #define HENC_SCRATCH_0 (0x1ac0) |
| #define P_HENC_SCRATCH_0 (volatile unsigned int *)((0x1ac0 << 2) + 0xff620000) |
| #define HENC_SCRATCH_1 (0x1ac1) |
| #define P_HENC_SCRATCH_1 (volatile unsigned int *)((0x1ac1 << 2) + 0xff620000) |
| #define HENC_SCRATCH_2 (0x1ac2) |
| #define P_HENC_SCRATCH_2 (volatile unsigned int *)((0x1ac2 << 2) + 0xff620000) |
| #define HENC_SCRATCH_3 (0x1ac3) |
| #define P_HENC_SCRATCH_3 (volatile unsigned int *)((0x1ac3 << 2) + 0xff620000) |
| #define HENC_SCRATCH_4 (0x1ac4) |
| #define P_HENC_SCRATCH_4 (volatile unsigned int *)((0x1ac4 << 2) + 0xff620000) |
| #define HENC_SCRATCH_5 (0x1ac5) |
| #define P_HENC_SCRATCH_5 (volatile unsigned int *)((0x1ac5 << 2) + 0xff620000) |
| #define HENC_SCRATCH_6 (0x1ac6) |
| #define P_HENC_SCRATCH_6 (volatile unsigned int *)((0x1ac6 << 2) + 0xff620000) |
| #define HENC_SCRATCH_7 (0x1ac7) |
| #define P_HENC_SCRATCH_7 (volatile unsigned int *)((0x1ac7 << 2) + 0xff620000) |
| #define HENC_SCRATCH_8 (0x1ac8) |
| #define P_HENC_SCRATCH_8 (volatile unsigned int *)((0x1ac8 << 2) + 0xff620000) |
| #define HENC_SCRATCH_9 (0x1ac9) |
| #define P_HENC_SCRATCH_9 (volatile unsigned int *)((0x1ac9 << 2) + 0xff620000) |
| #define HENC_SCRATCH_A (0x1aca) |
| #define P_HENC_SCRATCH_A (volatile unsigned int *)((0x1aca << 2) + 0xff620000) |
| #define HENC_SCRATCH_B (0x1acb) |
| #define P_HENC_SCRATCH_B (volatile unsigned int *)((0x1acb << 2) + 0xff620000) |
| #define HENC_SCRATCH_C (0x1acc) |
| #define P_HENC_SCRATCH_C (volatile unsigned int *)((0x1acc << 2) + 0xff620000) |
| #define HENC_SCRATCH_D (0x1acd) |
| #define P_HENC_SCRATCH_D (volatile unsigned int *)((0x1acd << 2) + 0xff620000) |
| #define HENC_SCRATCH_E (0x1ace) |
| #define P_HENC_SCRATCH_E (volatile unsigned int *)((0x1ace << 2) + 0xff620000) |
| #define HENC_SCRATCH_F (0x1acf) |
| #define P_HENC_SCRATCH_F (volatile unsigned int *)((0x1acf << 2) + 0xff620000) |
| #define HENC_SCRATCH_G (0x1ad0) |
| #define P_HENC_SCRATCH_G (volatile unsigned int *)((0x1ad0 << 2) + 0xff620000) |
| #define HENC_SCRATCH_H (0x1ad1) |
| #define P_HENC_SCRATCH_H (volatile unsigned int *)((0x1ad1 << 2) + 0xff620000) |
| #define HENC_SCRATCH_I (0x1ad2) |
| #define P_HENC_SCRATCH_I (volatile unsigned int *)((0x1ad2 << 2) + 0xff620000) |
| #define HENC_SCRATCH_J (0x1ad3) |
| #define P_HENC_SCRATCH_J (volatile unsigned int *)((0x1ad3 << 2) + 0xff620000) |
| #define HENC_SCRATCH_K (0x1ad4) |
| #define P_HENC_SCRATCH_K (volatile unsigned int *)((0x1ad4 << 2) + 0xff620000) |
| #define HENC_SCRATCH_L (0x1ad5) |
| #define P_HENC_SCRATCH_L (volatile unsigned int *)((0x1ad5 << 2) + 0xff620000) |
| #define HENC_SCRATCH_M (0x1ad6) |
| #define P_HENC_SCRATCH_M (volatile unsigned int *)((0x1ad6 << 2) + 0xff620000) |
| #define HENC_SCRATCH_N (0x1ad7) |
| #define P_HENC_SCRATCH_N (volatile unsigned int *)((0x1ad7 << 2) + 0xff620000) |
| // bit [7:0] data_feed_buff_id |
| #define IE_DATA_FEED_BUFF_INFO (0x1ad8) |
| #define P_IE_DATA_FEED_BUFF_INFO (volatile unsigned int *)((0x1ad8 << 2) + 0xff620000) |
| // |
| // Closing file: henc_regs.h |
| // |
| //------------------------------------------------------------------------------ |
| // VLC module level register offset |
| //------------------------------------------------------------------------------ |
| // |
| // Reading file: vlc_regs.h |
| // |
| //======================================================================== |
| // VLC module level register offset |
| //======================================================================== |
| // ----------------------------------------------- |
| // CBUS_BASE: DOS_HCODEC_VLC_CBUS_BASE = 0x0d |
| // ----------------------------------------------- |
| // Bit[31:28] - henc_status |
| // Bit[27:8] - reserved |
| // Bit[7] mc_hcmd_buff_enable |
| // Bit[6] mc_hcmd_use_mc_hcmd_buff |
| // Bit[5] mc_hcmd_use_mc_hcmd_hw_start |
| // Bit[4] no_mc_out_null_non_skipped_mb |
| // Bit[3] mc_out_even_skipped_mb |
| // Bit[2] - hcmd_enable |
| // Bit[1] - vlc_control_enable (0 will treat as soft_reset) |
| // Bit[0] - vlc_input_enable (enable input interface) |
| #define VLC_STATUS_CTRL (0x1d00) |
| #define P_VLC_STATUS_CTRL (volatile unsigned int *)((0x1d00 << 2) + 0xff620000) |
| // Bit [31] - small_luma_ignore_chroma |
| // Bit[30:16] - Reserved |
| // Bit [15] - enable_free_clk_mc_hcmd_buff |
| // Bit [14] - enable_free_clk_reg |
| // Bit [13] - enable_free_clk_stream |
| // Bit [12] - enable_free_clk_pre_buff |
| // Bit [11] - enable_free_clk_vb_buff |
| // Bit [10] - enable_free_clk_dc_input |
| // Bit [9] - enable_free_clk_input |
| // Bit [8] - enable_free_clk_mv_cal |
| // Bit [7] - enable_free_clk_status |
| // Bit [6] - enable_free_clk_mc_dblk_cmd_if |
| // Bit [5] - disable_mvd_enc_finished |
| // Bit [4] - I16MB_share_ipred_mode_with_I4MB |
| // Bit [3] - fixed_picture_qp |
| // Bit [2] - use_set_b8_mode ( not used now) |
| // Bit [1] - use_set_mb_skip_run |
| // Bit [0] - pop_coeff_even_all_zero |
| #define VLC_CONFIG (0x1d01) |
| #define P_VLC_CONFIG (volatile unsigned int *)((0x1d01 << 2) + 0xff620000) |
| // -------------------------------------------- |
| // Bitstream DDR Interface |
| // -------------------------------------------- |
| #define VLC_VB_START_PTR (0x1d10) |
| #define P_VLC_VB_START_PTR (volatile unsigned int *)((0x1d10 << 2) + 0xff620000) |
| #define VLC_VB_END_PTR (0x1d11) |
| #define P_VLC_VB_END_PTR (volatile unsigned int *)((0x1d11 << 2) + 0xff620000) |
| #define VLC_VB_WR_PTR (0x1d12) |
| #define P_VLC_VB_WR_PTR (volatile unsigned int *)((0x1d12 << 2) + 0xff620000) |
| // Read Only, VLC_VB_SW_RD_PTR or VLC_VB_HW_RD_PTR |
| #define VLC_VB_RD_PTR (0x1d13) |
| #define P_VLC_VB_RD_PTR (volatile unsigned int *)((0x1d13 << 2) + 0xff620000) |
| #define VLC_VB_SW_RD_PTR (0x1d14) |
| #define P_VLC_VB_SW_RD_PTR (volatile unsigned int *)((0x1d14 << 2) + 0xff620000) |
| // Read Only |
| #define VLC_VB_LEFT (0x1d15) |
| #define P_VLC_VB_LEFT (volatile unsigned int *)((0x1d15 << 2) + 0xff620000) |
| // VB FIFO Control |
| // bit [31:24] vb_full_int_enable_cpu[7:0] |
| // bit [23:16] vb_full_int_enable_amrisc[7:0] |
| // -bit 23 Video BUFFER LEFT < 0x400 Bytes |
| // -bit 22 Video BUFFER LEFT < 0x200 Bytes |
| // -bit 21 Video BUFFER LEFT < 0x100 Bytes |
| // -bit 20 Video BUFFER LEFT < 0x80 Bytes |
| // -bit 19 Video BUFFER LEFT < 0x40 Bytes |
| // -bit 18 Video BUFFER LEFT < 0x20 Bytes |
| // -bit 17 vbfifo left < 16 double words (8x64bits) |
| // -bit 16 vbfifo left < 8 double words (4x64bits) |
| // bit [15] wr_ptr_int_enable_cpu |
| // bit [14] wr_ptr_int_enable_amrisc |
| // bit [13] wr_ptr_int (Read Only, write 1 will clear) |
| // bit [12] vb_full_int_enable_cpu(Read Only) |
| // bit [11] vb_full_int_enable_amrisc(Read Only) |
| // bit [10] reserved |
| // bit [9] use_vb_hw_rd_ptr |
| // bit [8] vb_always_ready Set to 1 to ignore vb_level blocking DDR write |
| // bit [7] vb_ready_for_transfer (Read Only) |
| // bit [6] data_ready_for_transfer (Read Only) |
| // bits [5:3] vb_endian Set VB Endian inside DDR memory |
| // bit [2] vb_write_busy Read Only - indicate DDR write busy |
| // bit [1] vb_write_en Set to 1 to enable writing data to DDR memory |
| // bit [0] vb_soft_reset Soft reset |
| #define VLC_VB_CONTROL (0x1d16) |
| #define P_VLC_VB_CONTROL (volatile unsigned int *)((0x1d16 << 2) + 0xff620000) |
| // bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0 |
| // bit 30 A_urgent // default : 0 |
| // bit 29:24 A_brst_num // default : 0x3f |
| // bit 23:22 reserved |
| // bit 21:16 A_id // default : 0x20 |
| // bit 15:0 vb_left_hold // default : 0 |
| #define VLC_VB_MEM_CTL (0x1d17) |
| #define P_VLC_VB_MEM_CTL (volatile unsigned int *)((0x1d17 << 2) + 0xff620000) |
| // vb_wr_ptr address to generate interrupt |
| #define VLC_VB_INT_PTR (0x1d18) |
| #define P_VLC_VB_INT_PTR (volatile unsigned int *)((0x1d18 << 2) + 0xff620000) |
| // bit[31:12] reserved |
| // bit[11:0] vlc_wrrsp_count |
| #define VLC_WRRSP (0x1d19) |
| #define P_VLC_WRRSP (volatile unsigned int *)((0x1d19 << 2) + 0xff620000) |
| #define VLC_TOTAL_BYTES (0x1d1a) |
| #define P_VLC_TOTAL_BYTES (volatile unsigned int *)((0x1d1a << 2) + 0xff620000) |
| // bit [31:26] reserved |
| // bit [25] vb_flush |
| // bit [24] vb_reg_ready |
| // bit [23:16] vb_buff_left -- Read only |
| // bit [15:8] vb_buff_wr_point -- RW |
| // bit [7:0] vb_buff_rd_point -- RW |
| #define VLC_VB_BUFF (0x1d1b) |
| #define P_VLC_VB_BUFF (volatile unsigned int *)((0x1d1b << 2) + 0xff620000) |
| // bit[31] flush_vlc_pre_buff |
| // bit[30:27] reserved |
| // bit[26:24] vb_pre_buff_level |
| // bit[23:0] vb_pre_buff_data[55:32] |
| #define VLC_VB_PRE_BUFF_HI (0x1d1c) |
| #define P_VLC_VB_PRE_BUFF_HI (volatile unsigned int *)((0x1d1c << 2) + 0xff620000) |
| // bit[31:0] vb_pre_buff_data[31:0] |
| #define VLC_VB_PRE_BUFF_LOW (0x1d1d) |
| #define P_VLC_VB_PRE_BUFF_LOW (volatile unsigned int *)((0x1d1d << 2) + 0xff620000) |
| // bit[31] stream_encap_enable // 0x0000(00-03) will be changed to 0x000003(00-03) if enabled |
| // bit[30:29] stream_encap_delay // delay bytes for encap used |
| // bit[28:24] stream_buff_point |
| // bit[23:0] stream_buff_data |
| #define VLC_STREAM_BUFF (0x1d1e) |
| #define P_VLC_STREAM_BUFF (volatile unsigned int *)((0x1d1e << 2) + 0xff620000) |
| // bit[31] push_stream_block - Read Only (Will set if vb_buff full) |
| // bit[30] push_stream_busy - Read Only (busy when output one byte from stream_buf (max 2 clocks for 8 bits push) |
| // bit[29:28] stream_encap_status - Read Only |
| // bit[27:21] reserved |
| // Long Mode : (Amrisc need movilo and mvihi high to set stream_info) |
| // bit[20:16] push_stream_long_length (0 or 31 : Mid or Short mode) |
| // bit[15:0] push_stream_data |
| // Mid Mode : (Amrisc need movi to set stream_info) |
| // bit[15:12]] push_stream_mid_length (1-12 : mid mode active, 0-short mode, 15 - byte align) |
| // bit[11:0] push_stream_data |
| // Short Mode : (Amrisc can use mtspi to push stream directely) |
| // bit[7:5] push_stream_short_length (0-5 : short length, else - invalid) |
| // bit[4:0] push_stream_data |
| #define VLC_PUSH_STREAM (0x1d1f) |
| #define P_VLC_PUSH_STREAM (volatile unsigned int *)((0x1d1f << 2) + 0xff620000) |
| // bit[15:8] ELEMENT_LENGTH |
| // bit[7:1] reserved |
| // bit[0] Write - push start, Read - Push Busy |
| #define VLC_PUSH_ELEMENT (0x1d20) |
| #define P_VLC_PUSH_ELEMENT (volatile unsigned int *)((0x1d20 << 2) + 0xff620000) |
| #define VLC_ELEMENT_DATA (0x1d21) |
| #define P_VLC_ELEMENT_DATA (volatile unsigned int *)((0x1d21 << 2) + 0xff620000) |
| // bit[7] hcmd_intra_use_sw_info |
| // bit[6] hcmd_use_sw_info |
| // bit[5] always_use_info_0_cbp_blk |
| // bit[4] always_update_info_0_cbp_blk |
| // bit[3] reset_left_mb_wr |
| // bit[2] reset_top_mb_wr |
| // bit[1] set_left_mb_wr |
| // bit[0] set_top_mb_wr |
| #define VLC_SPECIAL_CTL (0x1d22) |
| #define P_VLC_SPECIAL_CTL (volatile unsigned int *)((0x1d22 << 2) + 0xff620000) |
| // bit[28] left_intra |
| // bit[27:22] left_quant |
| // bit[21:16] left_quant_c |
| // bit[12] top_intra |
| // bit[11:6] top_quant |
| // bit[5:0] top_quant_c |
| #define VLC_HCMD_T_L_INFO (0x1d23) |
| #define P_VLC_HCMD_T_L_INFO (volatile unsigned int *)((0x1d23 << 2) + 0xff620000) |
| // bit[12] cur_intra |
| // bit[11:6] cur_quant |
| // bit[5:0] cur_quant_c |
| #define VLC_HCMD_CUR_INFO (0x1d24) |
| #define P_VLC_HCMD_CUR_INFO (volatile unsigned int *)((0x1d24 << 2) + 0xff620000) |
| // bit[13] top_left_info_in_data_mv_cal |
| // bit[12] only_use_info_0_top_left_in_I |
| // bit[11] top_left_info_in_data |
| // bit[10] early_mix_mc_hcmd |
| // bit[9] update_top_left_mix |
| // bit[8] p_top_left_mix |
| // bit[7] mv_cal_mixed_type |
| // bit[6] mc_hcmd_mixed_type |
| // bit[5] use_seperate_int_control |
| // bit[4] hcmd_intra_use_q_info |
| // bit[3] hcmd_left_use_prev_info |
| // bit[2] hcmd_use_q_info |
| // bit[1] use_q_delta_quant |
| // bit[0] detect_I16_from_I4 |
| #define VLC_ADV_CONFIG (0x1d25) |
| #define P_VLC_ADV_CONFIG (volatile unsigned int *)((0x1d25 << 2) + 0xff620000) |
| // 31 - use_hcmd_mb_xy_auto |
| //23:16 - hcmd_max_mb_x |
| //15:8 - hcmd_mb_y_auto |
| // 7:0 - hcmd_mb_x_auto |
| #define VLC_HCMD_MBXY_AUTO (0x1d26) |
| #define P_VLC_HCMD_MBXY_AUTO (volatile unsigned int *)((0x1d26 << 2) + 0xff620000) |
| // bit[31:0] vlc_int_control_inter -- will be used when use_seperate_int_control is set |
| #define VLC_INT_CONTROL_INTER (0x1d2f) |
| #define P_VLC_INT_CONTROL_INTER (volatile unsigned int *)((0x1d2f << 2) + 0xff620000) |
| // -------------------------------------------- |
| // Picture VLC |
| // -------------------------------------------- |
| // (&(int|(~AND_enable))|(|(int&OR_enable))) |
| // bit[31] OR interrupt Enable Reserved |
| // bit[30] OR interrupt Enable for mv_busy |
| // bit[29] OR interrupt Enable for b8_mode_busy |
| // bit[28] OR interrupt Enable for mb_skip_run_busy |
| // bit[27] OR interrupt Enable for cbp_busy |
| // bit[26] OR interrupt Enable for Reserved |
| // bit[25] OR interrupt Enable for Reserved |
| // bit[24] OR interrupt Enable for mb_info_busy |
| // bit[23] AND interrupt Enable Reserved |
| // bit[22] AND interrupt Enable for mv_busy |
| // bit[21] AND interrupt Enable for b8_mode_busy |
| // bit[20] AND interrupt Enable for mb_skip_run_busy |
| // bit[19] AND interrupt Enable for cbp_busy |
| // bit[18] AND interrupt Enable for Reserved |
| // bit[17] AND interrupt Enable for Reserved |
| // bit[16] AND interrupt Enable for mb_info_busy |
| // bit[15] OR interrupt Enable Reserved |
| // bit[14] OR interrupt Enable for mvd |
| // bit[13] OR interrupt Enable for b8_mode |
| // bit[12] OR interrupt Enable for mb_skip_run |
| // bit[11] OR interrupt Enable for cbp_ready |
| // bit[10] OR interrupt Enable for c_ipred_mode_ready |
| // bit[9] OR interrupt Enable for ipred_mode_ready |
| // bit[8] OR interrupt Enable for mb_info_ready |
| // bit[7] AND interrupt Enable Reserved |
| // bit[6] AND interrupt Enable for mvd |
| // bit[5] AND interrupt Enable for b8_mode |
| // bit[4] AND interrupt Enable for mb_skip_run |
| // bit[3] AND interrupt Enable for cbp_ready |
| // bit[2] AND interrupt Enable for c_ipred_mode_ready |
| // bit[1] AND interrupt Enable for ipred_mode_ready |
| // bit[0] AND interrupt Enable for mb_info_ready |
| #define VLC_INT_CONTROL (0x1d30) |
| #define P_VLC_INT_CONTROL (volatile unsigned int *)((0x1d30 << 2) + 0xff620000) |
| // Bit[31:16] picture_height |
| // Bit[15:0] picture_width |
| #define VLC_PIC_SIZE (0x1d31) |
| #define P_VLC_PIC_SIZE (volatile unsigned int *)((0x1d31 << 2) + 0xff620000) |
| // [31:16] Reserved |
| // [15:3] pic_width_in_mbs_minus1 |
| // [2:0] picture_type |
| #define VLC_PIC_INFO (0x1d32) |
| #define P_VLC_PIC_INFO (volatile unsigned int *)((0x1d32 << 2) + 0xff620000) |
| // Bit[31:16] MB_NR |
| // Bit[15:8] MBY |
| // Bit[7:0] MBX |
| #define VLC_PIC_POSITION (0x1d33) |
| #define P_VLC_PIC_POSITION (volatile unsigned int *)((0x1d33 << 2) + 0xff620000) |
| // Bit[31] MV_busy |
| // Bit[30:6] Reserved |
| // Bit[15] Reserved |
| // Bit[14] vlc_input_MV_busy |
| // Bit[13] vlc_input_b8_mode_busy |
| // Bit[12] vlc_input_mb_skip_run_busy |
| // Bit[11] vlc_input_cbp_busy |
| // Bit[10] Reserved |
| // Bit[9] Reserved |
| // Bit[8] vlc_input_mb_info_busy |
| // Bit[7] Reserved |
| // Bit[6] mvd |
| // Bit[5] b8_mode |
| // Bit[4] mb_skip_run |
| // Bit[3] cbp |
| // Bit[2] c_ipred_mode |
| // Bit[1] ipred_mode |
| // Bit[0] mb_info ( mb_type, mb_x, mb_y) |
| #define VLC_INPUT_STATUS (0x1d34) |
| #define P_VLC_INPUT_STATUS (volatile unsigned int *)((0x1d34 << 2) + 0xff620000) |
| // Bit[31:28] detected_mb_type |
| // Bit[27:16] mb_y |
| // Bit[15:4] mb_x |
| // Bit[3:0] mb_type |
| #define VLC_MB_INFO (0x1d35) |
| #define P_VLC_MB_INFO (volatile unsigned int *)((0x1d35 << 2) + 0xff620000) |
| // commnad 0 -- no pending |
| // normal command + 1 is pending command |
| // |
| // bit 31:28 -- pending command 7 |
| // bit 27:24 -- pending command 6 |
| // bit 23:20 -- pending command 5 |
| // bit 19:16 -- pending command 4 |
| // bit 15:12 -- pending command 3 |
| // bit 11:8 -- pending command 2 |
| // bit 7:4 -- pending command 1 |
| // bit 3:0 -- pending command 0 |
| #define VLC_ENC_PEND_CMD (0x1d36) |
| #define P_VLC_ENC_PEND_CMD (volatile unsigned int *)((0x1d36 << 2) + 0xff620000) |
| // For I Slice |
| // Bit[31:16] Reserved |
| // Bit[15:0] IntraType |
| #define HENC_TOP_INFO_0 (0x1d37) |
| #define P_HENC_TOP_INFO_0 (volatile unsigned int *)((0x1d37 << 2) + 0xff620000) |
| #define HENC_LEFT_INFO_0 (0x1d38) |
| #define P_HENC_LEFT_INFO_0 (volatile unsigned int *)((0x1d38 << 2) + 0xff620000) |
| // For I Slice |
| // Bit[31:24] V_nnz |
| // Bit[23:16] U_nnz |
| // Bit[15:0] Y_nnz |
| #define HENC_TOP_INFO_1 (0x1d39) |
| #define P_HENC_TOP_INFO_1 (volatile unsigned int *)((0x1d39 << 2) + 0xff620000) |
| #define HENC_LEFT_INFO_1 (0x1d3a) |
| #define P_HENC_LEFT_INFO_1 (volatile unsigned int *)((0x1d3a << 2) + 0xff620000) |
| // bit[63:0] ipred_mode |
| #define VLC_IPRED_MODE_HI (0x1d3b) |
| #define P_VLC_IPRED_MODE_HI (volatile unsigned int *)((0x1d3b << 2) + 0xff620000) |
| #define VLC_IPRED_MODE_LO (0x1d3c) |
| #define P_VLC_IPRED_MODE_LO (volatile unsigned int *)((0x1d3c << 2) + 0xff620000) |
| // bit[15:8] SE delta quant |
| // bit[7:0] UE delta quant |
| #define VLC_DELTA_QP (0x1d3d) |
| #define P_VLC_DELTA_QP (volatile unsigned int *)((0x1d3d<
|