| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2017 NXP |
| */ |
| |
| #include <common.h> |
| #include <fsl_ddr_sdram.h> |
| #include <fsl_ddr_dimm_params.h> |
| #include <asm/arch/soc.h> |
| #include <asm/arch/clock.h> |
| #include "ddr.h" |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) |
| static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts) |
| { |
| int vdd; |
| |
| vdd = get_core_volt_from_fuse(); |
| /* Nothing to do for silicons doesn't support VID */ |
| if (vdd < 0) |
| return; |
| |
| if (vdd == 900) { |
| popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN; |
| debug("VID: configure DDR to support 900 mV\n"); |
| } |
| } |
| #endif |
| |
| void fsl_ddr_board_options(memctl_options_t *popts, |
| dimm_params_t *pdimm, |
| unsigned int ctrl_num) |
| { |
| const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
| ulong ddr_freq; |
| |
| if (ctrl_num > 1) { |
| printf("Not supported controller number %d\n", ctrl_num); |
| return; |
| } |
| if (!pdimm->n_ranks) |
| return; |
| |
| /* |
| * we use identical timing for all slots. If needed, change the code |
| * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; |
| */ |
| pbsp = udimms[0]; |
| |
| /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr |
| * freqency and n_banks specified in board_specific_parameters table. |
| */ |
| ddr_freq = get_ddr_freq(0) / 1000000; |
| while (pbsp->datarate_mhz_high) { |
| if (pbsp->n_ranks == pdimm->n_ranks) { |
| if (ddr_freq <= pbsp->datarate_mhz_high) { |
| popts->clk_adjust = pbsp->clk_adjust; |
| popts->wrlvl_start = pbsp->wrlvl_start; |
| popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
| popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
| goto found; |
| } |
| pbsp_highest = pbsp; |
| } |
| pbsp++; |
| } |
| |
| if (pbsp_highest) { |
| printf("Error: board specific timing not found for %lu MT/s\n", |
| ddr_freq); |
| printf("Trying to use the highest speed (%u) parameters\n", |
| pbsp_highest->datarate_mhz_high); |
| popts->clk_adjust = pbsp_highest->clk_adjust; |
| popts->wrlvl_start = pbsp_highest->wrlvl_start; |
| popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
| popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
| } else { |
| panic("DIMM is not supported by this board"); |
| } |
| found: |
| debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" |
| "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", |
| pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, |
| pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, |
| pbsp->wrlvl_ctl_3); |
| |
| |
| |
| popts->half_strength_driver_enable = 0; |
| /* |
| * Write leveling override |
| */ |
| popts->wrlvl_override = 1; |
| popts->wrlvl_sample = 0xf; |
| |
| |
| /* Enable ZQ calibration */ |
| popts->zq_en = 1; |
| |
| /* Enable DDR hashing */ |
| popts->addr_hash = 1; |
| |
| popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); |
| #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) |
| fsl_ddr_setup_0v9_volt(popts); |
| #endif |
| |
| popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | |
| DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; |
| } |
| |
| |
| int fsl_initdram(void) |
| { |
| puts("Initializing DDR....using SPD\n"); |
| |
| #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) |
| gd->ram_size = fsl_ddr_sdram_size(); |
| #else |
| gd->ram_size = fsl_ddr_sdram(); |
| #endif |
| return 0; |
| } |