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third-party-mirror / u-boot / 46a8da2338f5ca2afe2fd315c1a0722c99baa9df / . / cmd / amlogic / cmd_ddr_test.c
blob: 18d0206629afec946c181edfa6f21d8941c24b03 [file] [log] [blame]
#include <common.h>
#include <u-boot/sha256.h>
//#include <asm/arch/secure_apb.h>
//#include<stdio.h>
//#include <asm/io.h>
//#include <asm/arch/io.h>
//#include <asm/arch/register.h>
//#include <asm/arch-g9tv/mmc.h> //jiaxing debug
//extern void aml_cache_disable(void);
//#ifndef char* itoa(intnum,char*str,intradix)
#define USE_FOR_NEWMAN
#define USE_FOR_UBOOT_2018
#ifdef USE_FOR_NEWMAN
///*
int setenv(const char *varname, const char *varvalue)
{
return 1;
}
char *getenv(const char *name)
{
return NULL;
}
//*/
#endif
#define DWC_AC_PINMUX_TOTAL 28
#define DWC_DFI_PINMUX_TOTAL 26
//#define DDR_USE_DEFINE_TEMPLATE_CONFIG 1
#define DDR_STICKY_MAGIC_NUMBER 0x20180000
#define DDR_CHIP_ID 0x30
#define DDR_STICKY_SOURCE_DMC_STICKY 0x1
#define DDR_STICKY_SOURCE_SRAM 0x2
#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config
#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test
#define DDR_INIT_CONFIG_STICKY_MESSAGE_SRAM_ADDRESS 0x00040000
#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000
#define CONFIG_DDR_TYPE_DDR3 0
#define CONFIG_DDR_TYPE_DDR4 1
#define CONFIG_DDR_TYPE_LPDDR4 2
#define CONFIG_DDR_TYPE_LPDDR3 3
#define CONFIG_DDR_TYPE_LPDDR2 4
//#define CONFIG_DDR_TYPE_LPDDR4X 5
#define CONFIG_DDR_TYPE_AUTO 0xf
#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4
#define CONFIG_DDR0_16BIT_CH0 0x1
#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
/*
static uint32_t ddr_rd_16bit_on_32reg(uint32_t addr)
{
uint32_t read_value=0;
uint32_t addr_t=((addr>>2) << 2);
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
read_value=(read_value>>((addr%4)<<3))&0xffff;
return read_value;
}
static uint32_t ddr_wr_16bit_on_32reg(uint32_t addr,uint32_t value)
{
uint32_t read_value=0;
uint32_t write_value=0;
uint32_t addr_t=((addr>>2) << 2);
uint32_t offset=((addr%4)<<3);
read_value= *(volatile uint32_t *)(( unsigned long )(addr_t));
write_value=(value<<offset)|(read_value&(~(0xffff<<offset)));
*(volatile uint32_t *)(( unsigned long )(addr_t))=write_value;
return write_value;
}
*/
static uint32_t ddr_rd_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index)
{
uint32_t read_value=0;
uint32_t addr_t=0;
uint32_t offset=0;
if(size==8){
offset=((offset_index%4)<<3);
addr_t=(base_addr+((offset_index>>2) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
read_value=(read_value>>offset)&0xff;
}
if(size==16){
offset=((offset_index%2)<<4);
addr_t=(base_addr+((offset_index>>1) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
read_value=(read_value>>offset)&0xffff;
}
return read_value;
}
static uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index,uint32_t value)
{
uint32_t read_value=0;
uint32_t write_value=0;
uint32_t addr_t=0;
uint32_t offset=0;
if(size==8){
offset=((offset_index%4)<<3);
addr_t=(base_addr+((offset_index>>2) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
write_value=(value<<offset)|(read_value&(~(0xff<<offset)));
}
if(size==16){
offset=((offset_index%2)<<4);
addr_t=(base_addr+((offset_index>>1) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
write_value=(value<<offset)|(read_value&(~(0xffff<<offset)));
}
*(volatile uint32_t *)(( unsigned long )(addr_t))=write_value;
return write_value;
}
typedef struct ddr_set{
unsigned int magic;
unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin(bit0-3 read bit 4-7 write) 2 auto offset after window test (bit0-3 read bit 4-7 write) 3 auto window test index(bit 7 use for if enable usb download do window test ,bit 6 use for flash)
// unsigned int rsv_int0;
unsigned char board_id;
//board id reserve,,do not modify
unsigned char version;
// firmware reserve version,,do not modify
unsigned char DramType;
//support DramType should confirm with amlogic
//#define CONFIG_DDR_TYPE_DDR3 0
//#define CONFIG_DDR_TYPE_DDR4 1
//#define CONFIG_DDR_TYPE_LPDDR4 2
//#define CONFIG_DDR_TYPE_LPDDR3 3
//#define CONFIG_DDR_TYPE_LPDDR2 4
unsigned char DisabledDbyte;
//use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3
//bit 0 ---use byte 0 ,1 disable byte 0,
//bit 1 ---use byte 1 ,1 disable byte 1,
//bit 2 ---use byte 2 ,1 disable byte 2,
//bit 3 ---use byte 3 ,1 disable byte 3,
unsigned char Is2Ttiming;
//ddr3/ddr3 use 2t timing,now only support 2t timming
unsigned char HdtCtrl;
//training information control,do not modify
unsigned char dram_rank_config;
//support Dram connection type should confirm with amlogic
//#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0
//#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1
//#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0
//#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use chanel a cs0 cs1 chanel b cs0 cs1
//#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode
//#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve
//#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1
//#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0
/* rsv_char0. update for diagnose type define */
unsigned char diagnose;
/* imem/dmem define */
unsigned int imem_load_addr;
//system reserve,do not modify
unsigned int dmem_load_addr;
//system reserve,do not modify
unsigned short imem_load_size;
//system reserve,do not modify
unsigned short dmem_load_size;
//system reserve,do not modify
unsigned int ddr_base_addr;
//system reserve,do not modify
unsigned int ddr_start_offset;
//system reserve,do not modify
unsigned short dram_cs0_size_MB;
//config cs0 dram size ,like 1G DRAM ,setting 1024
unsigned short dram_cs1_size_MB;
//config cs1 dram size,like 512M DRAM ,setting 512
/* align8 */
unsigned short training_SequenceCtrl[2];
//system reserve,do not modify
unsigned char phy_odt_config_rank[2];
unsigned char rever1;
unsigned char rever2;
//training odt config ,only use for training
// [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
// [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
unsigned int dfi_odt_config;
//normal go status od config,use for normal status
//bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
//bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
//bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
//bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
//bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
//bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
//bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
//bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
//bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
//bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
unsigned short DRAMFreq[4];
//config dram frequency,use DRAMFreq[0],ohter reserve
unsigned char PllBypassEn;
//system reserve,do not modify
unsigned char ddr_rdbi_wr_enable;
//system reserve,do not modify
unsigned char ddr_rfc_type;
//config dram rfc type,according dram type,also can use same dram type max config
//#define DDR_RFC_TYPE_DDR3_512Mbx1 0
//#define DDR_RFC_TYPE_DDR3_512Mbx2 1
//#define DDR_RFC_TYPE_DDR3_512Mbx4 2
//#define DDR_RFC_TYPE_DDR3_512Mbx8 3
//#define DDR_RFC_TYPE_DDR3_512Mbx16 4
//#define DDR_RFC_TYPE_DDR4_2Gbx1 5
//#define DDR_RFC_TYPE_DDR4_2Gbx2 6
//#define DDR_RFC_TYPE_DDR4_2Gbx4 7
//#define DDR_RFC_TYPE_DDR4_2Gbx8 8
//#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
//#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
//#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
unsigned char enable_lpddr4x_mode;
//system reserve,do not modify
/* align8 */
unsigned int pll_ssc_mode;
//
/* pll ssc config:
*
* pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
* ppm = strength * 500
* mode: 0=center, 1=up, 2=down
*
* eg:
* 1. config 1000ppm center ss. then mode=0, strength=2
* .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
* 2. config 3000ppm down ss. then mode=2, strength=6
* .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
*/
unsigned short clk_drv_ohm;
//config soc clk pin signal driver stength ,select 20,30,40,60ohm
unsigned short cs_drv_ohm;
//config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm
unsigned short ac_drv_ohm;
//config soc normal address command pin driver stength ,select 20,30,40,60ohm
unsigned short soc_data_drv_ohm_p;
//config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
unsigned short soc_data_drv_ohm_n;
//config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
unsigned short soc_data_odt_ohm_p;
//config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
unsigned short soc_data_odt_ohm_n;
//config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
unsigned short dram_data_drv_ohm;
//config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
unsigned short dram_data_odt_ohm;
//config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
unsigned short dram_ac_odt_ohm;
//config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm
unsigned short soc_clk_slew_rate;
//system reserve,do not modify
unsigned short soc_cs_slew_rate;
//system reserve,do not modify
unsigned short soc_ac_slew_rate;
//system reserve,do not modify
unsigned short soc_data_slew_rate;
//system reserve,do not modify
unsigned short vref_output_permil; //phy
//setting same with vref_dram_permil
unsigned short vref_receiver_permil; //soc
//soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
unsigned short vref_dram_permil;
//soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
unsigned short max_core_timmming_frequency;
//use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
/* align8 */
unsigned char ac_trace_delay[10];
unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
unsigned char lpddr4_x8_mode;
//system reserve,do not modify ,take care ,please follow SI
unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
//use for lpddr3 /lpddr4 ca pinmux remap
unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
//[1],slt test parameter ,use for force delay line offset
//system reserve,do not modify
unsigned short tdqs2dq;//dq_bdlr_org;
unsigned char dram_data_wr_odt_ohm;
unsigned char bitTimeControl_2d;
//system reserve,do not modify
/* align8 */
unsigned int ddr_dmc_remap[5];
//system reserve,do not modify
/* align8 */
unsigned char ddr_lpddr34_ca_remap[4];
////use for lpddr3 /lpddr4 ca training data byte lane remap
unsigned char ddr_lpddr34_dq_remap[32];
////use for lpddr3 /lpddr4 ca pinmux remap
unsigned int dram_rtt_nom_wr_park[2];
//system reserve,do not modify
unsigned int ddr_func;
//system reserve,do not modify
/* align8 */
//unsigned long rsv_long0[2];
/* v1 end */
// /*
unsigned char read_dqs_delay[16];
unsigned char read_dq_bit_delay[72];
unsigned short write_dqs_delay[16];
// */
unsigned short write_dq_bit_delay[72];
unsigned short read_dqs_gate_delay[16];
unsigned char soc_bit_vref[32];
unsigned char dram_bit_vref[32];
///*
unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq
unsigned char dfi_mrl;
unsigned char dfi_hwtmrl;
unsigned char ARdPtrInitVal;
unsigned char retraining[16];
//override read bit delay
//extra
// unsigned short dmc_test_worst_window_tx;
// unsigned short dmc_test_worst_window_rx;
// */
}ddr_set_t;
ddr_set_t p_ddr_set_t;
char* itoa_ddr_test(int num,char*str,int radix)
{/*Ë÷Òý±í*/
printf("\nitoa_ddr_test 1\n");
char index[]="0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
unsigned unum;/*Öмä±äÁ¿*/
char temp;
int i=0,j,k;
/*È·¶¨unumµÄÖµ*/
if (radix == 10 && num<0) /*Ê®½øÖƸºÊý*/
{
unum = (unsigned)-num;
str[i++] = '-';
}
else
unum = (unsigned)num;/*ÆäËûÇé¿ö*/
/*ת»»*/
printf("\nitoa_ddr_test 2\n");
printf("\nunum=0x%08x\n",unum);
printf("\nunum2=0x%08x\n",(unum%(unsigned)radix));
printf("\nradix=0x%08x\n",radix);
str[0] = index[0];
printf("\nitoa_ddr_test 22\n");
unum /= radix;
printf("\nitoa_ddr_test 23\n");
do {
str[i++] = index[unum%(unsigned)radix];
unum /= radix;
}while(unum);
printf("\nitoa_ddr_test 3\n");
str[i] = '\0';
/*ÄæÐò*/
if (str[0] == '-')
k = 1;/*Ê®½øÖƸºÊý*/
else
k = 0;
printf("\nitoa_ddr_test 4\n");
for (j = k;j <= (i-1)/2;j++)
{
temp = str[j];
str[j] = str[i-1+k-j];
str[i-1+k-j] = temp;
}
return str;
}
//#endif
/*
char *strsep(char **stringp, const char *delim)
{
char *s;
const char *spanp;
int c, sc;
char *tok;
if ((s = *stringp)== NULL)
return (NULL);
for (tok = s;;) {
c = *s++;
spanp = delim;
do {
if ((sc =*spanp++) == c) {
if (c == 0)
s = NULL;
else
s[-1] = 0;
*stringp = s;
return (tok);
}
} while (sc != 0);
}
}
*/
int TOLOWER(int ch)
{
if ((unsigned int)(ch - 'A') < 26u )
ch += 'a' - 'A';
return ch;
}//´óд×Öĸת»»ÎªÐ¡Ð´×Öĸ¡£
int isxdigit(int ch)
{
return (unsigned int)( ch - '0') < 10u ||
(unsigned int)((ch | 0x20) - 'a') < 6u;
}//ÅжÏ×Ö·ûcÊÇ·ñΪʮÁù½øÖÆÊý×Ö¡£
//µ±cΪA-F,a-f»ò0-9Ö®¼äµÄÊ®Áù½øÖÆÊý×Öʱ£¬·µ»Ø·ÇÁãÖµ£¬·ñÔò·µ»ØÁã¡£
int isdigit(int ch)
{
return (unsigned int)(ch - '0') < 10u;
}//ÅжÏ×Ö·ûcÊÇ·ñΪÊý×Ö
unsigned int simple_guess_base(const char *cp)
{
if (cp[0] == '0') {
if (TOLOWER(cp[1]) == 'x' && isxdigit(cp[2]))
return 16;
else
// return 8;
return 10;
} else {
return 10;
}
}
unsigned int simple_strtoull_ddr(const char *cp, char **endp, unsigned int base)
{
unsigned int result = 0;
//printf("test sizeof(str_buf)==%d\n",1);
if(cp == NULL) //jiaxing add 20170616
return 0;
if (!base)
base = simple_guess_base(cp);
if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x')
cp += 2;
if (base == 10) {
while ((*cp)== '0')
cp++;
}
while (isxdigit(*cp)) {//¼ì²éµ±Ç°cpÊÇ·ñÊǸöÊ®Áù½øÖÆÊýÖµ£¬²»ÊÇÖ±½Ó·µ»Ø0
unsigned int value;
value = isdigit(*cp) ? *cp - '0' : TOLOWER(*cp) - 'a' + 10;
if (value >= base)
break;
result = result * base + value;
cp++;
}
if (endp)
*endp = (char *)cp;
return result;
}
unsigned int env_to_a_num(const char *env_name)
{
char *str_buf = NULL;
char buf[48];
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
str_buf = getenv(env_name);
unsigned int a_num = 0;
char *endp;
printf("str==%s\n",str_buf);
a_num=simple_strtoull_ddr(str_buf, &endp, 0);
printf("%s==0x%08x\n",str_buf,a_num);
return a_num;
}
unsigned int a_num_to_env(const char *env_name ,unsigned int *a_num)
{
char *str_buf=NULL;
char buf[1024];
//unsigned int str_to_numarry[48];
//str_buf = (char *)malloc(sizeof(char)*1024);
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
str_buf = getenv(env_name);
printf("str==%s\n",str_buf);
sprintf(buf, "0x%08x", *a_num);
printf( "%s==0x%08x", buf,*a_num);
setenv(env_name, buf);
run_command("save",0);
return 1;
}
unsigned int env_to_num(const char *env_name,unsigned int *num_arry)
{
char *str_buf = NULL;
char buf[1024];
unsigned int str_to_numarry[48];
//str_buf = (char *)malloc(sizeof(char)*1024);
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
str_buf = getenv(env_name);
char * str[48];
char *endp;
int i;
for (i = 0; i < 48; i++)
str_to_numarry[i] = 0;
printf("str==%s\n",str_buf);
for (i = 0; i < 48; i++) {
str[i] = strsep(&str_buf, ";");
//str[i] = strsep(&str_buf, " ");
if(str[i] == NULL)
break;
str_to_numarry[i] = simple_strtoull_ddr(str[i], &endp, 0);
//printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
//num_arry[i]=str_to_numarry[i];
}
for (i = 0; i < 48; i++) {
printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
num_arry[i] = str_to_numarry[i];
}
//num_arry=(unsigned int *)(&str_to_numarry);
return 1;
}
unsigned int num_to_env(const char *env_name,unsigned int *num_arry)
{
char *str_buf=NULL;
char buf[1024];
int i;
//unsigned int str_to_numarry[48];
//str_buf = (char *)malloc(sizeof(char)*1024);
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
str_buf = getenv(env_name);
//char * str[48];
printf("str==%s\n",str_buf);
sprintf(buf, "0x%08x", num_arry[0]);
for (i = 1; i < 48; i++) {
//num_arry[i]=0;
sprintf(buf, "%s;0x%08x", buf,num_arry[i]);
printf("%d %d\n", i,num_arry[i]);
}
//sprintf(str, "%lx", value);
printf( "%s", buf);
setenv(env_name, buf);
run_command("save",0);
//num_arry=(unsigned int *)(&str_to_numarry);
return 1;
}
#define TDATA32F 0xffffffff
#define TDATA32A 0xaaaaaaaa
#define TDATA325 0x55555555
#define PREG_STICKY_G12A_REG0 (0xff634400 + (0x070 << 2))
//#define DDR_TEST_AUTO_TEST_CMD_MAGIC 0x01234567
#define DMC_STICKY_0 ((0x0000 << 2) + 0xff639800)
#define DMC_STICKY_G12A_0 ((0x0000 << 2) + 0xff638800)
#define DMC_STICKY_MAGIC_0 0x12345678
#define DMC_STICKY_MAGIC_1 0xabcdbead
#define DMC_STICKY_UBOOT_WINDOW_MAGIC_1 0x22
#define DMC_STICKY_AUTO_TEST_CMD_INDEX_MAGIC_1 0x33
unsigned int dmc_sticky[64];
unsigned int sticky_reg_base_add=0;
//#define DDR_TEST_ACLCDLR
unsigned int global_boot_times= 0;
unsigned int watchdog_time_s= 20;
unsigned int global_ddr_clk=1;
unsigned int bdlr_100step=0;
unsigned int ui_1_32_100step=0;
unsigned int error_count =0;
unsigned int error_outof_count_flag=0;
unsigned int copy_test_flag = 0;
unsigned int training_pattern_flag = 0;
unsigned int test_start_addr=0x1080000;
unsigned int dq_lcd_bdl_value_aclcdlr_org_a;
unsigned int dq_lcd_bdl_value_bdlr0_org_a;
unsigned int dq_lcd_bdl_value_aclcdlr_min_a;
unsigned int dq_lcd_bdl_value_bdlr0_min_a;
unsigned int dq_lcd_bdl_value_aclcdlr_max_a;
unsigned int dq_lcd_bdl_value_bdlr0_max_a;
unsigned int dq_lcd_bdl_value_aclcdlr_status_a;
unsigned int dq_lcd_bdl_value_bdlr0_status_a;
unsigned int dq_lcd_bdl_value_aclcdlr_org_b;
unsigned int dq_lcd_bdl_value_bdlr0_org_b;
unsigned int dq_lcd_bdl_value_aclcdlr_min_b;
unsigned int dq_lcd_bdl_value_bdlr0_min_b;
unsigned int dq_lcd_bdl_value_aclcdlr_max_b;
unsigned int dq_lcd_bdl_value_bdlr0_max_b;
unsigned int dq_lcd_bdl_value_wdq_org_a[4];
unsigned int dq_lcd_bdl_value_rdqs_org_a[4];
unsigned int dq_lcd_bdl_value_wdq_min_a[4];
unsigned int dq_lcd_bdl_value_wdq_max_a[4];
unsigned int dq_lcd_bdl_value_rdqs_min_a[4];
unsigned int dq_lcd_bdl_value_rdqs_max_a[4];
unsigned int dq_lcd_bdl_value_wdq_status_a[4];
unsigned int dq_lcd_bdl_value_rdqs_status_a[4];
unsigned int dq_lcd_bdl_value_wdq_org_b[4];
unsigned int dq_lcd_bdl_value_rdqs_org_b[4];
unsigned int dq_lcd_bdl_value_wdq_min_b[4];
unsigned int dq_lcd_bdl_value_wdq_max_b[4];
unsigned int dq_lcd_bdl_value_rdqs_min_b[4];
unsigned int dq_lcd_bdl_value_rdqs_max_b[4];
unsigned int dq_lcd_bdl_value_wdq_status_b[4];
unsigned int dq_lcd_bdl_value_rdqs_status_b[4];
unsigned int acbdlr0_9_reg_org[10];
unsigned int acbdlr0_9_reg_setup_max[40];
unsigned int acbdlr0_9_reg_hold_max[40];
unsigned int acbdlr0_9_reg_setup_time[40];
unsigned int acbdlr0_9_reg_hold_time[40];
// unsigned int data_bdlr0_5_reg_org[6];
unsigned int data_bdlr0_5_reg_org[28];//4//4lane
unsigned int bdlr0_9_reg_setup_max[24*4];//4//4 lane 96 bdlr
unsigned int bdlr0_9_reg_hold_max[24*4];
unsigned int bdlr0_9_reg_setup_time[24*4];
unsigned int bdlr0_9_reg_hold_time[24*4];
#define readl(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
#define writel(data ,addr) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
#define wr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
#define rd_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
//#define CONFIG_DDR_CMD_BDL_TUNE
//#define CONFIG_CMD_DDR_TEST
#ifndef CONFIG_CHIP
//#define CONFIG_CHIP CHIP_OLD //CHIP_OLD// //#define CHIP_OLD 0 //#define CHIP_TXLX 1
#define CHIP_OLD 0
#define CHIP_TXLX 1
#define CHIP_A113 2
#define CHIP_G12 3
#define CONFIG_CHIP CHIP_G12// CHIP_OLD//
#endif
#define P_DDR_PHY_DEFAULT 0
#define P_DDR_PHY_GX_BABY 1
#define P_DDR_PHY_GX_TV_BABY 2
#define P_DDR_PHY_905X 3
//#define P_DDR_PHY_OLD_TAG 0
#define P_DDR_PHY_G12 4
#if (CONFIG_CHIP>=CHIP_G12)
#define CONFIG_DDR_PHY P_DDR_PHY_G12
#else
//#define CONFIG_CHIP CHIP_OLD//
//#define CONFIG_DDR_PHY P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
//#define CONFIG_DDR_PHY P_DDR_PHY_G12//P_DDR_PHY_DEFAULT// P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
#define CONFIG_DDR_PHY P_DDR_PHY_905X//P_DDR_PHY_DEFAULT// P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
//#define CONFIG_DDR_PHY_NEW_TAG1 P_DDR_PHY_G12
#endif
#define G12_AM_DDR_PLL_CNTL0 0xff638c00
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
#include <asm/arch/secure_apb.h>
#endif
#define PATTERN_USE_DDR_DES
#define USE_64BIT_POINTER
//#define USE_32BIT_POINTER
#ifdef USE_64BIT_POINTER
#define p_convter_int(a) ( unsigned int )( unsigned long )(a)
#define int_convter_p(a) ( unsigned long )(a)
#else
#define p_convter_int(a) ( unsigned int )(a)
#define int_convter_p(a) ( unsigned int )(a)
#endif
#ifdef PATTERN_USE_DDR_DES
#define des_pattern(a,b,c,d) (des[a]^pattern_##b[c][d])
#define des_inv_pattern(a,b,c,d) ( des[a]^(~(pattern_##b[c][d])))
#define des_xor_pattern(a,b) ( a^b)
//des[temp_i]^pattern_2[temp_k][temp_i]
#else
#define des_pattern(a,b,c,d) (des[a]&0)+pattern_##b[c][d]
#define des_inv_pattern(a,b,c,d) (des[a]&0)+~(pattern_##b[c][d])
#define des_xor_pattern(a,b) (a&0+b)
#endif
#define DDR_LCDLR_CK_USE_FAST_PATTERN
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
#define DDR_PREFETCH_CACHE
#endif
#ifdef DDR_PREFETCH_CACHE
#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P))
#else
#define ddr_pld_cache(P)
#endif
#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
#define DDR0_PUB_REG_BASE 0xc8836000
#define DDR1_PUB_REG_BASE 0xc8836000
#define CHANNEL_A_REG_BASE 0
#define CHANNEL_B_REG_BASE 0x2000
#define P_DDR0_CLK_CTRL 0xc8836c00
#define P_DDR1_CLK_CTRL 0xc8836c00
#define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
#define OPEN_CHANNEL_B_PHY_CLK() (writel((0), 0xc8836c00))
#define CLOSE_CHANNEL_A_PHY_CLK() (writel((5), 0xc8836c00))
#define CLOSE_CHANNEL_B_PHY_CLK() (writel((5), 0xc8836c00))
// #define P_ISA_TIMERE 0xc1109988
// #define get_us_time() (readl(P_ISA_TIMERE))
#define AM_DDR_PLL_CNTL 0xc8836800
#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2))
#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2))
#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2))
//0x98 reserved)
#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2))
#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2))
#define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2))
//0x9c reserved)
#define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2))
#define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2))
#define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2))
#define ACBDLR_MAX 0X1F
#define ACLCDLR_MAX 0XFF
#define DQBDLR_MAX 0X1F
#define DQLCDLR_MAX 0XFF
#define DXNGTR_MAX 0X7
#define ACBDLR_NUM 10
#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
#define DMC_REG_BASE 0xc8838000
#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
//bit 19:16. qos monitor channel select. select one at one time only.
//bit 15:0. port select for the selected channel.
#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
// qos_mon_clk_timer. How long to measure the bandwidth.
#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
// at the test period, the whole MMC request time.
#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
// at the test period, the whole MMC granted data cycles. 64bits unit.
#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
#elif (CONFIG_DDR_PHY == P_DDR_PHY_GX_TV_BABY)
#define DDR0_PUB_REG_BASE 0xc8836000
#define DDR1_PUB_REG_BASE 0xc8837000
#define CHANNEL_A_REG_BASE 0
#define CHANNEL_B_REG_BASE 0x1000
#define P_DDR0_CLK_CTRL 0xc8836c00
#define P_DDR1_CLK_CTRL 0xc8836c00
#define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
#define OPEN_CHANNEL_B_PHY_CLK() (writel((0), 0xc8837c00))
#define CLOSE_CHANNEL_A_PHY_CLK() (writel((0x12a), 0xc8836c00))
#define CLOSE_CHANNEL_B_PHY_CLK() (writel((0x12a), 0xc8837c00))
// #define P_ISA_TIMERE 0xc1109988
// #define get_us_time() (readl(P_ISA_TIMERE) )
#define AM_DDR_PLL_CNTL 0xc8836800
#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
#define DDR0_PUB_ZQ0SR (DDR0_PUB_REG_BASE+(0x93<<2))
//0x94 reserved)
#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2))
#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2))
#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2))
//0x98 reserved)
#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2))
#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2))
#define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2))
//0x9c reserved)
#define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2))
#define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2))
#define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2))
#define ACBDLR_MAX 0X1F
#define ACLCDLR_MAX 0XFF
#define DQBDLR_MAX 0X1F
#define DQLCDLR_MAX 0XFF
#define DXNGTR_MAX 0X7
#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
#define DMC_REG_BASE 0xc8838000
#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
//bit 19:16. qos monitor channel select. select one at one time only.
//bit 15:0. port select for the selected channel.
#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
// qos_mon_clk_timer. How long to measure the bandwidth.
#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
// at the test period, the whole MMC request time.
#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
// at the test period, the whole MMC granted data cycles. 64bits unit.
#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
// at the test period, the granted data cycles for the selected channel and ports.
#elif (CONFIG_DDR_PHY == P_DDR_PHY_905X)
// #define P_ISA_TIMERE 0xc1109988
// #define get_us_time() (readl(P_ISA_TIMERE) )
#if CONFIG_CHIP >=CHIP_TXLX
#define DDR0_PUB_REG_BASE ((0x0000 << 2) + 0xff636000)//DDR0_PUB_RIDR
#define DDR1_PUB_REG_BASE ((0x0000 << 2) + 0xff636000)//DDR0_PUB_RIDR
#define CHANNEL_A_REG_BASE 0
#define CHANNEL_B_REG_BASE 0//0x1000
#define MMC_REG_BASE ((0x0000 << 2) + 0xff637000) // #define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xff637000) 0xc8837000
#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
#define DDR0_PUB_DX0GCR0 ((0x01c0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX1GCR0 ((0x0200 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX2GCR0 ((0x0240 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
#define ACBDLR_MAX 0X3F
#define ACLCDLR_MAX 0X1FF
#define DQBDLR_MAX 0X3F
#define DQLCDLR_MAX 0X1FF
#define DXNGTR_MAX 0X1F
// #define DMC_REG_BASE MMC_REG_BASE
#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
//bit 19:16. qos monitor channel select. select one at one time only.
//bit 15:0. port select for the selected channel.
#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
// qos_mon_clk_timer. How long to measure the bandwidth.
#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
// at the test period, the whole MMC request time.
#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
// at the test period, the whole MMC granted data cycles. 64bits unit.
#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
// at the test period, the granted data cycles for the selected channel and ports.
#else
#define DDR0_PUB_REG_BASE 0xc8836000
#define DDR1_PUB_REG_BASE 0xc8836000
#define CHANNEL_A_REG_BASE 0
#define CHANNEL_B_REG_BASE 0//0x1000
#define MMC_REG_BASE 0xc8837000
#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
#define ACBDLR_MAX 0X3F
#define ACLCDLR_MAX 0X1FF
#define DQBDLR_MAX 0X3F
#define DQLCDLR_MAX 0X1FF
#define DXNGTR_MAX 0X1F
#define DDR0_PUB_DX0GCR0 ((0x1c0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX1GCR0 ((0x200 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX2GCR0 ((0x240 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
#ifndef DMC_REG_BASE
#define DMC_REG_BASE MMC_REG_BASE
#endif
#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
//bit 19:16. qos monitor channel select. select one at one time only.
//bit 15:0. port select for the selected channel.
#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
// qos_mon_clk_timer. How long to measure the bandwidth.
#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
// at the test period, the whole MMC request time.
#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
// at the test period, the whole MMC granted data cycles. 64bits unit.
#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
// at the test period, the granted data cycles for the selected channel and ports.
#endif
#elif (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT)
#define DDR0_PUB_REG_BASE 0xc8001000 //0xc8836000
#define DDR1_PUB_REG_BASE 0xc8001000 // 0xc8836000
#define CHANNEL_A_REG_BASE 0
#define CHANNEL_B_REG_BASE 0x2000
#define P_DDR0_CLK_CTRL 0xc8000800
#define P_DDR1_CLK_CTRL 0xc8002800
#define OPEN_CHANNEL_A_PHY_CLK() (writel((0x12b), 0xc8000800))
#define OPEN_CHANNEL_B_PHY_CLK() (writel((0x12b), 0xc8002800))
#define CLOSE_CHANNEL_A_PHY_CLK() (writel((0x12a), 0xc8000800))
#define CLOSE_CHANNEL_B_PHY_CLK() (writel((0x12a), 0xc8002800))
// #define P_ISA_TIMERE 0xc1109988
// #define get_us_time() (readl(P_ISA_TIMERE))
#define PREG_STICKY_REG0 0xc1100000+(0x207c<<2)
#define PREG_STICKY_REG1 0xc1100000+(0x207d<<2)
#define WATCHDOG_TC 0xc1100000+(0x2640<<2)// 0x2640
#define AM_DDR_PLL_CNTL 0xc8000400
#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x91<<2))
#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x92<<2))
#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x91<<2))
#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x92<<2))
#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
#define ACBDLR_MAX 0X1F
#define ACLCDLR_MAX 0XFF
#define DQBDLR_MAX 0X1F
#define DQLCDLR_MAX 0XFF
#define DXNGTR_MAX 0X7
#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
#define DMC_REG_BASE 0xc8006000
#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
//bit 19:16. qos monitor channel select. select one at one time only.
//bit 15:0. port select for the selected channel.
#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
// qos_mon_clk_timer. How long to measure the bandwidth.
#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
// at the test period, the whole MMC request time.
#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
// at the test period, the whole MMC granted data cycles. 64bits unit.
#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
// at the test period, the granted data cycles for the selected channel and ports.
#elif (CONFIG_DDR_PHY == P_DDR_PHY_G12)
#define DDR0_PUB_REG_BASE 0xff636000
#define DDR1_PUB_REG_BASE 0xff636000
#define CHANNEL_A_REG_BASE 0
#define CHANNEL_B_REG_BASE 0//0x1000
#define MMC_REG_BASE 0xff637000
#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
#define ACBDLR_MAX 0X3F
#define ACLCDLR_MAX 0X1FF
#define DQBDLR_MAX 0X3F
#define DQLCDLR_MAX 0X1FF
#define DXNGTR_MAX 0X1F
#define DDR0_PUB_DX0GCR0 ((0x1c0 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX1GCR0 ((0x200 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX2GCR0 ((0x240 << 2) + DDR0_PUB_REG_BASE)
#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
#ifndef DMC_REG_BASE
#define DMC_REG_BASE MMC_REG_BASE
#endif
#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
//bit 19:16. qos monitor channel select. select one at one time only.
//bit 15:0. port select for the selected channel.
#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
// qos_mon_clk_timer. How long to measure the bandwidth.
#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
// at the test period, the whole MMC request time.
#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
// at the test period, the whole MMC granted data cycles. 64bits unit.
#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
// at the test period, the granted data cycles for the selected channel and ports.
#endif
#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
#define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2))
#define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE + ( 0x004 << 2 ))// R/W - PHY General Configuration Register 0
#define DDR0_PUB_PGCR1 ( DDR0_PUB_REG_BASE + ( 0x005 << 2 )) // R/W - PHY General Configuration Register 1
#define DDR0_PUB_PGCR2 (DDR0_PUB_REG_BASE + ( 0x006 << 2 )) // R/W - PHY General Configuration Register 2
#define DDR0_PUB_PGCR3 ( DDR0_PUB_REG_BASE + ( 0x007 << 2 )) // R/W - PHY General Configuration Register 3
#define DDR0_PUB_PGCR4 ( DDR0_PUB_REG_BASE + ( 0x008 << 2 )) // R/W - PHY General Configuration Register 4
#define DDR0_PUB_PGCR5 (DDR0_PUB_REG_BASE + ( 0x009 << 2 )) // R/W - PHY General Configuration Register 5
#define DDR0_PUB_PGCR6 (DDR0_PUB_REG_BASE + ( 0x00A << 2 )) // R/W - PHY General Configuration Register 6
#define DDR0_PUB_PGCR7 (DDR0_PUB_REG_BASE + ( 0x00B << 2 )) // R/W - PHY General Configuration Register 7
#define DDR0_PUB_PGCR8 (DDR0_PUB_REG_BASE + ( 0x00C << 2 )) // R/W - PHY General Configuration Register 8
#define DDR1_PUB_PIR (DDR1_PUB_REG_BASE+(0x01<<2))
#define DDR1_PUB_PGCR0 (DDR0_PUB_REG_BASE + ( 0x004 << 2 )) // R/W - PHY General Configuration Register 0
#define DDR1_PUB_PGCR1 (DDR0_PUB_REG_BASE + ( 0x005 << 2 )) // R/W - PHY General Configuration Register 1
#define DDR1_PUB_PGCR2 ( DDR0_PUB_REG_BASE + ( 0x006 << 2 )) // R/W - PHY General Configuration Register 2
#define DDR1_PUB_PGCR3 (DDR0_PUB_REG_BASE + ( 0x007 << 2 )) // R/W - PHY General Configuration Register 3
#define DDR1_PUB_PGCR4 (DDR0_PUB_REG_BASE + ( 0x008 << 2 ) )// R/W - PHY General Configuration Register 4
#define DDR1_PUB_PGCR5 (DDR0_PUB_REG_BASE + ( 0x009 << 2 )) // R/W - PHY General Configuration Register 5
#define DDR1_PUB_PGCR6 (DDR0_PUB_REG_BASE + ( 0x00A << 2 )) // R/W - PHY General Configuration Register 6
#define DDR1_PUB_PGCR7 (DDR0_PUB_REG_BASE + ( 0x00B << 2 )) // R/W - PHY General Configuration Register 7
#define DDR1_PUB_PGCR8 (DDR0_PUB_REG_BASE + ( 0x00C << 2 ) )// R/W - PHY General Configuration Register 8
#define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE + ( 0x1d0 << 2 ))
#define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE + ( 0x1d1 << 2 ))
#define DDR0_PUB_DX0BDLR2 ( DDR0_PUB_REG_BASE + ( 0x1d2 << 2 ))
#define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE + ( 0x1d4 << 2 ))
#define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE + ( 0x1d5 << 2 ))
#define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE + ( 0x1d6 << 2 ))
#define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE + ( 0x1d8 << 2 ))
#define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE + ( 0x1e0 << 2 ))
#define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE + ( 0x1e1 << 2 ))
#define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE + ( 0x1e2 << 2 ))
#define DDR0_PUB_DX0LCDLR3 (DDR0_PUB_REG_BASE + ( 0x1e3 << 2 ))
#define DDR0_PUB_DX0LCDLR4 (DDR0_PUB_REG_BASE + ( 0x1e4 << 2 ))
#define DDR0_PUB_DX0LCDLR5 (DDR0_PUB_REG_BASE + ( 0x1e5 << 2 ))
#define DDR0_PUB_DX0MDLR0 (DDR0_PUB_REG_BASE + ( 0x1e8 << 2 ))
#define DDR0_PUB_DX0MDLR1 (DDR0_PUB_REG_BASE + ( 0x1e9 << 2) )
#define DDR0_PUB_DX0GTR0 (DDR0_PUB_REG_BASE + ( 0x1f0 << 2 ))
#define DDR0_PUB_DX0GTR1 (DDR0_PUB_REG_BASE + ( 0x1f1 << 2) )
#define DDR0_PUB_DX0GTR2 (DDR0_PUB_REG_BASE + ( 0x1f2 << 2) )
#define DDR0_PUB_DX0GTR3 (DDR0_PUB_REG_BASE + ( 0x1f3 << 2))
#define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE + ( 0x210 << 2) )
#define DDR0_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE + ( 0x211 << 2) )
#define DDR0_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE + ( 0x212 << 2) )
#define DDR0_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE + ( 0x214 << 2) )
#define DDR0_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE + ( 0x215 << 2) )
#define DDR0_PUB_DX1BDLR5 ( DDR0_PUB_REG_BASE + ( 0x216 << 2) )
#define DDR0_PUB_DX1BDLR6 ( DDR0_PUB_REG_BASE + ( 0x218 << 2) )
#define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE + ( 0x220 << 2) )
#define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE + ( 0x221 << 2) )
#define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE + ( 0x222 << 2) )
#define DDR0_PUB_DX1LCDLR3 (DDR0_PUB_REG_BASE + ( 0x223 << 2) )
#define DDR0_PUB_DX1LCDLR4 (DDR0_PUB_REG_BASE + ( 0x224 << 2) )
#define DDR0_PUB_DX1LCDLR5 (DDR0_PUB_REG_BASE + ( 0x225 << 2) )
#define DDR0_PUB_DX1MDLR0 (DDR0_PUB_REG_BASE + ( 0x228 << 2) )
#define DDR0_PUB_DX1MDLR1 (DDR0_PUB_REG_BASE + ( 0x229 << 2) )
#define DDR0_PUB_DX1GTR0 (DDR0_PUB_REG_BASE + ( 0x230 << 2 ))
#define DDR0_PUB_DX1GTR1 (DDR0_PUB_REG_BASE + ( 0x231 << 2) )
#define DDR0_PUB_DX1GTR2 (DDR0_PUB_REG_BASE + ( 0x232 << 2) )
#define DDR0_PUB_DX1GTR3 (DDR0_PUB_REG_BASE + ( 0x233 << 2) )
#define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE + ( 0x250 << 2) )
#define DDR0_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE + ( 0x251 << 2) )
#define DDR0_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE + ( 0x252 << 2) )
#define DDR0_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE + ( 0x254 << 2) )
#define DDR0_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE + ( 0x255 << 2) )
#define DDR0_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE + ( 0x256 << 2) )
#define DDR0_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE + ( 0x258 << 2) )
#define DDR0_PUB_DX2LCDLR0 ( DDR0_PUB_REG_BASE + ( 0x260 << 2) )
#define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE + ( 0x261 << 2) )
#define DDR0_PUB_DX2LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x262 << 2) )
#define DDR0_PUB_DX2LCDLR3 (DDR0_PUB_REG_BASE + ( 0x263 << 2) )
#define DDR0_PUB_DX2LCDLR4 (DDR0_PUB_REG_BASE + ( 0x264 << 2) )
#define DDR0_PUB_DX2LCDLR5 ( DDR0_PUB_REG_BASE + ( 0x265 << 2) )
#define DDR0_PUB_DX2MDLR0 (DDR0_PUB_REG_BASE + ( 0x268 << 2) )
#define DDR0_PUB_DX2MDLR1 (DDR0_PUB_REG_BASE + ( 0x269 << 2) )
#define DDR0_PUB_DX2GTR0 ( DDR0_PUB_REG_BASE + ( 0x270 << 2 ))
#define DDR0_PUB_DX2GTR1 (DDR0_PUB_REG_BASE + ( 0x271 << 2) )
#define DDR0_PUB_DX2GTR2 (DDR0_PUB_REG_BASE + ( 0x272 << 2) )
#define DDR0_PUB_DX2GTR3 (DDR0_PUB_REG_BASE + ( 0x273 << 2) )
#define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE + ( 0x290 << 2) )
#define DDR0_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE + ( 0x291 << 2) )
#define DDR0_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE + ( 0x292 << 2) )
#define DDR0_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE + ( 0x294 << 2) )
#define DDR0_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE + ( 0x295 << 2) )
#define DDR0_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE + ( 0x296 << 2) )
#define DDR0_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE + ( 0x298 << 2) )
#define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE + ( 0x2a0 << 2) )
#define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE + ( 0x2a1 << 2) )
#define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE + ( 0x2a2 << 2) )
#define DDR0_PUB_DX3LCDLR3 (DDR0_PUB_REG_BASE + ( 0x2a3 << 2) )
#define DDR0_PUB_DX3LCDLR4 (DDR0_PUB_REG_BASE + ( 0x2a4 << 2) )
#define DDR0_PUB_DX3LCDLR5 (DDR0_PUB_REG_BASE + ( 0x2a5 << 2) )
#define DDR0_PUB_DX3MDLR0 (DDR0_PUB_REG_BASE + ( 0x2a8 << 2) )
#define DDR0_PUB_DX3MDLR1 (DDR0_PUB_REG_BASE + ( 0x2a9 << 2) )
#define DDR0_PUB_DX3GTR0 (DDR0_PUB_REG_BASE + ( 0x2b0 << 2 ))
#define DDR0_PUB_DX3GTR1 ( DDR0_PUB_REG_BASE + ( 0x2b1 << 2) )
#define DDR0_PUB_DX3GTR2 ( DDR0_PUB_REG_BASE + ( 0x2b2 << 2) )
#define DDR0_PUB_DX3GTR3 ( DDR0_PUB_REG_BASE + ( 0x2b3 << 2) )
#define DDR1_PUB_DX0BDLR0 ( DDR0_PUB_REG_BASE + ( 0x1d0 << 2) )
#define DDR1_PUB_DX0BDLR1 ( DDR0_PUB_REG_BASE + ( 0x1d1 << 2) )
#define DDR1_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE + ( 0x1d2 << 2 ))
#define DDR1_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE + ( 0x1d4 << 2 ))
#define DDR1_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE + ( 0x1d5 << 2) )
#define DDR1_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE + ( 0x1d6 << 2) )
#define DDR1_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE + ( 0x1d8 << 2) )
#define DDR1_PUB_DX0LCDLR0 ( DDR0_PUB_REG_BASE + ( 0x1e0 << 2) )
#define DDR1_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE + ( 0x1e1 << 2 ))
#define DDR1_PUB_DX0LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x1e2 << 2) )
#define DDR1_PUB_DX0LCDLR3 (DDR0_PUB_REG_BASE + ( 0x1e3 << 2 ))
#define DDR1_PUB_DX0LCDLR4 ( DDR0_PUB_REG_BASE + ( 0x1e4 << 2) )
#define DDR1_PUB_DX0LCDLR5 (DDR0_PUB_REG_BASE + ( 0x1e5 << 2 ))
#define DDR1_PUB_DX0MDLR0 (DDR0_PUB_REG_BASE + ( 0x1e8 << 2 ))
#define DDR1_PUB_DX0MDLR1 (DDR0_PUB_REG_BASE + ( 0x1e9 << 2 ))
#define DDR1_PUB_DX0GTR0 (DDR0_PUB_REG_BASE + ( 0x1f0 << 2 ))
#define DDR1_PUB_DX0GTR1 (DDR0_PUB_REG_BASE + ( 0x1f1 << 2) )
#define DDR1_PUB_DX0GTR2 (DDR0_PUB_REG_BASE + ( 0x1f2 << 2) )
#define DDR1_PUB_DX0GTR3 (DDR0_PUB_REG_BASE + ( 0x1f3 << 2))
#define DDR1_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE + ( 0x210 << 2 ))
#define DDR1_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE + ( 0x211 << 2 ))
#define DDR1_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE + ( 0x212 << 2 ))
#define DDR1_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE + ( 0x214 << 2 ))
#define DDR1_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE + ( 0x215 << 2 ))
#define DDR1_PUB_DX1BDLR5 (DDR0_PUB_REG_BASE + ( 0x216 << 2 ))
#define DDR1_PUB_DX1BDLR6 (DDR0_PUB_REG_BASE + ( 0x218 << 2 ))
#define DDR1_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE + ( 0x220 << 2 ))
#define DDR1_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE + ( 0x221 << 2 ))
#define DDR1_PUB_DX1LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x222 << 2 ))
#define DDR1_PUB_DX1LCDLR3 (DDR0_PUB_REG_BASE + ( 0x223 << 2 ))
#define DDR1_PUB_DX1LCDLR4 ( DDR0_PUB_REG_BASE + ( 0x224 << 2 ))
#define DDR1_PUB_DX1LCDLR5 (DDR0_PUB_REG_BASE + ( 0x225 << 2 ))
#define DDR1_PUB_DX1MDLR0 (DDR0_PUB_REG_BASE + ( 0x228 << 2 ))
#define DDR1_PUB_DX1MDLR1 (DDR0_PUB_REG_BASE + ( 0x229 << 2 ))
#define DDR1_PUB_DX1GTR0 (DDR0_PUB_REG_BASE + ( 0x230 << 2 ))
#define DDR1_PUB_DX1GTR1 (DDR0_PUB_REG_BASE + ( 0x231 << 2 ))
#define DDR1_PUB_DX1GTR2 (DDR0_PUB_REG_BASE + ( 0x232 << 2 ))
#define DDR1_PUB_DX1GTR3 (DDR0_PUB_REG_BASE + ( 0x233 << 2 ))
#define DDR1_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE + ( 0x250 << 2 ))
#define DDR1_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE + ( 0x251 << 2 ))
#define DDR1_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE + ( 0x252 << 2 ))
#define DDR1_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE + ( 0x254 << 2 ))
#define DDR1_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE + ( 0x255 << 2 ))
#define DDR1_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE + ( 0x256 << 2 ))
#define DDR1_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE + ( 0x258 << 2 ))
#define DDR1_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE + ( 0x260 << 2 ))
#define DDR1_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE + ( 0x261 << 2 ))
#define DDR1_PUB_DX2LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x262 << 2 ))
#define DDR1_PUB_DX2LCDLR3 (DDR0_PUB_REG_BASE + ( 0x263 << 2 ))
#define DDR1_PUB_DX2LCDLR4 (DDR0_PUB_REG_BASE + ( 0x264 << 2 ))
#define DDR1_PUB_DX2LCDLR5 (DDR0_PUB_REG_BASE + ( 0x265 << 2 ))
#define DDR1_PUB_DX2MDLR0 (DDR0_PUB_REG_BASE + ( 0x268 << 2 ))
#define DDR1_PUB_DX2MDLR1 (DDR0_PUB_REG_BASE + ( 0x269 << 2 ))
#define DDR1_PUB_DX2GTR0 (DDR0_PUB_REG_BASE + ( 0x270 << 2 ))
#define DDR1_PUB_DX2GTR1 (DDR0_PUB_REG_BASE + ( 0x271 << 2 ))
#define DDR1_PUB_DX2GTR2 (DDR0_PUB_REG_BASE + ( 0x272 << 2 ))
#define DDR1_PUB_DX2GTR3 (DDR0_PUB_REG_BASE + ( 0x273 << 2 ))
#define DDR1_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE + ( 0x290 << 2 ))
#define DDR1_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE + ( 0x291 << 2 ))
#define DDR1_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE + ( 0x292 << 2 ))
#define DDR1_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE + ( 0x294 << 2 ))
#define DDR1_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE + ( 0x295 << 2 ))
#define DDR1_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE + ( 0x296 << 2 ))
#define DDR1_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE + ( 0x298 << 2 ))
#define DDR1_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE + ( 0x2a0 << 2 ))
#define DDR1_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE + ( 0x2a1 << 2 ))
#define DDR1_PUB_DX3LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x2a2 << 2 ))
#define DDR1_PUB_DX3LCDLR3 (DDR0_PUB_REG_BASE + ( 0x2a3 << 2 ))
#define DDR1_PUB_DX3LCDLR4 (DDR0_PUB_REG_BASE + ( 0x2a4 << 2 ))
#define DDR1_PUB_DX3LCDLR5 ( DDR0_PUB_REG_BASE + ( 0x2a5 << 2 ))
#define DDR1_PUB_DX3MDLR0 (DDR0_PUB_REG_BASE + ( 0x2a8 << 2 ))
#define DDR1_PUB_DX3MDLR1 (DDR0_PUB_REG_BASE + ( 0x2a9 << 2 ))
#define DDR1_PUB_DX3GTR0 (DDR0_PUB_REG_BASE + ( 0x2b0 << 2 ))
#define DDR1_PUB_DX3GTR1 (DDR0_PUB_REG_BASE + ( 0x2b1 << 2 ))
#define DDR1_PUB_DX3GTR2 (DDR0_PUB_REG_BASE + ( 0x2b2 << 2 ))
#define DDR1_PUB_DX3GTR3 (DDR0_PUB_REG_BASE + ( 0x2b3 << 2 ))
#define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE + ( 0x160 << 2 )) // R/W - LC Delay Line Present Register
#define DDR0_PUB_ACMDLR0 ( DDR0_PUB_REG_BASE + ( 0x168 << 2 )) // R/W - AC Master Delay Line Register 0
#define DDR0_PUB_ACMDLR1 ( DDR0_PUB_REG_BASE + ( 0x169 << 2 )) // R/W - Master Delay Line Register 1
#define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE + ( 0x150 << 2 )) // R/W - AC Bit Delay Line Register 0
#define DDR0_PUB_ACBDLR3 ( DDR0_PUB_REG_BASE + ( 0x153 << 2 ) ) // R/W - AC Bit Delay Line Register 3
#define DDR1_PUB_ACLCDLR (DDR0_PUB_REG_BASE + ( 0x160 << 2 ) )// R/W - LC Delay Line Present Register
#define DDR1_PUB_ACMDLR0 ( DDR0_PUB_REG_BASE + ( 0x168 << 2 )) // R/W - AC Master Delay Line Register 0
#define DDR1_PUB_ACMDLR1 ( DDR0_PUB_REG_BASE + ( 0x169 << 2 )) // R/W - Master Delay Line Register 1
#define DDR1_PUB_ACBDLR0 ( DDR0_PUB_REG_BASE + ( 0x150 << 2 ) )// R/W - AC Bit Delay Line Register 0
#define DDR0_PUB_ACMDLR DDR0_PUB_ACMDLR0
#define DDR1_PUB_ACMDLR DDR1_PUB_ACMDLR0
#define DDR0_PUB_DX0GTR DDR0_PUB_DX0GTR0
#define DDR0_PUB_DX1GTR DDR0_PUB_DX1GTR0
#define DDR0_PUB_DX2GTR DDR0_PUB_DX2GTR0
#define DDR0_PUB_DX3GTR DDR0_PUB_DX3GTR0
#define DDR1_PUB_DX0GTR DDR0_PUB_DX0GTR0
#define DDR1_PUB_DX1GTR DDR0_PUB_DX1GTR0
#define DDR1_PUB_DX2GTR DDR0_PUB_DX2GTR0
#define DDR1_PUB_DX3GTR DDR0_PUB_DX3GTR0
#define DDR0_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 )) // R/W - IO VREF Control Register 0
#define DDR0_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 )) // R/W - IO VREF Control Register 1
#define DDR0_PUB_VTCR0 ( DDR0_PUB_REG_BASE + ( 0x14A << 2 ) )// R/W - VREF Training Control Register 0
#define DDR0_PUB_VTCR1 ( DDR0_PUB_REG_BASE + ( 0x14B << 2 )) // R/W - VREF Training Control Register 1
#define DDR1_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 )) // R/W - IO VREF Control Register 0
#define DDR1_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 )) // R/W - IO VREF Control Register 1
#define DDR1_PUB_VTCR0 ( DDR0_PUB_REG_BASE + ( 0x14A << 2 )) // R/W - VREF Training Control Register 0
#define DDR1_PUB_VTCR1 ( DDR0_PUB_REG_BASE + ( 0x14B << 2 )) // R/W - VREF Training Control Register 1
//#define DDR0_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
//#define DDR1_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
#define DDR0_PUB_DX0GCR6 ( DDR0_PUB_REG_BASE + ( 0x1c6 << 2 ) )
#define DDR0_PUB_DX1GCR6 ( DDR0_PUB_REG_BASE + ( 0x206 << 2 ) )
#define DDR0_PUB_DX2GCR6 ( DDR0_PUB_REG_BASE + ( 0x246 << 2 ) )
#define DDR0_PUB_DX3GCR6 ( DDR0_PUB_REG_BASE + ( 0x286 << 2 ) )
#define DDR0_PUB_DCR ( DDR0_PUB_REG_BASE + ( 0x040 << 2 ) ) // R/W - DRAM Configuration Register
#define DDR0_PUB_MR0 ( DDR0_PUB_REG_BASE + ( 0x060 << 2 ) ) // R/W - Mode Register
#define DDR0_PUB_MR1 ( DDR0_PUB_REG_BASE + ( 0x061 << 2 ) ) // R/W - Extended Mode Register
#define DDR0_PUB_MR2 ( DDR0_PUB_REG_BASE + ( 0x062 << 2 ) ) // R/W - Extended Mode Register 2
#define DDR0_PUB_MR3 ( DDR0_PUB_REG_BASE + ( 0x063 << 2 ) ) // R/W - Extended Mode Register 3
#define DDR0_PUB_MR4 ( DDR0_PUB_REG_BASE + ( 0x064 << 2 ) ) // R/W - Extended Mode Register 4
#define DDR0_PUB_MR5 ( DDR0_PUB_REG_BASE + ( 0x065 << 2 ) ) // R/W - Extended Mode Register 5
#define DDR0_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
#define DDR0_PUB_MR7 ( DDR0_PUB_REG_BASE + ( 0x067 << 2 ) ) // R/W - Extended Mode Register 7
#define DDR0_PUB_MR11 ( DDR0_PUB_REG_BASE + ( 0x06B << 2 ) ) // R/W - Extended Mode Register 11
#define DDR0_PUB_RANKIDR ( DDR0_PUB_REG_BASE + ( 0x137 << 2 ) ) // R/W - Rank ID Register
#define DDR0_PUB_DTCR0 ( DDR0_PUB_REG_BASE + ( 0x080 << 2 ) ) // R/W - Data Training Configuration Register
#define DDR0_PUB_DTEDR0 ( DDR0_PUB_REG_BASE + ( 0x08C << 2 ) ) // R/W - Data Training Eye Data Register 0
#define DDR0_PUB_DTEDR1 ( DDR0_PUB_REG_BASE + ( 0x08D << 2 ) ) // R/W - Data Training Eye Data Register 1
#define DDR0_PUB_DTEDR2 ( DDR0_PUB_REG_BASE + ( 0x08E << 2 ) ) // R/W - Data Training Eye Data Register 2
#define DDR0_PUB_VTDR ( DDR0_PUB_REG_BASE + ( 0x08F << 2 ) ) // R/W - Vref Training Data Register
#else
#define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2))
#define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE+(0x02<<2))
#define DDR0_PUB_PGCR1 (DDR0_PUB_REG_BASE+(0x03<<2))
#define DDR1_PUB_PIR (DDR1_PUB_REG_BASE+(0x01<<2))
#define DDR1_PUB_PGCR0 (DDR1_PUB_REG_BASE+(0x02<<2))
#define DDR1_PUB_PGCR1 (DDR1_PUB_REG_BASE+(0x03<<2))
#define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE+(0xA7<<2))
#define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE+(0xC7<<2))
#define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE+(0xE7<<2))
#define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE+(0x107<<2))
#define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE+(0xA8<<2))
#define DDR0_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE+(0xA9<<2))
#define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE+(0xAA<<2))
#define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE+(0xAB<<2))
#define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE+(0xAC<<2))
#define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE+(0xAD<<2))
#define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE+(0xAE<<2))
#define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE+(0xAF<<2))
#define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE+(0xB0<<2))
#define DDR0_PUB_DX0MDLR (DDR0_PUB_REG_BASE+(0xB1<<2))
#define DDR0_PUB_DX0GTR (DDR0_PUB_REG_BASE+(0xB2<<2))
#define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE+(0xCE<<2))
#define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE+(0xCF<<2))
#define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE+(0xD0<<2))
#define DDR0_PUB_DX1MDLR (DDR0_PUB_REG_BASE+(0xD1<<2))
#define DDR0_PUB_DX1GTR (DDR0_PUB_REG_BASE+(0xD2<<2))
#define DDR0_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE+(0xEE<<2))
#define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE+(0xEF<<2))
#define DDR0_PUB_DX2LCDLR2 (DDR0_PUB_REG_BASE+(0xF0<<2))
#define DDR0_PUB_DX2MDLR (DDR0_PUB_REG_BASE+(0xF1<<2))
#define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE+(0x10E<<2))
#define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE+(0x10F<<2))
#define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE+(0x110<<2))
#define DDR0_PUB_DX3MDLR (DDR0_PUB_REG_BASE+(0x111<<2))
#define DDR0_PUB_DX3GTR (DDR0_PUB_REG_BASE+(0x112<<2))
#define DDR1_PUB_DX0LCDLR0 (DDR1_PUB_REG_BASE+(0xAE<<2))
#define DDR1_PUB_DX0LCDLR1 (DDR1_PUB_REG_BASE+(0xAF<<2))
#define DDR1_PUB_DX0LCDLR2 (DDR1_PUB_REG_BASE+(0xB0<<2))
#define DDR1_PUB_DX0MDLR (DDR1_PUB_REG_BASE+(0xB1<<2))
#define DDR1_PUB_DX0GTR (DDR1_PUB_REG_BASE+(0xB2<<2))
#define DDR1_PUB_DX1LCDLR0 (DDR1_PUB_REG_BASE+(0xCE<<2))
#define DDR1_PUB_DX1LCDLR1 (DDR1_PUB_REG_BASE+(0xCF<<2))
#define DDR1_PUB_DX1LCDLR2 (DDR1_PUB_REG_BASE+(0xD0<<2))
#define DDR1_PUB_DX1MDLR (DDR1_PUB_REG_BASE+(0xD1<<2))
#define DDR1_PUB_DX1GTR (DDR1_PUB_REG_BASE+(0xD2<<2))
#define DDR1_PUB_DX2LCDLR0 (DDR1_PUB_REG_BASE+(0xEE<<2))
#define DDR1_PUB_DX2LCDLR1 (DDR1_PUB_REG_BASE+(0xEF<<2))
#define DDR1_PUB_DX2LCDLR2 (DDR1_PUB_REG_BASE+(0xF0<<2))
#define DDR1_PUB_DX2MDLR (DDR1_PUB_REG_BASE+(0xF1<<2))
#define DDR1_PUB_DX3LCDLR0 (DDR1_PUB_REG_BASE+(0x10E<<2))
#define DDR1_PUB_DX3LCDLR1 (DDR1_PUB_REG_BASE+(0x10F<<2))
#define DDR1_PUB_DX3LCDLR2 (DDR1_PUB_REG_BASE+(0x110<<2))
#define DDR1_PUB_DX3MDLR (DDR1_PUB_REG_BASE+(0x111<<2))
#define DDR1_PUB_DX3GTR (DDR1_PUB_REG_BASE+(0x112<<2))
#define DDR0_PUB_ACMDLR (DDR0_PUB_REG_BASE+(0x0E<<2))
#define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE+(0x0F<<2))
#define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE+(0x10<<2))
#define DDR0_PUB_ACBDLR3 (DDR0_PUB_REG_BASE+(0x13<<2))
#define DDR1_PUB_ACMDLR (DDR1_PUB_REG_BASE+(0x0E<<2))
#define DDR1_PUB_ACLCDLR (DDR1_PUB_REG_BASE+(0x0F<<2))
#define DDR1_PUB_ACBDLR0 (DDR1_PUB_REG_BASE+(0x10<<2))
#define DDR0_PUB_ACMDLR0 DDR0_PUB_ACMDLR
#define DDR1_PUB_ACMDLR0 DDR1_PUB_ACMDLR
#define DDR0_PUB_DX0MDLR0 DDR0_PUB_DX0MDLR
#define DDR0_PUB_DX1MDLR0 DDR0_PUB_DX1MDLR
#define DDR0_PUB_DX2MDLR0 DDR0_PUB_DX2MDLR
#define DDR0_PUB_DX3MDLR0 DDR0_PUB_DX3MDLR
#define DDR1_PUB_DX0MDLR0 DDR0_PUB_DX0MDLR
#define DDR1_PUB_DX1MDLR0 DDR0_PUB_DX1MDLR
#define DDR1_PUB_DX2MDLR0 DDR0_PUB_DX2MDLR
#define DDR1_PUB_DX3MDLR0 DDR0_PUB_DX3MDLR
#define DDR0_PUB_DCR (DDR0_PUB_REG_BASE+(0x22<<2))
#define DDR0_PUB_MR0 (DDR0_PUB_REG_BASE+(0x27<<2))
#define DDR0_PUB_MR1 (DDR0_PUB_REG_BASE+(0x28<<2))
#define DDR0_PUB_MR2 (DDR0_PUB_REG_BASE+(0x29<<2))
#define DDR0_PUB_MR3 (DDR0_PUB_REG_BASE+(0x2A<<2))
#define DDR0_PUB_RANKIDR ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Rank ID Register
#define DDR0_PUB_DTCR0 ( DDR0_PUB_REG_BASE + ( 0<< 2 ) ) // R/W - Data Training Configuration Register
#define DDR0_PUB_DTEDR0 ( DDR0_PUB_REG_BASE + ( 0x0 << 2 ) ) // R/W - Data Training Eye Data Register 0
#define DDR0_PUB_DTEDR1 ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Data Training Eye Data Register 1
#define DDR0_PUB_DTEDR2 ( DDR0_PUB_REG_BASE + ( 0x0 << 2 ) ) // R/W - Data Training Eye Data Register 2
#define DDR0_PUB_VTDR ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Vref Training Data Register
#ifndef P_DDR0_CLK_CTRL
#define P_DDR0_CLK_CTRL 0xc8000800
#endif
#ifndef P_DDR1_CLK_CTRL
#define P_DDR1_CLK_CTRL 0xc8002800
#endif
#define DDR0_PUB_IOVCR0 (DDR0_PUB_REG_BASE+(0x8E<<2))
#define DDR0_PUB_IOVCR1 (DDR0_PUB_REG_BASE+(0x8F<<2))
#endif
#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
//unsigned int des[8];
/*
unsigned int pattern_1[4][8]=
{
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
0xff00ff00 ,
};
unsigned int pattern_2[4][8]={
0x0001fe00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0002fd00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0004fb00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0008f700 ,
0x0000ff00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0010ef00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0020df00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0040bf00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0000ff00 ,
0x00807f00 ,
0x0000ff00 ,
0x0000ff00 ,
0x0000ff00 ,
};
unsigned int pattern_3[4][8]={
0x00010000 ,
0x00000000 ,
0x00000000 ,
0x00000000 ,
0x00020000 ,
0x00000000 ,
0x00000000 ,
0x00000000 ,
0x00040000 ,
0x00000000 ,
0x00000000 ,
0x00000000 ,
0x00080000 ,
0x00000000 ,
0x00000000 ,
0x00000000 ,
0x00100000 ,
0x00000000 ,
0x00000000 ,
0x00000000 ,
0x00200000 ,
0x00000000 ,
0x00000000 ,
0x00000000 ,
0x00400000 ,
0x00000000 ,
0x00000000 ,
0x00000000 ,
0x00800000 ,
0x00000000 ,
0x00000000 ,
0x00000000 ,
};
unsigned int pattern_4[4][8]={
0x51c8c049 ,
0x2d43592c ,
0x0777b50b ,
0x9cd2ebe5 ,
0xc04199d5 ,
0xdc968dc0 ,
0xb8ba8a33 ,
0x35e4327f ,
0x51c8c049 ,
0x2d43592c ,
0x0777b50b ,
0x9cd2ebe5 ,
0xc04199d5 ,
0xdc968dc0 ,
0xb8ba8a33 ,
0x35e4327f ,
0x51c8c049 ,
0x2d43592c ,
0x0777b50b ,
0x9cd2ebe5 ,
0xc04199d5 ,
0xdc968dc0 ,
0xb8ba8a33 ,
0x35e4327f ,
0x51c8c049 ,
0x2d43592c ,
0x0777b50b ,
0x9cd2ebe5 ,
0xc04199d5 ,
0xdc968dc0 ,
0xb8ba8a33 ,
0x35e4327f ,
};
unsigned int pattern_5[4][8]={
0xaec9c149 ,
0xd243592c ,
0xf877b50b ,
0x63d2ebe5 ,
0x3f439bd5 ,
0x23968dc0 ,
0x47ba8a33 ,
0xcae4327f ,
0xaeccc449 ,
0xd243592c ,
0xf877b50b ,
0x63d2ebe5 ,
0x3f4991d5 ,
0x23968dc0 ,
0x47ba8a33 ,
0xcae4327f ,
0xaed8d049 ,
0xd243592c ,
0xf877b50b ,
0x63d2ebe5 ,
0x3f61b9d5 ,
0x23968dc0 ,
0x47ba8a33 ,
0xcae4327f ,
0xae888049 ,
0xd243592c ,
0xf877b50b ,
0x63d2ebe5 ,
0x3fc119d5 ,
0x23968dc0 ,
0x47ba8a33 ,
0xcae4327f ,
};
unsigned int pattern_6[4][8]={
0xaec9c149 ,
0xd243a62c ,
0xf8774a0b ,
0x63d214e5 ,
0x3f4366d5 ,
0x239672c0 ,
0x47ba7533 ,
0xcae4cd7f ,
0xaecc3f49 ,
0xd243a62c ,
0xf8774a0b ,
0x63d214e5 ,
0x3f4966d5 ,
0x239672c0 ,
0x47ba7533 ,
0xcae4cd7f ,
0xaed83f49 ,
0xd243a62c ,
0xf8774a0b ,
0x63d214e5 ,
0x3f6166d5 ,
0x239672c0 ,
0x47ba7533 ,
0xcae4cd7f ,
0xae883f49 ,
0xd243a62c ,
0xf8774a0b ,
0x63d214e5 ,
0x3fc166d5 ,
0x239672c0 ,
0x47ba7533 ,
0xcae4cd7f ,
};
unsigned int des[8] ={
0xaec83f49,
0xd243a62c,
0xf8774a0b,
0x63d214e5,
0x3f4166d5,
0x239672c0,
0x47ba7533,
0xcae4cd7f,
};
*/
/*
unsigned int des[8] ;
des[0] = 0xaec83f49;
des[1] = 0xd243a62c;
des[2] = 0xf8774a0b;
des[3] = 0x63d214e5;
des[4] = 0x3f4166d5;
des[5] = 0x239672c0;
des[6] = 0x47ba7533;
des[7] = 0xcae4cd7f;
pattern_1[0][0] = 0xff00ff00;
pattern_1[0][1] = 0xff00ff00;
pattern_1[0][2] = 0xff00ff00;
pattern_1[0][3] = 0xff00ff00;
pattern_1[0][4] = 0xff00ff00;
pattern_1[0][5] = 0xff00ff00;
pattern_1[0][6] = 0xff00ff00;
pattern_1[0][7] = 0xff00ff00;
pattern_1[1][0] = 0xff00ff00;
pattern_1[1][1] = 0xff00ff00;
pattern_1[1][2] = 0xff00ff00;
pattern_1[1][3] = 0xff00ff00;
pattern_1[1][4] = 0xff00ff00;
pattern_1[1][5] = 0xff00ff00;
pattern_1[1][6] = 0xff00ff00;
pattern_1[1][7] = 0xff00ff00;
pattern_1[2][0] = 0xff00ff00;
pattern_1[2][1] = 0xff00ff00;
pattern_1[2][2] = 0xff00ff00;
pattern_1[2][3] = 0xff00ff00;
pattern_1[2][4] = 0xff00ff00;
pattern_1[2][5] = 0xff00ff00;
pattern_1[2][6] = 0xff00ff00;
pattern_1[2][7] = 0xff00ff00;
pattern_1[3][0] = 0xff00ff00;
pattern_1[3][1] = 0xff00ff00;
pattern_1[3][2] = 0xff00ff00;
pattern_1[3][3] = 0xff00ff00;
pattern_1[3][4] = 0xff00ff00;
pattern_1[3][5] = 0xff00ff00;
pattern_1[3][6] = 0xff00ff00;
pattern_1[3][7] = 0xff00ff00;
pattern_2[0][0] = 0x0001fe00;
pattern_2[0][1] = 0x0000ff00;
pattern_2[0][2] = 0x0000ff00;
pattern_2[0][3] = 0x0000ff00;
pattern_2[0][4] = 0x0002fd00;
pattern_2[0][5] = 0x0000ff00;
pattern_2[0][6] = 0x0000ff00;
pattern_2[0][7] = 0x0000ff00;
pattern_2[1][0] = 0x0004fb00;
pattern_2[1][1] = 0x0000ff00;
pattern_2[1][2] = 0x0000ff00;
pattern_2[1][3] = 0x0000ff00;
pattern_2[1][4] = 0x0008f700;
pattern_2[1][5] = 0x0000ff00;
pattern_2[1][6] = 0x0000ff00;
pattern_2[1][7] = 0x0000ff00;
pattern_2[2][0] = 0x0010ef00;
pattern_2[2][1] = 0x0000ff00;
pattern_2[2][2] = 0x0000ff00;
pattern_2[2][3] = 0x0000ff00;
pattern_2[2][4] = 0x0020df00;
pattern_2[2][5] = 0x0000ff00;
pattern_2[2][6] = 0x0000ff00;
pattern_2[2][7] = 0x0000ff00;
pattern_2[3][0] = 0x0040bf00;
pattern_2[3][1] = 0x0000ff00;
pattern_2[3][2] = 0x0000ff00;
pattern_2[3][3] = 0x0000ff00;
pattern_2[3][4] = 0x00807f00;
pattern_2[3][5] = 0x0000ff00;
pattern_2[3][6] = 0x0000ff00;
pattern_2[3][7] = 0x0000ff00;
pattern_3[0][0] = 0x00010000;
pattern_3[0][1] = 0x00000000;
pattern_3[0][2] = 0x00000000;
pattern_3[0][3] = 0x00000000;
pattern_3[0][4] = 0x00020000;
pattern_3[0][5] = 0x00000000;
pattern_3[0][6] = 0x00000000;
pattern_3[0][7] = 0x00000000;
pattern_3[1][0] = 0x00040000;
pattern_3[1][1] = 0x00000000;
pattern_3[1][2] = 0x00000000;
pattern_3[1][3] = 0x00000000;
pattern_3[1][4] = 0x00080000;
pattern_3[1][5] = 0x00000000;
pattern_3[1][6] = 0x00000000;
pattern_3[1][7] = 0x00000000;
pattern_3[2][0] = 0x00100000;
pattern_3[2][1] = 0x00000000;
pattern_3[2][2] = 0x00000000;
pattern_3[2][3] = 0x00000000;
pattern_3[2][4] = 0x00200000;
pattern_3[2][5] = 0x00000000;
pattern_3[2][6] = 0x00000000;
pattern_3[2][7] = 0x00000000;
pattern_3[3][0] = 0x00400000;
pattern_3[3][1] = 0x00000000;
pattern_3[3][2] = 0x00000000;
pattern_3[3][3] = 0x00000000;
pattern_3[3][4] = 0x00800000;
pattern_3[3][5] = 0x00000000;
pattern_3[3][6] = 0x00000000;
pattern_3[3][7] = 0x00000000;
pattern_4[0][0] = 0x51c8c049 ;
pattern_4[0][1] = 0x2d43592c ;
pattern_4[0][2] = 0x0777b50b ;
pattern_4[0][3] = 0x9cd2ebe5 ;
pattern_4[0][4] = 0xc04199d5 ;
pattern_4[0][5] = 0xdc968dc0 ;
pattern_4[0][6] = 0xb8ba8a33 ;
pattern_4[0][7] = 0x35e4327f ;
pattern_4[1][0] = 0x51c8c049 ;
pattern_4[1][1] = 0x2d43592c ;
pattern_4[1][2] = 0x0777b50b ;
pattern_4[1][3] = 0x9cd2ebe5 ;
pattern_4[1][4] = 0xc04199d5 ;
pattern_4[1][5] = 0xdc968dc0 ;
pattern_4[1][6] = 0xb8ba8a33 ;
pattern_4[1][7] = 0x35e4327f ;
pattern_4[2][0] = 0x51c8c049 ;
pattern_4[2][1] = 0x2d43592c ;
pattern_4[2][2] = 0x0777b50b ;
pattern_4[2][3] = 0x9cd2ebe5 ;
pattern_4[2][4] = 0xc04199d5 ;
pattern_4[2][5] = 0xdc968dc0 ;
pattern_4[2][6] = 0xb8ba8a33 ;
pattern_4[2][7] = 0x35e4327f ;
pattern_4[3][0] = 0x51c8c049 ;
pattern_4[3][1] = 0x2d43592c ;
pattern_4[3][2] = 0x0777b50b ;
pattern_4[3][3] = 0x9cd2ebe5 ;
pattern_4[3][4] = 0xc04199d5 ;
pattern_4[3][5] = 0xdc968dc0 ;
pattern_4[3][6] = 0xb8ba8a33 ;
pattern_4[3][7] = 0x35e4327f ;
pattern_5[0][0] = 0xaec9c149 ;
pattern_5[0][1] = 0xd243592c ;
pattern_5[0][2] = 0xf877b50b ;
pattern_5[0][3] = 0x63d2ebe5 ;
pattern_5[0][4] = 0x3f439bd5 ;
pattern_5[0][5] = 0x23968dc0 ;
pattern_5[0][6] = 0x47ba8a33 ;
pattern_5[0][7] = 0xcae4327f ;
pattern_5[1][0] = 0xaeccc449 ;
pattern_5[1][1] = 0xd243592c ;
pattern_5[1][2] = 0xf877b50b ;
pattern_5[1][3] = 0x63d2ebe5 ;
pattern_5[1][4] = 0x3f4991d5 ;
pattern_5[1][5] = 0x23968dc0 ;
pattern_5[1][6] = 0x47ba8a33 ;
pattern_5[1][7] = 0xcae4327f ;
pattern_5[2][0] = 0xaed8d049 ;
pattern_5[2][1] = 0xd243592c ;
pattern_5[2][2] = 0xf877b50b ;
pattern_5[2][3] = 0x63d2ebe5 ;
pattern_5[2][4] = 0x3f61b9d5 ;
pattern_5[2][5] = 0x23968dc0 ;
pattern_5[2][6] = 0x47ba8a33 ;
pattern_5[2][7] = 0xcae4327f ;
pattern_5[3][0] = 0xae888049 ;
pattern_5[3][1] = 0xd243592c ;
pattern_5[3][2] = 0xf877b50b ;
pattern_5[3][3] = 0x63d2ebe5 ;
pattern_5[3][4] = 0x3fc119d5 ;
pattern_5[3][5] = 0x23968dc0 ;
pattern_5[3][6] = 0x47ba8a33 ;
pattern_5[3][7] = 0xcae4327f ;
pattern_6[0][1] = 0xd243a62c ;
pattern_6[0][2] = 0xf8774a0b ;
pattern_6[0][3] = 0x63d214e5 ;
pattern_6[0][4] = 0x3f4366d5 ;
pattern_6[0][5] = 0x239672c0 ;
pattern_6[0][6] = 0x47ba7533 ;
pattern_6[0][7] = 0xcae4cd7f ;
pattern_6[1][0] = 0xaecc3f49 ;
pattern_6[1][1] = 0xd243a62c ;
pattern_6[1][2] = 0xf8774a0b ;
pattern_6[1][3] = 0x63d214e5 ;
pattern_6[1][4] = 0x3f4966d5 ;
pattern_6[1][5] = 0x239672c0 ;
pattern_6[1][6] = 0x47ba7533 ;
pattern_6[1][7] = 0xcae4cd7f ;
pattern_6[2][0] = 0xaed83f49 ;
pattern_6[2][1] = 0xd243a62c ;
pattern_6[2][2] = 0xf8774a0b ;
pattern_6[2][3] = 0x63d214e5 ;
pattern_6[2][4] = 0x3f6166d5 ;
pattern_6[2][5] = 0x239672c0 ;
pattern_6[2][6] = 0x47ba7533 ;
pattern_6[2][7] = 0xcae4cd7f ;
pattern_6[3][0] = 0xae883f49 ;
pattern_6[3][1] = 0xd243a62c ;
pattern_6[3][2] = 0xf8774a0b ;
pattern_6[3][3] = 0x63d214e5 ;
pattern_6[3][4] = 0x3fc166d5 ;
pattern_6[3][5] = 0x239672c0 ;
pattern_6[3][6] = 0x47ba7533 ;
pattern_6[3][7] = 0xcae4cd7f ;
*/
#endif
#define DDR_TEST_START_ADDR 0x1080000// 0x10000000 //CONFIG_SYS_MEMTEST_START
#define DDR_TEST_SIZE 0x2000000
//#define DDR_TEST_SIZE 0x2000
#if (CONFIG_CHIP>=CHIP_TXLX)
#define P_EE_TIMER_E (volatile unsigned int *)((0x3c62 << 2) + 0xffd00000)
///*
//#ifndef P_PIN_MUX_REG1
// Pin Mux (9)
// ----------------------------
#if (CONFIG_CHIP==CHIP_TXLX)
#define PERIPHS_PIN_MUX_0 (0xff634400 + (0x2c << 2))
#define SEC_PERIPHS_PIN_MUX_0 (0xff634400 + (0x2c << 2))
#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(0xff634400 + (0x2c << 2))
#define PERIPHS_PIN_MUX_1 (0xff634400 + (0x2d << 2))
#define SEC_PERIPHS_PIN_MUX_1 (0xff634400 + (0x2d << 2))
#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(0xff634400 + (0x2d << 2))
#define PERIPHS_PIN_MUX_2 (0xff634400 + (0x2e << 2))
#define SEC_PERIPHS_PIN_MUX_2 (0xff634400 + (0x2e << 2))
#define P_PERIPHS_PIN_MUX_2 (volatile uint32_t *)(0xff634400 + (0x2e << 2))
#define PERIPHS_PIN_MUX_3 (0xff634400 + (0x2f << 2))
#define SEC_PERIPHS_PIN_MUX_3 (0xff634400 + (0x2f << 2))
#define P_PERIPHS_PIN_MUX_3 (volatile uint32_t *)(0xff634400 + (0x2f << 2))
#define PERIPHS_PIN_MUX_4 (0xff634400 + (0x30 << 2))
#define SEC_PERIPHS_PIN_MUX_4 (0xff634400 + (0x30 << 2))
#define P_PERIPHS_PIN_MUX_4 (volatile uint32_t *)(0xff634400 + (0x30 << 2))
#define PERIPHS_PIN_MUX_5 (0xff634400 + (0x31 << 2))
#define SEC_PERIPHS_PIN_MUX_5 (0xff634400 + (0x31 << 2))
#define P_PERIPHS_PIN_MUX_5 (volatile uint32_t *)(0xff634400 + (0x31 << 2))
#define PERIPHS_PIN_MUX_6 (0xff634400 + (0x32 << 2))
#define SEC_PERIPHS_PIN_MUX_6 (0xff634400 + (0x32 << 2))
#define P_PERIPHS_PIN_MUX_6 (volatile uint32_t *)(0xff634400 + (0x32 << 2))
#define PERIPHS_PIN_MUX_7 (0xff634400 + (0x33 << 2))
#define SEC_PERIPHS_PIN_MUX_7 (0xff634400 + (0x33 << 2))
#define P_PERIPHS_PIN_MUX_7 (volatile uint32_t *)(0xff634400 + (0x33 << 2))
#define PERIPHS_PIN_MUX_8 (0xff634400 + (0x34 << 2))
#define SEC_PERIPHS_PIN_MUX_8 (0xff634400 + (0x34 << 2))
#define P_PERIPHS_PIN_MUX_8 (volatile uint32_t *)(0xff634400 + (0x34 << 2))
#define PERIPHS_PIN_MUX_9 (0xff634400 + (0x35 << 2))
#define SEC_PERIPHS_PIN_MUX_9 (0xff634400 + (0x35 << 2))
#define P_PERIPHS_PIN_MUX_9 (volatile uint32_t *)(0xff634400 + (0x35 << 2))
#define PERIPHS_PIN_MUX_10 (0xff634400 + (0x36 << 2))
#define SEC_PERIPHS_PIN_MUX_10 (0xff634400 + (0x36 << 2))
#define P_PERIPHS_PIN_MUX_10 (volatile uint32_t *)(0xff634400 + (0x36 << 2))
#define PERIPHS_PIN_MUX_11 (0xff634400 + (0x37 << 2))
#define SEC_PERIPHS_PIN_MUX_11 (0xff634400 + (0x37 << 2))
#define P_PERIPHS_PIN_MUX_11 (volatile uint32_t *)(0xff634400 + (0x37 << 2))
#define PERIPHS_PIN_MUX_12 (0xff634400 + (0x38 << 2))
#define SEC_PERIPHS_PIN_MUX_12 (0xff634400 + (0x38 << 2))
#define P_PERIPHS_PIN_MUX_12 (volatile uint32_t *)(0xff634400 + (0x38 << 2))
#endif
#define P_PIN_MUX_REG1 P_PERIPHS_PIN_MUX_1// (((volatile unsigned *)(0xda834400 + (0x2d << 2))))
#define P_PIN_MUX_REG2 P_PERIPHS_PIN_MUX_2// (((volatile unsigned *)(0xda834400 + (0x2e << 2))))
#define P_PIN_MUX_REG3 P_PERIPHS_PIN_MUX_3//(((volatile unsigned *)(0xda834400 + (0x2f << 2))))
#define P_PIN_MUX_REG7 P_PERIPHS_PIN_MUX_7//(((volatile unsigned *)(0xda834400 + (0x33 << 2))))
//#endif
//#ifndef P_PWM_MISC_REG_AB
//#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
//#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
//#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
//#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
//#endif
//*/
//#define PWM_MISC_REG_AB (0x6c02)
//#define P_PWM_MISC_REG_AB (volatile unsigned int *)((0x6c02 << 2) + 0xffd00000)
//#define WATCHDOG_CNTL ((0x3c34 << 2) + 0xffd00000)
//#define WATCHDOG_CNTL1 ((0x3c35 << 2) + 0xffd00000)
//#define WATCHDOG_TCNT ((0x3c36 << 2) + 0xffd00000)
//#define WATCHDOG_RESET ((0x3c37 << 2) + 0xffd00000)
#else
//#define ddr_udelay(a) do{}while((a<<5)--);
#define P_EE_TIMER_E (volatile unsigned int *)(((0x2662 << 2) + 0xc1100000))
//#define WATCHDOG_CNTL 0xc11098d0
//#define WATCHDOG_CNTL1 0xc11098d4
//#define WATCHDOG_TCNT 0xc11098d8
//#define WATCHDOG_RESET 0xc11098dc
#ifndef P_WATCHDOG_CNTL
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
#define P_WATCHDOG_CNTL (volatile unsigned int *)0xc11098d0
#define P_WATCHDOG_CNTL1 (volatile unsigned int *) 0xc11098d4
#define P_WATCHDOG_TCNT (volatile unsigned int *)0xc11098d8
#define P_WATCHDOG_RESET (volatile unsigned int *) 0xc11098dc
#else
#define P_WATCHDOG_CNTL (volatile unsigned int *)(0xc1100000+(0x2640<<2))
//#define P_WATCHDOG_CNTL1 (volatile unsigned int *) 0xc11098d4
//#define P_WATCHDOG_TCNT (volatile unsigned int *)0xc11098d8
#define P_WATCHDOG_RESET (volatile unsigned int *)(0xc1100000+(0x2641<<2))
#endif
#endif
#ifndef P_PIN_MUX_REG1
#define P_PIN_MUX_REG1 (((volatile unsigned *)(0xda834400 + (0x2d << 2))))
#define P_PIN_MUX_REG2 (((volatile unsigned *)(0xda834400 + (0x2e << 2))))
#define P_PIN_MUX_REG3 (((volatile unsigned *)(0xda834400 + (0x2f << 2))))
#define P_PIN_MUX_REG7 (((volatile unsigned *)(0xda834400 + (0x33 << 2))))
#endif
#ifndef P_PWM_MISC_REG_AB
#define P_PWM_MISC_REG_AB (((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
#define P_PWM_PWM_B (((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
#define P_PWM_MISC_REG_CD (((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
#define P_PWM_PWM_D (((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
#endif
#ifndef P_EE_TIMER_E
#define P_EE_TIMER_E (((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
#endif
#endif
#define get_us_time() (*P_EE_TIMER_E)// (readl(P_ISA_TIMERE))
// #define P_ISA_TIMERE 0xc1109988
// #define get_us_time() (readl(P_ISA_TIMERE))
/*
#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xff807000 + (0x02 << 2))))
#define P_PWM_PWM_A (*((volatile unsigned *)((0x6c00 << 2) + 0xffd00000)))
#define AO_PIN_MUX_REG (*((volatile unsigned *)(0xff800000 + (0x05 << 2))))
*/
#define dwc_ddrphy_apb_wr(addr, dat) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+0xfe000000))=((uint16_t)dat)
#define dwc_ddrphy_apb_rd(addr) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+0xfe000000))
#define ACX_MAX 0x80
void ddr_udelay(unsigned int us)
{
//#ifndef CONFIG_PXP_EMULATOR
unsigned int t0 = (*((P_EE_TIMER_E)));
while ((*((P_EE_TIMER_E))) - t0 <= us)
;
//#endif
}
#define DDR_PARAMETER_SOURCE_FROM_DMC_STICKY 1
#define DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV 2
#define DDR_PARAMETER_SOURCE_FROM_UBOOT_IDME 3
#define DDR_PARAMETER_SOURCE_FROM_ORG_STICKY 4
#define DDR_PARAMETER_READ 1
#define DDR_PARAMETER_WRITE 2
#define DDR_PARAMETER_LEFT 1
#define DDR_PARAMETER_RIGHT 2
typedef struct ddr_test_struct {
unsigned int ddr_data_source ;
unsigned int ddr_data_test_size ;
unsigned int ddr_address_test_size ;
unsigned int ddr_test_watchdog_times_s ;
unsigned int ddr_test_lane_disable ;
unsigned int ddr_test_window_flag[8] ;
unsigned int ddr_test_window_data[100] ;
} ddr_test_struct_t;
ddr_test_struct_t *g_ddr_test_struct;
unsigned int read_write_window_test_parameter(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
{
if(source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
{
sticky_reg_base_add = (DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
if(read_write_flag == DDR_PARAMETER_WRITE)
wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
if(read_write_flag == DDR_PARAMETER_READ)
parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
}
if(source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
{
char *pre_env_name = "ddr_test_data_num";
char *env_name = "ddr_test_data_num_0000";
char *str_buf = NULL;
char *temp_s = NULL;
char *endp = NULL;
char buf[1024];
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
sprintf(buf, "0x%08x", parameter_value);
if(read_write_flag == DDR_PARAMETER_WRITE)
{
setenv(env_name, buf);
run_command("save",0);
}
if(read_write_flag == DDR_PARAMETER_READ)
{
temp_s = getenv(env_name);
if(temp_s)
parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
else
parameter_value = 0;
}
}
if(source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
{
sticky_reg_base_add=(PREG_STICKY_REG0);
if(read_write_flag==DDR_PARAMETER_WRITE)
wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
if(read_write_flag==DDR_PARAMETER_READ)
parameter_value=rd_reg((sticky_reg_base_add+(parameter_index<<2)));
}
return parameter_value;
}
unsigned int read_write_window_test_flag(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
{
if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
{
sticky_reg_base_add = PREG_STICKY_REG0;
if (read_write_flag == DDR_PARAMETER_WRITE)
wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
if (read_write_flag == DDR_PARAMETER_READ)
parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
}
if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
{
sticky_reg_base_add = (DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
if (read_write_flag == DDR_PARAMETER_WRITE)
wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
if (read_write_flag == DDR_PARAMETER_READ)
parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
}
if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
{
char *pre_env_name = "ddr_test_data_num";
char *env_name = "ddr_test_data_num_0000";
char *str_buf = NULL;
char *temp_s = NULL;
char *endp = NULL;
char buf[1024];
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
sprintf(buf, "0x%08x", parameter_value);
if (read_write_flag == DDR_PARAMETER_WRITE)
{
setenv(env_name, buf);
run_command("save",0);
}
if(read_write_flag == DDR_PARAMETER_READ)
{
temp_s = getenv(env_name);
if(temp_s)
parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
else
parameter_value = 0;
}
}
return parameter_value;
}
void ddr_test_watchdog_init(uint32_t msec)
{
// src: 24MHz
// div: 24000 for 1ms
// reset ao-22 and ee-21
// writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
*P_WATCHDOG_CNTL = (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1);
// set timeout
//*P_WATCHDOG_TCNT = msec;
// writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
*P_WATCHDOG_TCNT = msec;
//writel(0,(unsigned int )P_WATCHDOG_RESET);
*P_WATCHDOG_RESET = 0;
//*P_WATCHDOG_RESET = 0;
// enable
*P_WATCHDOG_CNTL = (*P_WATCHDOG_CNTL)|(1<<18);
//writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
//*P_WATCHDOG_CNTL |= (1<<18);
#else
*P_WATCHDOG_CNTL = (0<<24)|(msec*8-1);
//*P_WATCHDOG_TCNT=msec;
#endif
}
void ddr_test_watchdog_enable(uint32_t sec)
{
// src: 24MHz
// div: 24000 for 1ms
// reset ao-22 and ee-21
// writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
*P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
// set timeout
//*P_WATCHDOG_TCNT = msec;
// writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
if(sec*100>0xffff)
*P_WATCHDOG_TCNT=0xffff;
else
*P_WATCHDOG_TCNT=sec*100; //max 655s
//writel(0,(unsigned int )P_WATCHDOG_RESET);
*P_WATCHDOG_RESET=0;
//*P_WATCHDOG_RESET = 0;
// enable
*P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18);
//writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
//*P_WATCHDOG_CNTL |= (1<<18);
#else
//*P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(sec*8000-1);
*P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(0xffff);
printf("\nm8baby_watchdog max only 5s,please take care test size not too long for m8baby\n");
#endif
printf("\nP_WATCHDOG_ENABLE\n");
}
void ddr_test_watchdog_disable(void )
{
// src: 24MHz
// div: 24000 for 1ms
// reset ao-22 and ee-21
// writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
*P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
// set timeout
//*P_WATCHDOG_TCNT = msec;
// writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
//*P_WATCHDOG_TCNT=sec*100;
//writel(0,(unsigned int )P_WATCHDOG_RESET);
*P_WATCHDOG_RESET=0;
//*P_WATCHDOG_RESET = 0;
// enable
*P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)&(~(1<<18));
//writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
//*P_WATCHDOG_CNTL |= (1<<18);
#else
*P_WATCHDOG_CNTL=(0<<24)|(0<<19)|(24000-1);
#endif
printf("\nP_WATCHDOG_DISABLE\n");
}
void ddr_test_watchdog_clear(void )
{
// src: 24MHz
// div: 24000 for 1ms
// reset ao-22 and ee-21
// writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
//*P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
// set timeout
//*P_WATCHDOG_TCNT = msec;
// writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
//*P_WATCHDOG_TCNT=sec*100;
//writel(0,(unsigned int )P_WATCHDOG_RESET);
*P_WATCHDOG_RESET=0;
//*P_WATCHDOG_RESET = 0;
// enable
//*P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)&(~(1<<18));
//writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
//*P_WATCHDOG_CNTL |= (1<<18);
//printf("\nP_WATCHDOG_CLEAR,reg=0x%8x\n",(P_WATCHDOG_RESET));
}
void ddr_test_watchdog_reset_system(void)
{
//#define P_WATCHDOG_CNTL 0xc11098d0
//#define P_WATCHDOG_CNTL1 0xc11098d4
//#define P_WATCHDOG_TCNT 0xc11098d8
//#define P_WATCHDOG_RESET 0xc11098dc
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
int i;
while (1) {
/*
writel( 0x3 | (1 << 21) // sys reset en ao ee 3
| (1 << 23) // interrupt en
| (1 << 24) // clk en
| (1 << 25) // clk div en
| (1 << 26) // sys reset now ao ee 3
, (unsigned int )P_WATCHDOG_CNTL);
*/
*P_WATCHDOG_CNTL=
0x3 | (1 << 21) // sys reset en ao ee 3
| (1 << 23) // interrupt en
| (1 << 24) // clk en
| (1 << 25) // clk div en
| (1 << 26); // sys reset now ao ee 3;
//printf("\nP_WATCHDOG_CNTL reg_add_%x08==%x08",(unsigned int )P_WATCHDOG_CNTL,readl((unsigned int )P_WATCHDOG_CNTL));
//printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL));
//printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL));
printf("\nP_WATCHDOG_CNTLREG_ADD %x08==%x08",(unsigned int)(unsigned long)P_WATCHDOG_CNTL,
*P_WATCHDOG_CNTL);
//writel(0, (unsigned int )P_WATCHDOG_RESET);
*P_WATCHDOG_RESET=0;
// writel(readl((unsigned int )P_WATCHDOG_CNTL) | (1<<18), // watchdog en
//(unsigned int )P_WATCHDOG_CNTL);
*P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18);
for (i=0; i<100; i++)
*P_WATCHDOG_CNTL;
//readl((unsigned int )P_WATCHDOG_CNTL);/*Deceive gcc for waiting some cycles */
}
#else
//WRITE_CBUS_REG(WATCHDOG_TC, 0xf080000 | 2000);
*P_WATCHDOG_CNTL=(0xf080000 | 2000);
#endif
while(1);
}
//just tune for lcdlr
#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
#else
int do_ddr_fine_tune_lcdlr_env1(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf("\nEnter ddr_fine_tune_lcdlr_env function\n");
// if(!argc)
// goto DDR_TUNE_DQS_START;
int i = 0;
printf("\nargc== 0x%08x\n", argc);
for(i = 0; i<argc; i++)
{
printf("\nargv[%d]=%s\n",i,argv[i]);
}
//writel((0), 0xc8836c00);
OPEN_CHANNEL_A_PHY_CLK();
OPEN_CHANNEL_B_PHY_CLK();
//writel((0), 0xc8836c00);
char *endp;
// unsigned int *p_start_addr;
#define WR_RD_ADJ_USE_ENV 1
#define WR_RD_ADJ_USE_UART_INPUT 2
unsigned int wr_rd_adj_input_src=1;
int wr_adj_per[12]={
100 ,
1000,
100 ,
100 ,
100 ,
100 ,
100 ,
100 ,
100 ,
100 ,
100 ,
100 ,
};
int rd_adj_per[12]={
100 ,
100 ,
80 ,
80 ,
80 ,
80 ,
100 ,
100 ,
100 ,
100 ,
100 ,
100 ,
};
if(argc == 1)
printf("\nplease read help\n");
if(argc >= 2)
{
wr_rd_adj_input_src = simple_strtoull_ddr(argv[1], &endp, 10);
unsigned int i=0;
if(wr_rd_adj_input_src==WR_RD_ADJ_USE_UART_INPUT)
{
printf("\ntune ddr lcdlr use uart input\n");
if (argc>24+2)
argc=24+2;
for(i = 2;i<argc;i++)
{
if(i<(2+12))
wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 10);
else
rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 10);
}
}
// unsigned int = 0, max = 0xff, min = 0x00;
if(wr_rd_adj_input_src==WR_RD_ADJ_USE_ENV)
{
printf("\ntune ddr lcdlr use uboot env\n");
//char str[24];
const char *s;
// char *varname;
int value=0;
//*varname="env_ddrtest";
s = getenv("env_wr_lcdlr_pr");
if (s)
{//i=0;
//while(s_temp)
{
printf("%s",s);
//sscanf(s,"d%,",wr_adj_per);
//sprintf(str,"d%",s);
//getc
}
value = simple_strtoull_ddr(s, &endp, 16);
printf("%d",value);
}
s = getenv("env_rd_lcdlr_pr");
if (s)
{//i=0;
//while(s_temp)
{
printf("%s",s);
//sscanf(s,"d%,",rd_adj_per);
}
//value = simple_strtoull_ddr(s, &endp, 16);
}
//sprintf(str, "%lx", value);
// setenv("env_ddrtest", str);
//run_command("save",0);
if (argc>24+2)
argc=24+2;
for(i = 2;i<argc;i++)
{
if(i<(2+12))
wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 16);
else
rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 16);
}
}
printf(" int wr_adj_per[12]={\n");
for(i = 0;i<12;i++)
printf("%04d ,\n",wr_adj_per[i]);
printf("};\n");
printf(" int rd_adj_per[12]={\n");
for(i = 0;i<12;i++)
printf("%04d ,\n",rd_adj_per[i]);
printf("};\n");
#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))|(1<<29));
wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))|(1<<0));
wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))|(1<<29));
wr_reg(DDR1_PUB_PGCR6, (rd_reg(DDR1_PUB_PGCR6))|(1<<0));
#else
wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))|(1<<29));
wr_reg(DDR0_PUB_PGCR1, (rd_reg(DDR0_PUB_PGCR1))|(1<<26));
wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))|(1<<29));
wr_reg(DDR1_PUB_PGCR1, (rd_reg(DDR1_PUB_PGCR1))|(1<<26));
#endif
int lcdlr_w=0,lcdlr_r=0;
unsigned temp_reg=0;
int temp_count=0;
for( temp_count=0;temp_count<2;temp_count++)
{ temp_reg=(unsigned)(DDR0_PUB_ACLCDLR+(temp_count<<2));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
lcdlr_w=lcdlr_w?lcdlr_w:1;
lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
if(temp_count==1)
lcdlr_w=lcdlr_w&ACBDLR_MAX;
wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
}
#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
for( temp_count=2;temp_count<6;temp_count++)
{ temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
lcdlr_w=lcdlr_w?lcdlr_w:1;
lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0LCDLR1))))&DQLCDLR_MAX);
lcdlr_r=lcdlr_r?lcdlr_r:1;
lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
wr_reg(((uint64_t)(temp_reg)),(lcdlr_w));
wr_reg(((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0LCDLR1)),(lcdlr_r));
wr_reg(((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR1)),(lcdlr_r));
}
#else
for ( temp_count=2;temp_count<6;temp_count++) {
temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
lcdlr_w=lcdlr_w?lcdlr_w:1;
lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg)))>>8)&DQLCDLR_MAX);
lcdlr_r=lcdlr_r?lcdlr_r:1;
lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
}
#endif
for( temp_count=6;temp_count<8;temp_count++) {
temp_reg=(unsigned)(DDR1_PUB_ACLCDLR+((temp_count-6)<<2));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
lcdlr_w=lcdlr_w?lcdlr_w:1;
lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
if(temp_count==7)
lcdlr_w=lcdlr_w&ACBDLR_MAX;
wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
}
#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
for( temp_count=8;temp_count<12;temp_count++) {
temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-2));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
lcdlr_w=lcdlr_w?lcdlr_w:1;
lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR3-DDR1_PUB_DX0LCDLR1))))&DQLCDLR_MAX);
lcdlr_r=lcdlr_r?lcdlr_r:1;
lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
wr_reg(((uint64_t)(temp_reg)),(lcdlr_w));
wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR3-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR4-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
}
#else
for( temp_count=8;temp_count<12;temp_count++) {
temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-8));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&0xff);
lcdlr_w=lcdlr_w?lcdlr_w:1;
lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg)))>>8)&0xff);
lcdlr_r=lcdlr_r?lcdlr_r:1;
lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
}
#endif
#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))&(~(1<<0)));
wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))&(~(1<<29)));
wr_reg(DDR1_PUB_PGCR6, (rd_reg(DDR1_PUB_PGCR6))&(~(1<<0)));
wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))&(~(1<<29)));
#else
wr_reg(DDR0_PUB_PGCR1, (rd_reg(DDR0_PUB_PGCR1))&(~(1<<26)));
wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))&(~(1<<29)));
wr_reg(DDR1_PUB_PGCR1, (rd_reg(DDR1_PUB_PGCR1))&(~(1<<26)));
wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))&(~(1<<29)));
#endif
printf("\nend adjust lcdlr\n");
CLOSE_CHANNEL_A_PHY_CLK();
CLOSE_CHANNEL_B_PHY_CLK();
}
return 1;
}
U_BOOT_CMD(
ddr_test_tune_dqs_env, 30, 1, do_ddr_fine_tune_lcdlr_env1,
"do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3...",
"do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3... \n dcache off ? \n"
);
#endif
//*/
static void ddr_write(void *buff, unsigned int m_length)
{
unsigned int *p;
unsigned int i, j, n;
unsigned int m_len = m_length;
p = ( unsigned int *)buff;
while (m_len)
{
for (j=0;j<32;j++)
{
if (m_len >= 128)
n = 32;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
switch (i)
{
case 0:
case 9:
case 14:
case 25:
case 30:
*(p+i) = TDATA32F;
break;
case 1:
case 6:
case 8:
case 17:
case 22:
*(p+i) = 0;
break;
case 16:
case 23:
case 31:
*(p+i) = TDATA32A;
break;
case 7:
case 15:
case 24:
*(p+i) = TDATA325;
break;
case 2:
case 4:
case 10:
case 12:
case 19:
case 21:
case 27:
case 29:
*(p+i) = 1<<j;
break;
case 3:
case 5:
case 11:
case 13:
case 18:
case 20:
case 26:
case 28:
*(p+i) = ~(1<<j);
break;
}
}
if (m_len > 128)
{
m_len -= 128;
p += 32;
}
else
{
p += (m_len>>2);
m_len = 0;
break;
}
}
}
}
static void ddr_read(void *buff, unsigned int m_length)
{
unsigned int *p;
unsigned int i, j, n;
unsigned int m_len = m_length;
p = ( unsigned int *)buff;
while (m_len)
{
for (j=0;j<32;j++)
{
if (m_len >= 128)
n = 32;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
if ((error_outof_count_flag) && (error_count))
{
printf("Error data out of count");
m_len=0;
break;
}
switch (i)
{
case 0:
case 9:
case 14:
case 25:
case 30:
if (*(p+i) != TDATA32F)
{error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
}
break;
case 1:
case 6:
case 8:
case 17:
case 22:
if (*(p+i) != 0) {error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0);
}break;
case 16:
case 23:
case 31:
if (*(p+i) != TDATA32A) {error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A);
} break;
case 7:
case 15:
case 24:
if (*(p+i) != TDATA325) {error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325);
} break;
case 2:
case 4:
case 10:
case 12:
case 19:
case 21:
case 27:
case 29:
if (*(p+i) != 1<<j) {error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 1<<j);
} break;
case 3:
case 5:
case 11:
case 13:
case 18:
case 20:
case 26:
case 28:
if (*(p+i) != ~(1<<j)) {error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~(1<<j));
} break;
}
}
if (m_len > 128)
{
m_len -= 128;
p += 32;
}
else
{
p += (m_len>>2);
m_len = 0;
break;
}
}
}
}
static void ddr_write4(void *buff, unsigned int m_length)
{
unsigned int *p;
unsigned int i, j, n;
unsigned int m_len = m_length;
p = ( unsigned int *)buff;
while (m_len)
{
for (j=0;j<32;j++)
{
if (m_len >= 128)
n = 32;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
switch (i)
{
case 0:
case 1:
case 2:
case 3:
*(p+i) = 0xff00ff00;
break;
case 4:
case 5:
case 6:
case 7:
*(p+i) = ~0xff00ff00;
break;
case 8:
case 9:
case 10:
case 11:
*(p+i) = 0xaa55aa55;
break;
case 12:
case 13:
case 14:
case 15:
*(p+i) = ~0xaa55aa55;
break;
case 16:
case 17:
case 18:
case 19:
case 24:
case 25:
case 26:
case 27:
*(p+i) = 1<<j;
break;
case 20:
case 21:
case 22:
case 23:
case 28:
case 29:
case 30:
case 31:
*(p+i) = ~(1<<j);
break;
}
}
if (m_len > 128)
{
m_len -= 128;
p += 32;
}
else
{
p += (m_len>>2);
m_len = 0;
break;
}
}
}
}
static void ddr_read4(void *buff, unsigned int m_length)
{
unsigned int *p;
unsigned int i, j, n;
unsigned int m_len = m_length;
p = ( unsigned int *)buff;
while (m_len)
{
for (j=0;j<32;j++)
{
if (m_len >= 128)
n = 32;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
if ((error_outof_count_flag) && (error_count))
{
printf("Error data out of count");
m_len=0;
break;
}
switch (i)
{
case 0:
case 1:
case 2:
case 3: