| #ifndef _MPC8XX_IRQ_H |
| #define _MPC8XX_IRQ_H |
| |
| /* The MPC8xx cores have 16 possible interrupts. There are eight |
| * possible level sensitive interrupts assigned and generated internally |
| * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. |
| * There are eight external interrupts (IRQs) that can be configured |
| * as either level or edge sensitive. |
| * |
| * On some implementations, there is also the possibility of an 8259 |
| * through the PCI and PCI-ISA bridges. |
| * |
| * We don't support the 8259 (yet). |
| */ |
| #define NR_SIU_INTS 16 |
| #define NR_8259_INTS 0 |
| |
| #define NR_IRQS (NR_SIU_INTS + NR_8259_INTS) |
| |
| /* These values must be zero-based and map 1:1 with the SIU configuration. |
| * They are used throughout the 8xx I/O subsystem to generate |
| * interrupt masks, flags, and other control patterns. This is why the |
| * current kernel assumption of the 8259 as the base controller is such |
| * a pain in the butt. |
| */ |
| #define SIU_IRQ0 (0) /* Highest priority */ |
| #define SIU_LEVEL0 (1) |
| #define SIU_IRQ1 (2) |
| #define SIU_LEVEL1 (3) |
| #define SIU_IRQ2 (4) |
| #define SIU_LEVEL2 (5) |
| #define SIU_IRQ3 (6) |
| #define SIU_LEVEL3 (7) |
| #define SIU_IRQ4 (8) |
| #define SIU_LEVEL4 (9) |
| #define SIU_IRQ5 (10) |
| #define SIU_LEVEL5 (11) |
| #define SIU_IRQ6 (12) |
| #define SIU_LEVEL6 (13) |
| #define SIU_IRQ7 (14) |
| #define SIU_LEVEL7 (15) |
| |
| /* The internal interrupts we can configure as we see fit. |
| * My personal preference is CPM at level 2, which puts it above the |
| * MBX PCI/ISA/IDE interrupts. |
| */ |
| |
| #ifdef CFG_CPM_INTERRUPT |
| # define CPM_INTERRUPT CFG_CPM_INTERRUPT |
| #else |
| # define CPM_INTERRUPT SIU_LEVEL2 |
| #endif |
| |
| /* Some internal interrupt registers use an 8-bit mask for the interrupt |
| * level instead of a number. |
| */ |
| #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) |
| |
| #endif /* _MPC8XX_IRQ_H */ |
