| /* |
| * (C) Copyright 2002 |
| * Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
| * Keith Outwater, keith_outwater@mvis.com. |
| * |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| * |
| */ |
| |
| /* |
| * Virtex2 FPGA configuration support for the QUANTUM computer |
| */ |
| int fpga_boot(unsigned char *fpgadata, int size); |
| |
| #define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ |
| #define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ |
| #define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ |
| /* vim: set ts=4 sw=4 tw=78: */ |
