|  | /* | 
|  | * Bluestone board support | 
|  | * | 
|  | * Copyright (c) 2010, Applied Micro Circuits Corporation | 
|  | * Author: Tirumala R Marri <tmarri@apm.com> | 
|  | * | 
|  | * This program is free software; you can redistribute it and/or | 
|  | * modify it under the terms of the GNU General Public License as | 
|  | * published by the Free Software Foundation; either version 2 of | 
|  | * the License, or (at your option) any later version. | 
|  | * | 
|  | * This program is distributed in the hope that it will be useful, | 
|  | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 
|  | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the | 
|  | * GNU General Public License for more details. | 
|  | * | 
|  | * You should have received a copy of the GNU General Public License | 
|  | * along with this program; if not, write to the Free Software | 
|  | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 
|  | * MA 02111-1307 USA | 
|  | */ | 
|  |  | 
|  | #include <common.h> | 
|  | #include <asm/apm821xx.h> | 
|  | #include <libfdt.h> | 
|  | #include <fdt_support.h> | 
|  | #include <i2c.h> | 
|  | #include <asm/processor.h> | 
|  | #include <asm/io.h> | 
|  | #include <asm/mmu.h> | 
|  | #include <asm/ppc4xx-gpio.h> | 
|  |  | 
|  | int board_early_init_f(void) | 
|  | { | 
|  | /* | 
|  | * Setup the interrupt controller polarities, triggers, etc. | 
|  | */ | 
|  | mtdcr(UIC0SR, 0xffffffff);	/* clear all */ | 
|  | mtdcr(UIC0ER, 0x00000000);	/* disable all */ | 
|  | mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */ | 
|  | mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */ | 
|  | mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */ | 
|  | mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */ | 
|  | mtdcr(UIC0SR, 0xffffffff);	/* clear all */ | 
|  |  | 
|  | mtdcr(UIC1SR, 0xffffffff);	/* clear all */ | 
|  | mtdcr(UIC1ER, 0x00000000);	/* disable all */ | 
|  | mtdcr(UIC1CR, 0x00000000);	/* all non-critical */ | 
|  | mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */ | 
|  | mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */ | 
|  | mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */ | 
|  | mtdcr(UIC1SR, 0xffffffff);	/* clear all */ | 
|  |  | 
|  | mtdcr(UIC2SR, 0xffffffff);	/* clear all */ | 
|  | mtdcr(UIC2ER, 0x00000000);	/* disable all */ | 
|  | mtdcr(UIC2CR, 0x00000000);	/* all non-critical */ | 
|  | mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */ | 
|  | mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */ | 
|  | mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */ | 
|  | mtdcr(UIC2SR, 0xffffffff);	/* clear all */ | 
|  |  | 
|  | mtdcr(UIC3SR, 0xffffffff);	/* clear all */ | 
|  | mtdcr(UIC3ER, 0x00000000);	/* disable all */ | 
|  | mtdcr(UIC3CR, 0x00000000);	/* all non-critical */ | 
|  | mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */ | 
|  | mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */ | 
|  | mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */ | 
|  | mtdcr(UIC3SR, 0xffffffff);	/* clear all */ | 
|  |  | 
|  | /* | 
|  | * Configure PFC (Pin Function Control) registers | 
|  | * UART0: 2 pins | 
|  | */ | 
|  | mtsdr(SDR0_PFC1, 0x0000000); | 
|  |  | 
|  | return 0; | 
|  | } | 
|  |  | 
|  | int checkboard(void) | 
|  | { | 
|  | char *s = getenv("serial#"); | 
|  |  | 
|  | puts("Board: Bluestone Evaluation Board"); | 
|  |  | 
|  | if (s != NULL) { | 
|  | puts(", serial# "); | 
|  | puts(s); | 
|  | } | 
|  | putc('\n'); | 
|  |  | 
|  | return 0; | 
|  | } | 
|  |  | 
|  | int misc_init_r(void) | 
|  | { | 
|  | u32 sdr0_srst1 = 0; | 
|  |  | 
|  | /* Setup PLB4-AHB bridge based on the system address map */ | 
|  | mtdcr(AHB_TOP, 0x8000004B); | 
|  | mtdcr(AHB_BOT, 0x8000004B); | 
|  |  | 
|  | /* | 
|  | * The AHB Bridge core is held in reset after power-on or reset | 
|  | * so enable it now | 
|  | */ | 
|  | mfsdr(SDR0_SRST1, sdr0_srst1); | 
|  | sdr0_srst1 &= ~SDR0_SRST1_AHB; | 
|  | mtsdr(SDR0_SRST1, sdr0_srst1); | 
|  |  | 
|  | return 0; | 
|  | } |