|  | /* | 
|  | * (C) Copyright 2007 | 
|  | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | 
|  | * | 
|  | * See file CREDITS for list of people who contributed to this | 
|  | * project. | 
|  | * | 
|  | * This program is free software; you can redistribute it and/or | 
|  | * modify it under the terms of the GNU General Public License as | 
|  | * published by the Free Software Foundation; either version 2 of | 
|  | * the License, or (at your option) any later version. | 
|  | * | 
|  | * This program is distributed in the hope that it will be useful, | 
|  | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 
|  | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the | 
|  | * GNU General Public License for more details. | 
|  | * | 
|  | * You should have received a copy of the GNU General Public License | 
|  | * along with this program; if not, write to the Free Software | 
|  | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 
|  | * MA 02111-1307 USA | 
|  | */ | 
|  |  | 
|  | #include <common.h> | 
|  | #include <mpc5xxx.h> | 
|  | #include <pci.h> | 
|  |  | 
|  | #include "mt48lc16m16a2-75.h" | 
|  |  | 
|  | #ifndef CFG_RAMBOOT | 
|  | static void sdram_start (int hi_addr) | 
|  | { | 
|  | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | 
|  |  | 
|  | /* unlock mode register */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; | 
|  | __asm__ volatile ("sync"); | 
|  |  | 
|  | /* precharge all banks */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; | 
|  | __asm__ volatile ("sync"); | 
|  |  | 
|  | #if SDRAM_DDR | 
|  | /* set mode register: extended mode */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; | 
|  | __asm__ volatile ("sync"); | 
|  |  | 
|  | /* set mode register: reset DLL */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; | 
|  | __asm__ volatile ("sync"); | 
|  | #endif | 
|  |  | 
|  | /* precharge all banks */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; | 
|  | __asm__ volatile ("sync"); | 
|  |  | 
|  | /* auto refresh */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; | 
|  | __asm__ volatile ("sync"); | 
|  |  | 
|  | /* set mode register */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; | 
|  | __asm__ volatile ("sync"); | 
|  |  | 
|  | /* normal operation */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; | 
|  | __asm__ volatile ("sync"); | 
|  | } | 
|  | #endif | 
|  |  | 
|  | /* | 
|  | * ATTENTION: Although partially referenced initdram does NOT make real use | 
|  | *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE | 
|  | *            is something else than 0x00000000. | 
|  | */ | 
|  |  | 
|  | phys_size_t initdram (int board_type) | 
|  | { | 
|  | ulong dramsize = 0; | 
|  | ulong dramsize2 = 0; | 
|  | #ifndef CFG_RAMBOOT | 
|  | ulong test1, test2; | 
|  |  | 
|  | /* setup SDRAM chip selects */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */ | 
|  | __asm__ volatile ("sync"); | 
|  |  | 
|  | /* setup config registers */ | 
|  | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; | 
|  | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; | 
|  | __asm__ volatile ("sync"); | 
|  |  | 
|  | #if SDRAM_DDR && SDRAM_TAPDELAY | 
|  | /* set tap delay */ | 
|  | *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; | 
|  | __asm__ volatile ("sync"); | 
|  | #endif | 
|  |  | 
|  | /* find RAM size using SDRAM CS0 only */ | 
|  | sdram_start(0); | 
|  | test1 = (ulong )get_ram_size((long *)CFG_SDRAM_BASE, 0x10000000); | 
|  | sdram_start(1); | 
|  | test2 = (ulong )get_ram_size((long *)CFG_SDRAM_BASE, 0x10000000); | 
|  | if (test1 > test2) { | 
|  | sdram_start(0); | 
|  | dramsize = test1; | 
|  | } else { | 
|  | dramsize = test2; | 
|  | } | 
|  |  | 
|  | /* memory smaller than 1MB is impossible */ | 
|  | if (dramsize < (1 << 20)) { | 
|  | dramsize = 0; | 
|  | } | 
|  |  | 
|  | /* set SDRAM CS0 size according to the amount of RAM found */ | 
|  | if (dramsize > 0) { | 
|  | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; | 
|  | } else { | 
|  | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ | 
|  | } | 
|  |  | 
|  | #else /* CFG_RAMBOOT */ | 
|  |  | 
|  | /* retrieve size of memory connected to SDRAM CS0 */ | 
|  | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; | 
|  | if (dramsize >= 0x13) { | 
|  | dramsize = (1 << (dramsize - 0x13)) << 20; | 
|  | } else { | 
|  | dramsize = 0; | 
|  | } | 
|  |  | 
|  | /* retrieve size of memory connected to SDRAM CS1 */ | 
|  | dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; | 
|  | if (dramsize2 >= 0x13) { | 
|  | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; | 
|  | } else { | 
|  | dramsize2 = 0; | 
|  | } | 
|  |  | 
|  | #endif /* CFG_RAMBOOT */ | 
|  |  | 
|  | return dramsize + dramsize2; | 
|  | } | 
|  |  | 
|  | int checkboard (void) | 
|  | { | 
|  | puts ("Board: MUNICes\n"); | 
|  | return 0; | 
|  | } | 
|  |  | 
|  | #ifdef	CONFIG_PCI | 
|  | static struct pci_controller hose; | 
|  |  | 
|  | extern void pci_mpc5xxx_init(struct pci_controller *); | 
|  |  | 
|  | void pci_init_board(void) | 
|  | { | 
|  | pci_mpc5xxx_init(&hose); | 
|  | } | 
|  | #endif | 
|  |  | 
|  | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | 
|  | void | 
|  | ft_board_setup(void *blob, bd_t *bd) | 
|  | { | 
|  | ft_cpu_setup(blob, bd); | 
|  | } | 
|  | #endif |