| // ---------------------------------------------------------------------- |
| // regs.h header |
| // |
| // bus base define, update manually |
| // |
| // ---------------------------------------------------------------------- |
| // |
| #ifndef _BASE_REGISTER |
| #define _BASE_REGISTER |
| #define REG_BASE_AOBUS (0xFF800000L) |
| #define REG_BASE_PERIPHS (0xFF634000L) |
| #define REG_BASE_CBUS (0xFFD00000L) |
| #define REG_BASE_HIU (0xFF63C000L) |
| #define REG_BASE_VCBUS (0xFF900000L) |
| #define DMC_REG_BASE (0xFF638000L) |
| #define REG_BASE_DSI_HOST (0xFFD00000L)/* 0xFFD06000L*/ |
| |
| #endif /*_BASE_REGISTER*/ |
| |
| |
| #ifndef REG_OTHERS |
| #define REG_OTHERS |
| /* other regs */ |
| #define SPI_START_ADDR 0xFB000000 |
| #define P_SPI_START_ADDR (volatile unsigned int *)0xFB000000 |
| |
| /* name changed, need convert */ |
| #define AO_RTI_PIN_MUX_REG AO_RTI_PINMUX_REG0 |
| #define SEC_AO_RTI_PIN_MUX_REG SEC_AO_RTI_PINMUX_REG0 |
| #define P_AO_RTI_PIN_MUX_REG P_AO_RTI_PINMUX_REG0 |
| #define AO_RTI_PIN_MUX_REG2 AO_RTI_PINMUX_REG1 |
| #define SEC_AO_RTI_PIN_MUX_REG2 SEC_AO_RTI_PINMUX_REG1 |
| #define P_AO_RTI_PIN_MUX_REG2 P_AO_RTI_PINMUX_REG1 |
| |
| #endif /*REG_OTHERS*/ |
| |
| // ---------------------------------------------------------------------- |
| // This file is automatically generated for the SW team: |
| // |
| // From three scripts:./create_headers_from_register_map_h.pl, create_headers_from_secure_apb4_h.pl, create_headers_for_mmc_register_map_h.pl |
| // |
| // DO NOT EDIT!!!!! |
| // ---------------------------------------------------------------------- |
| // |
| |
| #ifndef REGS_H |
| #define REGS_H |
| |
| |
| // |
| // Reading file: ./register_map.h |
| // |
| // synopsys translate_off |
| // synopsys translate_on |
| // |
| // Reading file: periphs_reg.h |
| // |
| // $periphs/rtl/periphs_core register defines for the |
| // APB bus |
| // ------------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: UART0_CBUS_BASE = 0x90 |
| // ----------------------------------------------- |
| #define UART0_WFIFO (0x9000) |
| #define P_UART0_WFIFO (volatile uint32_t *)((0x9000 << 2) + 0xffd00000) |
| #define UART0_RFIFO (0x9001) |
| #define P_UART0_RFIFO (volatile uint32_t *)((0x9001 << 2) + 0xffd00000) |
| #define UART0_CONTROL (0x9002) |
| #define P_UART0_CONTROL (volatile uint32_t *)((0x9002 << 2) + 0xffd00000) |
| #define UART0_STATUS (0x9003) |
| #define P_UART0_STATUS (volatile uint32_t *)((0x9003 << 2) + 0xffd00000) |
| #define UART0_MISC (0x9004) |
| #define P_UART0_MISC (volatile uint32_t *)((0x9004 << 2) + 0xffd00000) |
| #define UART0_REG5 (0x9005) |
| #define P_UART0_REG5 (volatile uint32_t *)((0x9005 << 2) + 0xffd00000) |
| // ------------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: UART1_CBUS_BASE = 0x8c |
| // ----------------------------------------------- |
| #define UART1_WFIFO (0x8c00) |
| #define P_UART1_WFIFO (volatile uint32_t *)((0x8c00 << 2) + 0xffd00000) |
| #define UART1_RFIFO (0x8c01) |
| #define P_UART1_RFIFO (volatile uint32_t *)((0x8c01 << 2) + 0xffd00000) |
| #define UART1_CONTROL (0x8c02) |
| #define P_UART1_CONTROL (volatile uint32_t *)((0x8c02 << 2) + 0xffd00000) |
| #define UART1_STATUS (0x8c03) |
| #define P_UART1_STATUS (volatile uint32_t *)((0x8c03 << 2) + 0xffd00000) |
| #define UART1_MISC (0x8c04) |
| #define P_UART1_MISC (volatile uint32_t *)((0x8c04 << 2) + 0xffd00000) |
| #define UART1_REG5 (0x8c05) |
| #define P_UART1_REG5 (volatile uint32_t *)((0x8c05 << 2) + 0xffd00000) |
| // ------------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: I2C_M_0_CBUS_BASE = 0x7c |
| // ----------------------------------------------- |
| #define I2C_M_0_CONTROL_REG (0x7c00) |
| #define P_I2C_M_0_CONTROL_REG (volatile uint32_t *)((0x7c00 << 2) + 0xffd00000) |
| #define I2C_M_MANUAL_SDA_I 26 |
| #define I2C_M_MANUAL_SCL_I 25 |
| #define I2C_M_MANUAL_SDA_O 24 |
| #define I2C_M_MANUAL_SCL_O 23 |
| #define I2C_M_MANUAL_EN 22 |
| #define I2C_M_DELAY_MSB 21 |
| #define I2C_M_DELAY_LSB 12 |
| #define I2C_M_DATA_CNT_MSB 11 |
| #define I2C_M_DATA_CNT_LSB 8 |
| #define I2C_M_CURR_TOKEN_MSB 7 |
| #define I2C_M_CURR_TOKEN_LSB 4 |
| #define I2C_M_ERROR 3 |
| #define I2C_M_STATUS 2 |
| #define I2C_M_ACK_IGNORE 1 |
| #define I2C_M_START 0 |
| #define I2C_M_0_SLAVE_ADDR (0x7c01) |
| #define P_I2C_M_0_SLAVE_ADDR (volatile uint32_t *)((0x7c01 << 2) + 0xffd00000) |
| #define I2C_M_0_TOKEN_LIST0 (0x7c02) |
| #define P_I2C_M_0_TOKEN_LIST0 (volatile uint32_t *)((0x7c02 << 2) + 0xffd00000) |
| #define I2C_M_0_TOKEN_LIST1 (0x7c03) |
| #define P_I2C_M_0_TOKEN_LIST1 (volatile uint32_t *)((0x7c03 << 2) + 0xffd00000) |
| #define I2C_M_0_WDATA_REG0 (0x7c04) |
| #define P_I2C_M_0_WDATA_REG0 (volatile uint32_t *)((0x7c04 << 2) + 0xffd00000) |
| #define I2C_M_0_WDATA_REG1 (0x7c05) |
| #define P_I2C_M_0_WDATA_REG1 (volatile uint32_t *)((0x7c05 << 2) + 0xffd00000) |
| #define I2C_M_0_RDATA_REG0 (0x7c06) |
| #define P_I2C_M_0_RDATA_REG0 (volatile uint32_t *)((0x7c06 << 2) + 0xffd00000) |
| #define I2C_M_0_RDATA_REG1 (0x7c07) |
| #define P_I2C_M_0_RDATA_REG1 (volatile uint32_t *)((0x7c07 << 2) + 0xffd00000) |
| #define I2C_M_0_TIMEOUT_TH (0x7c08) |
| #define P_I2C_M_0_TIMEOUT_TH (volatile uint32_t *)((0x7c08 << 2) + 0xffd00000) |
| // ----------------------------------------------- |
| // CBUS_BASE: I2C_M_1_CBUS_BASE = 0x78 |
| // ----------------------------------------------- |
| #define I2C_M_1_CONTROL_REG (0x7800) |
| #define P_I2C_M_1_CONTROL_REG (volatile uint32_t *)((0x7800 << 2) + 0xffd00000) |
| #define I2C_M_1_SLAVE_ADDR (0x7801) |
| #define P_I2C_M_1_SLAVE_ADDR (volatile uint32_t *)((0x7801 << 2) + 0xffd00000) |
| #define I2C_M_1_TOKEN_LIST0 (0x7802) |
| #define P_I2C_M_1_TOKEN_LIST0 (volatile uint32_t *)((0x7802 << 2) + 0xffd00000) |
| #define I2C_M_1_TOKEN_LIST1 (0x7803) |
| #define P_I2C_M_1_TOKEN_LIST1 (volatile uint32_t *)((0x7803 << 2) + 0xffd00000) |
| #define I2C_M_1_WDATA_REG0 (0x7804) |
| #define P_I2C_M_1_WDATA_REG0 (volatile uint32_t *)((0x7804 << 2) + 0xffd00000) |
| #define I2C_M_1_WDATA_REG1 (0x7805) |
| #define P_I2C_M_1_WDATA_REG1 (volatile uint32_t *)((0x7805 << 2) + 0xffd00000) |
| #define I2C_M_1_RDATA_REG0 (0x7806) |
| #define P_I2C_M_1_RDATA_REG0 (volatile uint32_t *)((0x7806 << 2) + 0xffd00000) |
| #define I2C_M_1_RDATA_REG1 (0x7807) |
| #define P_I2C_M_1_RDATA_REG1 (volatile uint32_t *)((0x7807 << 2) + 0xffd00000) |
| #define I2C_M_1_TIMEOUT_TH (0x7808) |
| #define P_I2C_M_1_TIMEOUT_TH (volatile uint32_t *)((0x7808 << 2) + 0xffd00000) |
| // ------------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: I2C_M_2_CBUS_BASE = 0x74 |
| // ----------------------------------------------- |
| #define I2C_M_2_CONTROL_REG (0x7400) |
| #define P_I2C_M_2_CONTROL_REG (volatile uint32_t *)((0x7400 << 2) + 0xffd00000) |
| #define I2C_M_2_SLAVE_ADDR (0x7401) |
| #define P_I2C_M_2_SLAVE_ADDR (volatile uint32_t *)((0x7401 << 2) + 0xffd00000) |
| #define I2C_M_2_TOKEN_LIST0 (0x7402) |
| #define P_I2C_M_2_TOKEN_LIST0 (volatile uint32_t *)((0x7402 << 2) + 0xffd00000) |
| #define I2C_M_2_TOKEN_LIST1 (0x7403) |
| #define P_I2C_M_2_TOKEN_LIST1 (volatile uint32_t *)((0x7403 << 2) + 0xffd00000) |
| #define I2C_M_2_WDATA_REG0 (0x7404) |
| #define P_I2C_M_2_WDATA_REG0 (volatile uint32_t *)((0x7404 << 2) + 0xffd00000) |
| #define I2C_M_2_WDATA_REG1 (0x7405) |
| #define P_I2C_M_2_WDATA_REG1 (volatile uint32_t *)((0x7405 << 2) + 0xffd00000) |
| #define I2C_M_2_RDATA_REG0 (0x7406) |
| #define P_I2C_M_2_RDATA_REG0 (volatile uint32_t *)((0x7406 << 2) + 0xffd00000) |
| #define I2C_M_2_RDATA_REG1 (0x7407) |
| #define P_I2C_M_2_RDATA_REG1 (volatile uint32_t *)((0x7407 << 2) + 0xffd00000) |
| #define I2C_M_2_TIMEOUT_TH (0x7408) |
| #define P_I2C_M_2_TIMEOUT_TH (volatile uint32_t *)((0x7408 << 2) + 0xffd00000) |
| // ------------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: I2C_M_3_CBUS_BASE = 0x70 |
| // ----------------------------------------------- |
| #define I2C_M_3_CONTROL_REG (0x7000) |
| #define P_I2C_M_3_CONTROL_REG (volatile uint32_t *)((0x7000 << 2) + 0xffd00000) |
| #define I2C_M_3_SLAVE_ADDR (0x7001) |
| #define P_I2C_M_3_SLAVE_ADDR (volatile uint32_t *)((0x7001 << 2) + 0xffd00000) |
| #define I2C_M_3_TOKEN_LIST0 (0x7002) |
| #define P_I2C_M_3_TOKEN_LIST0 (volatile uint32_t *)((0x7002 << 2) + 0xffd00000) |
| #define I2C_M_3_TOKEN_LIST1 (0x7003) |
| #define P_I2C_M_3_TOKEN_LIST1 (volatile uint32_t *)((0x7003 << 2) + 0xffd00000) |
| #define I2C_M_3_WDATA_REG0 (0x7004) |
| #define P_I2C_M_3_WDATA_REG0 (volatile uint32_t *)((0x7004 << 2) + 0xffd00000) |
| #define I2C_M_3_WDATA_REG1 (0x7005) |
| #define P_I2C_M_3_WDATA_REG1 (volatile uint32_t *)((0x7005 << 2) + 0xffd00000) |
| #define I2C_M_3_RDATA_REG0 (0x7006) |
| #define P_I2C_M_3_RDATA_REG0 (volatile uint32_t *)((0x7006 << 2) + 0xffd00000) |
| #define I2C_M_3_RDATA_REG1 (0x7007) |
| #define P_I2C_M_3_RDATA_REG1 (volatile uint32_t *)((0x7007 << 2) + 0xffd00000) |
| #define I2C_M_3_TIMEOUT_TH (0x7008) |
| #define P_I2C_M_3_TIMEOUT_TH (volatile uint32_t *)((0x7008 << 2) + 0xffd00000) |
| // ------------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: PWM_AB_CBUS_BASE = 0x6c |
| // ----------------------------------------------- |
| #define PWM_PWM_A (0x6c00) |
| #define P_PWM_PWM_A (volatile uint32_t *)((0x6c00 << 2) + 0xffd00000) |
| #define PWM_PWM_B (0x6c01) |
| #define P_PWM_PWM_B (volatile uint32_t *)((0x6c01 << 2) + 0xffd00000) |
| #define PWM_MISC_REG_AB (0x6c02) |
| #define P_PWM_MISC_REG_AB (volatile uint32_t *)((0x6c02 << 2) + 0xffd00000) |
| #define PWM_DELTA_SIGMA_AB (0x6c03) |
| #define P_PWM_DELTA_SIGMA_AB (volatile uint32_t *)((0x6c03 << 2) + 0xffd00000) |
| #define PWM_TIME_AB (0x6c04) |
| #define P_PWM_TIME_AB (volatile uint32_t *)((0x6c04 << 2) + 0xffd00000) |
| #define PWM_A2 (0x6c05) |
| #define P_PWM_A2 (volatile uint32_t *)((0x6c05 << 2) + 0xffd00000) |
| #define PWM_B2 (0x6c06) |
| #define P_PWM_B2 (volatile uint32_t *)((0x6c06 << 2) + 0xffd00000) |
| #define PWM_BLINK_AB (0x6c07) |
| #define P_PWM_BLINK_AB (volatile uint32_t *)((0x6c07 << 2) + 0xffd00000) |
| // ------------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: PWM_CD_CBUS_BASE = 0x68 |
| // ----------------------------------------------- |
| #define PWM_PWM_C (0x6800) |
| #define P_PWM_PWM_C (volatile uint32_t *)((0x6800 << 2) + 0xffd00000) |
| #define PWM_PWM_D (0x6801) |
| #define P_PWM_PWM_D (volatile uint32_t *)((0x6801 << 2) + 0xffd00000) |
| #define PWM_MISC_REG_CD (0x6802) |
| #define P_PWM_MISC_REG_CD (volatile uint32_t *)((0x6802 << 2) + 0xffd00000) |
| #define PWM_DELTA_SIGMA_CD (0x6803) |
| #define P_PWM_DELTA_SIGMA_CD (volatile uint32_t *)((0x6803 << 2) + 0xffd00000) |
| #define PWM_TIME_CD (0x6804) |
| #define P_PWM_TIME_CD (volatile uint32_t *)((0x6804 << 2) + 0xffd00000) |
| #define PWM_C2 (0x6805) |
| #define P_PWM_C2 (volatile uint32_t *)((0x6805 << 2) + 0xffd00000) |
| #define PWM_D2 (0x6806) |
| #define P_PWM_D2 (volatile uint32_t *)((0x6806 << 2) + 0xffd00000) |
| #define PWM_BLINK_CD (0x6807) |
| #define P_PWM_BLINK_CD (volatile uint32_t *)((0x6807 << 2) + 0xffd00000) |
| // ------------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: MSR_CLK_CBUS_BASE = 0x60 |
| // ----------------------------------------------- |
| #define MSR_CLK_DUTY (0x6000) |
| #define P_MSR_CLK_DUTY (volatile uint32_t *)((0x6000 << 2) + 0xffd00000) |
| #define MSR_CLK_REG0 (0x6001) |
| #define P_MSR_CLK_REG0 (volatile uint32_t *)((0x6001 << 2) + 0xffd00000) |
| #define MSR_CLK_REG1 (0x6002) |
| #define P_MSR_CLK_REG1 (volatile uint32_t *)((0x6002 << 2) + 0xffd00000) |
| #define MSR_CLK_REG2 (0x6003) |
| #define P_MSR_CLK_REG2 (volatile uint32_t *)((0x6003 << 2) + 0xffd00000) |
| #define MSR_CLK_REG3 (0x6004) |
| #define P_MSR_CLK_REG3 (volatile uint32_t *)((0x6004 << 2) + 0xffd00000) |
| #define MSR_CLK_REG4 (0x6005) |
| #define P_MSR_CLK_REG4 (volatile uint32_t *)((0x6005 << 2) + 0xffd00000) |
| #define MSR_CLK_REG5 (0x6006) |
| #define P_MSR_CLK_REG5 (volatile uint32_t *)((0x6006 << 2) + 0xffd00000) |
| // ------------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: SPIFC_CBUS_BASE = 0x50 |
| // ----------------------------------------------- |
| #define SPI_FLASH_CMD (0x5000) |
| #define P_SPI_FLASH_CMD (volatile uint32_t *)((0x5000 << 2) + 0xffd00000) |
| #define SPI_FLASH_ADDR (0x5001) |
| #define P_SPI_FLASH_ADDR (volatile uint32_t *)((0x5001 << 2) + 0xffd00000) |
| #define SPI_FLASH_CTRL (0x5002) |
| #define P_SPI_FLASH_CTRL (volatile uint32_t *)((0x5002 << 2) + 0xffd00000) |
| #define SPI_FLASH_CTRL1 (0x5003) |
| #define P_SPI_FLASH_CTRL1 (volatile uint32_t *)((0x5003 << 2) + 0xffd00000) |
| #define SPI_FLASH_STATUS (0x5004) |
| #define P_SPI_FLASH_STATUS (volatile uint32_t *)((0x5004 << 2) + 0xffd00000) |
| #define SPI_FLASH_CTRL2 (0x5005) |
| #define P_SPI_FLASH_CTRL2 (volatile uint32_t *)((0x5005 << 2) + 0xffd00000) |
| #define SPI_FLASH_CLOCK (0x5006) |
| #define P_SPI_FLASH_CLOCK (volatile uint32_t *)((0x5006 << 2) + 0xffd00000) |
| #define SPI_FLASH_USER (0x5007) |
| #define P_SPI_FLASH_USER (volatile uint32_t *)((0x5007 << 2) + 0xffd00000) |
| #define SPI_FLASH_USER1 (0x5008) |
| #define P_SPI_FLASH_USER1 (volatile uint32_t *)((0x5008 << 2) + 0xffd00000) |
| #define SPI_FLASH_USER2 (0x5009) |
| #define P_SPI_FLASH_USER2 (volatile uint32_t *)((0x5009 << 2) + 0xffd00000) |
| #define SPI_FLASH_USER3 (0x500a) |
| #define P_SPI_FLASH_USER3 (volatile uint32_t *)((0x500a << 2) + 0xffd00000) |
| #define SPI_FLASH_USER4 (0x500b) |
| #define P_SPI_FLASH_USER4 (volatile uint32_t *)((0x500b << 2) + 0xffd00000) |
| #define SPI_FLASH_SLAVE (0x500c) |
| #define P_SPI_FLASH_SLAVE (volatile uint32_t *)((0x500c << 2) + 0xffd00000) |
| #define SPI_FLASH_SLAVE1 (0x500d) |
| #define P_SPI_FLASH_SLAVE1 (volatile uint32_t *)((0x500d << 2) + 0xffd00000) |
| #define SPI_FLASH_SLAVE2 (0x500e) |
| #define P_SPI_FLASH_SLAVE2 (volatile uint32_t *)((0x500e << 2) + 0xffd00000) |
| #define SPI_FLASH_SLAVE3 (0x500f) |
| #define P_SPI_FLASH_SLAVE3 (volatile uint32_t *)((0x500f << 2) + 0xffd00000) |
| #define SPI_FLASH_C0 (0x5010) |
| #define P_SPI_FLASH_C0 (volatile uint32_t *)((0x5010 << 2) + 0xffd00000) |
| #define SPI_FLASH_C1 (0x5011) |
| #define P_SPI_FLASH_C1 (volatile uint32_t *)((0x5011 << 2) + 0xffd00000) |
| #define SPI_FLASH_C2 (0x5012) |
| #define P_SPI_FLASH_C2 (volatile uint32_t *)((0x5012 << 2) + 0xffd00000) |
| #define SPI_FLASH_C3 (0x5013) |
| #define P_SPI_FLASH_C3 (volatile uint32_t *)((0x5013 << 2) + 0xffd00000) |
| #define SPI_FLASH_C4 (0x5014) |
| #define P_SPI_FLASH_C4 (volatile uint32_t *)((0x5014 << 2) + 0xffd00000) |
| #define SPI_FLASH_C5 (0x5015) |
| #define P_SPI_FLASH_C5 (volatile uint32_t *)((0x5015 << 2) + 0xffd00000) |
| #define SPI_FLASH_C6 (0x5016) |
| #define P_SPI_FLASH_C6 (volatile uint32_t *)((0x5016 << 2) + 0xffd00000) |
| #define SPI_FLASH_C7 (0x5017) |
| #define P_SPI_FLASH_C7 (volatile uint32_t *)((0x5017 << 2) + 0xffd00000) |
| #define SPI_FLASH_B8 (0x5018) |
| #define P_SPI_FLASH_B8 (volatile uint32_t *)((0x5018 << 2) + 0xffd00000) |
| #define SPI_FLASH_B9 (0x5019) |
| #define P_SPI_FLASH_B9 (volatile uint32_t *)((0x5019 << 2) + 0xffd00000) |
| #define SPI_FLASH_B10 (0x501a) |
| #define P_SPI_FLASH_B10 (volatile uint32_t *)((0x501a << 2) + 0xffd00000) |
| #define SPI_FLASH_B11 (0x501b) |
| #define P_SPI_FLASH_B11 (volatile uint32_t *)((0x501b << 2) + 0xffd00000) |
| #define SPI_FLASH_B12 (0x501c) |
| #define P_SPI_FLASH_B12 (volatile uint32_t *)((0x501c << 2) + 0xffd00000) |
| #define SPI_FLASH_B13 (0x501d) |
| #define P_SPI_FLASH_B13 (volatile uint32_t *)((0x501d << 2) + 0xffd00000) |
| #define SPI_FLASH_B14 (0x501e) |
| #define P_SPI_FLASH_B14 (volatile uint32_t *)((0x501e << 2) + 0xffd00000) |
| #define SPI_FLASH_B15 (0x501f) |
| #define P_SPI_FLASH_B15 (volatile uint32_t *)((0x501f << 2) + 0xffd00000) |
| // ------------------------------------------------------------------------------------ |
| //spicc 0 |
| // ----------------------------------------------- |
| // CBUS_BASE: SPICC0_CBUS_BASE = 0x4c |
| // ----------------------------------------------- |
| #define SPICC0_RXDATA (0x4c00) |
| #define P_SPICC0_RXDATA (volatile uint32_t *)((0x4c00 << 2) + 0xffd00000) |
| #define SPICC0_TXDATA (0x4c01) |
| #define P_SPICC0_TXDATA (volatile uint32_t *)((0x4c01 << 2) + 0xffd00000) |
| #define SPICC0_CONREG (0x4c02) |
| #define P_SPICC0_CONREG (volatile uint32_t *)((0x4c02 << 2) + 0xffd00000) |
| #define SPICC0_INTREG (0x4c03) |
| #define P_SPICC0_INTREG (volatile uint32_t *)((0x4c03 << 2) + 0xffd00000) |
| #define SPICC0_DMAREG (0x4c04) |
| #define P_SPICC0_DMAREG (volatile uint32_t *)((0x4c04 << 2) + 0xffd00000) |
| #define SPICC0_STATREG (0x4c05) |
| #define P_SPICC0_STATREG (volatile uint32_t *)((0x4c05 << 2) + 0xffd00000) |
| #define SPICC0_PERIODREG (0x4c06) |
| #define P_SPICC0_PERIODREG (volatile uint32_t *)((0x4c06 << 2) + 0xffd00000) |
| #define SPICC0_TESTREG (0x4c07) |
| #define P_SPICC0_TESTREG (volatile uint32_t *)((0x4c07 << 2) + 0xffd00000) |
| #define SPICC0_DRADDR (0x4c08) |
| #define P_SPICC0_DRADDR (volatile uint32_t *)((0x4c08 << 2) + 0xffd00000) |
| #define SPICC0_DWADDR (0x4c09) |
| #define P_SPICC0_DWADDR (volatile uint32_t *)((0x4c09 << 2) + 0xffd00000) |
| #define SPICC0_LD_CNTL0 (0x4c0a) |
| #define P_SPICC0_LD_CNTL0 (volatile uint32_t *)((0x4c0a << 2) + 0xffd00000) |
| #define SPICC0_LD_CNTL1 (0x4c0b) |
| #define P_SPICC0_LD_CNTL1 (volatile uint32_t *)((0x4c0b << 2) + 0xffd00000) |
| #define SPICC0_LD_RADDR (0x4c0c) |
| #define P_SPICC0_LD_RADDR (volatile uint32_t *)((0x4c0c << 2) + 0xffd00000) |
| #define SPICC0_LD_WADDR (0x4c0d) |
| #define P_SPICC0_LD_WADDR (volatile uint32_t *)((0x4c0d << 2) + 0xffd00000) |
| #define SPICC0_ENHANCE_CNTL (0x4c0e) |
| #define P_SPICC0_ENHANCE_CNTL (volatile uint32_t *)((0x4c0e << 2) + 0xffd00000) |
| #define SPICC0_ENHANCE_CNTL1 (0x4c0f) |
| #define P_SPICC0_ENHANCE_CNTL1 (volatile uint32_t *)((0x4c0f << 2) + 0xffd00000) |
| // ------------------------------------------------------------------------------------ |
| //spicc 1 |
| // ----------------------------------------------- |
| // CBUS_BASE: SPICC1_CBUS_BASE = 0x54 |
| // ----------------------------------------------- |
| #define SPICC1_RXDATA (0x5400) |
| #define P_SPICC1_RXDATA (volatile uint32_t *)((0x5400 << 2) + 0xffd00000) |
| #define SPICC1_TXDATA (0x5401) |
| #define P_SPICC1_TXDATA (volatile uint32_t *)((0x5401 << 2) + 0xffd00000) |
| #define SPICC1_CONREG (0x5402) |
| #define P_SPICC1_CONREG (volatile uint32_t *)((0x5402 << 2) + 0xffd00000) |
| #define SPICC1_INTREG (0x5403) |
| #define P_SPICC1_INTREG (volatile uint32_t *)((0x5403 << 2) + 0xffd00000) |
| #define SPICC1_DMAREG (0x5404) |
| #define P_SPICC1_DMAREG (volatile uint32_t *)((0x5404 << 2) + 0xffd00000) |
| #define SPICC1_STATREG (0x5405) |
| #define P_SPICC1_STATREG (volatile uint32_t *)((0x5405 << 2) + 0xffd00000) |
| #define SPICC1_PERIODREG (0x5406) |
| #define P_SPICC1_PERIODREG (volatile uint32_t *)((0x5406 << 2) + 0xffd00000) |
| #define SPICC1_TESTREG (0x5407) |
| #define P_SPICC1_TESTREG (volatile uint32_t *)((0x5407 << 2) + 0xffd00000) |
| #define SPICC1_DRADDR (0x5408) |
| #define P_SPICC1_DRADDR (volatile uint32_t *)((0x5408 << 2) + 0xffd00000) |
| #define SPICC1_DWADDR (0x5409) |
| #define P_SPICC1_DWADDR (volatile uint32_t *)((0x5409 << 2) + 0xffd00000) |
| #define SPICC1_LD_CNTL0 (0x540a) |
| #define P_SPICC1_LD_CNTL0 (volatile uint32_t *)((0x540a << 2) + 0xffd00000) |
| #define SPICC1_LD_CNTL1 (0x540b) |
| #define P_SPICC1_LD_CNTL1 (volatile uint32_t *)((0x540b << 2) + 0xffd00000) |
| #define SPICC1_LD_RADDR (0x540c) |
| #define P_SPICC1_LD_RADDR (volatile uint32_t *)((0x540c << 2) + 0xffd00000) |
| #define SPICC1_LD_WADDR (0x540d) |
| #define P_SPICC1_LD_WADDR (volatile uint32_t *)((0x540d << 2) + 0xffd00000) |
| #define SPICC1_ENHANCE_CNTL (0x540e) |
| #define P_SPICC1_ENHANCE_CNTL (volatile uint32_t *)((0x540e << 2) + 0xffd00000) |
| #define SPICC1_ENHANCE_CNTL1 (0x540f) |
| #define P_SPICC1_ENHANCE_CNTL1 (volatile uint32_t *)((0x540f << 2) + 0xffd00000) |
| // |
| // |
| // Closing file: periphs_reg.h |
| // |
| // |
| // Reading file: isa_reg.h |
| // |
| // $isa/rtl/isa_core register defines for the APB bus |
| // CBUS base slave address |
| // ----------------------------------------------- |
| // CBUS_BASE: ISA_CBUS_BASE = 0x3c |
| // ----------------------------------------------- |
| // Up to 256 registers for this base |
| #define ISA_DEBUG_REG0 (0x3c00) |
| #define P_ISA_DEBUG_REG0 (volatile uint32_t *)((0x3c00 << 2) + 0xffd00000) |
| #define ISA_DEBUG_REG1 (0x3c01) |
| #define P_ISA_DEBUG_REG1 (volatile uint32_t *)((0x3c01 << 2) + 0xffd00000) |
| #define ISA_DEBUG_REG2 (0x3c02) |
| #define P_ISA_DEBUG_REG2 (volatile uint32_t *)((0x3c02 << 2) + 0xffd00000) |
| #define ISA_DEBUG_REG3 (0x3c03) |
| #define P_ISA_DEBUG_REG3 (volatile uint32_t *)((0x3c03 << 2) + 0xffd00000) |
| #define ISA_PLL_CLK_SIM0 (0x3c08) |
| #define P_ISA_PLL_CLK_SIM0 (volatile uint32_t *)((0x3c08 << 2) + 0xffd00000) |
| #define ISA_CNTL_REG0 (0x3c09) |
| #define P_ISA_CNTL_REG0 (volatile uint32_t *)((0x3c09 << 2) + 0xffd00000) |
| // ----------------------------------------------------------- |
| #define AO_CPU_IRQ_IN0_INTR_STAT (0x3c10) |
| #define P_AO_CPU_IRQ_IN0_INTR_STAT (volatile uint32_t *)((0x3c10 << 2) + 0xffd00000) |
| #define AO_CPU_IRQ_IN0_INTR_STAT_CLR (0x3c11) |
| #define P_AO_CPU_IRQ_IN0_INTR_STAT_CLR (volatile uint32_t *)((0x3c11 << 2) + 0xffd00000) |
| #define AO_CPU_IRQ_IN0_INTR_MASK (0x3c12) |
| #define P_AO_CPU_IRQ_IN0_INTR_MASK (volatile uint32_t *)((0x3c12 << 2) + 0xffd00000) |
| #define AO_CPU_IRQ_IN0_INTR_FIRQ_SEL (0x3c13) |
| #define P_AO_CPU_IRQ_IN0_INTR_FIRQ_SEL (volatile uint32_t *)((0x3c13 << 2) + 0xffd00000) |
| #define GPIO_INTR_EDGE_POL (0x3c20) |
| #define P_GPIO_INTR_EDGE_POL (volatile uint32_t *)((0x3c20 << 2) + 0xffd00000) |
| #define GPIO_INTR_GPIO_SEL0 (0x3c21) |
| #define P_GPIO_INTR_GPIO_SEL0 (volatile uint32_t *)((0x3c21 << 2) + 0xffd00000) |
| #define GPIO_INTR_GPIO_SEL1 (0x3c22) |
| #define P_GPIO_INTR_GPIO_SEL1 (volatile uint32_t *)((0x3c22 << 2) + 0xffd00000) |
| #define GPIO_INTR_FILTER_SEL0 (0x3c23) |
| #define P_GPIO_INTR_FILTER_SEL0 (volatile uint32_t *)((0x3c23 << 2) + 0xffd00000) |
| // `define GLOBAL_INTR_DISABLE 8'h24 never used |
| #define MEDIA_CPU_INTR_STAT (0x3c28) |
| #define P_MEDIA_CPU_INTR_STAT (volatile uint32_t *)((0x3c28 << 2) + 0xffd00000) |
| #define MEDIA_CPU_INTR_STAT_CLR (0x3c29) |
| #define P_MEDIA_CPU_INTR_STAT_CLR (volatile uint32_t *)((0x3c29 << 2) + 0xffd00000) |
| #define MEDIA_CPU_INTR_MASK (0x3c2a) |
| #define P_MEDIA_CPU_INTR_MASK (volatile uint32_t *)((0x3c2a << 2) + 0xffd00000) |
| #define MEDIA_CPU_INTR_FIRQ_SEL (0x3c2b) |
| #define P_MEDIA_CPU_INTR_FIRQ_SEL (volatile uint32_t *)((0x3c2b << 2) + 0xffd00000) |
| // ----------------------------------------------------------- |
| #define ISA_BIST_REG0 (0x3c30) |
| #define P_ISA_BIST_REG0 (volatile uint32_t *)((0x3c30 << 2) + 0xffd00000) |
| #define ISA_BIST_REG1 (0x3c31) |
| #define P_ISA_BIST_REG1 (volatile uint32_t *)((0x3c31 << 2) + 0xffd00000) |
| // ----------------------------------------------------------- |
| #define WATCHDOG_CNTL (0x3c34) |
| #define P_WATCHDOG_CNTL (volatile uint32_t *)((0x3c34 << 2) + 0xffd00000) |
| #define WATCHDOG_CNTL1 (0x3c35) |
| #define P_WATCHDOG_CNTL1 (volatile uint32_t *)((0x3c35 << 2) + 0xffd00000) |
| #define WATCHDOG_TCNT (0x3c36) |
| #define P_WATCHDOG_TCNT (volatile uint32_t *)((0x3c36 << 2) + 0xffd00000) |
| #define WATCHDOG_RESET (0x3c37) |
| #define P_WATCHDOG_RESET (volatile uint32_t *)((0x3c37 << 2) + 0xffd00000) |
| // ----------------------------------------------------------- |
| #define AHB_ARBITER_REG (0x3c42) |
| #define P_AHB_ARBITER_REG (volatile uint32_t *)((0x3c42 << 2) + 0xffd00000) |
| #define AHB_ARBDEC_REG (0x3c43) |
| #define P_AHB_ARBDEC_REG (volatile uint32_t *)((0x3c43 << 2) + 0xffd00000) |
| #define AHB_ARBITER2_REG (0x3c4a) |
| #define P_AHB_ARBITER2_REG (volatile uint32_t *)((0x3c4a << 2) + 0xffd00000) |
| #define DEVICE_MMCP_CNTL (0x3c4b) |
| #define P_DEVICE_MMCP_CNTL (volatile uint32_t *)((0x3c4b << 2) + 0xffd00000) |
| #define AUDIO_MMCP_CNTL (0x3c4c) |
| #define P_AUDIO_MMCP_CNTL (volatile uint32_t *)((0x3c4c << 2) + 0xffd00000) |
| // ----------------------------------------------------------- |
| #define ISA_TIMER_MUX (0x3c50) |
| #define P_ISA_TIMER_MUX (volatile uint32_t *)((0x3c50 << 2) + 0xffd00000) |
| #define ISA_TIMERA (0x3c51) |
| #define P_ISA_TIMERA (volatile uint32_t *)((0x3c51 << 2) + 0xffd00000) |
| #define ISA_TIMERB (0x3c52) |
| #define P_ISA_TIMERB (volatile uint32_t *)((0x3c52 << 2) + 0xffd00000) |
| #define ISA_TIMERC (0x3c53) |
| #define P_ISA_TIMERC (volatile uint32_t *)((0x3c53 << 2) + 0xffd00000) |
| #define ISA_TIMERD (0x3c54) |
| #define P_ISA_TIMERD (volatile uint32_t *)((0x3c54 << 2) + 0xffd00000) |
| #define FBUF_ADDR (0x3c56) |
| #define P_FBUF_ADDR (volatile uint32_t *)((0x3c56 << 2) + 0xffd00000) |
| #define VIDEO_FRM_BUF_MSB_BIT 23 |
| #define VIDEO_FRM_BUF_LSB_BIT 2 |
| #define SDRAM_CTL0 (0x3c57) |
| #define P_SDRAM_CTL0 (volatile uint32_t *)((0x3c57 << 2) + 0xffd00000) |
| #define SDRAM_CTL2 (0x3c58) |
| #define P_SDRAM_CTL2 (volatile uint32_t *)((0x3c58 << 2) + 0xffd00000) |
| //`define AO_CPU_CTL 8'h59 |
| #define SDRAM_CTL4 (0x3c5a) |
| #define P_SDRAM_CTL4 (volatile uint32_t *)((0x3c5a << 2) + 0xffd00000) |
| #define SDRAM_CTL5 (0x3c5b) |
| #define P_SDRAM_CTL5 (volatile uint32_t *)((0x3c5b << 2) + 0xffd00000) |
| #define SDRAM_CTL6 (0x3c5c) |
| #define P_SDRAM_CTL6 (volatile uint32_t *)((0x3c5c << 2) + 0xffd00000) |
| #define SDRAM_CTL7 (0x3c5d) |
| #define P_SDRAM_CTL7 (volatile uint32_t *)((0x3c5d << 2) + 0xffd00000) |
| #define SDRAM_CTL8 (0x3c5e) |
| #define P_SDRAM_CTL8 (volatile uint32_t *)((0x3c5e << 2) + 0xffd00000) |
| #define AHB_MP4_MC_CTL (0x3c5f) |
| #define P_AHB_MP4_MC_CTL (volatile uint32_t *)((0x3c5f << 2) + 0xffd00000) |
| #define MEDIA_CPU_PCR (0x3c60) |
| #define P_MEDIA_CPU_PCR (volatile uint32_t *)((0x3c60 << 2) + 0xffd00000) |
| #define MEDIA_CPU_CTL (0x3c61) |
| #define P_MEDIA_CPU_CTL (volatile uint32_t *)((0x3c61 << 2) + 0xffd00000) |
| #define ISA_TIMERE (0x3c62) |
| #define P_ISA_TIMERE (volatile uint32_t *)((0x3c62 << 2) + 0xffd00000) |
| #define ISA_TIMERE_HI (0x3c63) |
| #define P_ISA_TIMERE_HI (volatile uint32_t *)((0x3c63 << 2) + 0xffd00000) |
| #define ISA_TIMER_MUX1 (0x3c64) |
| #define P_ISA_TIMER_MUX1 (volatile uint32_t *)((0x3c64 << 2) + 0xffd00000) |
| #define ISA_TIMERF (0x3c65) |
| #define P_ISA_TIMERF (volatile uint32_t *)((0x3c65 << 2) + 0xffd00000) |
| #define ISA_TIMERG (0x3c66) |
| #define P_ISA_TIMERG (volatile uint32_t *)((0x3c66 << 2) + 0xffd00000) |
| #define ISA_TIMERH (0x3c67) |
| #define P_ISA_TIMERH (volatile uint32_t *)((0x3c67 << 2) + 0xffd00000) |
| #define ISA_TIMERI (0x3c68) |
| #define P_ISA_TIMERI (volatile uint32_t *)((0x3c68 << 2) + 0xffd00000) |
| // --------------------------------------------- |
| #define AHB_BRIDGE_CNTL_WR (0x3c80) |
| #define P_AHB_BRIDGE_CNTL_WR (volatile uint32_t *)((0x3c80 << 2) + 0xffd00000) |
| #define AHB_BRIDGE_REMAP0 (0x3c81) |
| #define P_AHB_BRIDGE_REMAP0 (volatile uint32_t *)((0x3c81 << 2) + 0xffd00000) |
| #define AHB_BRIDGE_REMAP1 (0x3c82) |
| #define P_AHB_BRIDGE_REMAP1 (volatile uint32_t *)((0x3c82 << 2) + 0xffd00000) |
| #define AHB_BRIDGE_REMAP2 (0x3c83) |
| #define P_AHB_BRIDGE_REMAP2 (volatile uint32_t *)((0x3c83 << 2) + 0xffd00000) |
| #define AHB_BRIDGE_REMAP3 (0x3c84) |
| #define P_AHB_BRIDGE_REMAP3 (volatile uint32_t *)((0x3c84 << 2) + 0xffd00000) |
| #define AHB_BRIDGE_CNTL_REG1 (0x3c85) |
| #define P_AHB_BRIDGE_CNTL_REG1 (volatile uint32_t *)((0x3c85 << 2) + 0xffd00000) |
| #define AHB_BRIDGE_CNTL_REG2 (0x3c86) |
| #define P_AHB_BRIDGE_CNTL_REG2 (volatile uint32_t *)((0x3c86 << 2) + 0xffd00000) |
| // --------------------------------------------- |
| // |
| // Closing file: isa_reg.h |
| // |
| // |
| // Reading file: emmc_reg.h |
| // |
| // $periphs/rtl/periphs_core register defines for the |
| // APB bus |
| // ------------------------------------------------------------------------------------ |
| // ----------------------------------------------- |
| // CBUS_BASE: EMMCA_CBUS_BASE = 0x40c |
| // ----------------------------------------------- |
| #define EMMC_A_GCLOCK (0x40c00) |
| #define P_EMMC_A_GCLOCK (volatile uint32_t *)((0x40c00 << 2) + 0xffd00000) |
| #define EMMC_A_GDELAY0 (0x40c01) |
| #define P_EMMC_A_GDELAY0 (volatile uint32_t *)((0x40c01 << 2) + 0xffd00000) |
| #define EMMC_A_GDELAY1 (0x40c02) |
| #define P_EMMC_A_GDELAY1 (volatile uint32_t *)((0x40c02 << 2) + 0xffd00000) |
| #define EMMC_A_GADJUST (0x40c03) |
| #define P_EMMC_A_GADJUST (volatile uint32_t *)((0x40c03 << 2) + 0xffd00000) |
| #define EMMC_A_GCALOUT0 (0x40c04) |
| #define P_EMMC_A_GCALOUT0 (volatile uint32_t *)((0x40c04 << 2) + 0xffd00000) |
| #define EMMC_A_GCALOUT1 (0x40c05) |
| #define P_EMMC_A_GCALOUT1 (volatile uint32_t *)((0x40c05 << 2) + 0xffd00000) |
| #define EMMC_A_GCALOUT2 (0x40c06) |
| #define P_EMMC_A_GCALOUT2 (volatile uint32_t *)((0x40c06 << 2) + 0xffd00000) |
| #define EMMC_A_GCALOUT3 (0x40c07) |
| #define P_EMMC_A_GCALOUT3 (volatile uint32_t *)((0x40c07 << 2) + 0xffd00000) |
| #define EMMC_A_GADJ_LOG (0x40c08) |
| #define P_EMMC_A_GADJ_LOG (volatile uint32_t *)((0x40c08 << 2) + 0xffd00000) |
| #define EMMC_A_GCLKTEST_LOG (0x40c09) |
| #define P_EMMC_A_GCLKTEST_LOG (volatile uint32_t *)((0x40c09 << 2) + 0xffd00000) |
| #define EMMC_A_GCLKTEST_OUT (0x40c0a) |
| #define P_EMMC_A_GCLKTEST_OUT (volatile uint32_t *)((0x40c0a << 2) + 0xffd00000) |
| #define EMMC_A_GEYETEST_LOG (0x40c0b) |
| #define P_EMMC_A_GEYETEST_LOG (volatile uint32_t *)((0x40c0b << 2) + 0xffd00000) |
| #define EMMC_A_GEYETEST_OUT0 (0x40c0c) |
| #define P_EMMC_A_GEYETEST_OUT0 (volatile uint32_t *)((0x40c0c << 2) + 0xffd00000) |
| #define EMMC_A_GEYETEST_OUT1 (0x40c0d) |
| #define P_EMMC_A_GEYETEST_OUT1 (volatile uint32_t *)((0x40c0d << 2) + 0xffd00000) |
| #define EMMC_A_GINTF3 (0x40c0e) |
| #define P_EMMC_A_GINTF3 (volatile uint32_t *)((0x40c0e << 2) + 0xffd00000) |
| #define EMMC_A_GRESERVE (0x40c0f) |
| #define P_EMMC_A_GRESERVE (volatile uint32_t *)((0x40c0f << 2) + 0xffd00000) |
| #define EMMC_A_GSTART (0x40c10) |
| #define P_EMMC_A_GSTART (volatile uint32_t *)((0x40c10 << 2) + 0xffd00000) |
| #define EMMC_A_GCFG (0x40c11) |
| #define P_EMMC_A_GCFG (volatile uint32_t *)((0x40c11 << 2) + 0xffd00000) |
| #define EMMC_A_GSTATUS (0x40c12) |
| #define P_EMMC_A_GSTATUS (volatile uint32_t *)((0x40c12 << 2) + 0xffd00000) |
| #define EMMC_A_GIRQ_EN (0x40c13) |
| #define P_EMMC_A_GIRQ_EN (volatile uint32_t *)((0x40c13 << 2) + 0xffd00000) |
| #define EMMC_A_GCMD_CFG (0x40c14) |
| #define P_EMMC_A_GCMD_CFG (volatile uint32_t *)((0x40c14 << 2) + 0xffd00000) |
| #define EMMC_A_GCMD_ARG (0x40c15) |
| #define P_EMMC_A_GCMD_ARG (volatile uint32_t *)((0x40c15 << 2) + 0xffd00000) |
| #define EMMC_A_GCMD_DAT (0x40c16) |
| #define P_EMMC_A_GCMD_DAT (volatile uint32_t *)((0x40c16 << 2) + 0xffd00000) |
| #define EMMC_A_GCMD_RSP (0x40c17) |
| #define P_EMMC_A_GCMD_RSP (volatile uint32_t *)((0x40c17 << 2) + 0xffd00000) |
| #define EMMC_A_GCMD_RSP1 (0x40c18) |
| #define P_EMMC_A_GCMD_RSP1 (volatile uint32_t *)((0x40c18 << 2) + 0xffd00000) |
| #define EMMC_A_GCMD_RSP2 (0x40c19) |
| #define P_EMMC_A_GCMD_RSP2 (volatile uint32_t *)((0x40c19 << 2) + 0xffd00000) |
| #define EMMC_A_GCMD_RSP3 (0x40c1a) |
| #define P_EMMC_A_GCMD_RSP3 (volatile uint32_t *)((0x40c1a << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_6C (0x40c1b) |
| #define P_EMMC_A_RESERVED_6C (volatile uint32_t *)((0x40c1b << 2) + 0xffd00000) |
| #define EMMC_A_GCURR_CFG (0x40c1c) |
| #define P_EMMC_A_GCURR_CFG (volatile uint32_t *)((0x40c1c << 2) + 0xffd00000) |
| #define EMMC_A_GCURR_ARG (0x40c1d) |
| #define P_EMMC_A_GCURR_ARG (volatile uint32_t *)((0x40c1d << 2) + 0xffd00000) |
| #define EMMC_A_GCURR_DAT (0x40c1e) |
| #define P_EMMC_A_GCURR_DAT (volatile uint32_t *)((0x40c1e << 2) + 0xffd00000) |
| #define EMMC_A_GCURR_RSP (0x40c1f) |
| #define P_EMMC_A_GCURR_RSP (volatile uint32_t *)((0x40c1f << 2) + 0xffd00000) |
| #define EMMC_A_GNEXT_CFG (0x40c20) |
| #define P_EMMC_A_GNEXT_CFG (volatile uint32_t *)((0x40c20 << 2) + 0xffd00000) |
| #define EMMC_A_GNEXT_ARG (0x40c21) |
| #define P_EMMC_A_GNEXT_ARG (volatile uint32_t *)((0x40c21 << 2) + 0xffd00000) |
| #define EMMC_A_GNEXT_DAT (0x40c22) |
| #define P_EMMC_A_GNEXT_DAT (volatile uint32_t *)((0x40c22 << 2) + 0xffd00000) |
| #define EMMC_A_GNEXT_RSP (0x40c23) |
| #define P_EMMC_A_GNEXT_RSP (volatile uint32_t *)((0x40c23 << 2) + 0xffd00000) |
| #define EMMC_A_GRXD (0x40c24) |
| #define P_EMMC_A_GRXD (volatile uint32_t *)((0x40c24 << 2) + 0xffd00000) |
| #define EMMC_A_GTXD (0x40c25) |
| #define P_EMMC_A_GTXD (volatile uint32_t *)((0x40c25 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_00 (0x40c26) |
| #define P_EMMC_A_RESERVED_98_00 (volatile uint32_t *)((0x40c26 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_01 (0x40c27) |
| #define P_EMMC_A_RESERVED_98_01 (volatile uint32_t *)((0x40c27 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_02 (0x40c28) |
| #define P_EMMC_A_RESERVED_98_02 (volatile uint32_t *)((0x40c28 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_03 (0x40c29) |
| #define P_EMMC_A_RESERVED_98_03 (volatile uint32_t *)((0x40c29 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_04 (0x40c2a) |
| #define P_EMMC_A_RESERVED_98_04 (volatile uint32_t *)((0x40c2a << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_05 (0x40c2b) |
| #define P_EMMC_A_RESERVED_98_05 (volatile uint32_t *)((0x40c2b << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_06 (0x40c2c) |
| #define P_EMMC_A_RESERVED_98_06 (volatile uint32_t *)((0x40c2c << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_07 (0x40c2d) |
| #define P_EMMC_A_RESERVED_98_07 (volatile uint32_t *)((0x40c2d << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_08 (0x40c2e) |
| #define P_EMMC_A_RESERVED_98_08 (volatile uint32_t *)((0x40c2e << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_09 (0x40c2f) |
| #define P_EMMC_A_RESERVED_98_09 (volatile uint32_t *)((0x40c2f << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_10 (0x40c30) |
| #define P_EMMC_A_RESERVED_98_10 (volatile uint32_t *)((0x40c30 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_11 (0x40c31) |
| #define P_EMMC_A_RESERVED_98_11 (volatile uint32_t *)((0x40c31 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_12 (0x40c32) |
| #define P_EMMC_A_RESERVED_98_12 (volatile uint32_t *)((0x40c32 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_13 (0x40c33) |
| #define P_EMMC_A_RESERVED_98_13 (volatile uint32_t *)((0x40c33 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_14 (0x40c34) |
| #define P_EMMC_A_RESERVED_98_14 (volatile uint32_t *)((0x40c34 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_15 (0x40c35) |
| #define P_EMMC_A_RESERVED_98_15 (volatile uint32_t *)((0x40c35 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_16 (0x40c36) |
| #define P_EMMC_A_RESERVED_98_16 (volatile uint32_t *)((0x40c36 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_17 (0x40c37) |
| #define P_EMMC_A_RESERVED_98_17 (volatile uint32_t *)((0x40c37 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_18 (0x40c38) |
| #define P_EMMC_A_RESERVED_98_18 (volatile uint32_t *)((0x40c38 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_19 (0x40c39) |
| #define P_EMMC_A_RESERVED_98_19 (volatile uint32_t *)((0x40c39 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_20 (0x40c3a) |
| #define P_EMMC_A_RESERVED_98_20 (volatile uint32_t *)((0x40c3a << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_21 (0x40c3b) |
| #define P_EMMC_A_RESERVED_98_21 (volatile uint32_t *)((0x40c3b << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_22 (0x40c3c) |
| #define P_EMMC_A_RESERVED_98_22 (volatile uint32_t *)((0x40c3c << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_23 (0x40c3d) |
| #define P_EMMC_A_RESERVED_98_23 (volatile uint32_t *)((0x40c3d << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_24 (0x40c3e) |
| #define P_EMMC_A_RESERVED_98_24 (volatile uint32_t *)((0x40c3e << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_25 (0x40c3f) |
| #define P_EMMC_A_RESERVED_98_25 (volatile uint32_t *)((0x40c3f << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_26 (0x40c40) |
| #define P_EMMC_A_RESERVED_98_26 (volatile uint32_t *)((0x40c40 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_27 (0x40c41) |
| #define P_EMMC_A_RESERVED_98_27 (volatile uint32_t *)((0x40c41 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_28 (0x40c42) |
| #define P_EMMC_A_RESERVED_98_28 (volatile uint32_t *)((0x40c42 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_29 (0x40c43) |
| #define P_EMMC_A_RESERVED_98_29 (volatile uint32_t *)((0x40c43 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_30 (0x40c44) |
| #define P_EMMC_A_RESERVED_98_30 (volatile uint32_t *)((0x40c44 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_31 (0x40c45) |
| #define P_EMMC_A_RESERVED_98_31 (volatile uint32_t *)((0x40c45 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_32 (0x40c46) |
| #define P_EMMC_A_RESERVED_98_32 (volatile uint32_t *)((0x40c46 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_33 (0x40c47) |
| #define P_EMMC_A_RESERVED_98_33 (volatile uint32_t *)((0x40c47 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_34 (0x40c48) |
| #define P_EMMC_A_RESERVED_98_34 (volatile uint32_t *)((0x40c48 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_35 (0x40c49) |
| #define P_EMMC_A_RESERVED_98_35 (volatile uint32_t *)((0x40c49 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_36 (0x40c4a) |
| #define P_EMMC_A_RESERVED_98_36 (volatile uint32_t *)((0x40c4a << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_37 (0x40c4b) |
| #define P_EMMC_A_RESERVED_98_37 (volatile uint32_t *)((0x40c4b << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_38 (0x40c4c) |
| #define P_EMMC_A_RESERVED_98_38 (volatile uint32_t *)((0x40c4c << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_39 (0x40c4d) |
| #define P_EMMC_A_RESERVED_98_39 (volatile uint32_t *)((0x40c4d << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_40 (0x40c4e) |
| #define P_EMMC_A_RESERVED_98_40 (volatile uint32_t *)((0x40c4e << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_41 (0x40c4f) |
| #define P_EMMC_A_RESERVED_98_41 (volatile uint32_t *)((0x40c4f << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_42 (0x40c50) |
| #define P_EMMC_A_RESERVED_98_42 (volatile uint32_t *)((0x40c50 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_43 (0x40c51) |
| #define P_EMMC_A_RESERVED_98_43 (volatile uint32_t *)((0x40c51 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_44 (0x40c52) |
| #define P_EMMC_A_RESERVED_98_44 (volatile uint32_t *)((0x40c52 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_45 (0x40c53) |
| #define P_EMMC_A_RESERVED_98_45 (volatile uint32_t *)((0x40c53 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_46 (0x40c54) |
| #define P_EMMC_A_RESERVED_98_46 (volatile uint32_t *)((0x40c54 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_47 (0x40c55) |
| #define P_EMMC_A_RESERVED_98_47 (volatile uint32_t *)((0x40c55 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_48 (0x40c56) |
| #define P_EMMC_A_RESERVED_98_48 (volatile uint32_t *)((0x40c56 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_49 (0x40c57) |
| #define P_EMMC_A_RESERVED_98_49 (volatile uint32_t *)((0x40c57 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_50 (0x40c58) |
| #define P_EMMC_A_RESERVED_98_50 (volatile uint32_t *)((0x40c58 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_51 (0x40c59) |
| #define P_EMMC_A_RESERVED_98_51 (volatile uint32_t *)((0x40c59 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_52 (0x40c5a) |
| #define P_EMMC_A_RESERVED_98_52 (volatile uint32_t *)((0x40c5a << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_53 (0x40c5b) |
| #define P_EMMC_A_RESERVED_98_53 (volatile uint32_t *)((0x40c5b << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_54 (0x40c5c) |
| #define P_EMMC_A_RESERVED_98_54 (volatile uint32_t *)((0x40c5c << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_55 (0x40c5d) |
| #define P_EMMC_A_RESERVED_98_55 (volatile uint32_t *)((0x40c5d << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_56 (0x40c5e) |
| #define P_EMMC_A_RESERVED_98_56 (volatile uint32_t *)((0x40c5e << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_57 (0x40c5f) |
| #define P_EMMC_A_RESERVED_98_57 (volatile uint32_t *)((0x40c5f << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_58 (0x40c60) |
| #define P_EMMC_A_RESERVED_98_58 (volatile uint32_t *)((0x40c60 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_59 (0x40c61) |
| #define P_EMMC_A_RESERVED_98_59 (volatile uint32_t *)((0x40c61 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_60 (0x40c62) |
| #define P_EMMC_A_RESERVED_98_60 (volatile uint32_t *)((0x40c62 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_61 (0x40c63) |
| #define P_EMMC_A_RESERVED_98_61 (volatile uint32_t *)((0x40c63 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_62 (0x40c64) |
| #define P_EMMC_A_RESERVED_98_62 (volatile uint32_t *)((0x40c64 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_63 (0x40c65) |
| #define P_EMMC_A_RESERVED_98_63 (volatile uint32_t *)((0x40c65 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_64 (0x40c66) |
| #define P_EMMC_A_RESERVED_98_64 (volatile uint32_t *)((0x40c66 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_65 (0x40c67) |
| #define P_EMMC_A_RESERVED_98_65 (volatile uint32_t *)((0x40c67 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_66 (0x40c68) |
| #define P_EMMC_A_RESERVED_98_66 (volatile uint32_t *)((0x40c68 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_67 (0x40c69) |
| #define P_EMMC_A_RESERVED_98_67 (volatile uint32_t *)((0x40c69 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_68 (0x40c6a) |
| #define P_EMMC_A_RESERVED_98_68 (volatile uint32_t *)((0x40c6a << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_69 (0x40c6b) |
| #define P_EMMC_A_RESERVED_98_69 (volatile uint32_t *)((0x40c6b << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_70 (0x40c6c) |
| #define P_EMMC_A_RESERVED_98_70 (volatile uint32_t *)((0x40c6c << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_71 (0x40c6d) |
| #define P_EMMC_A_RESERVED_98_71 (volatile uint32_t *)((0x40c6d << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_72 (0x40c6e) |
| #define P_EMMC_A_RESERVED_98_72 (volatile uint32_t *)((0x40c6e << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_73 (0x40c6f) |
| #define P_EMMC_A_RESERVED_98_73 (volatile uint32_t *)((0x40c6f << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_74 (0x40c70) |
| #define P_EMMC_A_RESERVED_98_74 (volatile uint32_t *)((0x40c70 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_75 (0x40c71) |
| #define P_EMMC_A_RESERVED_98_75 (volatile uint32_t *)((0x40c71 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_76 (0x40c72) |
| #define P_EMMC_A_RESERVED_98_76 (volatile uint32_t *)((0x40c72 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_77 (0x40c73) |
| #define P_EMMC_A_RESERVED_98_77 (volatile uint32_t *)((0x40c73 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_78 (0x40c74) |
| #define P_EMMC_A_RESERVED_98_78 (volatile uint32_t *)((0x40c74 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_79 (0x40c75) |
| #define P_EMMC_A_RESERVED_98_79 (volatile uint32_t *)((0x40c75 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_80 (0x40c76) |
| #define P_EMMC_A_RESERVED_98_80 (volatile uint32_t *)((0x40c76 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_81 (0x40c77) |
| #define P_EMMC_A_RESERVED_98_81 (volatile uint32_t *)((0x40c77 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_82 (0x40c78) |
| #define P_EMMC_A_RESERVED_98_82 (volatile uint32_t *)((0x40c78 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_83 (0x40c79) |
| #define P_EMMC_A_RESERVED_98_83 (volatile uint32_t *)((0x40c79 << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_84 (0x40c7a) |
| #define P_EMMC_A_RESERVED_98_84 (volatile uint32_t *)((0x40c7a << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_85 (0x40c7b) |
| #define P_EMMC_A_RESERVED_98_85 (volatile uint32_t *)((0x40c7b << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_86 (0x40c7c) |
| #define P_EMMC_A_RESERVED_98_86 (volatile uint32_t *)((0x40c7c << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_87 (0x40c7d) |
| #define P_EMMC_A_RESERVED_98_87 (volatile uint32_t *)((0x40c7d << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_88 (0x40c7e) |
| #define P_EMMC_A_RESERVED_98_88 (volatile uint32_t *)((0x40c7e << 2) + 0xffd00000) |
| #define EMMC_A_RESERVED_98_89 (0x40c7f) |
| #define P_EMMC_A_RESERVED_98_89 (volatile uint32_t *)((0x40c7f << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_000 (0x40c80) |
| #define P_EMMC_A_GDESC_000 (volatile uint32_t *)((0x40c80 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_001 (0x40c81) |
| #define P_EMMC_A_GDESC_001 (volatile uint32_t *)((0x40c81 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_002 (0x40c82) |
| #define P_EMMC_A_GDESC_002 (volatile uint32_t *)((0x40c82 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_003 (0x40c83) |
| #define P_EMMC_A_GDESC_003 (volatile uint32_t *)((0x40c83 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_004 (0x40c84) |
| #define P_EMMC_A_GDESC_004 (volatile uint32_t *)((0x40c84 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_005 (0x40c85) |
| #define P_EMMC_A_GDESC_005 (volatile uint32_t *)((0x40c85 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_006 (0x40c86) |
| #define P_EMMC_A_GDESC_006 (volatile uint32_t *)((0x40c86 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_007 (0x40c87) |
| #define P_EMMC_A_GDESC_007 (volatile uint32_t *)((0x40c87 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_008 (0x40c88) |
| #define P_EMMC_A_GDESC_008 (volatile uint32_t *)((0x40c88 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_009 (0x40c89) |
| #define P_EMMC_A_GDESC_009 (volatile uint32_t *)((0x40c89 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_010 (0x40c8a) |
| #define P_EMMC_A_GDESC_010 (volatile uint32_t *)((0x40c8a << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_011 (0x40c8b) |
| #define P_EMMC_A_GDESC_011 (volatile uint32_t *)((0x40c8b << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_012 (0x40c8c) |
| #define P_EMMC_A_GDESC_012 (volatile uint32_t *)((0x40c8c << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_013 (0x40c8d) |
| #define P_EMMC_A_GDESC_013 (volatile uint32_t *)((0x40c8d << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_014 (0x40c8e) |
| #define P_EMMC_A_GDESC_014 (volatile uint32_t *)((0x40c8e << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_015 (0x40c8f) |
| #define P_EMMC_A_GDESC_015 (volatile uint32_t *)((0x40c8f << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_016 (0x40c90) |
| #define P_EMMC_A_GDESC_016 (volatile uint32_t *)((0x40c90 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_017 (0x40c91) |
| #define P_EMMC_A_GDESC_017 (volatile uint32_t *)((0x40c91 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_018 (0x40c92) |
| #define P_EMMC_A_GDESC_018 (volatile uint32_t *)((0x40c92 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_019 (0x40c93) |
| #define P_EMMC_A_GDESC_019 (volatile uint32_t *)((0x40c93 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_020 (0x40c94) |
| #define P_EMMC_A_GDESC_020 (volatile uint32_t *)((0x40c94 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_021 (0x40c95) |
| #define P_EMMC_A_GDESC_021 (volatile uint32_t *)((0x40c95 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_022 (0x40c96) |
| #define P_EMMC_A_GDESC_022 (volatile uint32_t *)((0x40c96 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_023 (0x40c97) |
| #define P_EMMC_A_GDESC_023 (volatile uint32_t *)((0x40c97 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_024 (0x40c98) |
| #define P_EMMC_A_GDESC_024 (volatile uint32_t *)((0x40c98 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_025 (0x40c99) |
| #define P_EMMC_A_GDESC_025 (volatile uint32_t *)((0x40c99 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_026 (0x40c9a) |
| #define P_EMMC_A_GDESC_026 (volatile uint32_t *)((0x40c9a << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_027 (0x40c9b) |
| #define P_EMMC_A_GDESC_027 (volatile uint32_t *)((0x40c9b << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_028 (0x40c9c) |
| #define P_EMMC_A_GDESC_028 (volatile uint32_t *)((0x40c9c << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_029 (0x40c9d) |
| #define P_EMMC_A_GDESC_029 (volatile uint32_t *)((0x40c9d << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_030 (0x40c9e) |
| #define P_EMMC_A_GDESC_030 (volatile uint32_t *)((0x40c9e << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_031 (0x40c9f) |
| #define P_EMMC_A_GDESC_031 (volatile uint32_t *)((0x40c9f << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_032 (0x40ca0) |
| #define P_EMMC_A_GDESC_032 (volatile uint32_t *)((0x40ca0 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_033 (0x40ca1) |
| #define P_EMMC_A_GDESC_033 (volatile uint32_t *)((0x40ca1 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_034 (0x40ca2) |
| #define P_EMMC_A_GDESC_034 (volatile uint32_t *)((0x40ca2 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_035 (0x40ca3) |
| #define P_EMMC_A_GDESC_035 (volatile uint32_t *)((0x40ca3 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_036 (0x40ca4) |
| #define P_EMMC_A_GDESC_036 (volatile uint32_t *)((0x40ca4 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_037 (0x40ca5) |
| #define P_EMMC_A_GDESC_037 (volatile uint32_t *)((0x40ca5 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_038 (0x40ca6) |
| #define P_EMMC_A_GDESC_038 (volatile uint32_t *)((0x40ca6 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_039 (0x40ca7) |
| #define P_EMMC_A_GDESC_039 (volatile uint32_t *)((0x40ca7 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_040 (0x40ca8) |
| #define P_EMMC_A_GDESC_040 (volatile uint32_t *)((0x40ca8 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_041 (0x40ca9) |
| #define P_EMMC_A_GDESC_041 (volatile uint32_t *)((0x40ca9 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_042 (0x40caa) |
| #define P_EMMC_A_GDESC_042 (volatile uint32_t *)((0x40caa << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_043 (0x40cab) |
| #define P_EMMC_A_GDESC_043 (volatile uint32_t *)((0x40cab << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_044 (0x40cac) |
| #define P_EMMC_A_GDESC_044 (volatile uint32_t *)((0x40cac << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_045 (0x40cad) |
| #define P_EMMC_A_GDESC_045 (volatile uint32_t *)((0x40cad << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_046 (0x40cae) |
| #define P_EMMC_A_GDESC_046 (volatile uint32_t *)((0x40cae << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_047 (0x40caf) |
| #define P_EMMC_A_GDESC_047 (volatile uint32_t *)((0x40caf << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_048 (0x40cb0) |
| #define P_EMMC_A_GDESC_048 (volatile uint32_t *)((0x40cb0 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_049 (0x40cb1) |
| #define P_EMMC_A_GDESC_049 (volatile uint32_t *)((0x40cb1 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_050 (0x40cb2) |
| #define P_EMMC_A_GDESC_050 (volatile uint32_t *)((0x40cb2 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_051 (0x40cb3) |
| #define P_EMMC_A_GDESC_051 (volatile uint32_t *)((0x40cb3 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_052 (0x40cb4) |
| #define P_EMMC_A_GDESC_052 (volatile uint32_t *)((0x40cb4 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_053 (0x40cb5) |
| #define P_EMMC_A_GDESC_053 (volatile uint32_t *)((0x40cb5 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_054 (0x40cb6) |
| #define P_EMMC_A_GDESC_054 (volatile uint32_t *)((0x40cb6 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_055 (0x40cb7) |
| #define P_EMMC_A_GDESC_055 (volatile uint32_t *)((0x40cb7 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_056 (0x40cb8) |
| #define P_EMMC_A_GDESC_056 (volatile uint32_t *)((0x40cb8 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_057 (0x40cb9) |
| #define P_EMMC_A_GDESC_057 (volatile uint32_t *)((0x40cb9 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_058 (0x40cba) |
| #define P_EMMC_A_GDESC_058 (volatile uint32_t *)((0x40cba << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_059 (0x40cbb) |
| #define P_EMMC_A_GDESC_059 (volatile uint32_t *)((0x40cbb << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_060 (0x40cbc) |
| #define P_EMMC_A_GDESC_060 (volatile uint32_t *)((0x40cbc << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_061 (0x40cbd) |
| #define P_EMMC_A_GDESC_061 (volatile uint32_t *)((0x40cbd << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_062 (0x40cbe) |
| #define P_EMMC_A_GDESC_062 (volatile uint32_t *)((0x40cbe << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_063 (0x40cbf) |
| #define P_EMMC_A_GDESC_063 (volatile uint32_t *)((0x40cbf << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_064 (0x40cc0) |
| #define P_EMMC_A_GDESC_064 (volatile uint32_t *)((0x40cc0 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_065 (0x40cc1) |
| #define P_EMMC_A_GDESC_065 (volatile uint32_t *)((0x40cc1 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_066 (0x40cc2) |
| #define P_EMMC_A_GDESC_066 (volatile uint32_t *)((0x40cc2 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_067 (0x40cc3) |
| #define P_EMMC_A_GDESC_067 (volatile uint32_t *)((0x40cc3 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_068 (0x40cc4) |
| #define P_EMMC_A_GDESC_068 (volatile uint32_t *)((0x40cc4 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_069 (0x40cc5) |
| #define P_EMMC_A_GDESC_069 (volatile uint32_t *)((0x40cc5 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_070 (0x40cc6) |
| #define P_EMMC_A_GDESC_070 (volatile uint32_t *)((0x40cc6 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_071 (0x40cc7) |
| #define P_EMMC_A_GDESC_071 (volatile uint32_t *)((0x40cc7 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_072 (0x40cc8) |
| #define P_EMMC_A_GDESC_072 (volatile uint32_t *)((0x40cc8 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_073 (0x40cc9) |
| #define P_EMMC_A_GDESC_073 (volatile uint32_t *)((0x40cc9 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_074 (0x40cca) |
| #define P_EMMC_A_GDESC_074 (volatile uint32_t *)((0x40cca << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_075 (0x40ccb) |
| #define P_EMMC_A_GDESC_075 (volatile uint32_t *)((0x40ccb << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_076 (0x40ccc) |
| #define P_EMMC_A_GDESC_076 (volatile uint32_t *)((0x40ccc << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_077 (0x40ccd) |
| #define P_EMMC_A_GDESC_077 (volatile uint32_t *)((0x40ccd << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_078 (0x40cce) |
| #define P_EMMC_A_GDESC_078 (volatile uint32_t *)((0x40cce << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_079 (0x40ccf) |
| #define P_EMMC_A_GDESC_079 (volatile uint32_t *)((0x40ccf << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_080 (0x40cd0) |
| #define P_EMMC_A_GDESC_080 (volatile uint32_t *)((0x40cd0 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_081 (0x40cd1) |
| #define P_EMMC_A_GDESC_081 (volatile uint32_t *)((0x40cd1 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_082 (0x40cd2) |
| #define P_EMMC_A_GDESC_082 (volatile uint32_t *)((0x40cd2 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_083 (0x40cd3) |
| #define P_EMMC_A_GDESC_083 (volatile uint32_t *)((0x40cd3 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_084 (0x40cd4) |
| #define P_EMMC_A_GDESC_084 (volatile uint32_t *)((0x40cd4 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_085 (0x40cd5) |
| #define P_EMMC_A_GDESC_085 (volatile uint32_t *)((0x40cd5 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_086 (0x40cd6) |
| #define P_EMMC_A_GDESC_086 (volatile uint32_t *)((0x40cd6 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_087 (0x40cd7) |
| #define P_EMMC_A_GDESC_087 (volatile uint32_t *)((0x40cd7 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_088 (0x40cd8) |
| #define P_EMMC_A_GDESC_088 (volatile uint32_t *)((0x40cd8 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_089 (0x40cd9) |
| #define P_EMMC_A_GDESC_089 (volatile uint32_t *)((0x40cd9 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_090 (0x40cda) |
| #define P_EMMC_A_GDESC_090 (volatile uint32_t *)((0x40cda << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_091 (0x40cdb) |
| #define P_EMMC_A_GDESC_091 (volatile uint32_t *)((0x40cdb << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_092 (0x40cdc) |
| #define P_EMMC_A_GDESC_092 (volatile uint32_t *)((0x40cdc << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_093 (0x40cdd) |
| #define P_EMMC_A_GDESC_093 (volatile uint32_t *)((0x40cdd << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_094 (0x40cde) |
| #define P_EMMC_A_GDESC_094 (volatile uint32_t *)((0x40cde << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_095 (0x40cdf) |
| #define P_EMMC_A_GDESC_095 (volatile uint32_t *)((0x40cdf << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_096 (0x40ce0) |
| #define P_EMMC_A_GDESC_096 (volatile uint32_t *)((0x40ce0 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_097 (0x40ce1) |
| #define P_EMMC_A_GDESC_097 (volatile uint32_t *)((0x40ce1 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_098 (0x40ce2) |
| #define P_EMMC_A_GDESC_098 (volatile uint32_t *)((0x40ce2 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_099 (0x40ce3) |
| #define P_EMMC_A_GDESC_099 (volatile uint32_t *)((0x40ce3 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_100 (0x40ce4) |
| #define P_EMMC_A_GDESC_100 (volatile uint32_t *)((0x40ce4 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_101 (0x40ce5) |
| #define P_EMMC_A_GDESC_101 (volatile uint32_t *)((0x40ce5 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_102 (0x40ce6) |
| #define P_EMMC_A_GDESC_102 (volatile uint32_t *)((0x40ce6 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_103 (0x40ce7) |
| #define P_EMMC_A_GDESC_103 (volatile uint32_t *)((0x40ce7 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_104 (0x40ce8) |
| #define P_EMMC_A_GDESC_104 (volatile uint32_t *)((0x40ce8 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_105 (0x40ce9) |
| #define P_EMMC_A_GDESC_105 (volatile uint32_t *)((0x40ce9 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_106 (0x40cea) |
| #define P_EMMC_A_GDESC_106 (volatile uint32_t *)((0x40cea << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_107 (0x40ceb) |
| #define P_EMMC_A_GDESC_107 (volatile uint32_t *)((0x40ceb << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_108 (0x40cec) |
| #define P_EMMC_A_GDESC_108 (volatile uint32_t *)((0x40cec << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_109 (0x40ced) |
| #define P_EMMC_A_GDESC_109 (volatile uint32_t *)((0x40ced << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_110 (0x40cee) |
| #define P_EMMC_A_GDESC_110 (volatile uint32_t *)((0x40cee << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_111 (0x40cef) |
| #define P_EMMC_A_GDESC_111 (volatile uint32_t *)((0x40cef << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_112 (0x40cf0) |
| #define P_EMMC_A_GDESC_112 (volatile uint32_t *)((0x40cf0 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_113 (0x40cf1) |
| #define P_EMMC_A_GDESC_113 (volatile uint32_t *)((0x40cf1 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_114 (0x40cf2) |
| #define P_EMMC_A_GDESC_114 (volatile uint32_t *)((0x40cf2 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_115 (0x40cf3) |
| #define P_EMMC_A_GDESC_115 (volatile uint32_t *)((0x40cf3 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_116 (0x40cf4) |
| #define P_EMMC_A_GDESC_116 (volatile uint32_t *)((0x40cf4 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_117 (0x40cf5) |
| #define P_EMMC_A_GDESC_117 (volatile uint32_t *)((0x40cf5 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_118 (0x40cf6) |
| #define P_EMMC_A_GDESC_118 (volatile uint32_t *)((0x40cf6 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_119 (0x40cf7) |
| #define P_EMMC_A_GDESC_119 (volatile uint32_t *)((0x40cf7 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_120 (0x40cf8) |
| #define P_EMMC_A_GDESC_120 (volatile uint32_t *)((0x40cf8 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_121 (0x40cf9) |
| #define P_EMMC_A_GDESC_121 (volatile uint32_t *)((0x40cf9 << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_122 (0x40cfa) |
| #define P_EMMC_A_GDESC_122 (volatile uint32_t *)((0x40cfa << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_123 (0x40cfb) |
| #define P_EMMC_A_GDESC_123 (volatile uint32_t *)((0x40cfb << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_124 (0x40cfc) |
| #define P_EMMC_A_GDESC_124 (volatile uint32_t *)((0x40cfc << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_125 (0x40cfd) |
| #define P_EMMC_A_GDESC_125 (volatile uint32_t *)((0x40cfd << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_126 (0x40cfe) |
| #define P_EMMC_A_GDESC_126 (volatile uint32_t *)((0x40cfe << 2) + 0xffd00000) |
| #define EMMC_A_GDESC_127 (0x40cff) |
| #define P_EMMC_A_GDESC_127 (volatile uint32_t *)((0x40cff << 2) + 0xffd00000) |
| #define EMMC_A_GPING_000 (0x40d00) |
| #define P_EMMC_A_GPING_000 (volatile uint32_t *)((0x40d00 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_001 (0x40d01) |
| #define P_EMMC_A_GPING_001 (volatile uint32_t *)((0x40d01 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_002 (0x40d02) |
| #define P_EMMC_A_GPING_002 (volatile uint32_t *)((0x40d02 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_003 (0x40d03) |
| #define P_EMMC_A_GPING_003 (volatile uint32_t *)((0x40d03 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_004 (0x40d04) |
| #define P_EMMC_A_GPING_004 (volatile uint32_t *)((0x40d04 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_005 (0x40d05) |
| #define P_EMMC_A_GPING_005 (volatile uint32_t *)((0x40d05 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_006 (0x40d06) |
| #define P_EMMC_A_GPING_006 (volatile uint32_t *)((0x40d06 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_007 (0x40d07) |
| #define P_EMMC_A_GPING_007 (volatile uint32_t *)((0x40d07 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_008 (0x40d08) |
| #define P_EMMC_A_GPING_008 (volatile uint32_t *)((0x40d08 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_009 (0x40d09) |
| #define P_EMMC_A_GPING_009 (volatile uint32_t *)((0x40d09 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_010 (0x40d0a) |
| #define P_EMMC_A_GPING_010 (volatile uint32_t *)((0x40d0a << 2) + 0xffd00000) |
| #define EMMC_A_GPING_011 (0x40d0b) |
| #define P_EMMC_A_GPING_011 (volatile uint32_t *)((0x40d0b << 2) + 0xffd00000) |
| #define EMMC_A_GPING_012 (0x40d0c) |
| #define P_EMMC_A_GPING_012 (volatile uint32_t *)((0x40d0c << 2) + 0xffd00000) |
| #define EMMC_A_GPING_013 (0x40d0d) |
| #define P_EMMC_A_GPING_013 (volatile uint32_t *)((0x40d0d << 2) + 0xffd00000) |
| #define EMMC_A_GPING_014 (0x40d0e) |
| #define P_EMMC_A_GPING_014 (volatile uint32_t *)((0x40d0e << 2) + 0xffd00000) |
| #define EMMC_A_GPING_015 (0x40d0f) |
| #define P_EMMC_A_GPING_015 (volatile uint32_t *)((0x40d0f << 2) + 0xffd00000) |
| #define EMMC_A_GPING_016 (0x40d10) |
| #define P_EMMC_A_GPING_016 (volatile uint32_t *)((0x40d10 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_017 (0x40d11) |
| #define P_EMMC_A_GPING_017 (volatile uint32_t *)((0x40d11 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_018 (0x40d12) |
| #define P_EMMC_A_GPING_018 (volatile uint32_t *)((0x40d12 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_019 (0x40d13) |
| #define P_EMMC_A_GPING_019 (volatile uint32_t *)((0x40d13 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_020 (0x40d14) |
| #define P_EMMC_A_GPING_020 (volatile uint32_t *)((0x40d14 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_021 (0x40d15) |
| #define P_EMMC_A_GPING_021 (volatile uint32_t *)((0x40d15 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_022 (0x40d16) |
| #define P_EMMC_A_GPING_022 (volatile uint32_t *)((0x40d16 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_023 (0x40d17) |
| #define P_EMMC_A_GPING_023 (volatile uint32_t *)((0x40d17 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_024 (0x40d18) |
| #define P_EMMC_A_GPING_024 (volatile uint32_t *)((0x40d18 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_025 (0x40d19) |
| #define P_EMMC_A_GPING_025 (volatile uint32_t *)((0x40d19 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_026 (0x40d1a) |
| #define P_EMMC_A_GPING_026 (volatile uint32_t *)((0x40d1a << 2) + 0xffd00000) |
| #define EMMC_A_GPING_027 (0x40d1b) |
| #define P_EMMC_A_GPING_027 (volatile uint32_t *)((0x40d1b << 2) + 0xffd00000) |
| #define EMMC_A_GPING_028 (0x40d1c) |
| #define P_EMMC_A_GPING_028 (volatile uint32_t *)((0x40d1c << 2) + 0xffd00000) |
| #define EMMC_A_GPING_029 (0x40d1d) |
| #define P_EMMC_A_GPING_029 (volatile uint32_t *)((0x40d1d << 2) + 0xffd00000) |
| #define EMMC_A_GPING_030 (0x40d1e) |
| #define P_EMMC_A_GPING_030 (volatile uint32_t *)((0x40d1e << 2) + 0xffd00000) |
| #define EMMC_A_GPING_031 (0x40d1f) |
| #define P_EMMC_A_GPING_031 (volatile uint32_t *)((0x40d1f << 2) + 0xffd00000) |
| #define EMMC_A_GPING_032 (0x40d20) |
| #define P_EMMC_A_GPING_032 (volatile uint32_t *)((0x40d20 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_033 (0x40d21) |
| #define P_EMMC_A_GPING_033 (volatile uint32_t *)((0x40d21 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_034 (0x40d22) |
| #define P_EMMC_A_GPING_034 (volatile uint32_t *)((0x40d22 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_035 (0x40d23) |
| #define P_EMMC_A_GPING_035 (volatile uint32_t *)((0x40d23 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_036 (0x40d24) |
| #define P_EMMC_A_GPING_036 (volatile uint32_t *)((0x40d24 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_037 (0x40d25) |
| #define P_EMMC_A_GPING_037 (volatile uint32_t *)((0x40d25 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_038 (0x40d26) |
| #define P_EMMC_A_GPING_038 (volatile uint32_t *)((0x40d26 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_039 (0x40d27) |
| #define P_EMMC_A_GPING_039 (volatile uint32_t *)((0x40d27 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_040 (0x40d28) |
| #define P_EMMC_A_GPING_040 (volatile uint32_t *)((0x40d28 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_041 (0x40d29) |
| #define P_EMMC_A_GPING_041 (volatile uint32_t *)((0x40d29 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_042 (0x40d2a) |
| #define P_EMMC_A_GPING_042 (volatile uint32_t *)((0x40d2a << 2) + 0xffd00000) |
| #define EMMC_A_GPING_043 (0x40d2b) |
| #define P_EMMC_A_GPING_043 (volatile uint32_t *)((0x40d2b << 2) + 0xffd00000) |
| #define EMMC_A_GPING_044 (0x40d2c) |
| #define P_EMMC_A_GPING_044 (volatile uint32_t *)((0x40d2c << 2) + 0xffd00000) |
| #define EMMC_A_GPING_045 (0x40d2d) |
| #define P_EMMC_A_GPING_045 (volatile uint32_t *)((0x40d2d << 2) + 0xffd00000) |
| #define EMMC_A_GPING_046 (0x40d2e) |
| #define P_EMMC_A_GPING_046 (volatile uint32_t *)((0x40d2e << 2) + 0xffd00000) |
| #define EMMC_A_GPING_047 (0x40d2f) |
| #define P_EMMC_A_GPING_047 (volatile uint32_t *)((0x40d2f << 2) + 0xffd00000) |
| #define EMMC_A_GPING_048 (0x40d30) |
| #define P_EMMC_A_GPING_048 (volatile uint32_t *)((0x40d30 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_049 (0x40d31) |
| #define P_EMMC_A_GPING_049 (volatile uint32_t *)((0x40d31 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_050 (0x40d32) |
| #define P_EMMC_A_GPING_050 (volatile uint32_t *)((0x40d32 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_051 (0x40d33) |
| #define P_EMMC_A_GPING_051 (volatile uint32_t *)((0x40d33 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_052 (0x40d34) |
| #define P_EMMC_A_GPING_052 (volatile uint32_t *)((0x40d34 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_053 (0x40d35) |
| #define P_EMMC_A_GPING_053 (volatile uint32_t *)((0x40d35 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_054 (0x40d36) |
| #define P_EMMC_A_GPING_054 (volatile uint32_t *)((0x40d36 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_055 (0x40d37) |
| #define P_EMMC_A_GPING_055 (volatile uint32_t *)((0x40d37 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_056 (0x40d38) |
| #define P_EMMC_A_GPING_056 (volatile uint32_t *)((0x40d38 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_057 (0x40d39) |
| #define P_EMMC_A_GPING_057 (volatile uint32_t *)((0x40d39 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_058 (0x40d3a) |
| #define P_EMMC_A_GPING_058 (volatile uint32_t *)((0x40d3a << 2) + 0xffd00000) |
| #define EMMC_A_GPING_059 (0x40d3b) |
| #define P_EMMC_A_GPING_059 (volatile uint32_t *)((0x40d3b << 2) + 0xffd00000) |
| #define EMMC_A_GPING_060 (0x40d3c) |
| #define P_EMMC_A_GPING_060 (volatile uint32_t *)((0x40d3c << 2) + 0xffd00000) |
| #define EMMC_A_GPING_061 (0x40d3d) |
| #define P_EMMC_A_GPING_061 (volatile uint32_t *)((0x40d3d << 2) + 0xffd00000) |
| #define EMMC_A_GPING_062 (0x40d3e) |
| #define P_EMMC_A_GPING_062 (volatile uint32_t *)((0x40d3e << 2) + 0xffd00000) |
| #define EMMC_A_GPING_063 (0x40d3f) |
| #define P_EMMC_A_GPING_063 (volatile uint32_t *)((0x40d3f << 2) + 0xffd00000) |
| #define EMMC_A_GPING_064 (0x40d40) |
| #define P_EMMC_A_GPING_064 (volatile uint32_t *)((0x40d40 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_065 (0x40d41) |
| #define P_EMMC_A_GPING_065 (volatile uint32_t *)((0x40d41 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_066 (0x40d42) |
| #define P_EMMC_A_GPING_066 (volatile uint32_t *)((0x40d42 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_067 (0x40d43) |
| #define P_EMMC_A_GPING_067 (volatile uint32_t *)((0x40d43 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_068 (0x40d44) |
| #define P_EMMC_A_GPING_068 (volatile uint32_t *)((0x40d44 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_069 (0x40d45) |
| #define P_EMMC_A_GPING_069 (volatile uint32_t *)((0x40d45 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_070 (0x40d46) |
| #define P_EMMC_A_GPING_070 (volatile uint32_t *)((0x40d46 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_071 (0x40d47) |
| #define P_EMMC_A_GPING_071 (volatile uint32_t *)((0x40d47 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_072 (0x40d48) |
| #define P_EMMC_A_GPING_072 (volatile uint32_t *)((0x40d48 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_073 (0x40d49) |
| #define P_EMMC_A_GPING_073 (volatile uint32_t *)((0x40d49 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_074 (0x40d4a) |
| #define P_EMMC_A_GPING_074 (volatile uint32_t *)((0x40d4a << 2) + 0xffd00000) |
| #define EMMC_A_GPING_075 (0x40d4b) |
| #define P_EMMC_A_GPING_075 (volatile uint32_t *)((0x40d4b << 2) + 0xffd00000) |
| #define EMMC_A_GPING_076 (0x40d4c) |
| #define P_EMMC_A_GPING_076 (volatile uint32_t *)((0x40d4c << 2) + 0xffd00000) |
| #define EMMC_A_GPING_077 (0x40d4d) |
| #define P_EMMC_A_GPING_077 (volatile uint32_t *)((0x40d4d << 2) + 0xffd00000) |
| #define EMMC_A_GPING_078 (0x40d4e) |
| #define P_EMMC_A_GPING_078 (volatile uint32_t *)((0x40d4e << 2) + 0xffd00000) |
| #define EMMC_A_GPING_079 (0x40d4f) |
| #define P_EMMC_A_GPING_079 (volatile uint32_t *)((0x40d4f << 2) + 0xffd00000) |
| #define EMMC_A_GPING_080 (0x40d50) |
| #define P_EMMC_A_GPING_080 (volatile uint32_t *)((0x40d50 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_081 (0x40d51) |
| #define P_EMMC_A_GPING_081 (volatile uint32_t *)((0x40d51 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_082 (0x40d52) |
| #define P_EMMC_A_GPING_082 (volatile uint32_t *)((0x40d52 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_083 (0x40d53) |
| #define P_EMMC_A_GPING_083 (volatile uint32_t *)((0x40d53 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_084 (0x40d54) |
| #define P_EMMC_A_GPING_084 (volatile uint32_t *)((0x40d54 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_085 (0x40d55) |
| #define P_EMMC_A_GPING_085 (volatile uint32_t *)((0x40d55 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_086 (0x40d56) |
| #define P_EMMC_A_GPING_086 (volatile uint32_t *)((0x40d56 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_087 (0x40d57) |
| #define P_EMMC_A_GPING_087 (volatile uint32_t *)((0x40d57 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_088 (0x40d58) |
| #define P_EMMC_A_GPING_088 (volatile uint32_t *)((0x40d58 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_089 (0x40d59) |
| #define P_EMMC_A_GPING_089 (volatile uint32_t *)((0x40d59 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_090 (0x40d5a) |
| #define P_EMMC_A_GPING_090 (volatile uint32_t *)((0x40d5a << 2) + 0xffd00000) |
| #define EMMC_A_GPING_091 (0x40d5b) |
| #define P_EMMC_A_GPING_091 (volatile uint32_t *)((0x40d5b << 2) + 0xffd00000) |
| #define EMMC_A_GPING_092 (0x40d5c) |
| #define P_EMMC_A_GPING_092 (volatile uint32_t *)((0x40d5c << 2) + 0xffd00000) |
| #define EMMC_A_GPING_093 (0x40d5d) |
| #define P_EMMC_A_GPING_093 (volatile uint32_t *)((0x40d5d << 2) + 0xffd00000) |
| #define EMMC_A_GPING_094 (0x40d5e) |
| #define P_EMMC_A_GPING_094 (volatile uint32_t *)((0x40d5e << 2) + 0xffd00000) |
| #define EMMC_A_GPING_095 (0x40d5f) |
| #define P_EMMC_A_GPING_095 (volatile uint32_t *)((0x40d5f << 2) + 0xffd00000) |
| #define EMMC_A_GPING_096 (0x40d60) |
| #define P_EMMC_A_GPING_096 (volatile uint32_t *)((0x40d60 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_097 (0x40d61) |
| #define P_EMMC_A_GPING_097 (volatile uint32_t *)((0x40d61 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_098 (0x40d62) |
| #define P_EMMC_A_GPING_098 (volatile uint32_t *)((0x40d62 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_099 (0x40d63) |
| #define P_EMMC_A_GPING_099 (volatile uint32_t *)((0x40d63 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_100 (0x40d64) |
| #define P_EMMC_A_GPING_100 (volatile uint32_t *)((0x40d64 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_101 (0x40d65) |
| #define P_EMMC_A_GPING_101 (volatile uint32_t *)((0x40d65 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_102 (0x40d66) |
| #define P_EMMC_A_GPING_102 (volatile uint32_t *)((0x40d66 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_103 (0x40d67) |
| #define P_EMMC_A_GPING_103 (volatile uint32_t *)((0x40d67 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_104 (0x40d68) |
| #define P_EMMC_A_GPING_104 (volatile uint32_t *)((0x40d68 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_105 (0x40d69) |
| #define P_EMMC_A_GPING_105 (volatile uint32_t *)((0x40d69 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_106 (0x40d6a) |
| #define P_EMMC_A_GPING_106 (volatile uint32_t *)((0x40d6a << 2) + 0xffd00000) |
| #define EMMC_A_GPING_107 (0x40d6b) |
| #define P_EMMC_A_GPING_107 (volatile uint32_t *)((0x40d6b << 2) + 0xffd00000) |
| #define EMMC_A_GPING_108 (0x40d6c) |
| #define P_EMMC_A_GPING_108 (volatile uint32_t *)((0x40d6c << 2) + 0xffd00000) |
| #define EMMC_A_GPING_109 (0x40d6d) |
| #define P_EMMC_A_GPING_109 (volatile uint32_t *)((0x40d6d << 2) + 0xffd00000) |
| #define EMMC_A_GPING_110 (0x40d6e) |
| #define P_EMMC_A_GPING_110 (volatile uint32_t *)((0x40d6e << 2) + 0xffd00000) |
| #define EMMC_A_GPING_111 (0x40d6f) |
| #define P_EMMC_A_GPING_111 (volatile uint32_t *)((0x40d6f << 2) + 0xffd00000) |
| #define EMMC_A_GPING_112 (0x40d70) |
| #define P_EMMC_A_GPING_112 (volatile uint32_t *)((0x40d70 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_113 (0x40d71) |
| #define P_EMMC_A_GPING_113 (volatile uint32_t *)((0x40d71 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_114 (0x40d72) |
| #define P_EMMC_A_GPING_114 (volatile uint32_t *)((0x40d72 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_115 (0x40d73) |
| #define P_EMMC_A_GPING_115 (volatile uint32_t *)((0x40d73 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_116 (0x40d74) |
| #define P_EMMC_A_GPING_116 (volatile uint32_t *)((0x40d74 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_117 (0x40d75) |
| #define P_EMMC_A_GPING_117 (volatile uint32_t *)((0x40d75 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_118 (0x40d76) |
| #define P_EMMC_A_GPING_118 (volatile uint32_t *)((0x40d76 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_119 (0x40d77) |
| #define P_EMMC_A_GPING_119 (volatile uint32_t *)((0x40d77 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_120 (0x40d78) |
| #define P_EMMC_A_GPING_120 (volatile uint32_t *)((0x40d78 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_121 (0x40d79) |
| #define P_EMMC_A_GPING_121 (volatile uint32_t *)((0x40d79 << 2) + 0xffd00000) |
| #define EMMC_A_GPING_122 (0x40d7a) |
| #define P_EMMC_A_GPING_122 (volatile uint32_t *)((0x40d7a << 2) + 0xffd00000) |
| #define EMMC_A_GPING_123 (0x40d7b) |
| #define P_EMMC_A_GPING_123 (volatile uint32_t *)((0x40d7b << 2) + 0xffd00000) |
| #define EMMC_A_GPING_124 (0x40d7c) |
| #define P_EMMC_A_GPING_124 (volatile uint32_t *)((0x40d7c << 2) + 0xffd00000) |
| #define EMMC_A_GPING_125 (0x40d7d) |
| #define P_EMMC_A_GPING_125 (volatile uint32_t *)((0x40d7d << 2) + 0xffd00000) |
| #define EMMC_A_GPING_126 (0x40d7e) |
| #define P_EMMC_A_GPING_126 (volatile uint32_t *)((0x40d7e << 2) + 0xffd00000) |
| #define EMMC_A_GPING_127 (0x40d7f) |
| #define P_EMMC_A_GPING_127 (volatile uint32_t *)((0x40d7f << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_000 (0x40d80) |
| #define P_EMMC_A_GPONG_000 (volatile uint32_t *)((0x40d80 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_001 (0x40d81) |
| #define P_EMMC_A_GPONG_001 (volatile uint32_t *)((0x40d81 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_002 (0x40d82) |
| #define P_EMMC_A_GPONG_002 (volatile uint32_t *)((0x40d82 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_003 (0x40d83) |
| #define P_EMMC_A_GPONG_003 (volatile uint32_t *)((0x40d83 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_004 (0x40d84) |
| #define P_EMMC_A_GPONG_004 (volatile uint32_t *)((0x40d84 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_005 (0x40d85) |
| #define P_EMMC_A_GPONG_005 (volatile uint32_t *)((0x40d85 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_006 (0x40d86) |
| #define P_EMMC_A_GPONG_006 (volatile uint32_t *)((0x40d86 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_007 (0x40d87) |
| #define P_EMMC_A_GPONG_007 (volatile uint32_t *)((0x40d87 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_008 (0x40d88) |
| #define P_EMMC_A_GPONG_008 (volatile uint32_t *)((0x40d88 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_009 (0x40d89) |
| #define P_EMMC_A_GPONG_009 (volatile uint32_t *)((0x40d89 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_010 (0x40d8a) |
| #define P_EMMC_A_GPONG_010 (volatile uint32_t *)((0x40d8a << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_011 (0x40d8b) |
| #define P_EMMC_A_GPONG_011 (volatile uint32_t *)((0x40d8b << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_012 (0x40d8c) |
| #define P_EMMC_A_GPONG_012 (volatile uint32_t *)((0x40d8c << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_013 (0x40d8d) |
| #define P_EMMC_A_GPONG_013 (volatile uint32_t *)((0x40d8d << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_014 (0x40d8e) |
| #define P_EMMC_A_GPONG_014 (volatile uint32_t *)((0x40d8e << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_015 (0x40d8f) |
| #define P_EMMC_A_GPONG_015 (volatile uint32_t *)((0x40d8f << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_016 (0x40d90) |
| #define P_EMMC_A_GPONG_016 (volatile uint32_t *)((0x40d90 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_017 (0x40d91) |
| #define P_EMMC_A_GPONG_017 (volatile uint32_t *)((0x40d91 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_018 (0x40d92) |
| #define P_EMMC_A_GPONG_018 (volatile uint32_t *)((0x40d92 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_019 (0x40d93) |
| #define P_EMMC_A_GPONG_019 (volatile uint32_t *)((0x40d93 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_020 (0x40d94) |
| #define P_EMMC_A_GPONG_020 (volatile uint32_t *)((0x40d94 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_021 (0x40d95) |
| #define P_EMMC_A_GPONG_021 (volatile uint32_t *)((0x40d95 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_022 (0x40d96) |
| #define P_EMMC_A_GPONG_022 (volatile uint32_t *)((0x40d96 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_023 (0x40d97) |
| #define P_EMMC_A_GPONG_023 (volatile uint32_t *)((0x40d97 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_024 (0x40d98) |
| #define P_EMMC_A_GPONG_024 (volatile uint32_t *)((0x40d98 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_025 (0x40d99) |
| #define P_EMMC_A_GPONG_025 (volatile uint32_t *)((0x40d99 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_026 (0x40d9a) |
| #define P_EMMC_A_GPONG_026 (volatile uint32_t *)((0x40d9a << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_027 (0x40d9b) |
| #define P_EMMC_A_GPONG_027 (volatile uint32_t *)((0x40d9b << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_028 (0x40d9c) |
| #define P_EMMC_A_GPONG_028 (volatile uint32_t *)((0x40d9c << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_029 (0x40d9d) |
| #define P_EMMC_A_GPONG_029 (volatile uint32_t *)((0x40d9d << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_030 (0x40d9e) |
| #define P_EMMC_A_GPONG_030 (volatile uint32_t *)((0x40d9e << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_031 (0x40d9f) |
| #define P_EMMC_A_GPONG_031 (volatile uint32_t *)((0x40d9f << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_032 (0x40da0) |
| #define P_EMMC_A_GPONG_032 (volatile uint32_t *)((0x40da0 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_033 (0x40da1) |
| #define P_EMMC_A_GPONG_033 (volatile uint32_t *)((0x40da1 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_034 (0x40da2) |
| #define P_EMMC_A_GPONG_034 (volatile uint32_t *)((0x40da2 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_035 (0x40da3) |
| #define P_EMMC_A_GPONG_035 (volatile uint32_t *)((0x40da3 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_036 (0x40da4) |
| #define P_EMMC_A_GPONG_036 (volatile uint32_t *)((0x40da4 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_037 (0x40da5) |
| #define P_EMMC_A_GPONG_037 (volatile uint32_t *)((0x40da5 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_038 (0x40da6) |
| #define P_EMMC_A_GPONG_038 (volatile uint32_t *)((0x40da6 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_039 (0x40da7) |
| #define P_EMMC_A_GPONG_039 (volatile uint32_t *)((0x40da7 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_040 (0x40da8) |
| #define P_EMMC_A_GPONG_040 (volatile uint32_t *)((0x40da8 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_041 (0x40da9) |
| #define P_EMMC_A_GPONG_041 (volatile uint32_t *)((0x40da9 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_042 (0x40daa) |
| #define P_EMMC_A_GPONG_042 (volatile uint32_t *)((0x40daa << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_043 (0x40dab) |
| #define P_EMMC_A_GPONG_043 (volatile uint32_t *)((0x40dab << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_044 (0x40dac) |
| #define P_EMMC_A_GPONG_044 (volatile uint32_t *)((0x40dac << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_045 (0x40dad) |
| #define P_EMMC_A_GPONG_045 (volatile uint32_t *)((0x40dad << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_046 (0x40dae) |
| #define P_EMMC_A_GPONG_046 (volatile uint32_t *)((0x40dae << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_047 (0x40daf) |
| #define P_EMMC_A_GPONG_047 (volatile uint32_t *)((0x40daf << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_048 (0x40db0) |
| #define P_EMMC_A_GPONG_048 (volatile uint32_t *)((0x40db0 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_049 (0x40db1) |
| #define P_EMMC_A_GPONG_049 (volatile uint32_t *)((0x40db1 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_050 (0x40db2) |
| #define P_EMMC_A_GPONG_050 (volatile uint32_t *)((0x40db2 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_051 (0x40db3) |
| #define P_EMMC_A_GPONG_051 (volatile uint32_t *)((0x40db3 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_052 (0x40db4) |
| #define P_EMMC_A_GPONG_052 (volatile uint32_t *)((0x40db4 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_053 (0x40db5) |
| #define P_EMMC_A_GPONG_053 (volatile uint32_t *)((0x40db5 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_054 (0x40db6) |
| #define P_EMMC_A_GPONG_054 (volatile uint32_t *)((0x40db6 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_055 (0x40db7) |
| #define P_EMMC_A_GPONG_055 (volatile uint32_t *)((0x40db7 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_056 (0x40db8) |
| #define P_EMMC_A_GPONG_056 (volatile uint32_t *)((0x40db8 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_057 (0x40db9) |
| #define P_EMMC_A_GPONG_057 (volatile uint32_t *)((0x40db9 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_058 (0x40dba) |
| #define P_EMMC_A_GPONG_058 (volatile uint32_t *)((0x40dba << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_059 (0x40dbb) |
| #define P_EMMC_A_GPONG_059 (volatile uint32_t *)((0x40dbb << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_060 (0x40dbc) |
| #define P_EMMC_A_GPONG_060 (volatile uint32_t *)((0x40dbc << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_061 (0x40dbd) |
| #define P_EMMC_A_GPONG_061 (volatile uint32_t *)((0x40dbd << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_062 (0x40dbe) |
| #define P_EMMC_A_GPONG_062 (volatile uint32_t *)((0x40dbe << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_063 (0x40dbf) |
| #define P_EMMC_A_GPONG_063 (volatile uint32_t *)((0x40dbf << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_064 (0x40dc0) |
| #define P_EMMC_A_GPONG_064 (volatile uint32_t *)((0x40dc0 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_065 (0x40dc1) |
| #define P_EMMC_A_GPONG_065 (volatile uint32_t *)((0x40dc1 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_066 (0x40dc2) |
| #define P_EMMC_A_GPONG_066 (volatile uint32_t *)((0x40dc2 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_067 (0x40dc3) |
| #define P_EMMC_A_GPONG_067 (volatile uint32_t *)((0x40dc3 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_068 (0x40dc4) |
| #define P_EMMC_A_GPONG_068 (volatile uint32_t *)((0x40dc4 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_069 (0x40dc5) |
| #define P_EMMC_A_GPONG_069 (volatile uint32_t *)((0x40dc5 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_070 (0x40dc6) |
| #define P_EMMC_A_GPONG_070 (volatile uint32_t *)((0x40dc6 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_071 (0x40dc7) |
| #define P_EMMC_A_GPONG_071 (volatile uint32_t *)((0x40dc7 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_072 (0x40dc8) |
| #define P_EMMC_A_GPONG_072 (volatile uint32_t *)((0x40dc8 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_073 (0x40dc9) |
| #define P_EMMC_A_GPONG_073 (volatile uint32_t *)((0x40dc9 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_074 (0x40dca) |
| #define P_EMMC_A_GPONG_074 (volatile uint32_t *)((0x40dca << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_075 (0x40dcb) |
| #define P_EMMC_A_GPONG_075 (volatile uint32_t *)((0x40dcb << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_076 (0x40dcc) |
| #define P_EMMC_A_GPONG_076 (volatile uint32_t *)((0x40dcc << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_077 (0x40dcd) |
| #define P_EMMC_A_GPONG_077 (volatile uint32_t *)((0x40dcd << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_078 (0x40dce) |
| #define P_EMMC_A_GPONG_078 (volatile uint32_t *)((0x40dce << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_079 (0x40dcf) |
| #define P_EMMC_A_GPONG_079 (volatile uint32_t *)((0x40dcf << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_080 (0x40dd0) |
| #define P_EMMC_A_GPONG_080 (volatile uint32_t *)((0x40dd0 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_081 (0x40dd1) |
| #define P_EMMC_A_GPONG_081 (volatile uint32_t *)((0x40dd1 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_082 (0x40dd2) |
| #define P_EMMC_A_GPONG_082 (volatile uint32_t *)((0x40dd2 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_083 (0x40dd3) |
| #define P_EMMC_A_GPONG_083 (volatile uint32_t *)((0x40dd3 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_084 (0x40dd4) |
| #define P_EMMC_A_GPONG_084 (volatile uint32_t *)((0x40dd4 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_085 (0x40dd5) |
| #define P_EMMC_A_GPONG_085 (volatile uint32_t *)((0x40dd5 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_086 (0x40dd6) |
| #define P_EMMC_A_GPONG_086 (volatile uint32_t *)((0x40dd6 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_087 (0x40dd7) |
| #define P_EMMC_A_GPONG_087 (volatile uint32_t *)((0x40dd7 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_088 (0x40dd8) |
| #define P_EMMC_A_GPONG_088 (volatile uint32_t *)((0x40dd8 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_089 (0x40dd9) |
| #define P_EMMC_A_GPONG_089 (volatile uint32_t *)((0x40dd9 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_090 (0x40dda) |
| #define P_EMMC_A_GPONG_090 (volatile uint32_t *)((0x40dda << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_091 (0x40ddb) |
| #define P_EMMC_A_GPONG_091 (volatile uint32_t *)((0x40ddb << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_092 (0x40ddc) |
| #define P_EMMC_A_GPONG_092 (volatile uint32_t *)((0x40ddc << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_093 (0x40ddd) |
| #define P_EMMC_A_GPONG_093 (volatile uint32_t *)((0x40ddd << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_094 (0x40dde) |
| #define P_EMMC_A_GPONG_094 (volatile uint32_t *)((0x40dde << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_095 (0x40ddf) |
| #define P_EMMC_A_GPONG_095 (volatile uint32_t *)((0x40ddf << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_096 (0x40de0) |
| #define P_EMMC_A_GPONG_096 (volatile uint32_t *)((0x40de0 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_097 (0x40de1) |
| #define P_EMMC_A_GPONG_097 (volatile uint32_t *)((0x40de1 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_098 (0x40de2) |
| #define P_EMMC_A_GPONG_098 (volatile uint32_t *)((0x40de2 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_099 (0x40de3) |
| #define P_EMMC_A_GPONG_099 (volatile uint32_t *)((0x40de3 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_100 (0x40de4) |
| #define P_EMMC_A_GPONG_100 (volatile uint32_t *)((0x40de4 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_101 (0x40de5) |
| #define P_EMMC_A_GPONG_101 (volatile uint32_t *)((0x40de5 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_102 (0x40de6) |
| #define P_EMMC_A_GPONG_102 (volatile uint32_t *)((0x40de6 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_103 (0x40de7) |
| #define P_EMMC_A_GPONG_103 (volatile uint32_t *)((0x40de7 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_104 (0x40de8) |
| #define P_EMMC_A_GPONG_104 (volatile uint32_t *)((0x40de8 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_105 (0x40de9) |
| #define P_EMMC_A_GPONG_105 (volatile uint32_t *)((0x40de9 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_106 (0x40dea) |
| #define P_EMMC_A_GPONG_106 (volatile uint32_t *)((0x40dea << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_107 (0x40deb) |
| #define P_EMMC_A_GPONG_107 (volatile uint32_t *)((0x40deb << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_108 (0x40dec) |
| #define P_EMMC_A_GPONG_108 (volatile uint32_t *)((0x40dec << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_109 (0x40ded) |
| #define P_EMMC_A_GPONG_109 (volatile uint32_t *)((0x40ded << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_110 (0x40dee) |
| #define P_EMMC_A_GPONG_110 (volatile uint32_t *)((0x40dee << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_111 (0x40def) |
| #define P_EMMC_A_GPONG_111 (volatile uint32_t *)((0x40def << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_112 (0x40df0) |
| #define P_EMMC_A_GPONG_112 (volatile uint32_t *)((0x40df0 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_113 (0x40df1) |
| #define P_EMMC_A_GPONG_113 (volatile uint32_t *)((0x40df1 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_114 (0x40df2) |
| #define P_EMMC_A_GPONG_114 (volatile uint32_t *)((0x40df2 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_115 (0x40df3) |
| #define P_EMMC_A_GPONG_115 (volatile uint32_t *)((0x40df3 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_116 (0x40df4) |
| #define P_EMMC_A_GPONG_116 (volatile uint32_t *)((0x40df4 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_117 (0x40df5) |
| #define P_EMMC_A_GPONG_117 (volatile uint32_t *)((0x40df5 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_118 (0x40df6) |
| #define P_EMMC_A_GPONG_118 (volatile uint32_t *)((0x40df6 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_119 (0x40df7) |
| #define P_EMMC_A_GPONG_119 (volatile uint32_t *)((0x40df7 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_120 (0x40df8) |
| #define P_EMMC_A_GPONG_120 (volatile uint32_t *)((0x40df8 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_121 (0x40df9) |
| #define P_EMMC_A_GPONG_121 (volatile uint32_t *)((0x40df9 << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_122 (0x40dfa) |
| #define P_EMMC_A_GPONG_122 (volatile uint32_t *)((0x40dfa << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_123 (0x40dfb) |
| #define P_EMMC_A_GPONG_123 (volatile uint32_t *)((0x40dfb << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_124 (0x40dfc) |
| #define P_EMMC_A_GPONG_124 (volatile uint32_t *)((0x40dfc << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_125 (0x40dfd) |
| #define P_EMMC_A_GPONG_125 (volatile uint32_t *)((0x40dfd << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_126 (0x40dfe) |
| #define P_EMMC_A_GPONG_126 (volatile uint32_t *)((0x40dfe << 2) + 0xffd00000) |
| #define EMMC_A_GPONG_127 (0x40dff) |
| #define P_EMMC_A_GPONG_127 (volatile uint32_t *)((0x40dff << 2) + 0xffd00000) |
| // ----------------------------------------------- |
| // CBUS_BASE: EMMCB_CBUS_BASE = 0x414 |
| // ----------------------------------------------- |
| #define EMMC_B_GCLOCK (0x41400) |
| #define P_EMMC_B_GCLOCK (volatile uint32_t *)((0x41400 << 2) + 0xffd00000) |
| #define EMMC_B_GDELAY0 (0x41401) |
| #define P_EMMC_B_GDELAY0 (volatile uint32_t *)((0x41401 << 2) + 0xffd00000) |
| #define EMMC_B_GDELAY1 (0x41402) |
| #define P_EMMC_B_GDELAY1 (volatile uint32_t *)((0x41402 << 2) + 0xffd00000) |
| #define EMMC_B_GADJUST (0x41403) |
| #define P_EMMC_B_GADJUST (volatile uint32_t *)((0x41403 << 2) + 0xffd00000) |
| #define EMMC_B_GCALOUT0 (0x41404) |
| #define P_EMMC_B_GCALOUT0 (volatile uint32_t *)((0x41404 << 2) + 0xffd00000) |
| #define EMMC_B_GCALOUT1 (0x41405) |
| #define P_EMMC_B_GCALOUT1 (volatile uint32_t *)((0x41405 << 2) + 0xffd00000) |
| #define EMMC_B_GCALOUT2 (0x41406) |
| #define P_EMMC_B_GCALOUT2 (volatile uint32_t *)((0x41406 << 2) + 0xffd00000) |
| #define EMMC_B_GCALOUT3 (0x41407) |
| #define P_EMMC_B_GCALOUT3 (volatile uint32_t *)((0x41407 << 2) + 0xffd00000) |
| #define EMMC_B_GADJ_LOG (0x41408) |
| #define P_EMMC_B_GADJ_LOG (volatile uint32_t *)((0x41408 << 2) + 0xffd00000) |
| #define EMMC_B_GCLKTEST_LOG (0x41409) |
| #define P_EMMC_B_GCLKTEST_LOG (volatile uint32_t *)((0x41409 << 2) + 0xffd00000) |
| #define EMMC_B_GCLKTEST_OUT (0x4140a) |
| #define P_EMMC_B_GCLKTEST_OUT (volatile uint32_t *)((0x4140a << 2) + 0xffd00000) |
| #define EMMC_B_GEYETEST_LOG (0x4140b) |
| #define P_EMMC_B_GEYETEST_LOG (volatile uint32_t *)((0x4140b << 2) + 0xffd00000) |
| #define EMMC_B_GEYETEST_OUT0 (0x4140c) |
| #define P_EMMC_B_GEYETEST_OUT0 (volatile uint32_t *)((0x4140c << 2) + 0xffd00000) |
| #define EMMC_B_GEYETEST_OUT1 (0x4140d) |
| #define P_EMMC_B_GEYETEST_OUT1 (volatile uint32_t *)((0x4140d << 2) + 0xffd00000) |
| #define EMMC_B_GINTF3 (0x4140e) |
| #define P_EMMC_B_GINTF3 (volatile uint32_t *)((0x4140e << 2) + 0xffd00000) |
| #define EMMC_B_GRESERVE (0x4140f) |
| #define P_EMMC_B_GRESERVE (volatile uint32_t *)((0x4140f << 2) + 0xffd00000) |
| #define EMMC_B_GSTART (0x41410) |
| #define P_EMMC_B_GSTART (volatile uint32_t *)((0x41410 << 2) + 0xffd00000) |
| #define EMMC_B_GCFG (0x41411) |
| #define P_EMMC_B_GCFG (volatile uint32_t *)((0x41411 << 2) + 0xffd00000) |
| #define EMMC_B_GSTATUS (0x41412) |
| #define P_EMMC_B_GSTATUS (volatile uint32_t *)((0x41412 << 2) + 0xffd00000) |
| #define EMMC_B_GIRQ_EN (0x41413) |
| #define P_EMMC_B_GIRQ_EN (volatile uint32_t *)((0x41413 << 2) + 0xffd00000) |
| #define EMMC_B_GCMD_CFG (0x41414) |
| #define P_EMMC_B_GCMD_CFG (volatile uint32_t *)((0x41414 << 2) + 0xffd00000) |
| #define EMMC_B_GCMD_ARG (0x41415) |
| #define P_EMMC_B_GCMD_ARG (volatile uint32_t *)((0x41415 << 2) + 0xffd00000) |
| #define EMMC_B_GCMD_DAT (0x41416) |
| #define P_EMMC_B_GCMD_DAT (volatile uint32_t *)((0x41416 << 2) + 0xffd00000) |
| #define EMMC_B_GCMD_RSP (0x41417) |
| #define P_EMMC_B_GCMD_RSP (volatile uint32_t *)((0x41417 << 2) + 0xffd00000) |
| #define EMMC_B_GCMD_RSP1 (0x41418) |
| #define P_EMMC_B_GCMD_RSP1 (volatile uint32_t *)((0x41418 << 2) + 0xffd00000) |
| #define EMMC_B_GCMD_RSP2 (0x41419) |
| #define P_EMMC_B_GCMD_RSP2 (volatile uint32_t *)((0x41419 << 2) + 0xffd00000) |
| #define EMMC_B_GCMD_RSP3 (0x4141a) |
| #define P_EMMC_B_GCMD_RSP3 (volatile uint32_t *)((0x4141a << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_6C (0x4141b) |
| #define P_EMMC_B_RESERVED_6C (volatile uint32_t *)((0x4141b << 2) + 0xffd00000) |
| #define EMMC_B_GCURR_CFG (0x4141c) |
| #define P_EMMC_B_GCURR_CFG (volatile uint32_t *)((0x4141c << 2) + 0xffd00000) |
| #define EMMC_B_GCURR_ARG (0x4141d) |
| #define P_EMMC_B_GCURR_ARG (volatile uint32_t *)((0x4141d << 2) + 0xffd00000) |
| #define EMMC_B_GCURR_DAT (0x4141e) |
| #define P_EMMC_B_GCURR_DAT (volatile uint32_t *)((0x4141e << 2) + 0xffd00000) |
| #define EMMC_B_GCURR_RSP (0x4141f) |
| #define P_EMMC_B_GCURR_RSP (volatile uint32_t *)((0x4141f << 2) + 0xffd00000) |
| #define EMMC_B_GNEXT_CFG (0x41420) |
| #define P_EMMC_B_GNEXT_CFG (volatile uint32_t *)((0x41420 << 2) + 0xffd00000) |
| #define EMMC_B_GNEXT_ARG (0x41421) |
| #define P_EMMC_B_GNEXT_ARG (volatile uint32_t *)((0x41421 << 2) + 0xffd00000) |
| #define EMMC_B_GNEXT_DAT (0x41422) |
| #define P_EMMC_B_GNEXT_DAT (volatile uint32_t *)((0x41422 << 2) + 0xffd00000) |
| #define EMMC_B_GNEXT_RSP (0x41423) |
| #define P_EMMC_B_GNEXT_RSP (volatile uint32_t *)((0x41423 << 2) + 0xffd00000) |
| #define EMMC_B_GRXD (0x41424) |
| #define P_EMMC_B_GRXD (volatile uint32_t *)((0x41424 << 2) + 0xffd00000) |
| #define EMMC_B_GTXD (0x41425) |
| #define P_EMMC_B_GTXD (volatile uint32_t *)((0x41425 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_00 (0x41426) |
| #define P_EMMC_B_RESERVED_98_00 (volatile uint32_t *)((0x41426 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_01 (0x41427) |
| #define P_EMMC_B_RESERVED_98_01 (volatile uint32_t *)((0x41427 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_02 (0x41428) |
| #define P_EMMC_B_RESERVED_98_02 (volatile uint32_t *)((0x41428 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_03 (0x41429) |
| #define P_EMMC_B_RESERVED_98_03 (volatile uint32_t *)((0x41429 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_04 (0x4142a) |
| #define P_EMMC_B_RESERVED_98_04 (volatile uint32_t *)((0x4142a << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_05 (0x4142b) |
| #define P_EMMC_B_RESERVED_98_05 (volatile uint32_t *)((0x4142b << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_06 (0x4142c) |
| #define P_EMMC_B_RESERVED_98_06 (volatile uint32_t *)((0x4142c << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_07 (0x4142d) |
| #define P_EMMC_B_RESERVED_98_07 (volatile uint32_t *)((0x4142d << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_08 (0x4142e) |
| #define P_EMMC_B_RESERVED_98_08 (volatile uint32_t *)((0x4142e << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_09 (0x4142f) |
| #define P_EMMC_B_RESERVED_98_09 (volatile uint32_t *)((0x4142f << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_10 (0x41430) |
| #define P_EMMC_B_RESERVED_98_10 (volatile uint32_t *)((0x41430 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_11 (0x41431) |
| #define P_EMMC_B_RESERVED_98_11 (volatile uint32_t *)((0x41431 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_12 (0x41432) |
| #define P_EMMC_B_RESERVED_98_12 (volatile uint32_t *)((0x41432 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_13 (0x41433) |
| #define P_EMMC_B_RESERVED_98_13 (volatile uint32_t *)((0x41433 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_14 (0x41434) |
| #define P_EMMC_B_RESERVED_98_14 (volatile uint32_t *)((0x41434 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_15 (0x41435) |
| #define P_EMMC_B_RESERVED_98_15 (volatile uint32_t *)((0x41435 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_16 (0x41436) |
| #define P_EMMC_B_RESERVED_98_16 (volatile uint32_t *)((0x41436 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_17 (0x41437) |
| #define P_EMMC_B_RESERVED_98_17 (volatile uint32_t *)((0x41437 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_18 (0x41438) |
| #define P_EMMC_B_RESERVED_98_18 (volatile uint32_t *)((0x41438 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_19 (0x41439) |
| #define P_EMMC_B_RESERVED_98_19 (volatile uint32_t *)((0x41439 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_20 (0x4143a) |
| #define P_EMMC_B_RESERVED_98_20 (volatile uint32_t *)((0x4143a << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_21 (0x4143b) |
| #define P_EMMC_B_RESERVED_98_21 (volatile uint32_t *)((0x4143b << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_22 (0x4143c) |
| #define P_EMMC_B_RESERVED_98_22 (volatile uint32_t *)((0x4143c << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_23 (0x4143d) |
| #define P_EMMC_B_RESERVED_98_23 (volatile uint32_t *)((0x4143d << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_24 (0x4143e) |
| #define P_EMMC_B_RESERVED_98_24 (volatile uint32_t *)((0x4143e << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_25 (0x4143f) |
| #define P_EMMC_B_RESERVED_98_25 (volatile uint32_t *)((0x4143f << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_26 (0x41440) |
| #define P_EMMC_B_RESERVED_98_26 (volatile uint32_t *)((0x41440 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_27 (0x41441) |
| #define P_EMMC_B_RESERVED_98_27 (volatile uint32_t *)((0x41441 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_28 (0x41442) |
| #define P_EMMC_B_RESERVED_98_28 (volatile uint32_t *)((0x41442 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_29 (0x41443) |
| #define P_EMMC_B_RESERVED_98_29 (volatile uint32_t *)((0x41443 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_30 (0x41444) |
| #define P_EMMC_B_RESERVED_98_30 (volatile uint32_t *)((0x41444 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_31 (0x41445) |
| #define P_EMMC_B_RESERVED_98_31 (volatile uint32_t *)((0x41445 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_32 (0x41446) |
| #define P_EMMC_B_RESERVED_98_32 (volatile uint32_t *)((0x41446 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_33 (0x41447) |
| #define P_EMMC_B_RESERVED_98_33 (volatile uint32_t *)((0x41447 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_34 (0x41448) |
| #define P_EMMC_B_RESERVED_98_34 (volatile uint32_t *)((0x41448 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_35 (0x41449) |
| #define P_EMMC_B_RESERVED_98_35 (volatile uint32_t *)((0x41449 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_36 (0x4144a) |
| #define P_EMMC_B_RESERVED_98_36 (volatile uint32_t *)((0x4144a << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_37 (0x4144b) |
| #define P_EMMC_B_RESERVED_98_37 (volatile uint32_t *)((0x4144b << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_38 (0x4144c) |
| #define P_EMMC_B_RESERVED_98_38 (volatile uint32_t *)((0x4144c << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_39 (0x4144d) |
| #define P_EMMC_B_RESERVED_98_39 (volatile uint32_t *)((0x4144d << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_40 (0x4144e) |
| #define P_EMMC_B_RESERVED_98_40 (volatile uint32_t *)((0x4144e << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_41 (0x4144f) |
| #define P_EMMC_B_RESERVED_98_41 (volatile uint32_t *)((0x4144f << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_42 (0x41450) |
| #define P_EMMC_B_RESERVED_98_42 (volatile uint32_t *)((0x41450 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_43 (0x41451) |
| #define P_EMMC_B_RESERVED_98_43 (volatile uint32_t *)((0x41451 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_44 (0x41452) |
| #define P_EMMC_B_RESERVED_98_44 (volatile uint32_t *)((0x41452 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_45 (0x41453) |
| #define P_EMMC_B_RESERVED_98_45 (volatile uint32_t *)((0x41453 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_46 (0x41454) |
| #define P_EMMC_B_RESERVED_98_46 (volatile uint32_t *)((0x41454 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_47 (0x41455) |
| #define P_EMMC_B_RESERVED_98_47 (volatile uint32_t *)((0x41455 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_48 (0x41456) |
| #define P_EMMC_B_RESERVED_98_48 (volatile uint32_t *)((0x41456 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_49 (0x41457) |
| #define P_EMMC_B_RESERVED_98_49 (volatile uint32_t *)((0x41457 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_50 (0x41458) |
| #define P_EMMC_B_RESERVED_98_50 (volatile uint32_t *)((0x41458 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_51 (0x41459) |
| #define P_EMMC_B_RESERVED_98_51 (volatile uint32_t *)((0x41459 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_52 (0x4145a) |
| #define P_EMMC_B_RESERVED_98_52 (volatile uint32_t *)((0x4145a << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_53 (0x4145b) |
| #define P_EMMC_B_RESERVED_98_53 (volatile uint32_t *)((0x4145b << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_54 (0x4145c) |
| #define P_EMMC_B_RESERVED_98_54 (volatile uint32_t *)((0x4145c << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_55 (0x4145d) |
| #define P_EMMC_B_RESERVED_98_55 (volatile uint32_t *)((0x4145d << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_56 (0x4145e) |
| #define P_EMMC_B_RESERVED_98_56 (volatile uint32_t *)((0x4145e << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_57 (0x4145f) |
| #define P_EMMC_B_RESERVED_98_57 (volatile uint32_t *)((0x4145f << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_58 (0x41460) |
| #define P_EMMC_B_RESERVED_98_58 (volatile uint32_t *)((0x41460 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_59 (0x41461) |
| #define P_EMMC_B_RESERVED_98_59 (volatile uint32_t *)((0x41461 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_60 (0x41462) |
| #define P_EMMC_B_RESERVED_98_60 (volatile uint32_t *)((0x41462 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_61 (0x41463) |
| #define P_EMMC_B_RESERVED_98_61 (volatile uint32_t *)((0x41463 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_62 (0x41464) |
| #define P_EMMC_B_RESERVED_98_62 (volatile uint32_t *)((0x41464 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_63 (0x41465) |
| #define P_EMMC_B_RESERVED_98_63 (volatile uint32_t *)((0x41465 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_64 (0x41466) |
| #define P_EMMC_B_RESERVED_98_64 (volatile uint32_t *)((0x41466 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_65 (0x41467) |
| #define P_EMMC_B_RESERVED_98_65 (volatile uint32_t *)((0x41467 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_66 (0x41468) |
| #define P_EMMC_B_RESERVED_98_66 (volatile uint32_t *)((0x41468 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_67 (0x41469) |
| #define P_EMMC_B_RESERVED_98_67 (volatile uint32_t *)((0x41469 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_68 (0x4146a) |
| #define P_EMMC_B_RESERVED_98_68 (volatile uint32_t *)((0x4146a << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_69 (0x4146b) |
| #define P_EMMC_B_RESERVED_98_69 (volatile uint32_t *)((0x4146b << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_70 (0x4146c) |
| #define P_EMMC_B_RESERVED_98_70 (volatile uint32_t *)((0x4146c << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_71 (0x4146d) |
| #define P_EMMC_B_RESERVED_98_71 (volatile uint32_t *)((0x4146d << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_72 (0x4146e) |
| #define P_EMMC_B_RESERVED_98_72 (volatile uint32_t *)((0x4146e << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_73 (0x4146f) |
| #define P_EMMC_B_RESERVED_98_73 (volatile uint32_t *)((0x4146f << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_74 (0x41470) |
| #define P_EMMC_B_RESERVED_98_74 (volatile uint32_t *)((0x41470 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_75 (0x41471) |
| #define P_EMMC_B_RESERVED_98_75 (volatile uint32_t *)((0x41471 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_76 (0x41472) |
| #define P_EMMC_B_RESERVED_98_76 (volatile uint32_t *)((0x41472 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_77 (0x41473) |
| #define P_EMMC_B_RESERVED_98_77 (volatile uint32_t *)((0x41473 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_78 (0x41474) |
| #define P_EMMC_B_RESERVED_98_78 (volatile uint32_t *)((0x41474 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_79 (0x41475) |
| #define P_EMMC_B_RESERVED_98_79 (volatile uint32_t *)((0x41475 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_80 (0x41476) |
| #define P_EMMC_B_RESERVED_98_80 (volatile uint32_t *)((0x41476 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_81 (0x41477) |
| #define P_EMMC_B_RESERVED_98_81 (volatile uint32_t *)((0x41477 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_82 (0x41478) |
| #define P_EMMC_B_RESERVED_98_82 (volatile uint32_t *)((0x41478 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_83 (0x41479) |
| #define P_EMMC_B_RESERVED_98_83 (volatile uint32_t *)((0x41479 << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_84 (0x4147a) |
| #define P_EMMC_B_RESERVED_98_84 (volatile uint32_t *)((0x4147a << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_85 (0x4147b) |
| #define P_EMMC_B_RESERVED_98_85 (volatile uint32_t *)((0x4147b << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_86 (0x4147c) |
| #define P_EMMC_B_RESERVED_98_86 (volatile uint32_t *)((0x4147c << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_87 (0x4147d) |
| #define P_EMMC_B_RESERVED_98_87 (volatile uint32_t *)((0x4147d << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_88 (0x4147e) |
| #define P_EMMC_B_RESERVED_98_88 (volatile uint32_t *)((0x4147e << 2) + 0xffd00000) |
| #define EMMC_B_RESERVED_98_89 (0x4147f) |
| #define P_EMMC_B_RESERVED_98_89 (volatile uint32_t *)((0x4147f << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_000 (0x41480) |
| #define P_EMMC_B_GDESC_000 (volatile uint32_t *)((0x41480 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_001 (0x41481) |
| #define P_EMMC_B_GDESC_001 (volatile uint32_t *)((0x41481 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_002 (0x41482) |
| #define P_EMMC_B_GDESC_002 (volatile uint32_t *)((0x41482 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_003 (0x41483) |
| #define P_EMMC_B_GDESC_003 (volatile uint32_t *)((0x41483 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_004 (0x41484) |
| #define P_EMMC_B_GDESC_004 (volatile uint32_t *)((0x41484 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_005 (0x41485) |
| #define P_EMMC_B_GDESC_005 (volatile uint32_t *)((0x41485 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_006 (0x41486) |
| #define P_EMMC_B_GDESC_006 (volatile uint32_t *)((0x41486 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_007 (0x41487) |
| #define P_EMMC_B_GDESC_007 (volatile uint32_t *)((0x41487 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_008 (0x41488) |
| #define P_EMMC_B_GDESC_008 (volatile uint32_t *)((0x41488 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_009 (0x41489) |
| #define P_EMMC_B_GDESC_009 (volatile uint32_t *)((0x41489 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_010 (0x4148a) |
| #define P_EMMC_B_GDESC_010 (volatile uint32_t *)((0x4148a << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_011 (0x4148b) |
| #define P_EMMC_B_GDESC_011 (volatile uint32_t *)((0x4148b << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_012 (0x4148c) |
| #define P_EMMC_B_GDESC_012 (volatile uint32_t *)((0x4148c << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_013 (0x4148d) |
| #define P_EMMC_B_GDESC_013 (volatile uint32_t *)((0x4148d << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_014 (0x4148e) |
| #define P_EMMC_B_GDESC_014 (volatile uint32_t *)((0x4148e << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_015 (0x4148f) |
| #define P_EMMC_B_GDESC_015 (volatile uint32_t *)((0x4148f << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_016 (0x41490) |
| #define P_EMMC_B_GDESC_016 (volatile uint32_t *)((0x41490 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_017 (0x41491) |
| #define P_EMMC_B_GDESC_017 (volatile uint32_t *)((0x41491 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_018 (0x41492) |
| #define P_EMMC_B_GDESC_018 (volatile uint32_t *)((0x41492 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_019 (0x41493) |
| #define P_EMMC_B_GDESC_019 (volatile uint32_t *)((0x41493 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_020 (0x41494) |
| #define P_EMMC_B_GDESC_020 (volatile uint32_t *)((0x41494 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_021 (0x41495) |
| #define P_EMMC_B_GDESC_021 (volatile uint32_t *)((0x41495 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_022 (0x41496) |
| #define P_EMMC_B_GDESC_022 (volatile uint32_t *)((0x41496 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_023 (0x41497) |
| #define P_EMMC_B_GDESC_023 (volatile uint32_t *)((0x41497 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_024 (0x41498) |
| #define P_EMMC_B_GDESC_024 (volatile uint32_t *)((0x41498 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_025 (0x41499) |
| #define P_EMMC_B_GDESC_025 (volatile uint32_t *)((0x41499 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_026 (0x4149a) |
| #define P_EMMC_B_GDESC_026 (volatile uint32_t *)((0x4149a << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_027 (0x4149b) |
| #define P_EMMC_B_GDESC_027 (volatile uint32_t *)((0x4149b << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_028 (0x4149c) |
| #define P_EMMC_B_GDESC_028 (volatile uint32_t *)((0x4149c << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_029 (0x4149d) |
| #define P_EMMC_B_GDESC_029 (volatile uint32_t *)((0x4149d << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_030 (0x4149e) |
| #define P_EMMC_B_GDESC_030 (volatile uint32_t *)((0x4149e << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_031 (0x4149f) |
| #define P_EMMC_B_GDESC_031 (volatile uint32_t *)((0x4149f << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_032 (0x414a0) |
| #define P_EMMC_B_GDESC_032 (volatile uint32_t *)((0x414a0 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_033 (0x414a1) |
| #define P_EMMC_B_GDESC_033 (volatile uint32_t *)((0x414a1 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_034 (0x414a2) |
| #define P_EMMC_B_GDESC_034 (volatile uint32_t *)((0x414a2 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_035 (0x414a3) |
| #define P_EMMC_B_GDESC_035 (volatile uint32_t *)((0x414a3 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_036 (0x414a4) |
| #define P_EMMC_B_GDESC_036 (volatile uint32_t *)((0x414a4 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_037 (0x414a5) |
| #define P_EMMC_B_GDESC_037 (volatile uint32_t *)((0x414a5 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_038 (0x414a6) |
| #define P_EMMC_B_GDESC_038 (volatile uint32_t *)((0x414a6 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_039 (0x414a7) |
| #define P_EMMC_B_GDESC_039 (volatile uint32_t *)((0x414a7 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_040 (0x414a8) |
| #define P_EMMC_B_GDESC_040 (volatile uint32_t *)((0x414a8 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_041 (0x414a9) |
| #define P_EMMC_B_GDESC_041 (volatile uint32_t *)((0x414a9 << 2) + 0xffd00000) |
| #define EMMC_B_GDESC_042 (0x414aa) |
| #define P_EMMC_B_GDESC_042 (volatile uint32_t *)((0x414aa << 2) + 0xffd00000 |
