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third-party-mirror / u-boot / ebfa12bad535ccbe7783f61b8f13e3fe260a0703 / . / arch / arm / include / asm / arch-g12a / secure_apb.h
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// ----------------------------------------------------------------------
// This file is automatically generated from the script:
//
// ./create_headers_from_register_map_h.pl
//
// and was applied to the file
//
// ./register_map.h
//
// DO NOT EDIT!!!!!
// ----------------------------------------------------------------------
//
#include <asm/arch/regs.h>
#ifdef REGISTER_H
#else
#define REGISTER_H
#endif
// ----------------------------------------------------------------------
// This file is automatically generated from the script:
//
// ./create_headers_from_secure_apb4_h.pl
//
// and was applied to the file
//
// ./secure_apb4_ee.h ./ao_rti_reg.h
//
// DO NOT EDIT!!!!!
// ----------------------------------------------------------------------
//
#ifdef SECURE_APB_H
#else
#define SECURE_APB_H
//
// Reading file: ./secure_apb4_ee.h
//
// synopsys translate_off
// synopsys translate_on
//========================================================================
// MIPI_DSI_PHY
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF644000
// APB4_DECODER_SECURE_BASE 32'hFF644000
//`define MIPI_DSI_PHY_START 8'h00
//`define MIPI_DSI_PHY_END 16'hffff
#define MIPI_DSI_PHY_CTRL (0xff644000 + (0x000 << 2))
#define SEC_MIPI_DSI_PHY_CTRL (0xff644000 + (0x000 << 2))
#define P_MIPI_DSI_PHY_CTRL (volatile uint32_t *)(0xff644000 + (0x000 << 2))
#define MIPI_DSI_CHAN_CTRL (0xff644000 + (0x001 << 2))
#define SEC_MIPI_DSI_CHAN_CTRL (0xff644000 + (0x001 << 2))
#define P_MIPI_DSI_CHAN_CTRL (volatile uint32_t *)(0xff644000 + (0x001 << 2))
#define MIPI_DSI_CHAN_STS (0xff644000 + (0x002 << 2))
#define SEC_MIPI_DSI_CHAN_STS (0xff644000 + (0x002 << 2))
#define P_MIPI_DSI_CHAN_STS (volatile uint32_t *)(0xff644000 + (0x002 << 2))
#define MIPI_DSI_CLK_TIM (0xff644000 + (0x003 << 2))
#define SEC_MIPI_DSI_CLK_TIM (0xff644000 + (0x003 << 2))
#define P_MIPI_DSI_CLK_TIM (volatile uint32_t *)(0xff644000 + (0x003 << 2))
#define MIPI_DSI_HS_TIM (0xff644000 + (0x004 << 2))
#define SEC_MIPI_DSI_HS_TIM (0xff644000 + (0x004 << 2))
#define P_MIPI_DSI_HS_TIM (volatile uint32_t *)(0xff644000 + (0x004 << 2))
#define MIPI_DSI_LP_TIM (0xff644000 + (0x005 << 2))
#define SEC_MIPI_DSI_LP_TIM (0xff644000 + (0x005 << 2))
#define P_MIPI_DSI_LP_TIM (volatile uint32_t *)(0xff644000 + (0x005 << 2))
#define MIPI_DSI_ANA_UP_TIM (0xff644000 + (0x006 << 2))
#define SEC_MIPI_DSI_ANA_UP_TIM (0xff644000 + (0x006 << 2))
#define P_MIPI_DSI_ANA_UP_TIM (volatile uint32_t *)(0xff644000 + (0x006 << 2))
#define MIPI_DSI_INIT_TIM (0xff644000 + (0x007 << 2))
#define SEC_MIPI_DSI_INIT_TIM (0xff644000 + (0x007 << 2))
#define P_MIPI_DSI_INIT_TIM (volatile uint32_t *)(0xff644000 + (0x007 << 2))
#define MIPI_DSI_WAKEUP_TIM (0xff644000 + (0x008 << 2))
#define SEC_MIPI_DSI_WAKEUP_TIM (0xff644000 + (0x008 << 2))
#define P_MIPI_DSI_WAKEUP_TIM (volatile uint32_t *)(0xff644000 + (0x008 << 2))
#define MIPI_DSI_LPOK_TIM (0xff644000 + (0x009 << 2))
#define SEC_MIPI_DSI_LPOK_TIM (0xff644000 + (0x009 << 2))
#define P_MIPI_DSI_LPOK_TIM (volatile uint32_t *)(0xff644000 + (0x009 << 2))
#define MIPI_DSI_LP_WCHDOG (0xff644000 + (0x00a << 2))
#define SEC_MIPI_DSI_LP_WCHDOG (0xff644000 + (0x00a << 2))
#define P_MIPI_DSI_LP_WCHDOG (volatile uint32_t *)(0xff644000 + (0x00a << 2))
#define MIPI_DSI_ANA_CTRL (0xff644000 + (0x00b << 2))
#define SEC_MIPI_DSI_ANA_CTRL (0xff644000 + (0x00b << 2))
#define P_MIPI_DSI_ANA_CTRL (volatile uint32_t *)(0xff644000 + (0x00b << 2))
#define MIPI_DSI_CLK_TIM1 (0xff644000 + (0x00c << 2))
#define SEC_MIPI_DSI_CLK_TIM1 (0xff644000 + (0x00c << 2))
#define P_MIPI_DSI_CLK_TIM1 (volatile uint32_t *)(0xff644000 + (0x00c << 2))
#define MIPI_DSI_TURN_WCHDOG (0xff644000 + (0x00d << 2))
#define SEC_MIPI_DSI_TURN_WCHDOG (0xff644000 + (0x00d << 2))
#define P_MIPI_DSI_TURN_WCHDOG (volatile uint32_t *)(0xff644000 + (0x00d << 2))
#define MIPI_DSI_ULPS_CHECK (0xff644000 + (0x00e << 2))
#define SEC_MIPI_DSI_ULPS_CHECK (0xff644000 + (0x00e << 2))
#define P_MIPI_DSI_ULPS_CHECK (volatile uint32_t *)(0xff644000 + (0x00e << 2))
#define MIPI_DSI_TEST_CTRL0 (0xff644000 + (0x00f << 2))
#define SEC_MIPI_DSI_TEST_CTRL0 (0xff644000 + (0x00f << 2))
#define P_MIPI_DSI_TEST_CTRL0 (volatile uint32_t *)(0xff644000 + (0x00f << 2))
#define MIPI_DSI_TEST_CTRL1 (0xff644000 + (0x010 << 2))
#define SEC_MIPI_DSI_TEST_CTRL1 (0xff644000 + (0x010 << 2))
#define P_MIPI_DSI_TEST_CTRL1 (volatile uint32_t *)(0xff644000 + (0x010 << 2))
//========================================================================
// Temp sensor PLL
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF634800
// APB4_DECODER_SECURE_BASE 32'hFF634800
#define TS_PLL_CFG_REG1 (0xff634800 + (0x001 << 2))
#define SEC_TS_PLL_CFG_REG1 (0xff634800 + (0x001 << 2))
#define P_TS_PLL_CFG_REG1 (volatile uint32_t *)(0xff634800 + (0x001 << 2))
#define TS_PLL_CFG_REG2 (0xff634800 + (0x002 << 2))
#define SEC_TS_PLL_CFG_REG2 (0xff634800 + (0x002 << 2))
#define P_TS_PLL_CFG_REG2 (volatile uint32_t *)(0xff634800 + (0x002 << 2))
#define TS_PLL_CFG_REG3 (0xff634800 + (0x003 << 2))
#define SEC_TS_PLL_CFG_REG3 (0xff634800 + (0x003 << 2))
#define P_TS_PLL_CFG_REG3 (volatile uint32_t *)(0xff634800 + (0x003 << 2))
#define TS_PLL_CFG_REG4 (0xff634800 + (0x004 << 2))
#define SEC_TS_PLL_CFG_REG4 (0xff634800 + (0x004 << 2))
#define P_TS_PLL_CFG_REG4 (volatile uint32_t *)(0xff634800 + (0x004 << 2))
#define TS_PLL_CFG_REG5 (0xff634800 + (0x005 << 2))
#define SEC_TS_PLL_CFG_REG5 (0xff634800 + (0x005 << 2))
#define P_TS_PLL_CFG_REG5 (volatile uint32_t *)(0xff634800 + (0x005 << 2))
#define TS_PLL_CFG_REG6 (0xff634800 + (0x006 << 2))
#define SEC_TS_PLL_CFG_REG6 (0xff634800 + (0x006 << 2))
#define P_TS_PLL_CFG_REG6 (volatile uint32_t *)(0xff634800 + (0x006 << 2))
#define TS_PLL_CFG_REG7 (0xff634800 + (0x007 << 2))
#define SEC_TS_PLL_CFG_REG7 (0xff634800 + (0x007 << 2))
#define P_TS_PLL_CFG_REG7 (volatile uint32_t *)(0xff634800 + (0x007 << 2))
#define TS_PLL_STAT0 (0xff634800 + (0x010 << 2))
#define SEC_TS_PLL_STAT0 (0xff634800 + (0x010 << 2))
#define P_TS_PLL_STAT0 (volatile uint32_t *)(0xff634800 + (0x010 << 2))
#define TS_PLL_STAT1 (0xff634800 + (0x011 << 2))
#define SEC_TS_PLL_STAT1 (0xff634800 + (0x011 << 2))
#define P_TS_PLL_STAT1 (volatile uint32_t *)(0xff634800 + (0x011 << 2))
#define TS_PLL_STAT2 (0xff634800 + (0x012 << 2))
#define SEC_TS_PLL_STAT2 (0xff634800 + (0x012 << 2))
#define P_TS_PLL_STAT2 (volatile uint32_t *)(0xff634800 + (0x012 << 2))
#define TS_PLL_STAT3 (0xff634800 + (0x013 << 2))
#define SEC_TS_PLL_STAT3 (0xff634800 + (0x013 << 2))
#define P_TS_PLL_STAT3 (volatile uint32_t *)(0xff634800 + (0x013 << 2))
#define TS_PLL_STAT4 (0xff634800 + (0x014 << 2))
#define SEC_TS_PLL_STAT4 (0xff634800 + (0x014 << 2))
#define P_TS_PLL_STAT4 (volatile uint32_t *)(0xff634800 + (0x014 << 2))
#define TS_PLL_STAT5 (0xff634800 + (0x015 << 2))
#define SEC_TS_PLL_STAT5 (0xff634800 + (0x015 << 2))
#define P_TS_PLL_STAT5 (volatile uint32_t *)(0xff634800 + (0x015 << 2))
#define TS_PLL_STAT6 (0xff634800 + (0x016 << 2))
#define SEC_TS_PLL_STAT6 (0xff634800 + (0x016 << 2))
#define P_TS_PLL_STAT6 (volatile uint32_t *)(0xff634800 + (0x016 << 2))
#define TS_PLL_STAT7 (0xff634800 + (0x017 << 2))
#define SEC_TS_PLL_STAT7 (0xff634800 + (0x017 << 2))
#define P_TS_PLL_STAT7 (volatile uint32_t *)(0xff634800 + (0x017 << 2))
#define TS_PLL_STAT8 (0xff634800 + (0x018 << 2))
#define SEC_TS_PLL_STAT8 (0xff634800 + (0x018 << 2))
#define P_TS_PLL_STAT8 (volatile uint32_t *)(0xff634800 + (0x018 << 2))
#define TS_PLL_STAT9 (0xff634800 + (0x019 << 2))
#define SEC_TS_PLL_STAT9 (0xff634800 + (0x019 << 2))
#define P_TS_PLL_STAT9 (volatile uint32_t *)(0xff634800 + (0x019 << 2))
//========================================================================
// Temp sensor DDR
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF634C00
// APB4_DECODER_SECURE_BASE 32'hFF634C00
#define TS_DDR_CFG_REG1 (0xff634c00 + (0x001 << 2))
#define SEC_TS_DDR_CFG_REG1 (0xff634c00 + (0x001 << 2))
#define P_TS_DDR_CFG_REG1 (volatile uint32_t *)(0xff634c00 + (0x001 << 2))
#define TS_DDR_CFG_REG2 (0xff634c00 + (0x002 << 2))
#define SEC_TS_DDR_CFG_REG2 (0xff634c00 + (0x002 << 2))
#define P_TS_DDR_CFG_REG2 (volatile uint32_t *)(0xff634c00 + (0x002 << 2))
#define TS_DDR_CFG_REG3 (0xff634c00 + (0x003 << 2))
#define SEC_TS_DDR_CFG_REG3 (0xff634c00 + (0x003 << 2))
#define P_TS_DDR_CFG_REG3 (volatile uint32_t *)(0xff634c00 + (0x003 << 2))
#define TS_DDR_CFG_REG4 (0xff634c00 + (0x004 << 2))
#define SEC_TS_DDR_CFG_REG4 (0xff634c00 + (0x004 << 2))
#define P_TS_DDR_CFG_REG4 (volatile uint32_t *)(0xff634c00 + (0x004 << 2))
#define TS_DDR_CFG_REG5 (0xff634c00 + (0x005 << 2))
#define SEC_TS_DDR_CFG_REG5 (0xff634c00 + (0x005 << 2))
#define P_TS_DDR_CFG_REG5 (volatile uint32_t *)(0xff634c00 + (0x005 << 2))
#define TS_DDR_CFG_REG6 (0xff634c00 + (0x006 << 2))
#define SEC_TS_DDR_CFG_REG6 (0xff634c00 + (0x006 << 2))
#define P_TS_DDR_CFG_REG6 (volatile uint32_t *)(0xff634c00 + (0x006 << 2))
#define TS_DDR_CFG_REG7 (0xff634c00 + (0x007 << 2))
#define SEC_TS_DDR_CFG_REG7 (0xff634c00 + (0x007 << 2))
#define P_TS_DDR_CFG_REG7 (volatile uint32_t *)(0xff634c00 + (0x007 << 2))
#define TS_DDR_STAT0 (0xff634c00 + (0x010 << 2))
#define SEC_TS_DDR_STAT0 (0xff634c00 + (0x010 << 2))
#define P_TS_DDR_STAT0 (volatile uint32_t *)(0xff634c00 + (0x010 << 2))
#define TS_DDR_STAT1 (0xff634c00 + (0x011 << 2))
#define SEC_TS_DDR_STAT1 (0xff634c00 + (0x011 << 2))
#define P_TS_DDR_STAT1 (volatile uint32_t *)(0xff634c00 + (0x011 << 2))
#define TS_DDR_STAT2 (0xff634c00 + (0x012 << 2))
#define SEC_TS_DDR_STAT2 (0xff634c00 + (0x012 << 2))
#define P_TS_DDR_STAT2 (volatile uint32_t *)(0xff634c00 + (0x012 << 2))
#define TS_DDR_STAT3 (0xff634c00 + (0x013 << 2))
#define SEC_TS_DDR_STAT3 (0xff634c00 + (0x013 << 2))
#define P_TS_DDR_STAT3 (volatile uint32_t *)(0xff634c00 + (0x013 << 2))
#define TS_DDR_STAT4 (0xff634c00 + (0x014 << 2))
#define SEC_TS_DDR_STAT4 (0xff634c00 + (0x014 << 2))
#define P_TS_DDR_STAT4 (volatile uint32_t *)(0xff634c00 + (0x014 << 2))
#define TS_DDR_STAT5 (0xff634c00 + (0x015 << 2))
#define SEC_TS_DDR_STAT5 (0xff634c00 + (0x015 << 2))
#define P_TS_DDR_STAT5 (volatile uint32_t *)(0xff634c00 + (0x015 << 2))
#define TS_DDR_STAT6 (0xff634c00 + (0x016 << 2))
#define SEC_TS_DDR_STAT6 (0xff634c00 + (0x016 << 2))
#define P_TS_DDR_STAT6 (volatile uint32_t *)(0xff634c00 + (0x016 << 2))
#define TS_DDR_STAT7 (0xff634c00 + (0x017 << 2))
#define SEC_TS_DDR_STAT7 (0xff634c00 + (0x017 << 2))
#define P_TS_DDR_STAT7 (volatile uint32_t *)(0xff634c00 + (0x017 << 2))
#define TS_DDR_STAT8 (0xff634c00 + (0x018 << 2))
#define SEC_TS_DDR_STAT8 (0xff634c00 + (0x018 << 2))
#define P_TS_DDR_STAT8 (volatile uint32_t *)(0xff634c00 + (0x018 << 2))
#define TS_DDR_STAT9 (0xff634c00 + (0x019 << 2))
#define SEC_TS_DDR_STAT9 (0xff634c00 + (0x019 << 2))
#define P_TS_DDR_STAT9 (volatile uint32_t *)(0xff634c00 + (0x019 << 2))
//========================================================================
// Temp sensor GPU
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF635000
// APB4_DECODER_SECURE_BASE 32'hFF635000
//`define TS_GPU_CFG_REG1 8'h01
//`define TS_GPU_CFG_REG2 8'h02
//`define TS_GPU_CFG_REG3 8'h03
//`define TS_GPU_CFG_REG4 8'h04
//`define TS_GPU_CFG_REG5 8'h05
//`define TS_GPU_CFG_REG6 8'h06
//`define TS_GPU_CFG_REG7 8'h07
//`define TS_GPU_STAT0 8'h10
//`define TS_GPU_STAT1 8'h11
//`define TS_GPU_STAT2 8'h12
//`define TS_GPU_STAT3 8'h13
//`define TS_GPU_STAT4 8'h14
//`define TS_GPU_STAT5 8'h15
//`define TS_GPU_STAT6 8'h16
//`define TS_GPU_STAT7 8'h17
//`define TS_GPU_STAT8 8'h18
//`define TS_GPU_STAT9 8'h19
//========================================================================
// RNG
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF634000
// APB4_DECODER_SECURE_BASE 32'hFF634000
//========================================================================
// ACODEC
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF632000
// APB4_DECODER_SECURE_BASE 32'hFF632000
#define ACODEC_0 (0xff632000 + (0x000 << 2))
#define SEC_ACODEC_0 (0xff632000 + (0x000 << 2))
#define P_ACODEC_0 (volatile uint32_t *)(0xff632000 + (0x000 << 2))
#define ACODEC_1 (0xff632000 + (0x001 << 2))
#define SEC_ACODEC_1 (0xff632000 + (0x001 << 2))
#define P_ACODEC_1 (volatile uint32_t *)(0xff632000 + (0x001 << 2))
#define ACODEC_2 (0xff632000 + (0x002 << 2))
#define SEC_ACODEC_2 (0xff632000 + (0x002 << 2))
#define P_ACODEC_2 (volatile uint32_t *)(0xff632000 + (0x002 << 2))
#define ACODEC_3 (0xff632000 + (0x003 << 2))
#define SEC_ACODEC_3 (0xff632000 + (0x003 << 2))
#define P_ACODEC_3 (volatile uint32_t *)(0xff632000 + (0x003 << 2))
#define ACODEC_4 (0xff632000 + (0x004 << 2))
#define SEC_ACODEC_4 (0xff632000 + (0x004 << 2))
#define P_ACODEC_4 (volatile uint32_t *)(0xff632000 + (0x004 << 2))
#define ACODEC_5 (0xff632000 + (0x005 << 2))
#define SEC_ACODEC_5 (0xff632000 + (0x005 << 2))
#define P_ACODEC_5 (volatile uint32_t *)(0xff632000 + (0x005 << 2))
#define ACODEC_6 (0xff632000 + (0x006 << 2))
#define SEC_ACODEC_6 (0xff632000 + (0x006 << 2))
#define P_ACODEC_6 (volatile uint32_t *)(0xff632000 + (0x006 << 2))
#define ACODEC_7 (0xff632000 + (0x007 << 2))
#define SEC_ACODEC_7 (0xff632000 + (0x007 << 2))
#define P_ACODEC_7 (volatile uint32_t *)(0xff632000 + (0x007 << 2))
//========================================================================
// AML USB PHY A
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF636000
// APB4_DECODER_SECURE_BASE 32'hFF636000
#define AMLUSB_A0 (0xff636000 + (0x000 << 2))
#define SEC_AMLUSB_A0 (0xff636000 + (0x000 << 2))
#define P_AMLUSB_A0 (volatile uint32_t *)(0xff636000 + (0x000 << 2))
#define AMLUSB_A1 (0xff636000 + (0x001 << 2))
#define SEC_AMLUSB_A1 (0xff636000 + (0x001 << 2))
#define P_AMLUSB_A1 (volatile uint32_t *)(0xff636000 + (0x001 << 2))
#define AMLUSB_A2 (0xff636000 + (0x002 << 2))
#define SEC_AMLUSB_A2 (0xff636000 + (0x002 << 2))
#define P_AMLUSB_A2 (volatile uint32_t *)(0xff636000 + (0x002 << 2))
#define AMLUSB_A3 (0xff636000 + (0x003 << 2))
#define SEC_AMLUSB_A3 (0xff636000 + (0x003 << 2))
#define P_AMLUSB_A3 (volatile uint32_t *)(0xff636000 + (0x003 << 2))
#define AMLUSB_A4 (0xff636000 + (0x004 << 2))
#define SEC_AMLUSB_A4 (0xff636000 + (0x004 << 2))
#define P_AMLUSB_A4 (volatile uint32_t *)(0xff636000 + (0x004 << 2))
#define AMLUSB_A5 (0xff636000 + (0x005 << 2))
#define SEC_AMLUSB_A5 (0xff636000 + (0x005 << 2))
#define P_AMLUSB_A5 (volatile uint32_t *)(0xff636000 + (0x005 << 2))
#define AMLUSB_A6 (0xff636000 + (0x006 << 2))
#define SEC_AMLUSB_A6 (0xff636000 + (0x006 << 2))
#define P_AMLUSB_A6 (volatile uint32_t *)(0xff636000 + (0x006 << 2))
#define AMLUSB_A7 (0xff636000 + (0x007 << 2))
#define SEC_AMLUSB_A7 (0xff636000 + (0x007 << 2))
#define P_AMLUSB_A7 (volatile uint32_t *)(0xff636000 + (0x007 << 2))
#define AMLUSB_A8 (0xff636000 + (0x008 << 2))
#define SEC_AMLUSB_A8 (0xff636000 + (0x008 << 2))
#define P_AMLUSB_A8 (volatile uint32_t *)(0xff636000 + (0x008 << 2))
#define AMLUSB_A9 (0xff636000 + (0x009 << 2))
#define SEC_AMLUSB_A9 (0xff636000 + (0x009 << 2))
#define P_AMLUSB_A9 (volatile uint32_t *)(0xff636000 + (0x009 << 2))
#define AMLUSB_A10 (0xff636000 + (0x00a << 2))
#define SEC_AMLUSB_A10 (0xff636000 + (0x00a << 2))
#define P_AMLUSB_A10 (volatile uint32_t *)(0xff636000 + (0x00a << 2))
#define AMLUSB_A11 (0xff636000 + (0x00b << 2))
#define SEC_AMLUSB_A11 (0xff636000 + (0x00b << 2))
#define P_AMLUSB_A11 (volatile uint32_t *)(0xff636000 + (0x00b << 2))
#define AMLUSB_A12 (0xff636000 + (0x00c << 2))
#define SEC_AMLUSB_A12 (0xff636000 + (0x00c << 2))
#define P_AMLUSB_A12 (volatile uint32_t *)(0xff636000 + (0x00c << 2))
#define AMLUSB_A13 (0xff636000 + (0x00d << 2))
#define SEC_AMLUSB_A13 (0xff636000 + (0x00d << 2))
#define P_AMLUSB_A13 (volatile uint32_t *)(0xff636000 + (0x00d << 2))
#define AMLUSB_A14 (0xff636000 + (0x00e << 2))
#define SEC_AMLUSB_A14 (0xff636000 + (0x00e << 2))
#define P_AMLUSB_A14 (volatile uint32_t *)(0xff636000 + (0x00e << 2))
#define AMLUSB_A15 (0xff636000 + (0x00f << 2))
#define SEC_AMLUSB_A15 (0xff636000 + (0x00f << 2))
#define P_AMLUSB_A15 (volatile uint32_t *)(0xff636000 + (0x00f << 2))
#define AMLUSB_A16 (0xff636000 + (0x010 << 2))
#define SEC_AMLUSB_A16 (0xff636000 + (0x010 << 2))
#define P_AMLUSB_A16 (volatile uint32_t *)(0xff636000 + (0x010 << 2))
#define AMLUSB_A17 (0xff636000 + (0x011 << 2))
#define SEC_AMLUSB_A17 (0xff636000 + (0x011 << 2))
#define P_AMLUSB_A17 (volatile uint32_t *)(0xff636000 + (0x011 << 2))
#define AMLUSB_A18 (0xff636000 + (0x012 << 2))
#define SEC_AMLUSB_A18 (0xff636000 + (0x012 << 2))
#define P_AMLUSB_A18 (volatile uint32_t *)(0xff636000 + (0x012 << 2))
#define AMLUSB_A19 (0xff636000 + (0x013 << 2))
#define SEC_AMLUSB_A19 (0xff636000 + (0x013 << 2))
#define P_AMLUSB_A19 (volatile uint32_t *)(0xff636000 + (0x013 << 2))
#define AMLUSB_A20 (0xff636000 + (0x014 << 2))
#define SEC_AMLUSB_A20 (0xff636000 + (0x014 << 2))
#define P_AMLUSB_A20 (volatile uint32_t *)(0xff636000 + (0x014 << 2))
#define AMLUSB_A21 (0xff636000 + (0x015 << 2))
#define SEC_AMLUSB_A21 (0xff636000 + (0x015 << 2))
#define P_AMLUSB_A21 (volatile uint32_t *)(0xff636000 + (0x015 << 2))
#define AMLUSB_A22 (0xff636000 + (0x016 << 2))
#define SEC_AMLUSB_A22 (0xff636000 + (0x016 << 2))
#define P_AMLUSB_A22 (volatile uint32_t *)(0xff636000 + (0x016 << 2))
#define AMLUSB_A23 (0xff636000 + (0x017 << 2))
#define SEC_AMLUSB_A23 (0xff636000 + (0x017 << 2))
#define P_AMLUSB_A23 (volatile uint32_t *)(0xff636000 + (0x017 << 2))
#define AMLUSB_A24 (0xff636000 + (0x018 << 2))
#define SEC_AMLUSB_A24 (0xff636000 + (0x018 << 2))
#define P_AMLUSB_A24 (volatile uint32_t *)(0xff636000 + (0x018 << 2))
#define AMLUSB_A25 (0xff636000 + (0x019 << 2))
#define SEC_AMLUSB_A25 (0xff636000 + (0x019 << 2))
#define P_AMLUSB_A25 (volatile uint32_t *)(0xff636000 + (0x019 << 2))
#define AMLUSB_A26 (0xff636000 + (0x01a << 2))
#define SEC_AMLUSB_A26 (0xff636000 + (0x01a << 2))
#define P_AMLUSB_A26 (volatile uint32_t *)(0xff636000 + (0x01a << 2))
#define AMLUSB_A27 (0xff636000 + (0x01b << 2))
#define SEC_AMLUSB_A27 (0xff636000 + (0x01b << 2))
#define P_AMLUSB_A27 (volatile uint32_t *)(0xff636000 + (0x01b << 2))
#define AMLUSB_A28 (0xff636000 + (0x01c << 2))
#define SEC_AMLUSB_A28 (0xff636000 + (0x01c << 2))
#define P_AMLUSB_A28 (volatile uint32_t *)(0xff636000 + (0x01c << 2))
#define AMLUSB_A29 (0xff636000 + (0x01d << 2))
#define SEC_AMLUSB_A29 (0xff636000 + (0x01d << 2))
#define P_AMLUSB_A29 (volatile uint32_t *)(0xff636000 + (0x01d << 2))
#define AMLUSB_A30 (0xff636000 + (0x01e << 2))
#define SEC_AMLUSB_A30 (0xff636000 + (0x01e << 2))
#define P_AMLUSB_A30 (volatile uint32_t *)(0xff636000 + (0x01e << 2))
#define AMLUSB_A31 (0xff636000 + (0x01f << 2))
#define SEC_AMLUSB_A31 (0xff636000 + (0x01f << 2))
#define P_AMLUSB_A31 (volatile uint32_t *)(0xff636000 + (0x01f << 2))
//========================================================================
// AML USB PHY B
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF63A000
// APB4_DECODER_SECURE_BASE 32'hFF63A000
#define AMLUSB_B0 (0xff63a000 + (0x000 << 2))
#define SEC_AMLUSB_B0 (0xff63a000 + (0x000 << 2))
#define P_AMLUSB_B0 (volatile uint32_t *)(0xff63a000 + (0x000 << 2))
#define AMLUSB_B1 (0xff63a000 + (0x001 << 2))
#define SEC_AMLUSB_B1 (0xff63a000 + (0x001 << 2))
#define P_AMLUSB_B1 (volatile uint32_t *)(0xff63a000 + (0x001 << 2))
#define AMLUSB_B2 (0xff63a000 + (0x002 << 2))
#define SEC_AMLUSB_B2 (0xff63a000 + (0x002 << 2))
#define P_AMLUSB_B2 (volatile uint32_t *)(0xff63a000 + (0x002 << 2))
#define AMLUSB_B3 (0xff63a000 + (0x003 << 2))
#define SEC_AMLUSB_B3 (0xff63a000 + (0x003 << 2))
#define P_AMLUSB_B3 (volatile uint32_t *)(0xff63a000 + (0x003 << 2))
#define AMLUSB_B4 (0xff63a000 + (0x004 << 2))
#define SEC_AMLUSB_B4 (0xff63a000 + (0x004 << 2))
#define P_AMLUSB_B4 (volatile uint32_t *)(0xff63a000 + (0x004 << 2))
#define AMLUSB_B5 (0xff63a000 + (0x005 << 2))
#define SEC_AMLUSB_B5 (0xff63a000 + (0x005 << 2))
#define P_AMLUSB_B5 (volatile uint32_t *)(0xff63a000 + (0x005 << 2))
#define AMLUSB_B6 (0xff63a000 + (0x006 << 2))
#define SEC_AMLUSB_B6 (0xff63a000 + (0x006 << 2))
#define P_AMLUSB_B6 (volatile uint32_t *)(0xff63a000 + (0x006 << 2))
#define AMLUSB_B7 (0xff63a000 + (0x007 << 2))
#define SEC_AMLUSB_B7 (0xff63a000 + (0x007 << 2))
#define P_AMLUSB_B7 (volatile uint32_t *)(0xff63a000 + (0x007 << 2))
#define AMLUSB_B8 (0xff63a000 + (0x008 << 2))
#define SEC_AMLUSB_B8 (0xff63a000 + (0x008 << 2))
#define P_AMLUSB_B8 (volatile uint32_t *)(0xff63a000 + (0x008 << 2))
#define AMLUSB_B9 (0xff63a000 + (0x009 << 2))
#define SEC_AMLUSB_B9 (0xff63a000 + (0x009 << 2))
#define P_AMLUSB_B9 (volatile uint32_t *)(0xff63a000 + (0x009 << 2))
#define AMLUSB_B10 (0xff63a000 + (0x00a << 2))
#define SEC_AMLUSB_B10 (0xff63a000 + (0x00a << 2))
#define P_AMLUSB_B10 (volatile uint32_t *)(0xff63a000 + (0x00a << 2))
#define AMLUSB_B11 (0xff63a000 + (0x00b << 2))
#define SEC_AMLUSB_B11 (0xff63a000 + (0x00b << 2))
#define P_AMLUSB_B11 (volatile uint32_t *)(0xff63a000 + (0x00b << 2))
#define AMLUSB_B12 (0xff63a000 + (0x00c << 2))
#define SEC_AMLUSB_B12 (0xff63a000 + (0x00c << 2))
#define P_AMLUSB_B12 (volatile uint32_t *)(0xff63a000 + (0x00c << 2))
#define AMLUSB_B13 (0xff63a000 + (0x00d << 2))
#define SEC_AMLUSB_B13 (0xff63a000 + (0x00d << 2))
#define P_AMLUSB_B13 (volatile uint32_t *)(0xff63a000 + (0x00d << 2))
#define AMLUSB_B14 (0xff63a000 + (0x00e << 2))
#define SEC_AMLUSB_B14 (0xff63a000 + (0x00e << 2))
#define P_AMLUSB_B14 (volatile uint32_t *)(0xff63a000 + (0x00e << 2))
#define AMLUSB_B15 (0xff63a000 + (0x00f << 2))
#define SEC_AMLUSB_B15 (0xff63a000 + (0x00f << 2))
#define P_AMLUSB_B15 (volatile uint32_t *)(0xff63a000 + (0x00f << 2))
#define AMLUSB_B16 (0xff63a000 + (0x010 << 2))
#define SEC_AMLUSB_B16 (0xff63a000 + (0x010 << 2))
#define P_AMLUSB_B16 (volatile uint32_t *)(0xff63a000 + (0x010 << 2))
#define AMLUSB_B17 (0xff63a000 + (0x011 << 2))
#define SEC_AMLUSB_B17 (0xff63a000 + (0x011 << 2))
#define P_AMLUSB_B17 (volatile uint32_t *)(0xff63a000 + (0x011 << 2))
#define AMLUSB_B18 (0xff63a000 + (0x012 << 2))
#define SEC_AMLUSB_B18 (0xff63a000 + (0x012 << 2))
#define P_AMLUSB_B18 (volatile uint32_t *)(0xff63a000 + (0x012 << 2))
#define AMLUSB_B19 (0xff63a000 + (0x013 << 2))
#define SEC_AMLUSB_B19 (0xff63a000 + (0x013 << 2))
#define P_AMLUSB_B19 (volatile uint32_t *)(0xff63a000 + (0x013 << 2))
#define AMLUSB_B20 (0xff63a000 + (0x014 << 2))
#define SEC_AMLUSB_B20 (0xff63a000 + (0x014 << 2))
#define P_AMLUSB_B20 (volatile uint32_t *)(0xff63a000 + (0x014 << 2))
#define AMLUSB_B21 (0xff63a000 + (0x015 << 2))
#define SEC_AMLUSB_B21 (0xff63a000 + (0x015 << 2))
#define P_AMLUSB_B21 (volatile uint32_t *)(0xff63a000 + (0x015 << 2))
#define AMLUSB_B22 (0xff63a000 + (0x016 << 2))
#define SEC_AMLUSB_B22 (0xff63a000 + (0x016 << 2))
#define P_AMLUSB_B22 (volatile uint32_t *)(0xff63a000 + (0x016 << 2))
#define AMLUSB_B23 (0xff63a000 + (0x017 << 2))
#define SEC_AMLUSB_B23 (0xff63a000 + (0x017 << 2))
#define P_AMLUSB_B23 (volatile uint32_t *)(0xff63a000 + (0x017 << 2))
#define AMLUSB_B24 (0xff63a000 + (0x018 << 2))
#define SEC_AMLUSB_B24 (0xff63a000 + (0x018 << 2))
#define P_AMLUSB_B24 (volatile uint32_t *)(0xff63a000 + (0x018 << 2))
#define AMLUSB_B25 (0xff63a000 + (0x019 << 2))
#define SEC_AMLUSB_B25 (0xff63a000 + (0x019 << 2))
#define P_AMLUSB_B25 (volatile uint32_t *)(0xff63a000 + (0x019 << 2))
#define AMLUSB_B26 (0xff63a000 + (0x01a << 2))
#define SEC_AMLUSB_B26 (0xff63a000 + (0x01a << 2))
#define P_AMLUSB_B26 (volatile uint32_t *)(0xff63a000 + (0x01a << 2))
#define AMLUSB_B27 (0xff63a000 + (0x01b << 2))
#define SEC_AMLUSB_B27 (0xff63a000 + (0x01b << 2))
#define P_AMLUSB_B27 (volatile uint32_t *)(0xff63a000 + (0x01b << 2))
#define AMLUSB_B28 (0xff63a000 + (0x01c << 2))
#define SEC_AMLUSB_B28 (0xff63a000 + (0x01c << 2))
#define P_AMLUSB_B28 (volatile uint32_t *)(0xff63a000 + (0x01c << 2))
#define AMLUSB_B29 (0xff63a000 + (0x01d << 2))
#define SEC_AMLUSB_B29 (0xff63a000 + (0x01d << 2))
#define P_AMLUSB_B29 (volatile uint32_t *)(0xff63a000 + (0x01d << 2))
#define AMLUSB_B30 (0xff63a000 + (0x01e << 2))
#define SEC_AMLUSB_B30 (0xff63a000 + (0x01e << 2))
#define P_AMLUSB_B30 (volatile uint32_t *)(0xff63a000 + (0x01e << 2))
#define AMLUSB_B31 (0xff63a000 + (0x01f << 2))
#define SEC_AMLUSB_B31 (0xff63a000 + (0x01f << 2))
#define P_AMLUSB_B31 (volatile uint32_t *)(0xff63a000 + (0x01f << 2))
//========================================================================
// PERIPHS
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF634400
// APB4_DECODER_SECURE_BASE 32'hFF634400
// The following are handled by $periphs/rtl/periphs_reg.v
//`define PREG_CTLREG0_ADDR 8'h00
// ----------------------------
// ----------------------------
//`define PREG_JTAG_GPIO_ADDR 8'h0b // DWORD base address (0xc120002c >> 2)
// ----------------------------
// Pre-defined GPIO addresses
// ----------------------------
#define PREG_PAD_GPIO0_EN_N (0xff634400 + (0x010 << 2))
#define SEC_PREG_PAD_GPIO0_EN_N (0xff634400 + (0x010 << 2))
#define P_PREG_PAD_GPIO0_EN_N (volatile uint32_t *)(0xff634400 + (0x010 << 2))
#define PREG_PAD_GPIO0_O (0xff634400 + (0x011 << 2))
#define SEC_PREG_PAD_GPIO0_O (0xff634400 + (0x011 << 2))
#define P_PREG_PAD_GPIO0_O (volatile uint32_t *)(0xff634400 + (0x011 << 2))
#define PREG_PAD_GPIO0_I (0xff634400 + (0x012 << 2))
#define SEC_PREG_PAD_GPIO0_I (0xff634400 + (0x012 << 2))
#define P_PREG_PAD_GPIO0_I (volatile uint32_t *)(0xff634400 + (0x012 << 2))
// ----------------------------
#define PREG_PAD_GPIO1_EN_N (0xff634400 + (0x013 << 2))
#define SEC_PREG_PAD_GPIO1_EN_N (0xff634400 + (0x013 << 2))
#define P_PREG_PAD_GPIO1_EN_N (volatile uint32_t *)(0xff634400 + (0x013 << 2))
#define PREG_PAD_GPIO1_O (0xff634400 + (0x014 << 2))
#define SEC_PREG_PAD_GPIO1_O (0xff634400 + (0x014 << 2))
#define P_PREG_PAD_GPIO1_O (volatile uint32_t *)(0xff634400 + (0x014 << 2))
#define PREG_PAD_GPIO1_I (0xff634400 + (0x015 << 2))
#define SEC_PREG_PAD_GPIO1_I (0xff634400 + (0x015 << 2))
#define P_PREG_PAD_GPIO1_I (volatile uint32_t *)(0xff634400 + (0x015 << 2))
// ----------------------------
#define PREG_PAD_GPIO2_EN_N (0xff634400 + (0x016 << 2))
#define SEC_PREG_PAD_GPIO2_EN_N (0xff634400 + (0x016 << 2))
#define P_PREG_PAD_GPIO2_EN_N (volatile uint32_t *)(0xff634400 + (0x016 << 2))
#define PREG_PAD_GPIO2_O (0xff634400 + (0x017 << 2))
#define SEC_PREG_PAD_GPIO2_O (0xff634400 + (0x017 << 2))
#define P_PREG_PAD_GPIO2_O (volatile uint32_t *)(0xff634400 + (0x017 << 2))
#define PREG_PAD_GPIO2_I (0xff634400 + (0x018 << 2))
#define SEC_PREG_PAD_GPIO2_I (0xff634400 + (0x018 << 2))
#define P_PREG_PAD_GPIO2_I (volatile uint32_t *)(0xff634400 + (0x018 << 2))
// ----------------------------
#define PREG_PAD_GPIO3_EN_N (0xff634400 + (0x019 << 2))
#define SEC_PREG_PAD_GPIO3_EN_N (0xff634400 + (0x019 << 2))
#define P_PREG_PAD_GPIO3_EN_N (volatile uint32_t *)(0xff634400 + (0x019 << 2))
#define PREG_PAD_GPIO3_O (0xff634400 + (0x01a << 2))
#define SEC_PREG_PAD_GPIO3_O (0xff634400 + (0x01a << 2))
#define P_PREG_PAD_GPIO3_O (volatile uint32_t *)(0xff634400 + (0x01a << 2))
#define PREG_PAD_GPIO3_I (0xff634400 + (0x01b << 2))
#define SEC_PREG_PAD_GPIO3_I (0xff634400 + (0x01b << 2))
#define P_PREG_PAD_GPIO3_I (volatile uint32_t *)(0xff634400 + (0x01b << 2))
// ----------------------------
#define PREG_PAD_GPIO4_EN_N (0xff634400 + (0x01c << 2))
#define SEC_PREG_PAD_GPIO4_EN_N (0xff634400 + (0x01c << 2))
#define P_PREG_PAD_GPIO4_EN_N (volatile uint32_t *)(0xff634400 + (0x01c << 2))
#define PREG_PAD_GPIO4_O (0xff634400 + (0x01d << 2))
#define SEC_PREG_PAD_GPIO4_O (0xff634400 + (0x01d << 2))
#define P_PREG_PAD_GPIO4_O (volatile uint32_t *)(0xff634400 + (0x01d << 2))
#define PREG_PAD_GPIO4_I (0xff634400 + (0x01e << 2))
#define SEC_PREG_PAD_GPIO4_I (0xff634400 + (0x01e << 2))
#define P_PREG_PAD_GPIO4_I (volatile uint32_t *)(0xff634400 + (0x01e << 2))
// ----------------------------
#define PREG_PAD_GPIO5_EN_N (0xff634400 + (0x020 << 2))
#define SEC_PREG_PAD_GPIO5_EN_N (0xff634400 + (0x020 << 2))
#define P_PREG_PAD_GPIO5_EN_N (volatile uint32_t *)(0xff634400 + (0x020 << 2))
#define PREG_PAD_GPIO5_O (0xff634400 + (0x021 << 2))
#define SEC_PREG_PAD_GPIO5_O (0xff634400 + (0x021 << 2))
#define P_PREG_PAD_GPIO5_O (volatile uint32_t *)(0xff634400 + (0x021 << 2))
#define PREG_PAD_GPIO5_I (0xff634400 + (0x022 << 2))
#define SEC_PREG_PAD_GPIO5_I (0xff634400 + (0x022 << 2))
#define P_PREG_PAD_GPIO5_I (volatile uint32_t *)(0xff634400 + (0x022 << 2))
// ----------------------------
// ----------------------------
// Pad conntrols
// ----------------------------
//`define PAD_PULL_UP_REG6 8'h39
#define PAD_PULL_UP_REG0 (0xff634400 + (0x03a << 2))
#define SEC_PAD_PULL_UP_REG0 (0xff634400 + (0x03a << 2))
#define P_PAD_PULL_UP_REG0 (volatile uint32_t *)(0xff634400 + (0x03a << 2))
#define PAD_PULL_UP_REG1 (0xff634400 + (0x03b << 2))
#define SEC_PAD_PULL_UP_REG1 (0xff634400 + (0x03b << 2))
#define P_PAD_PULL_UP_REG1 (volatile uint32_t *)(0xff634400 + (0x03b << 2))
#define PAD_PULL_UP_REG2 (0xff634400 + (0x03c << 2))
#define SEC_PAD_PULL_UP_REG2 (0xff634400 + (0x03c << 2))
#define P_PAD_PULL_UP_REG2 (volatile uint32_t *)(0xff634400 + (0x03c << 2))
#define PAD_PULL_UP_REG3 (0xff634400 + (0x03d << 2))
#define SEC_PAD_PULL_UP_REG3 (0xff634400 + (0x03d << 2))
#define P_PAD_PULL_UP_REG3 (volatile uint32_t *)(0xff634400 + (0x03d << 2))
#define PAD_PULL_UP_REG4 (0xff634400 + (0x03e << 2))
#define SEC_PAD_PULL_UP_REG4 (0xff634400 + (0x03e << 2))
#define P_PAD_PULL_UP_REG4 (volatile uint32_t *)(0xff634400 + (0x03e << 2))
#define PAD_PULL_UP_REG5 (0xff634400 + (0x03f << 2))
#define SEC_PAD_PULL_UP_REG5 (0xff634400 + (0x03f << 2))
#define P_PAD_PULL_UP_REG5 (volatile uint32_t *)(0xff634400 + (0x03f << 2))
// ----------------------------
// Random (2)
// ----------------------------
//`define RAND64_ADDR0 8'h40 // DWORD base address (0xc1200138 >> 2)
//`define RAND64_ADDR1 8'h41 // DWORD base address (0xc120013c >> 2)
// ---------------------------
// Ethernet (1)
// ----------------------------
//`define PREG_ETHERNET_ADDR0 8'h42 // DWORD base address (0xc1200290 >> 2)
// ---------------------------
// AM_ANALOG_TOP
// ----------------------------
//`define PREG_AM_ANALOG_ADDR 8'h43 // DWORD base address (0xc1200298 >> 2)
// ---------------------------
// Mali55 (1)
// ----------------------------
//`define PREG_MALI_BYTE_CNTL 8'h44
// ---------------------------
// WIFI (1)
// ----------------------------
//`define PREG_WIFI_CNTL 8'h45
#define PAD_PULL_UP_EN_REG0 (0xff634400 + (0x048 << 2))
#define SEC_PAD_PULL_UP_EN_REG0 (0xff634400 + (0x048 << 2))
#define P_PAD_PULL_UP_EN_REG0 (volatile uint32_t *)(0xff634400 + (0x048 << 2))
#define PAD_PULL_UP_EN_REG1 (0xff634400 + (0x049 << 2))
#define SEC_PAD_PULL_UP_EN_REG1 (0xff634400 + (0x049 << 2))
#define P_PAD_PULL_UP_EN_REG1 (volatile uint32_t *)(0xff634400 + (0x049 << 2))
#define PAD_PULL_UP_EN_REG2 (0xff634400 + (0x04a << 2))
#define SEC_PAD_PULL_UP_EN_REG2 (0xff634400 + (0x04a << 2))
#define P_PAD_PULL_UP_EN_REG2 (volatile uint32_t *)(0xff634400 + (0x04a << 2))
#define PAD_PULL_UP_EN_REG3 (0xff634400 + (0x04b << 2))
#define SEC_PAD_PULL_UP_EN_REG3 (0xff634400 + (0x04b << 2))
#define P_PAD_PULL_UP_EN_REG3 (volatile uint32_t *)(0xff634400 + (0x04b << 2))
#define PAD_PULL_UP_EN_REG4 (0xff634400 + (0x04c << 2))
#define SEC_PAD_PULL_UP_EN_REG4 (0xff634400 + (0x04c << 2))
#define P_PAD_PULL_UP_EN_REG4 (volatile uint32_t *)(0xff634400 + (0x04c << 2))
#define PAD_PULL_UP_EN_REG5 (0xff634400 + (0x04d << 2))
#define SEC_PAD_PULL_UP_EN_REG5 (0xff634400 + (0x04d << 2))
#define P_PAD_PULL_UP_EN_REG5 (volatile uint32_t *)(0xff634400 + (0x04d << 2))
//`define PAD_PULL_UP_EN_REG6 8'h4e
// ---------------------------
#define PREG_ETH_REG0 (0xff634400 + (0x050 << 2))
#define SEC_PREG_ETH_REG0 (0xff634400 + (0x050 << 2))
#define P_PREG_ETH_REG0 (volatile uint32_t *)(0xff634400 + (0x050 << 2))
#define PREG_ETH_REG1 (0xff634400 + (0x051 << 2))
#define SEC_PREG_ETH_REG1 (0xff634400 + (0x051 << 2))
#define P_PREG_ETH_REG1 (volatile uint32_t *)(0xff634400 + (0x051 << 2))
#define PREG_NAND_CFG_KEY0 (0xff634400 + (0x052 << 2))
#define SEC_PREG_NAND_CFG_KEY0 (0xff634400 + (0x052 << 2))
#define P_PREG_NAND_CFG_KEY0 (volatile uint32_t *)(0xff634400 + (0x052 << 2))
#define PREG_NAND_CFG_KEY1 (0xff634400 + (0x053 << 2))
#define SEC_PREG_NAND_CFG_KEY1 (0xff634400 + (0x053 << 2))
#define P_PREG_NAND_CFG_KEY1 (volatile uint32_t *)(0xff634400 + (0x053 << 2))
#define PREG_VPU_SECURE0 (0xff634400 + (0x054 << 2))
#define SEC_PREG_VPU_SECURE0 (0xff634400 + (0x054 << 2))
#define P_PREG_VPU_SECURE0 (volatile uint32_t *)(0xff634400 + (0x054 << 2))
#define PREG_VPU_SECURE1 (0xff634400 + (0x055 << 2))
#define SEC_PREG_VPU_SECURE1 (0xff634400 + (0x055 << 2))
#define P_PREG_VPU_SECURE1 (volatile uint32_t *)(0xff634400 + (0x055 << 2))
#define PREG_ETH_REG2 (0xff634400 + (0x056 << 2))
#define SEC_PREG_ETH_REG2 (0xff634400 + (0x056 << 2))
#define P_PREG_ETH_REG2 (volatile uint32_t *)(0xff634400 + (0x056 << 2))
#define PREG_ETH_REG3 (0xff634400 + (0x057 << 2))
#define SEC_PREG_ETH_REG3 (0xff634400 + (0x057 << 2))
#define P_PREG_ETH_REG3 (volatile uint32_t *)(0xff634400 + (0x057 << 2))
#define PREG_ETH_REG4 (0xff634400 + (0x058 << 2))
#define SEC_PREG_ETH_REG4 (0xff634400 + (0x058 << 2))
#define P_PREG_ETH_REG4 (volatile uint32_t *)(0xff634400 + (0x058 << 2))
// ---------------------------
// Generic production test
// ----------------------------
#define PROD_TEST_REG0 (0xff634400 + (0x060 << 2))
#define SEC_PROD_TEST_REG0 (0xff634400 + (0x060 << 2))
#define P_PROD_TEST_REG0 (volatile uint32_t *)(0xff634400 + (0x060 << 2))
#define PROD_TEST_REG1 (0xff634400 + (0x061 << 2))
#define SEC_PROD_TEST_REG1 (0xff634400 + (0x061 << 2))
#define P_PROD_TEST_REG1 (volatile uint32_t *)(0xff634400 + (0x061 << 2))
#define PROD_TEST_REG2 (0xff634400 + (0x062 << 2))
#define SEC_PROD_TEST_REG2 (0xff634400 + (0x062 << 2))
#define P_PROD_TEST_REG2 (volatile uint32_t *)(0xff634400 + (0x062 << 2))
#define PROD_TEST_REG3 (0xff634400 + (0x063 << 2))
#define SEC_PROD_TEST_REG3 (0xff634400 + (0x063 << 2))
#define P_PROD_TEST_REG3 (volatile uint32_t *)(0xff634400 + (0x063 << 2))
// am_analog_top
// ----------------------------
//`define METAL_REVISION 8'h6a
//`define ADC_TOP_MISC 8'h6b
//`define DPLL_TOP_MISC 8'h6c
//`define ANALOG_TOP_MISC 8'h6d
//`define AM_ANALOG_TOP_REG0 8'h6e
//`define AM_ANALOG_TOP_REG1 8'h6f
// ---------------------------
// Sticky regs
// ----------------------------
#define PREG_STICKY_REG0 (0xff634400 + (0x070 << 2))
#define SEC_PREG_STICKY_REG0 (0xff634400 + (0x070 << 2))
#define P_PREG_STICKY_REG0 (volatile uint32_t *)(0xff634400 + (0x070 << 2))
#define PREG_STICKY_REG1 (0xff634400 + (0x071 << 2))
#define SEC_PREG_STICKY_REG1 (0xff634400 + (0x071 << 2))
#define P_PREG_STICKY_REG1 (volatile uint32_t *)(0xff634400 + (0x071 << 2))
#define PREG_STICKY_REG2 (0xff634400 + (0x072 << 2))
#define SEC_PREG_STICKY_REG2 (0xff634400 + (0x072 << 2))
#define P_PREG_STICKY_REG2 (volatile uint32_t *)(0xff634400 + (0x072 << 2))
#define PREG_STICKY_REG3 (0xff634400 + (0x073 << 2))
#define SEC_PREG_STICKY_REG3 (0xff634400 + (0x073 << 2))
#define P_PREG_STICKY_REG3 (volatile uint32_t *)(0xff634400 + (0x073 << 2))
#define PREG_STICKY_REG4 (0xff634400 + (0x074 << 2))
#define SEC_PREG_STICKY_REG4 (0xff634400 + (0x074 << 2))
#define P_PREG_STICKY_REG4 (volatile uint32_t *)(0xff634400 + (0x074 << 2))
#define PREG_STICKY_REG5 (0xff634400 + (0x075 << 2))
#define SEC_PREG_STICKY_REG5 (0xff634400 + (0x075 << 2))
#define P_PREG_STICKY_REG5 (volatile uint32_t *)(0xff634400 + (0x075 << 2))
#define PREG_STICKY_REG6 (0xff634400 + (0x076 << 2))
#define SEC_PREG_STICKY_REG6 (0xff634400 + (0x076 << 2))
#define P_PREG_STICKY_REG6 (volatile uint32_t *)(0xff634400 + (0x076 << 2))
#define PREG_STICKY_REG7 (0xff634400 + (0x077 << 2))
#define SEC_PREG_STICKY_REG7 (0xff634400 + (0x077 << 2))
#define P_PREG_STICKY_REG7 (volatile uint32_t *)(0xff634400 + (0x077 << 2))
#define PREG_STICKY_REG8 (0xff634400 + (0x078 << 2))
#define SEC_PREG_STICKY_REG8 (0xff634400 + (0x078 << 2))
#define P_PREG_STICKY_REG8 (volatile uint32_t *)(0xff634400 + (0x078 << 2))
#define PREG_STICKY_REG9 (0xff634400 + (0x079 << 2))
#define SEC_PREG_STICKY_REG9 (0xff634400 + (0x079 << 2))
#define P_PREG_STICKY_REG9 (volatile uint32_t *)(0xff634400 + (0x079 << 2))
//`define PREG_WRITE_ONCE_REG 8'h7e
// ---------------------------
// AM Ring Oscillator
// ----------------------------
#define AM_RING_OSC_REG0 (0xff634400 + (0x07f << 2))
#define SEC_AM_RING_OSC_REG0 (0xff634400 + (0x07f << 2))
#define P_AM_RING_OSC_REG0 (volatile uint32_t *)(0xff634400 + (0x07f << 2))
// Control whether to provide random number to HDMITX20
//`define HDMITX20_RNDNUM 8'h80
// ---------------------------
// Bus Monitoring
// ----------------------------
#define BUS_MONITOR_CNTL (0xff634400 + (0x081 << 2))
#define SEC_BUS_MONITOR_CNTL (0xff634400 + (0x081 << 2))
#define P_BUS_MONITOR_CNTL (volatile uint32_t *)(0xff634400 + (0x081 << 2))
#define BUS_MON0_ADDR (0xff634400 + (0x082 << 2))
#define SEC_BUS_MON0_ADDR (0xff634400 + (0x082 << 2))
#define P_BUS_MON0_ADDR (volatile uint32_t *)(0xff634400 + (0x082 << 2))
#define BUS_MON0_DATA (0xff634400 + (0x083 << 2))
#define SEC_BUS_MON0_DATA (0xff634400 + (0x083 << 2))
#define P_BUS_MON0_DATA (volatile uint32_t *)(0xff634400 + (0x083 << 2))
#define BUS_MON0_DATA_MSK (0xff634400 + (0x084 << 2))
#define SEC_BUS_MON0_DATA_MSK (0xff634400 + (0x084 << 2))
#define P_BUS_MON0_DATA_MSK (volatile uint32_t *)(0xff634400 + (0x084 << 2))
#define BUS_MON1_ADDR (0xff634400 + (0x085 << 2))
#define SEC_BUS_MON1_ADDR (0xff634400 + (0x085 << 2))
#define P_BUS_MON1_ADDR (volatile uint32_t *)(0xff634400 + (0x085 << 2))
#define BUS_MON1_DATA (0xff634400 + (0x086 << 2))
#define SEC_BUS_MON1_DATA (0xff634400 + (0x086 << 2))
#define P_BUS_MON1_DATA (volatile uint32_t *)(0xff634400 + (0x086 << 2))
#define BUS_MON1_DATA_MSK (0xff634400 + (0x087 << 2))
#define SEC_BUS_MON1_DATA_MSK (0xff634400 + (0x087 << 2))
#define P_BUS_MON1_DATA_MSK (volatile uint32_t *)(0xff634400 + (0x087 << 2))
#define ASYNC_FIFO_LOCK_ADR (0xff634400 + (0x088 << 2))
#define SEC_ASYNC_FIFO_LOCK_ADR (0xff634400 + (0x088 << 2))
#define P_ASYNC_FIFO_LOCK_ADR (volatile uint32_t *)(0xff634400 + (0x088 << 2))
#define SECE_TIMER_CTRL (0xff634400 + (0x089 << 2))
#define SEC_SECE_TIMER_CTRL (0xff634400 + (0x089 << 2))
#define P_SECE_TIMER_CTRL (volatile uint32_t *)(0xff634400 + (0x089 << 2))
#define SECE_TIMER_LOW (0xff634400 + (0x08a << 2))
#define SEC_SECE_TIMER_LOW (0xff634400 + (0x08a << 2))
#define P_SECE_TIMER_LOW (volatile uint32_t *)(0xff634400 + (0x08a << 2))
#define SECE_TIMER_HIG (0xff634400 + (0x08b << 2))
#define SEC_SECE_TIMER_HIG (0xff634400 + (0x08b << 2))
#define P_SECE_TIMER_HIG (volatile uint32_t *)(0xff634400 + (0x08b << 2))
// ---------------------------
// System CPU control registers
// ----------------------------
#define SYS_CPU_POR_CFG0 (0xff634400 + (0x090 << 2))
#define SEC_SYS_CPU_POR_CFG0 (0xff634400 + (0x090 << 2))
#define P_SYS_CPU_POR_CFG0 (volatile uint32_t *)(0xff634400 + (0x090 << 2))
#define SYS_CPU_POR_CFG1 (0xff634400 + (0x091 << 2))
#define SEC_SYS_CPU_POR_CFG1 (0xff634400 + (0x091 << 2))
#define P_SYS_CPU_POR_CFG1 (volatile uint32_t *)(0xff634400 + (0x091 << 2))
#define SYS_CPU_CFG0 (0xff634400 + (0x092 << 2))
#define SEC_SYS_CPU_CFG0 (0xff634400 + (0x092 << 2))
#define P_SYS_CPU_CFG0 (volatile uint32_t *)(0xff634400 + (0x092 << 2))
#define SYS_CPU_CFG1 (0xff634400 + (0x093 << 2))
#define SEC_SYS_CPU_CFG1 (0xff634400 + (0x093 << 2))
#define P_SYS_CPU_CFG1 (volatile uint32_t *)(0xff634400 + (0x093 << 2))
#define SYS_CPU_CFG2 (0xff634400 + (0x094 << 2))
#define SEC_SYS_CPU_CFG2 (0xff634400 + (0x094 << 2))
#define P_SYS_CPU_CFG2 (volatile uint32_t *)(0xff634400 + (0x094 << 2))
#define SYS_CPU_CFG3 (0xff634400 + (0x095 << 2))
#define SEC_SYS_CPU_CFG3 (0xff634400 + (0x095 << 2))
#define P_SYS_CPU_CFG3 (volatile uint32_t *)(0xff634400 + (0x095 << 2))
#define SYS_CPU_CFG4 (0xff634400 + (0x096 << 2))
#define SEC_SYS_CPU_CFG4 (0xff634400 + (0x096 << 2))
#define P_SYS_CPU_CFG4 (volatile uint32_t *)(0xff634400 + (0x096 << 2))
#define SYS_CPU_CFG5 (0xff634400 + (0x097 << 2))
#define SEC_SYS_CPU_CFG5 (0xff634400 + (0x097 << 2))
#define P_SYS_CPU_CFG5 (volatile uint32_t *)(0xff634400 + (0x097 << 2))
#define SYS_CPU_CFG6 (0xff634400 + (0x098 << 2))
#define SEC_SYS_CPU_CFG6 (0xff634400 + (0x098 << 2))
#define P_SYS_CPU_CFG6 (volatile uint32_t *)(0xff634400 + (0x098 << 2))
#define SYS_CPU_CFG7 (0xff634400 + (0x099 << 2))
#define SEC_SYS_CPU_CFG7 (0xff634400 + (0x099 << 2))
#define P_SYS_CPU_CFG7 (volatile uint32_t *)(0xff634400 + (0x099 << 2))
#define SYS_CPU_CFG8 (0xff634400 + (0x09a << 2))
#define SEC_SYS_CPU_CFG8 (0xff634400 + (0x09a << 2))
#define P_SYS_CPU_CFG8 (volatile uint32_t *)(0xff634400 + (0x09a << 2))
#define SYS_CPU_CFG9 (0xff634400 + (0x09b << 2))
#define SEC_SYS_CPU_CFG9 (0xff634400 + (0x09b << 2))
#define P_SYS_CPU_CFG9 (volatile uint32_t *)(0xff634400 + (0x09b << 2))
#define SYS_CPU_CFG10 (0xff634400 + (0x09c << 2))
#define SEC_SYS_CPU_CFG10 (0xff634400 + (0x09c << 2))
#define P_SYS_CPU_CFG10 (volatile uint32_t *)(0xff634400 + (0x09c << 2))
//`define SYS_CPU_CFG11 8'h9d
//`define SYS_CPU_CFG12 8'h9e
//`define SYS_CPU_CFG13 8'h9f
#define SYS_CPU_STATUS0 (0xff634400 + (0x0a0 << 2))
#define SEC_SYS_CPU_STATUS0 (0xff634400 + (0x0a0 << 2))
#define P_SYS_CPU_STATUS0 (volatile uint32_t *)(0xff634400 + (0x0a0 << 2))
#define SYS_CPU_STATUS1 (0xff634400 + (0x0a1 << 2))
#define SEC_SYS_CPU_STATUS1 (0xff634400 + (0x0a1 << 2))
#define P_SYS_CPU_STATUS1 (volatile uint32_t *)(0xff634400 + (0x0a1 << 2))
#define SYS_CPU_STATUS2 (0xff634400 + (0x0a2 << 2))
#define SEC_SYS_CPU_STATUS2 (0xff634400 + (0x0a2 << 2))
#define P_SYS_CPU_STATUS2 (volatile uint32_t *)(0xff634400 + (0x0a2 << 2))
#define SYS_CPU_STATUS3 (0xff634400 + (0x0a3 << 2))
#define SEC_SYS_CPU_STATUS3 (0xff634400 + (0x0a3 << 2))
#define P_SYS_CPU_STATUS3 (volatile uint32_t *)(0xff634400 + (0x0a3 << 2))
#define SYS_CPU_STATUS4 (0xff634400 + (0x0a4 << 2))
#define SEC_SYS_CPU_STATUS4 (0xff634400 + (0x0a4 << 2))
#define P_SYS_CPU_STATUS4 (volatile uint32_t *)(0xff634400 + (0x0a4 << 2))
#define SYS_CPU_STATUS5 (0xff634400 + (0x0a5 << 2))
#define SEC_SYS_CPU_STATUS5 (0xff634400 + (0x0a5 << 2))
#define P_SYS_CPU_STATUS5 (volatile uint32_t *)(0xff634400 + (0x0a5 << 2))
#define SYS_CPU_MISC (0xff634400 + (0x0a8 << 2))
#define SEC_SYS_CPU_MISC (0xff634400 + (0x0a8 << 2))
#define P_SYS_CPU_MISC (volatile uint32_t *)(0xff634400 + (0x0a8 << 2))
// ----------------------------
// Pin Mux (9)
// ----------------------------
#define PERIPHS_LOCK_PAD (0xff634400 + (0x0ae << 2))
#define SEC_PERIPHS_LOCK_PAD (0xff634400 + (0x0ae << 2))
#define P_PERIPHS_LOCK_PAD (volatile uint32_t *)(0xff634400 + (0x0ae << 2))
#define PERIPHS_LOCK_PIN_MUX (0xff634400 + (0x0af << 2))
#define SEC_PERIPHS_LOCK_PIN_MUX (0xff634400 + (0x0af << 2))
#define P_PERIPHS_LOCK_PIN_MUX (volatile uint32_t *)(0xff634400 + (0x0af << 2))
#define PERIPHS_PIN_MUX_0 (0xff634400 + (0x0b0 << 2))
#define SEC_PERIPHS_PIN_MUX_0 (0xff634400 + (0x0b0 << 2))
#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(0xff634400 + (0x0b0 << 2))
#define PERIPHS_PIN_MUX_1 (0xff634400 + (0x0b1 << 2))
#define SEC_PERIPHS_PIN_MUX_1 (0xff634400 + (0x0b1 << 2))
#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(0xff634400 + (0x0b1 << 2))
#define PERIPHS_PIN_MUX_2 (0xff634400 + (0x0b2 << 2))
#define SEC_PERIPHS_PIN_MUX_2 (0xff634400 + (0x0b2 << 2))
#define P_PERIPHS_PIN_MUX_2 (volatile uint32_t *)(0xff634400 + (0x0b2 << 2))
#define PERIPHS_PIN_MUX_3 (0xff634400 + (0x0b3 << 2))
#define SEC_PERIPHS_PIN_MUX_3 (0xff634400 + (0x0b3 << 2))
#define P_PERIPHS_PIN_MUX_3 (volatile uint32_t *)(0xff634400 + (0x0b3 << 2))
#define PERIPHS_PIN_MUX_4 (0xff634400 + (0x0b4 << 2))
#define SEC_PERIPHS_PIN_MUX_4 (0xff634400 + (0x0b4 << 2))
#define P_PERIPHS_PIN_MUX_4 (volatile uint32_t *)(0xff634400 + (0x0b4 << 2))
#define PERIPHS_PIN_MUX_5 (0xff634400 + (0x0b5 << 2))
#define SEC_PERIPHS_PIN_MUX_5 (0xff634400 + (0x0b5 << 2))
#define P_PERIPHS_PIN_MUX_5 (volatile uint32_t *)(0xff634400 + (0x0b5 << 2))
#define PERIPHS_PIN_MUX_6 (0xff634400 + (0x0b6 << 2))
#define SEC_PERIPHS_PIN_MUX_6 (0xff634400 + (0x0b6 << 2))
#define P_PERIPHS_PIN_MUX_6 (volatile uint32_t *)(0xff634400 + (0x0b6 << 2))
#define PERIPHS_PIN_MUX_7 (0xff634400 + (0x0b7 << 2))
#define SEC_PERIPHS_PIN_MUX_7 (0xff634400 + (0x0b7 << 2))
#define P_PERIPHS_PIN_MUX_7 (volatile uint32_t *)(0xff634400 + (0x0b7 << 2))
#define PERIPHS_PIN_MUX_8 (0xff634400 + (0x0b8 << 2))
#define SEC_PERIPHS_PIN_MUX_8 (0xff634400 + (0x0b8 << 2))
#define P_PERIPHS_PIN_MUX_8 (volatile uint32_t *)(0xff634400 + (0x0b8 << 2))
#define PERIPHS_PIN_MUX_9 (0xff634400 + (0x0b9 << 2))
#define SEC_PERIPHS_PIN_MUX_9 (0xff634400 + (0x0b9 << 2))
#define P_PERIPHS_PIN_MUX_9 (volatile uint32_t *)(0xff634400 + (0x0b9 << 2))
#define PERIPHS_PIN_MUX_A (0xff634400 + (0x0ba << 2))
#define SEC_PERIPHS_PIN_MUX_A (0xff634400 + (0x0ba << 2))
#define P_PERIPHS_PIN_MUX_A (volatile uint32_t *)(0xff634400 + (0x0ba << 2))
#define PERIPHS_PIN_MUX_B (0xff634400 + (0x0bb << 2))
#define SEC_PERIPHS_PIN_MUX_B (0xff634400 + (0x0bb << 2))
#define P_PERIPHS_PIN_MUX_B (volatile uint32_t *)(0xff634400 + (0x0bb << 2))
#define PERIPHS_PIN_MUX_C (0xff634400 + (0x0bc << 2))
#define SEC_PERIPHS_PIN_MUX_C (0xff634400 + (0x0bc << 2))
#define P_PERIPHS_PIN_MUX_C (volatile uint32_t *)(0xff634400 + (0x0bc << 2))
#define PERIPHS_PIN_MUX_D (0xff634400 + (0x0bd << 2))
#define SEC_PERIPHS_PIN_MUX_D (0xff634400 + (0x0bd << 2))
#define P_PERIPHS_PIN_MUX_D (volatile uint32_t *)(0xff634400 + (0x0bd << 2))
#define PERIPHS_PIN_MUX_E (0xff634400 + (0x0be << 2))
#define SEC_PERIPHS_PIN_MUX_E (0xff634400 + (0x0be << 2))
#define P_PERIPHS_PIN_MUX_E (volatile uint32_t *)(0xff634400 + (0x0be << 2))
#define PERIPHS_PIN_MUX_F (0xff634400 + (0x0bf << 2))
#define SEC_PERIPHS_PIN_MUX_F (0xff634400 + (0x0bf << 2))
#define P_PERIPHS_PIN_MUX_F (volatile uint32_t *)(0xff634400 + (0x0bf << 2))
#define EFUSE_CFG_LOCK (0xff634400 + (0x0c0 << 2))
#define SEC_EFUSE_CFG_LOCK (0xff634400 + (0x0c0 << 2))
#define P_EFUSE_CFG_LOCK (volatile uint32_t *)(0xff634400 + (0x0c0 << 2))
#define EFUSE_CLK_A53_CFG01 (0xff634400 + (0x0c1 << 2))
#define SEC_EFUSE_CLK_A53_CFG01 (0xff634400 + (0x0c1 << 2))
#define P_EFUSE_CLK_A53_CFG01 (volatile uint32_t *)(0xff634400 + (0x0c1 << 2))
#define EFUSE_CLK_A53_CFG2 (0xff634400 + (0x0c2 << 2))
#define SEC_EFUSE_CLK_A53_CFG2 (0xff634400 + (0x0c2 << 2))
#define P_EFUSE_CLK_A53_CFG2 (volatile uint32_t *)(0xff634400 + (0x0c2 << 2))
#define EFUSE_CLK_ENCP_CFG0 (0xff634400 + (0x0c3 << 2))
#define SEC_EFUSE_CLK_ENCP_CFG0 (0xff634400 + (0x0c3 << 2))
#define P_EFUSE_CLK_ENCP_CFG0 (volatile uint32_t *)(0xff634400 + (0x0c3 << 2))
#define EFUSE_CLK_MALI_CFG0 (0xff634400 + (0x0c4 << 2))
#define SEC_EFUSE_CLK_MALI_CFG0 (0xff634400 + (0x0c4 << 2))
#define P_EFUSE_CLK_MALI_CFG0 (volatile uint32_t *)(0xff634400 + (0x0c4 << 2))
#define EFUSE_CLK_HEVCB_CFG0 (0xff634400 + (0x0c5 << 2))
#define SEC_EFUSE_CLK_HEVCB_CFG0 (0xff634400 + (0x0c5 << 2))
#define P_EFUSE_CLK_HEVCB_CFG0 (volatile uint32_t *)(0xff634400 + (0x0c5 << 2))
#define PAD_DS_REG0A (0xff634400 + (0x0d0 << 2))
#define SEC_PAD_DS_REG0A (0xff634400 + (0x0d0 << 2))
#define P_PAD_DS_REG0A (volatile uint32_t *)(0xff634400 + (0x0d0 << 2))
#define PAD_DS_REG1A (0xff634400 + (0x0d1 << 2))
#define SEC_PAD_DS_REG1A (0xff634400 + (0x0d1 << 2))
#define P_PAD_DS_REG1A (volatile uint32_t *)(0xff634400 + (0x0d1 << 2))
#define PAD_DS_REG2A (0xff634400 + (0x0d2 << 2))
#define SEC_PAD_DS_REG2A (0xff634400 + (0x0d2 << 2))
#define P_PAD_DS_REG2A (volatile uint32_t *)(0xff634400 + (0x0d2 << 2))
#define PAD_DS_REG2B (0xff634400 + (0x0d3 << 2))
#define SEC_PAD_DS_REG2B (0xff634400 + (0x0d3 << 2))
#define P_PAD_DS_REG2B (volatile uint32_t *)(0xff634400 + (0x0d3 << 2))
#define PAD_DS_REG3A (0xff634400 + (0x0d4 << 2))
#define SEC_PAD_DS_REG3A (0xff634400 + (0x0d4 << 2))
#define P_PAD_DS_REG3A (volatile uint32_t *)(0xff634400 + (0x0d4 << 2))
#define PAD_DS_REG4A (0xff634400 + (0x0d5 << 2))
#define SEC_PAD_DS_REG4A (0xff634400 + (0x0d5 << 2))
#define P_PAD_DS_REG4A (volatile uint32_t *)(0xff634400 + (0x0d5 << 2))
#define PAD_DS_REG5A (0xff634400 + (0x0d6 << 2))
#define SEC_PAD_DS_REG5A (0xff634400 + (0x0d6 << 2))
#define P_PAD_DS_REG5A (volatile uint32_t *)(0xff634400 + (0x0d6 << 2))
//========================================================================
// RESET_SEC - Registers
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF64E000
// APB4_DECODER_SECURE_BASE 32'hFF64E000
#define RESET0_SEC_REGISTER (0xff64e000 + (0x000 << 2))
#define SEC_RESET0_SEC_REGISTER (0xff64e000 + (0x000 << 2))
#define P_RESET0_SEC_REGISTER (volatile uint32_t *)(0xff64e000 + (0x000 << 2))
#define RESET1_SEC_REGISTER (0xff64e000 + (0x001 << 2))
#define SEC_RESET1_SEC_REGISTER (0xff64e000 + (0x001 << 2))
#define P_RESET1_SEC_REGISTER (volatile uint32_t *)(0xff64e000 + (0x001 << 2))
#define RESET2_SEC_REGISTER (0xff64e000 + (0x002 << 2))
#define SEC_RESET2_SEC_REGISTER (0xff64e000 + (0x002 << 2))
#define P_RESET2_SEC_REGISTER (volatile uint32_t *)(0xff64e000 + (0x002 << 2))
#define RESET0_SEC_LEVEL (0xff64e000 + (0x010 << 2))
#define SEC_RESET0_SEC_LEVEL (0xff64e000 + (0x010 << 2))
#define P_RESET0_SEC_LEVEL (volatile uint32_t *)(0xff64e000 + (0x010 << 2))
#define RESET1_SEC_LEVEL (0xff64e000 + (0x011 << 2))
#define SEC_RESET1_SEC_LEVEL (0xff64e000 + (0x011 << 2))
#define P_RESET1_SEC_LEVEL (volatile uint32_t *)(0xff64e000 + (0x011 << 2))
#define RESET2_SEC_LEVEL (0xff64e000 + (0x012 << 2))
#define SEC_RESET2_SEC_LEVEL (0xff64e000 + (0x012 << 2))
#define P_RESET2_SEC_LEVEL (volatile uint32_t *)(0xff64e000 + (0x012 << 2))
#define RESET0_SEC_MASK (0xff64e000 + (0x020 << 2))
#define SEC_RESET0_SEC_MASK (0xff64e000 + (0x020 << 2))
#define P_RESET0_SEC_MASK (volatile uint32_t *)(0xff64e000 + (0x020 << 2))
#define RESET1_SEC_MASK (0xff64e000 + (0x021 << 2))
#define SEC_RESET1_SEC_MASK (0xff64e000 + (0x021 << 2))
#define P_RESET1_SEC_MASK (volatile uint32_t *)(0xff64e000 + (0x021 << 2))
#define RESET2_SEC_MASK (0xff64e000 + (0x022 << 2))
#define SEC_RESET2_SEC_MASK (0xff64e000 + (0x022 << 2))
#define P_RESET2_SEC_MASK (volatile uint32_t *)(0xff64e000 + (0x022 << 2))
//========================================================================
// AUDIO locker - Registers
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF64a000
// APB4_DECODER_SECURE_BASE 32'hFF64a000
#define AUD_LOCK_EN (0xff64a000 + (0x000 << 2))
#define SEC_AUD_LOCK_EN (0xff64a000 + (0x000 << 2))
#define P_AUD_LOCK_EN (volatile uint32_t *)(0xff64a000 + (0x000 << 2))
#define AUD_LOCK_SW_RESET (0xff64a000 + (0x001 << 2))
#define SEC_AUD_LOCK_SW_RESET (0xff64a000 + (0x001 << 2))
#define P_AUD_LOCK_SW_RESET (volatile uint32_t *)(0xff64a000 + (0x001 << 2))
#define AUD_LOCK_SW_LATCH (0xff64a000 + (0x002 << 2))
#define SEC_AUD_LOCK_SW_LATCH (0xff64a000 + (0x002 << 2))
#define P_AUD_LOCK_SW_LATCH (volatile uint32_t *)(0xff64a000 + (0x002 << 2))
#define AUD_LOCK_HW_LATCH (0xff64a000 + (0x003 << 2))
#define SEC_AUD_LOCK_HW_LATCH (0xff64a000 + (0x003 << 2))
#define P_AUD_LOCK_HW_LATCH (volatile uint32_t *)(0xff64a000 + (0x003 << 2))
#define AUD_LOCK_REFCLK_SRC (0xff64a000 + (0x004 << 2))
#define SEC_AUD_LOCK_REFCLK_SRC (0xff64a000 + (0x004 << 2))
#define P_AUD_LOCK_REFCLK_SRC (volatile uint32_t *)(0xff64a000 + (0x004 << 2))
#define AUD_LOCK_REFCLK_LAT_INT (0xff64a000 + (0x005 << 2))
#define SEC_AUD_LOCK_REFCLK_LAT_INT (0xff64a000 + (0x005 << 2))
#define P_AUD_LOCK_REFCLK_LAT_INT (volatile uint32_t *)(0xff64a000 + (0x005 << 2))
#define AUD_LOCK_IMCLK_LAT_INT (0xff64a000 + (0x006 << 2))
#define SEC_AUD_LOCK_IMCLK_LAT_INT (0xff64a000 + (0x006 << 2))
#define P_AUD_LOCK_IMCLK_LAT_INT (volatile uint32_t *)(0xff64a000 + (0x006 << 2))
#define AUD_LOCK_OMCLK_LAT_INT (0xff64a000 + (0x007 << 2))
#define SEC_AUD_LOCK_OMCLK_LAT_INT (0xff64a000 + (0x007 << 2))
#define P_AUD_LOCK_OMCLK_LAT_INT (volatile uint32_t *)(0xff64a000 + (0x007 << 2))
#define AUD_LOCK_REFCLK_DS_INT (0xff64a000 + (0x008 << 2))
#define SEC_AUD_LOCK_REFCLK_DS_INT (0xff64a000 + (0x008 << 2))
#define P_AUD_LOCK_REFCLK_DS_INT (volatile uint32_t *)(0xff64a000 + (0x008 << 2))
#define AUD_LOCK_IMCLK_DS_INT (0xff64a000 + (0x009 << 2))
#define SEC_AUD_LOCK_IMCLK_DS_INT (0xff64a000 + (0x009 << 2))
#define P_AUD_LOCK_IMCLK_DS_INT (volatile uint32_t *)(0xff64a000 + (0x009 << 2))
#define AUD_LOCK_OMCLK_DS_INT (0xff64a000 + (0x00a << 2))
#define SEC_AUD_LOCK_OMCLK_DS_INT (0xff64a000 + (0x00a << 2))
#define P_AUD_LOCK_OMCLK_DS_INT (volatile uint32_t *)(0xff64a000 + (0x00a << 2))
#define AUD_LOCK_INT_CLR (0xff64a000 + (0x00b << 2))
#define SEC_AUD_LOCK_INT_CLR (0xff64a000 + (0x00b << 2))
#define P_AUD_LOCK_INT_CLR (volatile uint32_t *)(0xff64a000 + (0x00b << 2))
#define AUD_LOCK_GCLK_CTRL (0xff64a000 + (0x00c << 2))
#define SEC_AUD_LOCK_GCLK_CTRL (0xff64a000 + (0x00c << 2))
#define P_AUD_LOCK_GCLK_CTRL (volatile uint32_t *)(0xff64a000 + (0x00c << 2))
#define AUD_LOCK_INT_CTRL (0xff64a000 + (0x00d << 2))
#define SEC_AUD_LOCK_INT_CTRL (0xff64a000 + (0x00d << 2))
#define P_AUD_LOCK_INT_CTRL (volatile uint32_t *)(0xff64a000 + (0x00d << 2))
#define RO_REF2IMCLK_CNT_L (0xff64a000 + (0x010 << 2))
#define SEC_RO_REF2IMCLK_CNT_L (0xff64a000 + (0x010 << 2))
#define P_RO_REF2IMCLK_CNT_L (volatile uint32_t *)(0xff64a000 + (0x010 << 2))
#define RO_REF2IMCLK_CNT_H (0xff64a000 + (0x011 << 2))
#define SEC_RO_REF2IMCLK_CNT_H (0xff64a000 + (0x011 << 2))
#define P_RO_REF2IMCLK_CNT_H (volatile uint32_t *)(0xff64a000 + (0x011 << 2))
#define RO_REF2OMCLK_CNT_L (0xff64a000 + (0x012 << 2))
#define SEC_RO_REF2OMCLK_CNT_L (0xff64a000 + (0x012 << 2))
#define P_RO_REF2OMCLK_CNT_L (volatile uint32_t *)(0xff64a000 + (0x012 << 2))
#define RO_REF2OMCLK_CNT_H (0xff64a000 + (0x013 << 2))
#define SEC_RO_REF2OMCLK_CNT_H (0xff64a000 + (0x013 << 2))
#define P_RO_REF2OMCLK_CNT_H (volatile uint32_t *)(0xff64a000 + (0x013 << 2))
#define RO_IMCLK2REF_CNT_L (0xff64a000 + (0x014 << 2))
#define SEC_RO_IMCLK2REF_CNT_L (0xff64a000 + (0x014 << 2))
#define P_RO_IMCLK2REF_CNT_L (volatile uint32_t *)(0xff64a000 + (0x014 << 2))
#define RO_IMCLK2REF_CNT_H (0xff64a000 + (0x015 << 2))
#define SEC_RO_IMCLK2REF_CNT_H (0xff64a000 + (0x015 << 2))
#define P_RO_IMCLK2REF_CNT_H (volatile uint32_t *)(0xff64a000 + (0x015 << 2))
#define RO_OMCLK2REF_CNT_L (0xff64a000 + (0x016 << 2))
#define SEC_RO_OMCLK2REF_CNT_L (0xff64a000 + (0x016 << 2))
#define P_RO_OMCLK2REF_CNT_L (volatile uint32_t *)(0xff64a000 + (0x016 << 2))
#define RO_OMCLK2REF_CNT_H (0xff64a000 + (0x017 << 2))
#define SEC_RO_OMCLK2REF_CNT_H (0xff64a000 + (0x017 << 2))
#define P_RO_OMCLK2REF_CNT_H (volatile uint32_t *)(0xff64a000 + (0x017 << 2))
#define RO_REFCLK_PKG_CNT (0xff64a000 + (0x018 << 2))
#define SEC_RO_REFCLK_PKG_CNT (0xff64a000 + (0x018 << 2))
#define P_RO_REFCLK_PKG_CNT (volatile uint32_t *)(0xff64a000 + (0x018 << 2))
#define RO_IMCLK_PKG_CNT (0xff64a000 + (0x019 << 2))
#define SEC_RO_IMCLK_PKG_CNT (0xff64a000 + (0x019 << 2))
#define P_RO_IMCLK_PKG_CNT (volatile uint32_t *)(0xff64a000 + (0x019 << 2))
#define RO_OMCLK_PKG_CNT (0xff64a000 + (0x01a << 2))
#define SEC_RO_OMCLK_PKG_CNT (0xff64a000 + (0x01a << 2))
#define P_RO_OMCLK_PKG_CNT (volatile uint32_t *)(0xff64a000 + (0x01a << 2))
#define RO_AUD_LOCK_INT_STATUS (0xff64a000 + (0x01b << 2))
#define SEC_RO_AUD_LOCK_INT_STATUS (0xff64a000 + (0x01b << 2))
#define P_RO_AUD_LOCK_INT_STATUS (volatile uint32_t *)(0xff64a000 + (0x01b << 2))
//========================================================================
// AUDIO - Registers
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF642000
// APB4_DECODER_SECURE_BASE 32'hFF642000
#define EE_AUDIO_CLK_GATE_EN (0xff642000 + (0x000 << 2))
#define SEC_EE_AUDIO_CLK_GATE_EN (0xff642000 + (0x000 << 2))
#define P_EE_AUDIO_CLK_GATE_EN (volatile uint32_t *)(0xff642000 + (0x000 << 2))
#define EE_AUDIO_MCLK_A_CTRL (0xff642000 + (0x001 << 2))
#define SEC_EE_AUDIO_MCLK_A_CTRL (0xff642000 + (0x001 << 2))
#define P_EE_AUDIO_MCLK_A_CTRL (volatile uint32_t *)(0xff642000 + (0x001 << 2))
#define EE_AUDIO_MCLK_B_CTRL (0xff642000 + (0x002 << 2))
#define SEC_EE_AUDIO_MCLK_B_CTRL (0xff642000 + (0x002 << 2))
#define P_EE_AUDIO_MCLK_B_CTRL (volatile uint32_t *)(0xff642000 + (0x002 << 2))
#define EE_AUDIO_MCLK_C_CTRL (0xff642000 + (0x003 << 2))
#define SEC_EE_AUDIO_MCLK_C_CTRL (0xff642000 + (0x003 << 2))
#define P_EE_AUDIO_MCLK_C_CTRL (volatile uint32_t *)(0xff642000 + (0x003 << 2))
#define EE_AUDIO_MCLK_D_CTRL (0xff642000 + (0x004 << 2))
#define SEC_EE_AUDIO_MCLK_D_CTRL (0xff642000 + (0x004 << 2))
#define P_EE_AUDIO_MCLK_D_CTRL (volatile uint32_t *)(0xff642000 + (0x004 << 2))
#define EE_AUDIO_MCLK_E_CTRL (0xff642000 + (0x005 << 2))
#define SEC_EE_AUDIO_MCLK_E_CTRL (0xff642000 + (0x005 << 2))
#define P_EE_AUDIO_MCLK_E_CTRL (volatile uint32_t *)(0xff642000 + (0x005 << 2))
#define EE_AUDIO_MCLK_F_CTRL (0xff642000 + (0x006 << 2))
#define SEC_EE_AUDIO_MCLK_F_CTRL (0xff642000 + (0x006 << 2))
#define P_EE_AUDIO_MCLK_F_CTRL (volatile uint32_t *)(0xff642000 + (0x006 << 2))
#define EE_AUDIO_PAD_CTRL0 (0xff642000 + (0x007 << 2))
#define SEC_EE_AUDIO_PAD_CTRL0 (0xff642000 + (0x007 << 2))
#define P_EE_AUDIO_PAD_CTRL0 (volatile uint32_t *)(0xff642000 + (0x007 << 2))
#define EE_AUDIO_PAD_CTRL1 (0xff642000 + (0x008 << 2))
#define SEC_EE_AUDIO_PAD_CTRL1 (0xff642000 + (0x008 << 2))
#define P_EE_AUDIO_PAD_CTRL1 (volatile uint32_t *)(0xff642000 + (0x008 << 2))
#define EE_AUDIO_SW_RESET (0xff642000 + (0x009 << 2))
#define SEC_EE_AUDIO_SW_RESET (0xff642000 + (0x009 << 2))
#define P_EE_AUDIO_SW_RESET (volatile uint32_t *)(0xff642000 + (0x009 << 2))
#define EE_AUDIO_MST_A_SCLK_CTRL0 (0xff642000 + (0x010 << 2))
#define SEC_EE_AUDIO_MST_A_SCLK_CTRL0 (0xff642000 + (0x010 << 2))
#define P_EE_AUDIO_MST_A_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x010 << 2))
#define EE_AUDIO_MST_A_SCLK_CTRL1 (0xff642000 + (0x011 << 2))
#define SEC_EE_AUDIO_MST_A_SCLK_CTRL1 (0xff642000 + (0x011 << 2))
#define P_EE_AUDIO_MST_A_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x011 << 2))
#define EE_AUDIO_MST_B_SCLK_CTRL0 (0xff642000 + (0x012 << 2))
#define SEC_EE_AUDIO_MST_B_SCLK_CTRL0 (0xff642000 + (0x012 << 2))
#define P_EE_AUDIO_MST_B_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x012 << 2))
#define EE_AUDIO_MST_B_SCLK_CTRL1 (0xff642000 + (0x013 << 2))
#define SEC_EE_AUDIO_MST_B_SCLK_CTRL1 (0xff642000 + (0x013 << 2))
#define P_EE_AUDIO_MST_B_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x013 << 2))
#define EE_AUDIO_MST_C_SCLK_CTRL0 (0xff642000 + (0x014 << 2))
#define SEC_EE_AUDIO_MST_C_SCLK_CTRL0 (0xff642000 + (0x014 << 2))
#define P_EE_AUDIO_MST_C_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x014 << 2))
#define EE_AUDIO_MST_C_SCLK_CTRL1 (0xff642000 + (0x015 << 2))
#define SEC_EE_AUDIO_MST_C_SCLK_CTRL1 (0xff642000 + (0x015 << 2))
#define P_EE_AUDIO_MST_C_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x015 << 2))
#define EE_AUDIO_MST_D_SCLK_CTRL0 (0xff642000 + (0x016 << 2))
#define SEC_EE_AUDIO_MST_D_SCLK_CTRL0 (0xff642000 + (0x016 << 2))
#define P_EE_AUDIO_MST_D_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x016 << 2))
#define EE_AUDIO_MST_D_SCLK_CTRL1 (0xff642000 + (0x017 << 2))
#define SEC_EE_AUDIO_MST_D_SCLK_CTRL1 (0xff642000 + (0x017 << 2))
#define P_EE_AUDIO_MST_D_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x017 << 2))
#define EE_AUDIO_MST_E_SCLK_CTRL0 (0xff642000 + (0x018 << 2))
#define SEC_EE_AUDIO_MST_E_SCLK_CTRL0 (0xff642000 + (0x018 << 2))
#define P_EE_AUDIO_MST_E_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x018 << 2))
#define EE_AUDIO_MST_E_SCLK_CTRL1 (0xff642000 + (0x019 << 2))
#define SEC_EE_AUDIO_MST_E_SCLK_CTRL1 (0xff642000 + (0x019 << 2))
#define P_EE_AUDIO_MST_E_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x019 << 2))
#define EE_AUDIO_MST_F_SCLK_CTRL0 (0xff642000 + (0x01a << 2))
#define SEC_EE_AUDIO_MST_F_SCLK_CTRL0 (0xff642000 + (0x01a << 2))
#define P_EE_AUDIO_MST_F_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x01a << 2))
#define EE_AUDIO_MST_F_SCLK_CTRL1 (0xff642000 + (0x01b << 2))
#define SEC_EE_AUDIO_MST_F_SCLK_CTRL1 (0xff642000 + (0x01b << 2))
#define P_EE_AUDIO_MST_F_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x01b << 2))
#define EE_AUDIO_CLK_TDMIN_A_CTRL (0xff642000 + (0x020 << 2))
#define SEC_EE_AUDIO_CLK_TDMIN_A_CTRL (0xff642000 + (0x020 << 2))
#define P_EE_AUDIO_CLK_TDMIN_A_CTRL (volatile uint32_t *)(0xff642000 + (0x020 << 2))
#define EE_AUDIO_CLK_TDMIN_B_CTRL (0xff642000 + (0x021 << 2))
#define SEC_EE_AUDIO_CLK_TDMIN_B_CTRL (0xff642000 + (0x021 << 2))
#define P_EE_AUDIO_CLK_TDMIN_B_CTRL (volatile uint32_t *)(0xff642000 + (0x021 << 2))
#define EE_AUDIO_CLK_TDMIN_C_CTRL (0xff642000 + (0x022 << 2))
#define SEC_EE_AUDIO_CLK_TDMIN_C_CTRL (0xff642000 + (0x022 << 2))
#define P_EE_AUDIO_CLK_TDMIN_C_CTRL (volatile uint32_t *)(0xff642000 + (0x022 << 2))
#define EE_AUDIO_CLK_TDMIN_LB_CTRL (0xff642000 + (0x023 << 2))
#define SEC_EE_AUDIO_CLK_TDMIN_LB_CTRL (0xff642000 + (0x023 << 2))
#define P_EE_AUDIO_CLK_TDMIN_LB_CTRL (volatile uint32_t *)(0xff642000 + (0x023 << 2))
#define EE_AUDIO_CLK_TDMOUT_A_CTRL (0xff642000 + (0x024 << 2))
#define SEC_EE_AUDIO_CLK_TDMOUT_A_CTRL (0xff642000 + (0x024 << 2))
#define P_EE_AUDIO_CLK_TDMOUT_A_CTRL (volatile uint32_t *)(0xff642000 + (0x024 << 2))
#define EE_AUDIO_CLK_TDMOUT_B_CTRL (0xff642000 + (0x025 << 2))
#define SEC_EE_AUDIO_CLK_TDMOUT_B_CTRL (0xff642000 + (0x025 << 2))
#define P_EE_AUDIO_CLK_TDMOUT_B_CTRL (volatile uint32_t *)(0xff642000 + (0x025 << 2))
#define EE_AUDIO_CLK_TDMOUT_C_CTRL (0xff642000 + (0x026 << 2))
#define SEC_EE_AUDIO_CLK_TDMOUT_C_CTRL (0xff642000 + (0x026 << 2))
#define P_EE_AUDIO_CLK_TDMOUT_C_CTRL (volatile uint32_t *)(0xff642000 + (0x026 << 2))
#define EE_AUDIO_CLK_SPDIFIN_CTRL (0xff642000 + (0x027 << 2))
#define SEC_EE_AUDIO_CLK_SPDIFIN_CTRL (0xff642000 + (0x027 << 2))
#define P_EE_AUDIO_CLK_SPDIFIN_CTRL (volatile uint32_t *)(0xff642000 + (0x027 << 2))
#define EE_AUDIO_CLK_SPDIFOUT_CTRL (0xff642000 + (0x028 << 2))
#define SEC_EE_AUDIO_CLK_SPDIFOUT_CTRL (0xff642000 + (0x028 << 2))
#define P_EE_AUDIO_CLK_SPDIFOUT_CTRL (volatile uint32_t *)(0xff642000 + (0x028 << 2))
#define EE_AUDIO_CLK_RESAMPLE_CTRL (0xff642000 + (0x029 << 2))
#define SEC_EE_AUDIO_CLK_RESAMPLE_CTRL (0xff642000 + (0x029 << 2))
#define P_EE_AUDIO_CLK_RESAMPLE_CTRL (volatile uint32_t *)(0xff642000 + (0x029 << 2))
#define EE_AUDIO_CLK_LOCKER_CTRL (0xff642000 + (0x02a << 2))
#define SEC_EE_AUDIO_CLK_LOCKER_CTRL (0xff642000 + (0x02a << 2))
#define P_EE_AUDIO_CLK_LOCKER_CTRL (volatile uint32_t *)(0xff642000 + (0x02a << 2))
#define EE_AUDIO_CLK_PDMIN_CTRL0 (0xff642000 + (0x02b << 2))
#define SEC_EE_AUDIO_CLK_PDMIN_CTRL0 (0xff642000 + (0x02b << 2))
#define P_EE_AUDIO_CLK_PDMIN_CTRL0 (volatile uint32_t *)(0xff642000 + (0x02b << 2))
#define EE_AUDIO_CLK_PDMIN_CTRL1 (0xff642000 + (0x02c << 2))
#define SEC_EE_AUDIO_CLK_PDMIN_CTRL1 (0xff642000 + (0x02c << 2))
#define P_EE_AUDIO_CLK_PDMIN_CTRL1 (volatile uint32_t *)(0xff642000 + (0x02c << 2))
#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL (0xff642000 + (0x02d << 2))
#define SEC_EE_AUDIO_CLK_SPDIFOUT_B_CTRL (0xff642000 + (0x02d << 2))
#define P_EE_AUDIO_CLK_SPDIFOUT_B_CTRL (volatile uint32_t *)(0xff642000 + (0x02d << 2))
#define EE_AUDIO_TODDR_A_CTRL0 (0xff642000 + (0x040 << 2))
#define SEC_EE_AUDIO_TODDR_A_CTRL0 (0xff642000 + (0x040 << 2))
#define P_EE_AUDIO_TODDR_A_CTRL0 (volatile uint32_t *)(0xff642000 + (0x040 << 2))
#define EE_AUDIO_TODDR_A_CTRL1 (0xff642000 + (0x041 << 2))
#define SEC_EE_AUDIO_TODDR_A_CTRL1 (0xff642000 + (0x041 << 2))
#define P_EE_AUDIO_TODDR_A_CTRL1 (volatile uint32_t *)(0xff642000 + (0x041 << 2))
#define EE_AUDIO_TODDR_A_START_ADDR (0xff642000 + (0x042 << 2))
#define SEC_EE_AUDIO_TODDR_A_START_ADDR (0xff642000 + (0x042 << 2))
#define P_EE_AUDIO_TODDR_A_START_ADDR (volatile uint32_t *)(0xff642000 + (0x042 << 2))
#define EE_AUDIO_TODDR_A_FINISH_ADDR (0xff642000 + (0x043 << 2))
#define SEC_EE_AUDIO_TODDR_A_FINISH_ADDR (0xff642000 + (0x043 << 2))
#define P_EE_AUDIO_TODDR_A_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x043 << 2))
#define EE_AUDIO_TODDR_A_INT_ADDR (0xff642000 + (0x044 << 2))
#define SEC_EE_AUDIO_TODDR_A_INT_ADDR (0xff642000 + (0x044 << 2))
#define P_EE_AUDIO_TODDR_A_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x044 << 2))
#define EE_AUDIO_TODDR_A_STATUS1 (0xff642000 + (0x045 << 2))
#define SEC_EE_AUDIO_TODDR_A_STATUS1 (0xff642000 + (0x045 << 2))
#define P_EE_AUDIO_TODDR_A_STATUS1 (volatile uint32_t *)(0xff642000 + (0x045 << 2))
#define EE_AUDIO_TODDR_A_STATUS2 (0xff642000 + (0x046 << 2))
#define SEC_EE_AUDIO_TODDR_A_STATUS2 (0xff642000 + (0x046 << 2))
#define P_EE_AUDIO_TODDR_A_STATUS2 (volatile uint32_t *)(0xff642000 + (0x046 << 2))
#define EE_AUDIO_TODDR_A_START_ADDRB (0xff642000 + (0x047 << 2))
#define SEC_EE_AUDIO_TODDR_A_START_ADDRB (0xff642000 + (0x047 << 2))
#define P_EE_AUDIO_TODDR_A_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x047 << 2))
#define EE_AUDIO_TODDR_A_FINISH_ADDRB (0xff642000 + (0x048 << 2))
#define SEC_EE_AUDIO_TODDR_A_FINISH_ADDRB (0xff642000 + (0x048 << 2))
#define P_EE_AUDIO_TODDR_A_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x048 << 2))
#define EE_AUDIO_TODDR_A_INIT_ADDR (0xff642000 + (0x049 << 2))
#define SEC_EE_AUDIO_TODDR_A_INIT_ADDR (0xff642000 + (0x049 << 2))
#define P_EE_AUDIO_TODDR_A_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x049 << 2))
#define EE_AUDIO_TODDR_B_CTRL0 (0xff642000 + (0x050 << 2))
#define SEC_EE_AUDIO_TODDR_B_CTRL0 (0xff642000 + (0x050 << 2))
#define P_EE_AUDIO_TODDR_B_CTRL0 (volatile uint32_t *)(0xff642000 + (0x050 << 2))
#define EE_AUDIO_TODDR_B_CTRL1 (0xff642000 + (0x051 << 2))
#define SEC_EE_AUDIO_TODDR_B_CTRL1 (0xff642000 + (0x051 << 2))
#define P_EE_AUDIO_TODDR_B_CTRL1 (volatile uint32_t *)(0xff642000 + (0x051 << 2))
#define EE_AUDIO_TODDR_B_START_ADDR (0xff642000 + (0x052 << 2))
#define SEC_EE_AUDIO_TODDR_B_START_ADDR (0xff642000 + (0x052 << 2))
#define P_EE_AUDIO_TODDR_B_START_ADDR (volatile uint32_t *)(0xff642000 + (0x052 << 2))
#define EE_AUDIO_TODDR_B_FINISH_ADDR (0xff642000 + (0x053 << 2))
#define SEC_EE_AUDIO_TODDR_B_FINISH_ADDR (0xff642000 + (0x053 << 2))
#define P_EE_AUDIO_TODDR_B_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x053 << 2))
#define EE_AUDIO_TODDR_B_INT_ADDR (0xff642000 + (0x054 << 2))
#define SEC_EE_AUDIO_TODDR_B_INT_ADDR (0xff642000 + (0x054 << 2))
#define P_EE_AUDIO_TODDR_B_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x054 << 2))
#define EE_AUDIO_TODDR_B_STATUS1 (0xff642000 + (0x055 << 2))
#define SEC_EE_AUDIO_TODDR_B_STATUS1 (0xff642000 + (0x055 << 2))
#define P_EE_AUDIO_TODDR_B_STATUS1 (volatile uint32_t *)(0xff642000 + (0x055 << 2))
#define EE_AUDIO_TODDR_B_STATUS2 (0xff642000 + (0x056 << 2))
#define SEC_EE_AUDIO_TODDR_B_STATUS2 (0xff642000 + (0x056 << 2))
#define P_EE_AUDIO_TODDR_B_STATUS2 (volatile uint32_t *)(0xff642000 + (0x056 << 2))
#define EE_AUDIO_TODDR_B_START_ADDRB (0xff642000 + (0x057 << 2))
#define SEC_EE_AUDIO_TODDR_B_START_ADDRB (0xff642000 + (0x057 << 2))
#define P_EE_AUDIO_TODDR_B_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x057 << 2))
#define EE_AUDIO_TODDR_B_FINISH_ADDRB (0xff642000 + (0x058 << 2))
#define SEC_EE_AUDIO_TODDR_B_FINISH_ADDRB (0xff642000 + (0x058 << 2))
#define P_EE_AUDIO_TODDR_B_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x058 << 2))
#define EE_AUDIO_TODDR_B_INIT_ADDR (0xff642000 + (0x059 << 2))
#define SEC_EE_AUDIO_TODDR_B_INIT_ADDR (0xff642000 + (0x059 << 2))
#define P_EE_AUDIO_TODDR_B_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x059 << 2))
#define EE_AUDIO_TODDR_C_CTRL0 (0xff642000 + (0x060 << 2))
#define SEC_EE_AUDIO_TODDR_C_CTRL0 (0xff642000 + (0x060 << 2))
#define P_EE_AUDIO_TODDR_C_CTRL0 (volatile uint32_t *)(0xff642000 + (0x060 << 2))
#define EE_AUDIO_TODDR_C_CTRL1 (0xff642000 + (0x061 << 2))
#define SEC_EE_AUDIO_TODDR_C_CTRL1 (0xff642000 + (0x061 << 2))
#define P_EE_AUDIO_TODDR_C_CTRL1 (volatile uint32_t *)(0xff642000 + (0x061 << 2))
#define EE_AUDIO_TODDR_C_START_ADDR (0xff642000 + (0x062 << 2))
#define SEC_EE_AUDIO_TODDR_C_START_ADDR (0xff642000 + (0x062 << 2))
#define P_EE_AUDIO_TODDR_C_START_ADDR (volatile uint32_t *)(0xff642000 + (0x062 << 2))
#define EE_AUDIO_TODDR_C_FINISH_ADDR (0xff642000 + (0x063 << 2))
#define SEC_EE_AUDIO_TODDR_C_FINISH_ADDR (0xff642000 + (0x063 << 2))
#define P_EE_AUDIO_TODDR_C_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x063 << 2))
#define EE_AUDIO_TODDR_C_INT_ADDR (0xff642000 + (0x064 << 2))
#define SEC_EE_AUDIO_TODDR_C_INT_ADDR (0xff642000 + (0x064 << 2))
#define P_EE_AUDIO_TODDR_C_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x064 << 2))
#define EE_AUDIO_TODDR_C_STATUS1 (0xff642000 + (0x065 << 2))
#define SEC_EE_AUDIO_TODDR_C_STATUS1 (0xff642000 + (0x065 << 2))
#define P_EE_AUDIO_TODDR_C_STATUS1 (volatile uint32_t *)(0xff642000 + (0x065 << 2))
#define EE_AUDIO_TODDR_C_STATUS2 (0xff642000 + (0x066 << 2))
#define SEC_EE_AUDIO_TODDR_C_STATUS2 (0xff642000 + (0x066 << 2))
#define P_EE_AUDIO_TODDR_C_STATUS2 (volatile uint32_t *)(0xff642000 + (0x066 << 2))
#define EE_AUDIO_TODDR_C_START_ADDRB (0xff642000 + (0x067 << 2))
#define SEC_EE_AUDIO_TODDR_C_START_ADDRB (0xff642000 + (0x067 << 2))
#define P_EE_AUDIO_TODDR_C_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x067 << 2))
#define EE_AUDIO_TODDR_C_FINISH_ADDRB (0xff642000 + (0x068 << 2))
#define SEC_EE_AUDIO_TODDR_C_FINISH_ADDRB (0xff642000 + (0x068 << 2))
#define P_EE_AUDIO_TODDR_C_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x068 << 2))
#define EE_AUDIO_TODDR_C_INIT_ADDR (0xff642000 + (0x069 << 2))
#define SEC_EE_AUDIO_TODDR_C_INIT_ADDR (0xff642000 + (0x069 << 2))
#define P_EE_AUDIO_TODDR_C_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x069 << 2))
#define EE_AUDIO_FRDDR_A_CTRL0 (0xff642000 + (0x070 << 2))
#define SEC_EE_AUDIO_FRDDR_A_CTRL0 (0xff642000 + (0x070 << 2))
#define P_EE_AUDIO_FRDDR_A_CTRL0 (volatile uint32_t *)(0xff642000 + (0x070 << 2))
#define EE_AUDIO_FRDDR_A_CTRL1 (0xff642000 + (0x071 << 2))
#define SEC_EE_AUDIO_FRDDR_A_CTRL1 (0xff642000 + (0x071 << 2))
#define P_EE_AUDIO_FRDDR_A_CTRL1 (volatile uint32_t *)(0xff642000 + (0x071 << 2))
#define EE_AUDIO_FRDDR_A_START_ADDR (0xff642000 + (0x072 << 2))
#define SEC_EE_AUDIO_FRDDR_A_START_ADDR (0xff642000 + (0x072 << 2))
#define P_EE_AUDIO_FRDDR_A_START_ADDR (volatile uint32_t *)(0xff642000 + (0x072 << 2))
#define EE_AUDIO_FRDDR_A_FINISH_ADDR (0xff642000 + (0x073 << 2))
#define SEC_EE_AUDIO_FRDDR_A_FINISH_ADDR (0xff642000 + (0x073 << 2))
#define P_EE_AUDIO_FRDDR_A_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x073 << 2))
#define EE_AUDIO_FRDDR_A_INT_ADDR (0xff642000 + (0x074 << 2))
#define SEC_EE_AUDIO_FRDDR_A_INT_ADDR (0xff642000 + (0x074 << 2))
#define P_EE_AUDIO_FRDDR_A_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x074 << 2))
#define EE_AUDIO_FRDDR_A_STATUS1 (0xff642000 + (0x075 << 2))
#define SEC_EE_AUDIO_FRDDR_A_STATUS1 (0xff642000 + (0x075 << 2))
#define P_EE_AUDIO_FRDDR_A_STATUS1 (volatile uint32_t *)(0xff642000 + (0x075 << 2))
#define EE_AUDIO_FRDDR_A_STATUS2 (0xff642000 + (0x076 << 2))
#define SEC_EE_AUDIO_FRDDR_A_STATUS2 (0xff642000 + (0x076 << 2))
#define P_EE_AUDIO_FRDDR_A_STATUS2 (volatile uint32_t *)(0xff642000 + (0x076 << 2))
#define EE_AUDIO_FRDDR_A_START_ADDRB (0xff642000 + (0x077 << 2))
#define SEC_EE_AUDIO_FRDDR_A_START_ADDRB (0xff642000 + (0x077 << 2))
#define P_EE_AUDIO_FRDDR_A_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x077 << 2))
#define EE_AUDIO_FRDDR_A_FINISH_ADDRB (0xff642000 + (0x078 << 2))
#define SEC_EE_AUDIO_FRDDR_A_FINISH_ADDRB (0xff642000 + (0x078 << 2))
#define P_EE_AUDIO_FRDDR_A_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x078 << 2))
#define EE_AUDIO_FRDDR_A_INIT_ADDR (0xff642000 + (0x079 << 2))
#define SEC_EE_AUDIO_FRDDR_A_INIT_ADDR (0xff642000 + (0x079 << 2))
#define P_EE_AUDIO_FRDDR_A_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x079 << 2))
#define EE_AUDIO_FRDDR_B_CTRL0 (0xff642000 + (0x080 << 2))
#define SEC_EE_AUDIO_FRDDR_B_CTRL0 (0xff642000 + (0x080 << 2))
#define P_EE_AUDIO_FRDDR_B_CTRL0 (volatile uint32_t *)(0xff642000 + (0x080 << 2))
#define EE_AUDIO_FRDDR_B_CTRL1 (0xff642000 + (0x081 << 2))
#define SEC_EE_AUDIO_FRDDR_B_CTRL1 (0xff642000 + (0x081 << 2))
#define P_EE_AUDIO_FRDDR_B_CTRL1 (volatile uint32_t *)(0xff642000 + (0x081 << 2))
#define EE_AUDIO_FRDDR_B_START_ADDR (0xff642000 + (0x082 << 2))
#define SEC_EE_AUDIO_FRDDR_B_START_ADDR (0xff642000 + (0x082 << 2))
#define P_EE_AUDIO_FRDDR_B_START_ADDR (volatile uint32_t *)(0xff642000 + (0x082 << 2))
#define EE_AUDIO_FRDDR_B_FINISH_ADDR (0xff642000 + (0x083 << 2))
#define SEC_EE_AUDIO_FRDDR_B_FINISH_ADDR (0xff642000 + (0x083 << 2))
#define P_EE_AUDIO_FRDDR_B_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x083 << 2))
#define EE_AUDIO_FRDDR_B_INT_ADDR (0xff642000 + (0x084 << 2))
#define SEC_EE_AUDIO_FRDDR_B_INT_ADDR (0xff642000 + (0x084 << 2))
#define P_EE_AUDIO_FRDDR_B_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x084 << 2))
#define EE_AUDIO_FRDDR_B_STATUS1 (0xff642000 + (0x085 << 2))
#define SEC_EE_AUDIO_FRDDR_B_STATUS1 (0xff642000 + (0x085 << 2))
#define P_EE_AUDIO_FRDDR_B_STATUS1 (volatile uint32_t *)(0xff642000 + (0x085 << 2))
#define EE_AUDIO_FRDDR_B_STATUS2 (0xff642000 + (0x086 << 2))
#define SEC_EE_AUDIO_FRDDR_B_STATUS2 (0xff642000 + (0x086 << 2))
#define P_EE_AUDIO_FRDDR_B_STATUS2 (volatile uint32_t *)(0xff642000 + (0x086 << 2))
#define EE_AUDIO_FRDDR_B_START_ADDRB (0xff642000 + (0x087 << 2))
#define SEC_EE_AUDIO_FRDDR_B_START_ADDRB (0xff642000 + (0x087 << 2))
#define P_EE_AUDIO_FRDDR_B_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x087 << 2))
#define EE_AUDIO_FRDDR_B_FINISH_ADDRB (0xff642000 + (0x088 << 2))
#define SEC_EE_AUDIO_FRDDR_B_FINISH_ADDRB (0xff642000 + (0x088 << 2))
#define P_EE_AUDIO_FRDDR_B_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x088 << 2))
#define EE_AUDIO_FRDDR_B_INIT_ADDR (0xff642000 + (0x089 << 2))
#define SEC_EE_AUDIO_FRDDR_B_INIT_ADDR (0xff642000 + (0x089 << 2))
#define P_EE_AUDIO_FRDDR_B_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x089 << 2))
#define EE_AUDIO_FRDDR_C_CTRL0 (0xff642000 + (0x090 << 2))
#define SEC_EE_AUDIO_FRDDR_C_CTRL0 (0xff642000 + (0x090 << 2))
#define P_EE_AUDIO_FRDDR_C_CTRL0 (volatile uint32_t *)(0xff642000 + (0x090 << 2))
#define EE_AUDIO_FRDDR_C_CTRL1 (0xff642000 + (0x091 << 2))
#define SEC_EE_AUDIO_FRDDR_C_CTRL1 (0xff642000 + (0x091 << 2))
#define P_EE_AUDIO_FRDDR_C_CTRL1 (volatile uint32_t *)(0xff642000 + (0x091 << 2))
#define EE_AUDIO_FRDDR_C_START_ADDR (0xff642000 + (0x092 << 2))
#define SEC_EE_AUDIO_FRDDR_C_START_ADDR (0xff642000 + (0x092 << 2))
#define P_EE_AUDIO_FRDDR_C_START_ADDR (volatile uint32_t *)(0xff642000 + (0x092 << 2))
#define EE_AUDIO_FRDDR_C_FINISH_ADDR (0xff642000 + (0x093 << 2))
#define SEC_EE_AUDIO_FRDDR_C_FINISH_ADDR (0xff642000 + (0x093 << 2))
#define P_EE_AUDIO_FRDDR_C_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x093 << 2))
#define EE_AUDIO_FRDDR_C_INT_ADDR (0xff642000 + (0x094 << 2))
#define SEC_EE_AUDIO_FRDDR_C_INT_ADDR (0xff642000 + (0x094 << 2))
#define P_EE_AUDIO_FRDDR_C_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x094 << 2))
#define EE_AUDIO_FRDDR_C_STATUS1 (0xff642000 + (0x095 << 2))
#define SEC_EE_AUDIO_FRDDR_C_STATUS1 (0xff642000 + (0x095 << 2))
#define P_EE_AUDIO_FRDDR_C_STATUS1 (volatile uint32_t *)(0xff642000 + (0x095 << 2))
#define EE_AUDIO_FRDDR_C_STATUS2 (0xff642000 + (0x096 << 2))
#define SEC_EE_AUDIO_FRDDR_C_STATUS2 (0xff642000 + (0x096 << 2))
#define P_EE_AUDIO_FRDDR_C_STATUS2 (volatile uint32_t *)(0xff642000 + (0x096 << 2))
#define EE_AUDIO_FRDDR_C_START_ADDRB (0xff642000 + (0x097 << 2))
#define SEC_EE_AUDIO_FRDDR_C_START_ADDRB (0xff642000 + (0x097 << 2))
#define P_EE_AUDIO_FRDDR_C_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x097 << 2))
#define EE_AUDIO_FRDDR_C_FINISH_ADDRB (0xff642000 + (0x098 << 2))
#define SEC_EE_AUDIO_FRDDR_C_FINISH_ADDRB (0xff642000 + (0x098 << 2))
#define P_EE_AUDIO_FRDDR_C_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x098 << 2))
#define EE_AUDIO_FRDDR_C_INIT_ADDR (0xff642000 + (0x099 << 2))
#define SEC_EE_AUDIO_FRDDR_C_INIT_ADDR (0xff642000 + (0x099 << 2))
#define P_EE_AUDIO_FRDDR_C_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x099 << 2))
#define EE_AUDIO_ARB_CTRL (0xff642000 + (0x0a0 << 2))
#define SEC_EE_AUDIO_ARB_CTRL (0xff642000 + (0x0a0 << 2))
#define P_EE_AUDIO_ARB_CTRL (volatile uint32_t *)(0xff642000 + (0x0a0 << 2))
#define EE_AUDIO_LB_CTRL0 (0xff642000 + (0x0b0 << 2))
#define SEC_EE_AUDIO_LB_CTRL0 (0xff642000 + (0x0b0 << 2))
#define P_EE_AUDIO_LB_CTRL0 (volatile uint32_t *)(0xff642000 + (0x0b0 << 2))
#define EE_AUDIO_LB_CTRL1 (0xff642000 + (0x0b1 << 2))
#define SEC_EE_AUDIO_LB_CTRL1 (0xff642000 + (0x0b1 << 2))
#define P_EE_AUDIO_LB_CTRL1 (volatile uint32_t *)(0xff642000 + (0x0b1 << 2))
#define EE_AUDIO_LB_DAT_CH_ID0 (0xff642000 + (0x0b2 << 2))
#define SEC_EE_AUDIO_LB_DAT_CH_ID0 (0xff642000 + (0x0b2 << 2))
#define P_EE_AUDIO_LB_DAT_CH_ID0 (volatile uint32_t *)(0xff642000 + (0x0b2 << 2))
#define EE_AUDIO_LB_DAT_CH_ID1 (0xff642000 + (0x0b3 << 2))
#define SEC_EE_AUDIO_LB_DAT_CH_ID1 (0xff642000 + (0x0b3 << 2))
#define P_EE_AUDIO_LB_DAT_CH_ID1 (volatile uint32_t *)(0xff642000 + (0x0b3 << 2))
#define EE_AUDIO_LB_LB_CH_ID0 (0xff642000 + (0x0b4 << 2))
#define SEC_EE_AUDIO_LB_LB_CH_ID0 (0xff642000 + (0x0b4 << 2))
#define P_EE_AUDIO_LB_LB_CH_ID0 (volatile uint32_t *)(0xff642000 + (0x0b4 << 2))
#define EE_AUDIO_LB_LB_CH_ID1 (0xff642000 + (0x0b5 << 2))
#define SEC_EE_AUDIO_LB_LB_CH_ID1 (0xff642000 + (0x0b5 << 2))
#define P_EE_AUDIO_LB_LB_CH_ID1 (volatile uint32_t *)(0xff642000 + (0x0b5 << 2))
#define EE_AUDIO_LB_STS (0xff642000 + (0x0b6 << 2))
#define SEC_EE_AUDIO_LB_STS (0xff642000 + (0x0b6 << 2))
#define P_EE_AUDIO_LB_STS (volatile uint32_t *)(0xff642000 + (0x0b6 << 2))
#define EE_AUDIO_TDMIN_A_CTRL (0xff642000 + (0x0c0 << 2))
#define SEC_EE_AUDIO_TDMIN_A_CTRL (0xff642000 + (0x0c0 << 2))
#define P_EE_AUDIO_TDMIN_A_CTRL (volatile uint32_t *)(0xff642000 + (0x0c0 << 2))
#define EE_AUDIO_TDMIN_A_SWAP (0xff642000 + (0x0c1 << 2))
#define SEC_EE_AUDIO_TDMIN_A_SWAP (0xff642000 + (0x0c1 << 2))
#define P_EE_AUDIO_TDMIN_A_SWAP (volatile uint32_t *)(0xff642000 + (0x0c1 << 2))
#define EE_AUDIO_TDMIN_A_MASK0 (0xff642000 + (0x0c2 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MASK0 (0xff642000 + (0x0c2 << 2))
#define P_EE_AUDIO_TDMIN_A_MASK0 (volatile uint32_t *)(0xff642000 + (0x0c2 << 2))
#define EE_AUDIO_TDMIN_A_MASK1 (0xff642000 + (0x0c3 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MASK1 (0xff642000 + (0x0c3 << 2))
#define P_EE_AUDIO_TDMIN_A_MASK1 (volatile uint32_t *)(0xff642000 + (0x0c3 << 2))
#define EE_AUDIO_TDMIN_A_MASK2 (0xff642000 + (0x0c4 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MASK2 (0xff642000 + (0x0c4 << 2))
#define P_EE_AUDIO_TDMIN_A_MASK2 (volatile uint32_t *)(0xff642000 + (0x0c4 << 2))
#define EE_AUDIO_TDMIN_A_MASK3 (0xff642000 + (0x0c5 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MASK3 (0xff642000 + (0x0c5 << 2))
#define P_EE_AUDIO_TDMIN_A_MASK3 (volatile uint32_t *)(0xff642000 + (0x0c5 << 2))
#define EE_AUDIO_TDMIN_A_STAT (0xff642000 + (0x0c6 << 2))
#define SEC_EE_AUDIO_TDMIN_A_STAT (0xff642000 + (0x0c6 << 2))
#define P_EE_AUDIO_TDMIN_A_STAT (volatile uint32_t *)(0xff642000 + (0x0c6 << 2))
#define EE_AUDIO_TDMIN_A_MUTE_VAL (0xff642000 + (0x0c7 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MUTE_VAL (0xff642000 + (0x0c7 << 2))
#define P_EE_AUDIO_TDMIN_A_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0c7 << 2))
#define EE_AUDIO_TDMIN_A_MUTE0 (0xff642000 + (0x0c8 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MUTE0 (0xff642000 + (0x0c8 << 2))
#define P_EE_AUDIO_TDMIN_A_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0c8 << 2))
#define EE_AUDIO_TDMIN_A_MUTE1 (0xff642000 + (0x0c9 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MUTE1 (0xff642000 + (0x0c9 << 2))
#define P_EE_AUDIO_TDMIN_A_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0c9 << 2))
#define EE_AUDIO_TDMIN_A_MUTE2 (0xff642000 + (0x0ca << 2))
#define SEC_EE_AUDIO_TDMIN_A_MUTE2 (0xff642000 + (0x0ca << 2))
#define P_EE_AUDIO_TDMIN_A_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0ca << 2))
#define EE_AUDIO_TDMIN_A_MUTE3 (0xff642000 + (0x0cb << 2))
#define SEC_EE_AUDIO_TDMIN_A_MUTE3 (0xff642000 + (0x0cb << 2))
#define P_EE_AUDIO_TDMIN_A_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0cb << 2))
#define EE_AUDIO_TDMIN_B_CTRL (0xff642000 + (0x0d0 << 2))
#define SEC_EE_AUDIO_TDMIN_B_CTRL (0xff642000 + (0x0d0 << 2))
#define P_EE_AUDIO_TDMIN_B_CTRL (volatile uint32_t *)(0xff642000 + (0x0d0 << 2))
#define EE_AUDIO_TDMIN_B_SWAP (0xff642000 + (0x0d1 << 2))
#define SEC_EE_AUDIO_TDMIN_B_SWAP (0xff642000 + (0x0d1 << 2))
#define P_EE_AUDIO_TDMIN_B_SWAP (volatile uint32_t *)(0xff642000 + (0x0d1 << 2))
#define EE_AUDIO_TDMIN_B_MASK0 (0xff642000 + (0x0d2 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MASK0 (0xff642000 + (0x0d2 << 2))
#define P_EE_AUDIO_TDMIN_B_MASK0 (volatile uint32_t *)(0xff642000 + (0x0d2 << 2))
#define EE_AUDIO_TDMIN_B_MASK1 (0xff642000 + (0x0d3 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MASK1 (0xff642000 + (0x0d3 << 2))
#define P_EE_AUDIO_TDMIN_B_MASK1 (volatile uint32_t *)(0xff642000 + (0x0d3 << 2))
#define EE_AUDIO_TDMIN_B_MASK2 (0xff642000 + (0x0d4 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MASK2 (0xff642000 + (0x0d4 << 2))
#define P_EE_AUDIO_TDMIN_B_MASK2 (volatile uint32_t *)(0xff642000 + (0x0d4 << 2))
#define EE_AUDIO_TDMIN_B_MASK3 (0xff642000 + (0x0d5 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MASK3 (0xff642000 + (0x0d5 << 2))
#define P_EE_AUDIO_TDMIN_B_MASK3 (volatile uint32_t *)(0xff642000 + (0x0d5 << 2))
#define EE_AUDIO_TDMIN_B_STAT (0xff642000 + (0x0d6 << 2))
#define SEC_EE_AUDIO_TDMIN_B_STAT (0xff642000 + (0x0d6 << 2))
#define P_EE_AUDIO_TDMIN_B_STAT (volatile uint32_t *)(0xff642000 + (0x0d6 << 2))
#define EE_AUDIO_TDMIN_B_MUTE_VAL (0xff642000 + (0x0d7 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MUTE_VAL (0xff642000 + (0x0d7 << 2))
#define P_EE_AUDIO_TDMIN_B_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0d7 << 2))
#define EE_AUDIO_TDMIN_B_MUTE0 (0xff642000 + (0x0d8 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MUTE0 (0xff642000 + (0x0d8 << 2))
#define P_EE_AUDIO_TDMIN_B_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0d8 << 2))
#define EE_AUDIO_TDMIN_B_MUTE1 (0xff642000 + (0x0d9 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MUTE1 (0xff642000 + (0x0d9 << 2))
#define P_EE_AUDIO_TDMIN_B_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0d9 << 2))
#define EE_AUDIO_TDMIN_B_MUTE2 (0xff642000 + (0x0da << 2))
#define SEC_EE_AUDIO_TDMIN_B_MUTE2 (0xff642000 + (0x0da << 2))
#define P_EE_AUDIO_TDMIN_B_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0da << 2))
#define EE_AUDIO_TDMIN_B_MUTE3 (0xff642000 + (0x0db << 2))
#define SEC_EE_AUDIO_TDMIN_B_MUTE3 (0xff642000 + (0x0db << 2))
#define P_EE_AUDIO_TDMIN_B_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0db << 2))
#define EE_AUDIO_TDMIN_C_CTRL (0xff642000 + (0x0e0 << 2))
#define SEC_EE_AUDIO_TDMIN_C_CTRL (0xff642000 + (0x0e0 << 2))
#define P_EE_AUDIO_TDMIN_C_CTRL (volatile uint32_t *)(0xff642000 + (0x0e0 << 2))
#define EE_AUDIO_TDMIN_C_SWAP (0xff642000 + (0x0e1 << 2))
#define SEC_EE_AUDIO_TDMIN_C_SWAP (0xff642000 + (0x0e1 << 2))
#define P_EE_AUDIO_TDMIN_C_SWAP (volatile uint32_t *)(0xff642000 + (0x0e1 << 2))
#define EE_AUDIO_TDMIN_C_MASK0 (0xff642000 + (0x0e2 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MASK0 (0xff642000 + (0x0e2 << 2))
#define P_EE_AUDIO_TDMIN_C_MASK0 (volatile uint32_t *)(0xff642000 + (0x0e2 << 2))
#define EE_AUDIO_TDMIN_C_MASK1 (0xff642000 + (0x0e3 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MASK1 (0xff642000 + (0x0e3 << 2))
#define P_EE_AUDIO_TDMIN_C_MASK1 (volatile uint32_t *)(0xff642000 + (0x0e3 << 2))
#define EE_AUDIO_TDMIN_C_MASK2 (0xff642000 + (0x0e4 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MASK2 (0xff642000 + (0x0e4 << 2))
#define P_EE_AUDIO_TDMIN_C_MASK2 (volatile uint32_t *)(0xff642000 + (0x0e4 << 2))
#define EE_AUDIO_TDMIN_C_MASK3 (0xff642000 + (0x0e5 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MASK3 (0xff642000 + (0x0e5 << 2))
#define P_EE_AUDIO_TDMIN_C_MASK3 (volatile uint32_t *)(0xff642000 + (0x0e5 << 2))
#define EE_AUDIO_TDMIN_C_STAT (0xff642000 + (0x0e6 << 2))
#define SEC_EE_AUDIO_TDMIN_C_STAT (0xff642000 + (0x0e6 << 2))
#define P_EE_AUDIO_TDMIN_C_STAT (volatile uint32_t *)(0xff642000 + (0x0e6 << 2))
#define EE_AUDIO_TDMIN_C_MUTE_VAL (0xff642000 + (0x0e7 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MUTE_VAL (0xff642000 + (0x0e7 << 2))
#define P_EE_AUDIO_TDMIN_C_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0e7 << 2))
#define EE_AUDIO_TDMIN_C_MUTE0 (0xff642000 + (0x0e8 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MUTE0 (0xff642000 + (0x0e8 << 2))
#define P_EE_AUDIO_TDMIN_C_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0e8 << 2))
#define EE_AUDIO_TDMIN_C_MUTE1 (0xff642000 + (0x0e9 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MUTE1 (0xff642000 + (0x0e9 << 2))
#define P_EE_AUDIO_TDMIN_C_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0e9 << 2))
#define EE_AUDIO_TDMIN_C_MUTE2 (0xff642000 + (0x0ea << 2))
#define SEC_EE_AUDIO_TDMIN_C_MUTE2 (0xff642000 + (0x0ea << 2))
#define P_EE_AUDIO_TDMIN_C_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0ea << 2))
#define EE_AUDIO_TDMIN_C_MUTE3 (0xff642000 + (0x0eb << 2))
#define SEC_EE_AUDIO_TDMIN_C_MUTE3 (0xff642000 + (0x0eb << 2))
#define P_EE_AUDIO_TDMIN_C_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0eb << 2))
#define EE_AUDIO_TDMIN_LB_CTRL (0xff642000 + (0x0f0 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_CTRL (0xff642000 + (0x0f0 << 2))
#define P_EE_AUDIO_TDMIN_LB_CTRL (volatile uint32_t *)(0xff642000 + (0x0f0 << 2))
#define EE_AUDIO_TDMIN_LB_SWAP (0xff642000 + (0x0f1 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_SWAP (0xff642000 + (0x0f1 << 2))
#define P_EE_AUDIO_TDMIN_LB_SWAP (volatile uint32_t *)(0xff642000 + (0x0f1 << 2))
#define EE_AUDIO_TDMIN_LB_MASK0 (0xff642000 + (0x0f2 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MASK0 (0xff642000 + (0x0f2 << 2))
#define P_EE_AUDIO_TDMIN_LB_MASK0 (volatile uint32_t *)(0xff642000 + (0x0f2 << 2))
#define EE_AUDIO_TDMIN_LB_MASK1 (0xff642000 + (0x0f3 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MASK1 (0xff642000 + (0x0f3 << 2))
#define P_EE_AUDIO_TDMIN_LB_MASK1 (volatile uint32_t *)(0xff642000 + (0x0f3 << 2))
#define EE_AUDIO_TDMIN_LB_MASK2 (0xff642000 + (0x0f4 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MASK2 (0xff642000 + (0x0f4 << 2))
#define P_EE_AUDIO_TDMIN_LB_MASK2 (volatile uint32_t *)(0xff642000 + (0x0f4 << 2))
#define EE_AUDIO_TDMIN_LB_MASK3 (0xff642000 + (0x0f5 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MASK3 (0xff642000 + (0x0f5 << 2))
#define P_EE_AUDIO_TDMIN_LB_MASK3 (volatile uint32_t *)(0xff642000 + (0x0f5 << 2))
#define EE_AUDIO_TDMIN_LB_STAT (0xff642000 + (0x0f6 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_STAT (0xff642000 + (0x0f6 << 2))
#define P_EE_AUDIO_TDMIN_LB_STAT (volatile uint32_t *)(0xff642000 + (0x0f6 << 2))
#define EE_AUDIO_TDMIN_LB_MUTE_VAL (0xff642000 + (0x0f7 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MUTE_VAL (0xff642000 + (0x0f7 << 2))
#define P_EE_AUDIO_TDMIN_LB_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0f7 << 2))
#define EE_AUDIO_TDMIN_LB_MUTE0 (0xff642000 + (0x0f8 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MUTE0 (0xff642000 + (0x0f8 << 2))
#define P_EE_AUDIO_TDMIN_LB_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0f8 << 2))
#define EE_AUDIO_TDMIN_LB_MUTE1 (0xff642000 + (0x0f9 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MUTE1 (0xff642000 + (0x0f9 << 2))
#define P_EE_AUDIO_TDMIN_LB_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0f9 << 2))
#define EE_AUDIO_TDMIN_LB_MUTE2 (0xff642000 + (0x0fa << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MUTE2 (0xff642000 + (0x0fa << 2))
#define P_EE_AUDIO_TDMIN_LB_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0fa << 2))
#define EE_AUDIO_TDMIN_LB_MUTE3 (0xff642000 + (0x0fb << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MUTE3 (0xff642000 + (0x0fb << 2))
#define P_EE_AUDIO_TDMIN_LB_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0fb << 2))
#define EE_AUDIO_SPDIFIN_CTRL0 (0xff642000 + (0x100 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL0 (0xff642000 + (0x100 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL0 (volatile uint32_t *)(0xff642000 + (0x100 << 2))
#define EE_AUDIO_SPDIFIN_CTRL1 (0xff642000 + (0x101 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL1 (0xff642000 + (0x101 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL1 (volatile uint32_t *)(0xff642000 + (0x101 << 2))
#define EE_AUDIO_SPDIFIN_CTRL2 (0xff642000 + (0x102 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL2 (0xff642000 + (0x102 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL2 (volatile uint32_t *)(0xff642000 + (0x102 << 2))
#define EE_AUDIO_SPDIFIN_CTRL3 (0xff642000 + (0x103 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL3 (0xff642000 + (0x103 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL3 (volatile uint32_t *)(0xff642000 + (0x103 << 2))
#define EE_AUDIO_SPDIFIN_CTRL4 (0xff642000 + (0x104 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL4 (0xff642000 + (0x104 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL4 (volatile uint32_t *)(0xff642000 + (0x104 << 2))
#define EE_AUDIO_SPDIFIN_CTRL5 (0xff642000 + (0x105 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL5 (0xff642000 + (0x105 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL5 (volatile uint32_t *)(0xff642000 + (0x105 << 2))
#define EE_AUDIO_SPDIFIN_CTRL6 (0xff642000 + (0x106 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL6 (0xff642000 + (0x106 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL6 (volatile uint32_t *)(0xff642000 + (0x106 << 2))
#define EE_AUDIO_SPDIFIN_STAT0 (0xff642000 + (0x107 << 2))
#define SEC_EE_AUDIO_SPDIFIN_STAT0 (0xff642000 + (0x107 << 2))
#define P_EE_AUDIO_SPDIFIN_STAT0 (volatile uint32_t *)(0xff642000 + (0x107 << 2))
#define EE_AUDIO_SPDIFIN_STAT1 (0xff642000 + (0x108 << 2))
#define SEC_EE_AUDIO_SPDIFIN_STAT1 (0xff642000 + (0x108 << 2))
#define P_EE_AUDIO_SPDIFIN_STAT1 (volatile uint32_t *)(0xff642000 + (0x108 << 2))
#define EE_AUDIO_SPDIFIN_STAT2 (0xff642000 + (0x109 << 2))
#define SEC_EE_AUDIO_SPDIFIN_STAT2 (0xff642000 + (0x109 << 2))
#define P_EE_AUDIO_SPDIFIN_STAT2 (volatile uint32_t *)(0xff642000 + (0x109 << 2))
#define EE_AUDIO_SPDIFIN_MUTE_VAL (0xff642000 + (0x10a << 2))
#define SEC_EE_AUDIO_SPDIFIN_MUTE_VAL (0xff642000 + (0x10a << 2))
#define P_EE_AUDIO_SPDIFIN_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x10a << 2))
#define EE_AUDIO_RESAMPLE_CTRL0 (0xff642000 + (0x110 << 2))
#define SEC_EE_AUDIO_RESAMPLE_CTRL0 (0xff642000 + (0x110 << 2))
#define P_EE_AUDIO_RESAMPLE_CTRL0 (volatile uint32_t *)(0xff642000 + (0x110 << 2))
#define EE_AUDIO_RESAMPLE_CTRL1 (0xff642000 + (0x111 << 2))
#define SEC_EE_AUDIO_RESAMPLE_CTRL1 (0xff642000 + (0x111 << 2))
#define P_EE_AUDIO_RESAMPLE_CTRL1 (volatile uint32_t *)(0xff642000 + (0x111 << 2))
#define EE_AUDIO_RESAMPLE_CTRL2 (0xff642000 + (0x112 << 2))
#define SEC_EE_AUDIO_RESAMPLE_CTRL2 (0xff642000 + (0x112 << 2))
#define P_EE_AUDIO_RESAMPLE_CTRL2 (volatile uint32_t *)(0xff642000 + (0x112 << 2))
#define EE_AUDIO_RESAMPLE_CTRL3 (0xff642000 + (0x113 << 2))
#define SEC_EE_AUDIO_RESAMPLE_CTRL3 (0xff642000 + (0x113 << 2))
#define P_EE_AUDIO_RESAMPLE_CTRL3 (volatile uint32_t *)(0xff642000 + (0x113 << 2))
#define EE_AUDIO_RESAMPLE_COEF0 (0xff642000 + (0x114 << 2))
#define SEC_EE_AUDIO_RESAMPLE_COEF0 (0xff642000 + (0x114 << 2))
#define P_EE_AUDIO_RESAMPLE_COEF0 (volatile uint32_t *)(0xff642000 + (0x114 << 2))
#define EE_AUDIO_RESAMPLE_COEF1 (0xff642000 + (0x115 << 2))
#define SEC_EE_AUDIO_RESAMPLE_COEF1 (0xff642000 + (0x115 << 2))
#define P_EE_AUDIO_RESAMPLE_COEF1 (volatile uint32_t *)(0xff642000 + (0x115 << 2))
#define EE_AUDIO_RESAMPLE_COEF2 (0xff642000 + (0x116 << 2))
#define SEC_EE_AUDIO_RESAMPLE_COEF2 (0xff642000 + (0x116 << 2))
#define P_EE_AUDIO_RESAMPLE_COEF2 (volatile uint32_t *)(0xff642000 + (0x116 << 2))
#define EE_AUDIO_RESAMPLE_COEF3 (0xff642000 + (0x117 << 2))
#define SEC_EE_AUDIO_RESAMPLE_COEF3 (0xff642000 + (0x117 << 2))
#define P_EE_AUDIO_RESAMPLE_COEF3 (volatile uint32_t *)(0xff642000 + (0x117 << 2))
#define EE_AUDIO_RESAMPLE_COEF4 (0xff642000 + (0x118 << 2))
#define SEC_EE_AUDIO_RESAMPLE_COEF4 (0xff642000 + (0x118 << 2))
#define P_EE_AUDIO_RESAMPLE_COEF4 (volatile uint32_t *)(0xff642000 + (0x118 << 2))
#define EE_AUDIO_RESAMPLE_STATUS1 (0xff642000 + (0x119 << 2))
#define SEC_EE_AUDIO_RESAMPLE_STATUS1 (0xff642000 + (0x119 << 2))
#define P_EE_AUDIO_RESAMPLE_STATUS1 (volatile uint32_t *)(0xff642000 + (0x119 << 2))
#define EE_AUDIO_SPDIFOUT_STAT (0xff642000 + (0x120 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_STAT (0xff642000 + (0x120 << 2))
#define P_EE_AUDIO_SPDIFOUT_STAT (volatile uint32_t *)(0xff642000 + (0x120 << 2))
#define EE_AUDIO_SPDIFOUT_GAIN0 (0xff642000 + (0x121 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_GAIN0 (0xff642000 + (0x121 << 2))
#define P_EE_AUDIO_SPDIFOUT_GAIN0 (volatile uint32_t *)(0xff642000 + (0x121 << 2))
#define EE_AUDIO_SPDIFOUT_GAIN1 (0xff642000 + (0x122 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_GAIN1 (0xff642000 + (0x122 << 2))
#define P_EE_AUDIO_SPDIFOUT_GAIN1 (volatile uint32_t *)(0xff642000 + (0x122 << 2))
#define EE_AUDIO_SPDIFOUT_CTRL0 (0xff642000 + (0x123 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CTRL0 (0xff642000 + (0x123 << 2))
#define P_EE_AUDIO_SPDIFOUT_CTRL0 (volatile uint32_t *)(0xff642000 + (0x123 << 2))
#define EE_AUDIO_SPDIFOUT_CTRL1 (0xff642000 + (0x124 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CTRL1 (0xff642000 + (0x124 << 2))
#define P_EE_AUDIO_SPDIFOUT_CTRL1 (volatile uint32_t *)(0xff642000 + (0x124 << 2))
#define EE_AUDIO_SPDIFOUT_PREAMB (0xff642000 + (0x125 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_PREAMB (0xff642000 + (0x125 << 2))
#define P_EE_AUDIO_SPDIFOUT_PREAMB (volatile uint32_t *)(0xff642000 + (0x125 << 2))
#define EE_AUDIO_SPDIFOUT_SWAP (0xff642000 + (0x126 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_SWAP (0xff642000 + (0x126 << 2))
#define P_EE_AUDIO_SPDIFOUT_SWAP (volatile uint32_t *)(0xff642000 + (0x126 << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS0 (0xff642000 + (0x127 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS0 (0xff642000 + (0x127 << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS0 (volatile uint32_t *)(0xff642000 + (0x127 << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS1 (0xff642000 + (0x128 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS1 (0xff642000 + (0x128 << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS1 (volatile uint32_t *)(0xff642000 + (0x128 << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS2 (0xff642000 + (0x129 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS2 (0xff642000 + (0x129 << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS2 (volatile uint32_t *)(0xff642000 + (0x129 << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS3 (0xff642000 + (0x12a << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS3 (0xff642000 + (0x12a << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS3 (volatile uint32_t *)(0xff642000 + (0x12a << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS4 (0xff642000 + (0x12b << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS4 (0xff642000 + (0x12b << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS4 (volatile uint32_t *)(0xff642000 + (0x12b << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS5 (0xff642000 + (0x12c << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS5 (0xff642000 + (0x12c << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS5 (volatile uint32_t *)(0xff642000 + (0x12c << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS6 (0xff642000 + (0x12d << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS6 (0xff642000 + (0x12d << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS6 (volatile uint32_t *)(0xff642000 + (0x12d << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS7 (0xff642000 + (0x12e << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS7 (0xff642000 + (0x12e << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS7 (volatile uint32_t *)(0xff642000 + (0x12e << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS8 (0xff642000 + (0x12f << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS8 (0xff642000 + (0x12f << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS8 (volatile uint32_t *)(0xff642000 + (0x12f << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS9 (0xff642000 + (0x130 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS9 (0xff642000 + (0x130 << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS9 (volatile uint32_t *)(0xff642000 + (0x130 << 2))
#define EE_AUDIO_SPDIFOUT_CHSTSA (0xff642000 + (0x131 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTSA (0xff642000 + (0x131 << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTSA (volatile uint32_t *)(0xff642000 + (0x131 << 2))
#define EE_AUDIO_SPDIFOUT_CHSTSB (0xff642000 + (0x132 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTSB (0xff642000 + (0x132 << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTSB (volatile uint32_t *)(0xff642000 + (0x132 << 2))
#define EE_AUDIO_SPDIFOUT_MUTE_VAL (0xff642000 + (0x133 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_MUTE_VAL (0xff642000 + (0x133 << 2))
#define P_EE_AUDIO_SPDIFOUT_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x133 << 2))
#define EE_AUDIO_TDMOUT_A_CTRL0 (0xff642000 + (0x140 << 2))
#define SEC_EE_AUDIO_TDMOUT_A_CTRL0 (0xff642000 + (0x140 << 2))
#define P_EE_AUDIO_TDMOUT_A_CTRL0 (volatile uint32_t *)(0xff642000 + (0x140 << 2))
#define EE_AUDIO_TDMOUT_A_CTRL1 (0xff642000 + (0x141 << 2))
#define SEC_EE_AUDIO_TDMOUT_A_CTRL1 (0xff642000 + (0x141 << 2))
#define P_EE_AUDIO_TDMOUT_A_CTRL1 (volatile uint32_t *)(0xff642000 + (0x141 << 2))
#define EE_AUDIO_TDMOUT_A_SWAP (0xff642000 + (0x142 << 2))
#define SEC_EE_AUDIO_TDMOUT_A_SWAP (0xff642000 + (0x142 << 2))
#define P_EE_AUDIO_TDMOUT_A_SWAP (volatile uint32_t *)(0xff642000 + (0x142 << 2))
#define EE_AUDIO_TDMOUT_A_MASK0 (0xff642000 + (0x143 << 2))
#define SEC_EE_AUDIO_TDMOUT_A_MASK0 (0xff642000 + (0x143 << 2))
#define P_EE_AUDIO_TDMOUT_A_MASK0 (volatile uint32_t *)(0xff642000 + (0x143 << 2))
#define EE_AUDIO_TDMOUT_A_MASK1 (0xff642000 + (0x144 << 2))
#define SEC_EE_AUDIO_TDMOUT_A_MASK1 (0xff642000 + (0x144 << 2))
#define P_EE_AUDIO_TDMOUT_A_MASK1 (volatile uint32_t *)(0xff642000 + (0x144 << 2))
#define EE_AUDIO_TDMOUT_A_MASK2 (0xff642000 + (0x145 << 2))
#define SEC_EE_AUDIO_TDMOUT_A_MASK2 (0xff642000 + (0x145 << 2))
#define P_EE_AUDIO_TDMOUT_A_MASK2 (volatile uint32_t *)(0xff642000 + (0x145 << 2))
#define EE_AUDIO_TDMOUT_A_MASK3 (0xff642000 + (0x146 << 2))
#define SEC_EE_AUDIO_TDMOUT_A_MASK3 (0xff642000 + (0x146 << 2))
#define P_EE_AUDIO_TDMOUT_A_MASK3 (volatile uint32_t *)(0xff642000 + (0x146 << 2))
#define EE_AUDIO_TDMOUT_A_STAT (0xff642000 + (0x147 << 2))
#define SEC_EE_AUDIO_TDMOUT_A_STAT (0xff642000 + (0x147 << 2))
#define P_EE_AUDIO_TDMOUT_A_STAT (volatile uint32_t *)(0xff642000 + (0x147 << 2))
#define EE_AUDIO_TDMOUT_A_GAIN0 (0xff642000 + (0x148 << 2))
#define SEC_EE_AUDIO_TDMOUT_A_GAIN0 (0xff642000 + (0x148 << 2))
#define P_EE_AUDIO_TDMOUT_A_GAIN0 (volatile uint32_t *)(0xff642000 + (0x148 << 2))
#define EE_AUDIO_TDMOUT_A_GAIN1 (0xff642000 + (0x149 << 2))
#define SEC_EE_AUDIO_TDMOUT_A_GAIN1 (0xff642000 + (0x149 << 2))
#define P_EE_AUDIO_TDMOUT_A_GAIN1 (volatile uint32_t *)(0xff642000 + (0x149 << 2))
#define EE_AUDIO_TDMOUT_A_MUTE_VAL (0xff642000 + (0x14a << 2))
#define SEC_EE_AUDIO_TDMOUT_A_MUTE_VAL (0xff642000 + (0x14a << 2))
#define P_EE_AUDIO_TDMOUT_A_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x14a << 2))
#define EE_AUDIO_TDMOUT_A_MUTE0 (0xff642000 + (0x14b << 2))
#define SEC_EE_AUDIO_TDMOUT_A_MUTE0 (0xff642000 + (0x14b << 2))
#define P_EE_AUDIO_TDMOUT_A_MUTE0 (volatile uint32_t *)(0xff642000 + (0x14b << 2))
#define EE_AUDIO_TDMOUT_A_MUTE1 (0xff642000 + (0x14c << 2))
#define SEC_EE_AUDIO_TDMOUT_A_MUTE1 (0xff642000 + (0x14c << 2))
#define P_EE_AUDIO_TDMOUT_A_MUTE1 (volatile uint32_t *)(0xff642000 + (0x14c << 2))
#define EE_AUDIO_TDMOUT_A_MUTE2 (0xff642000 + (0x14d << 2))
#define SEC_EE_AUDIO_TDMOUT_A_MUTE2 (0xff642000 + (0x14d << 2))
#define P_EE_AUDIO_TDMOUT_A_MUTE2 (volatile uint32_t *)(0xff642000 + (0x14d << 2))
#define EE_AUDIO_TDMOUT_A_MUTE3 (0xff642000 + (0x14e << 2))
#define SEC_EE_AUDIO_TDMOUT_A_MUTE3 (0xff642000 + (0x14e << 2))
#define P_EE_AUDIO_TDMOUT_A_MUTE3 (volatile uint32_t *)(0xff642000 + (0x14e << 2))
#define EE_AUDIO_TDMOUT_A_MASK_VAL (0xff642000 + (0x14f << 2))
#define SEC_EE_AUDIO_TDMOUT_A_MASK_VAL (0xff642000 + (0x14f << 2))
#define P_EE_AUDIO_TDMOUT_A_MASK_VAL (volatile uint32_t *)(0xff642000 + (0x14f << 2))
#define EE_AUDIO_TDMOUT_B_CTRL0 (0xff642000 + (0x150 << 2))
#define SEC_EE_AUDIO_TDMOUT_B_CTRL0 (0xff642000 + (0x150 << 2))
#define P_EE_AUDIO_TDMOUT_B_CTRL0 (volatile uint32_t *)(0xff642000 + (0x150 << 2))
#define EE_AUDIO_TDMOUT_B_CTRL1 (0xff642000 + (0x151 << 2))
#define SEC_EE_AUDIO_TDMOUT_B_CTRL1 (0xff642000 + (0x151 << 2))
#define P_EE_AUDIO_TDMOUT_B_CTRL1 (volatile uint32_t *)(0xff642000 + (0x151 << 2))
#define EE_AUDIO_TDMOUT_B_SWAP (0xff642000 + (0x152 << 2))
#define SEC_EE_AUDIO_TDMOUT_B_SWAP (0xff642000 + (0x152 << 2))
#define P_EE_AUDIO_TDMOUT_B_SWAP (volatile uint32_t *)(0xff642000 + (0x152 << 2))
#define EE_AUDIO_TDMOUT_B_MASK0 (0xff642000 + (0x153 << 2))
#define SEC_EE_AUDIO_TDMOUT_B_MASK0 (0xff642000 + (0x153 << 2))
#define P_EE_AUDIO_TDMOUT_B_MASK0 (volatile uint32_t *)(0xff642000 + (0x153 << 2))
#define EE_AUDIO_TDMOUT_B_MASK1 (0xff642000 + (0x154 << 2))
#define SEC_EE_AUDIO_TDMOUT_B_MASK1 (0xff642000 + (0x154 << 2))
#define P_EE_AUDIO_TDMOUT_B_MASK1 (volatile uint32_t *)(0xff642000 + (0x154 << 2))
#define EE_AUDIO_TDMOUT_B_MASK2 (0xff642000 + (0x155 << 2))
#define SEC_EE_AUDIO_TDMOUT_B_MASK2 (0xff642000 + (0x155 << 2))
#define P_EE_AUDIO_TDMOUT_B_MASK2 (volatile uint32_t *)(0xff642000 + (0x155 << 2))
#define EE_AUDIO_TDMOUT_B_MASK3 (0xff642000 + (0x156 << 2))
#define SEC_EE_AUDIO_TDMOUT_B_MASK3 (0xff642000 + (0x156 << 2))
#define P_EE_AUDIO_TDMOUT_B_MASK3 (volatile uint32_t *)(0xff642000 + (0x156 << 2))
#define EE_AUDIO_TDMOUT_B_STAT (0xff642000 + (0x157 << 2))
#define SEC_EE_AUDIO_TDMOUT_B_STAT (0xff642000 + (0x157 << 2))
#define P_EE_AUDIO_TDMOUT_B_STAT (volatile uint32_t *)(0xff642000 + (0x157 << 2))
#define EE_AUDIO_TDMOUT_B_GAIN0 (0xff642000 + (0x158 << 2))
#define SEC_EE_AUDIO_TDMOUT_B_GAIN0 (0xff642000 + (0x158 << 2))
#define P_EE_AUDIO_TDMOUT_B_GAIN0 (volatile uint32_t *)(0xff642000 + (0x158 << 2))
#define EE_AUDIO_TDMOUT_B_GAIN1 (0xff642000 + (0x159 << 2))
#define SEC_EE_AUDIO_TDMOUT_B_GAIN1 (0xff642000 + (0x159 << 2))
#define P_EE_AUDIO_TDMOUT_B_GAIN1 (volatile uint32_t *)(0xff642000 + (0x159 << 2))
#define EE_AUDIO_TDMOUT_B_MUTE_VAL (0xff642000 + (0x15a << 2))
#define SEC_EE_AUDIO_TDMOUT_B_MUTE_VAL (0xff642000 + (0x15a << 2))
#define P_EE_AUDIO_TDMOUT_B_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x15a << 2))
#define EE_AUDIO_TDMOUT_B_MUTE0 (0xff642000 + (0x15b << 2))
#define SEC_EE_AUDIO_TDMOUT_B_MUTE0 (0xff642000 + (0x15b << 2))
#define P_EE_AUDIO_TDMOUT_B_MUTE0 (volatile uint32_t *)(0xff642000 + (0x15b << 2))
#define EE_AUDIO_TDMOUT_B_MUTE1 (0xff642000 + (0x15c << 2))
#define SEC_EE_AUDIO_TDMOUT_B_MUTE1 (0xff642000 + (0x15c << 2))
#define P_EE_AUDIO_TDMOUT_B_MUTE1 (volatile uint32_t *)(0xff642000 + (0x15c << 2))
#define EE_AUDIO_TDMOUT_B_MUTE2 (0xff642000 + (0x15d << 2))
#define SEC_EE_AUDIO_TDMOUT_B_MUTE2 (0xff642000 + (0x15d << 2))
#define P_EE_AUDIO_TDMOUT_B_MUTE2 (volatile uint32_t *)(0xff642000 + (0x15d << 2))
#define EE_AUDIO_TDMOUT_B_MUTE3 (0xff642000 + (0x15e << 2))
#define SEC_EE_AUDIO_TDMOUT_B_MUTE3 (0xff642000 + (0x15e << 2))
#define P_EE_AUDIO_TDMOUT_B_MUTE3 (volatile uint32_t *)(0xff642000 + (0x15e << 2))
#define EE_AUDIO_TDMOUT_B_MASK_VAL (0xff642000 + (0x15f << 2))
#define SEC_EE_AUDIO_TDMOUT_B_MASK_VAL (0xff642000 + (0x15f << 2))
#define P_EE_AUDIO_TDMOUT_B_MASK_VAL (volatile uint32_t *)(0xff642000 + (0x15f << 2))
#define EE_AUDIO_TDMOUT_C_CTRL0 (0xff642000 + (0x160 << 2))
#define SEC_EE_AUDIO_TDMOUT_C_CTRL0 (0xff642000 + (0x160 << 2))
#define P_EE_AUDIO_TDMOUT_C_CTRL0 (volatile uint32_t *)(0xff642000 + (0x160 << 2))
#define EE_AUDIO_TDMOUT_C_CTRL1 (0xff642000 + (0x161 << 2))
#define SEC_EE_AUDIO_TDMOUT_C_CTRL1 (0xff642000 + (0x161 << 2))
#define P_EE_AUDIO_TDMOUT_C_CTRL1 (volatile uint32_t *)(0xff642000 + (0x161 << 2))
#define EE_AUDIO_TDMOUT_C_SWAP (0xff642000 + (0x162 << 2))
#define SEC_EE_AUDIO_TDMOUT_C_SWAP (0xff642000 + (0x162 << 2))
#define P_EE_AUDIO_TDMOUT_C_SWAP (volatile uint32_t *)(0xff642000 + (0x162 << 2))
#define EE_AUDIO_TDMOUT_C_MASK0 (0xff642000 + (0x163 << 2))
#define SEC_EE_AUDIO_TDMOUT_C_MASK0 (0xff642000 + (0x163 << 2))
#define P_EE_AUDIO_TDMOUT_C_MASK0 (volatile uint32_t *)(0xff642000 + (0x163 << 2))
#define EE_AUDIO_TDMOUT_C_MASK1 (0xff642000 + (0x164 << 2))
#define SEC_EE_AUDIO_TDMOUT_C_MASK1 (0xff642000 + (0x164 << 2))
#define P_EE_AUDIO_TDMOUT_C_MASK1 (volatile uint32_t *)(0xff642000 + (0x164 << 2))
#define EE_AUDIO_TDMOUT_C_MASK2 (0xff642000 + (0x165 << 2))
#define SEC_EE_AUDIO_TDMOUT_C_MASK2 (0xff642000 + (0x165 << 2))
#define P_EE_AUDIO_TDMOUT_C_MASK2 (volatile uint32_t *)(0xff642000 + (0x165 << 2))
#define EE_AUDIO_TDMOUT_C_MASK3 (0xff642000 + (0x166 << 2))
#define SEC_EE_AUDIO_TDMOUT_C_MASK3 (0xff642000 + (0x166 << 2))
#define P_EE_AUDIO_TDMOUT_C_MASK3 (volatile uint32_t *)(0xff642000 + (0x166 << 2))
#define EE_AUDIO_TDMOUT_C_STAT (0xff642000 + (0x167 << 2))
#define SEC_EE_AUDIO_TDMOUT_C_STAT (0xff642000 + (0x167 << 2))
#define P_EE_AUDIO_TDMOUT_C_STAT (volatile uint32_t *)(0xff642000 + (0x167 << 2))
#define EE_AUDIO_TDMOUT_C_GAIN0 (0xff642000 + (0x168 << 2))
#define SEC_EE_AUDIO_TDMOUT_C_GAIN0 (0xff642000 + (0x168 << 2))
#define P_EE_AUDIO_TDMOUT_C_GAIN0 (volatile uint32_t *)(0xff642000 + (0x168 << 2))
#define EE_AUDIO_TDMOUT_C_GAIN1 (0xff642000 + (0x169 << 2))
#define SEC_EE_AUDIO_TDMOUT_C_GAIN1 (0xff642000 + (0x169 << 2))
#define P_EE_AUDIO_TDMOUT_C_GAIN1 (volatile uint32_t *)(0xff642000 + (0x169 << 2))
#define EE_AUDIO_TDMOUT_C_MUTE_VAL (0xff642000 + (0x16a << 2))
#define SEC_EE_AUDIO_TDMOUT_C_MUTE_VAL (0xff642000 + (0x16a << 2))
#define P_EE_AUDIO_TDMOUT_C_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x16a << 2))
#define EE_AUDIO_TDMOUT_C_MUTE0 (0xff642000 + (0x16b << 2))
#define SEC_EE_AUDIO_TDMOUT_C_MUTE0 (0xff642000 + (0x16b << 2))
#define P_EE_AUDIO_TDMOUT_C_MUTE0 (volatile uint32_t *)(0xff642000 + (0x16b << 2))
#define EE_AUDIO_TDMOUT_C_MUTE1 (0xff642000 + (0x16c << 2))
#define SEC_EE_AUDIO_TDMOUT_C_MUTE1 (0xff642000 + (0x16c << 2))
#define P_EE_AUDIO_TDMOUT_C_MUTE1 (volatile uint32_t *)(0xff642000 + (0x16c << 2))
#define EE_AUDIO_TDMOUT_C_MUTE2 (0xff642000 + (0x16d << 2))
#define SEC_EE_AUDIO_TDMOUT_C_MUTE2 (0xff642000 + (0x16d << 2))
#define P_EE_AUDIO_TDMOUT_C_MUTE2 (volatile uint32_t *)(0xff642000 + (0x16d << 2))
#define EE_AUDIO_TDMOUT_C_MUTE3 (0xff642000 + (0x16e << 2))
#define SEC_EE_AUDIO_TDMOUT_C_MUTE3 (0xff642000 + (0x16e << 2))
#define P_EE_AUDIO_TDMOUT_C_MUTE3 (volatile uint32_t *)(0xff642000 + (0x16e << 2))
#define EE_AUDIO_TDMOUT_C_MASK_VAL (0xff642000 + (0x16f << 2))
#define SEC_EE_AUDIO_TDMOUT_C_MASK_VAL (0xff642000 + (0x16f << 2))
#define P_EE_AUDIO_TDMOUT_C_MASK_VAL (volatile uint32_t *)(0xff642000 + (0x16f << 2))
#define EE_AUDIO_POW_DET_CTRL0 (0xff642000 + (0x180 << 2))
#define SEC_EE_AUDIO_POW_DET_CTRL0 (0xff642000 + (0x180 << 2))
#define P_EE_AUDIO_POW_DET_CTRL0 (volatile uint32_t *)(0xff642000 + (0x180 << 2))
#define EE_AUDIO_POW_DET_CTRL1 (0xff642000 + (0x181 << 2))
#define SEC_EE_AUDIO_POW_DET_CTRL1 (0xff642000 + (0x181 << 2))
#define P_EE_AUDIO_POW_DET_CTRL1 (volatile uint32_t *)(0xff642000 + (0x181 << 2))
#define EE_AUDIO_POW_DET_TH_HI (0xff642000 + (0x182 << 2))
#define SEC_EE_AUDIO_POW_DET_TH_HI (0xff642000 + (0x182 << 2))
#define P_EE_AUDIO_POW_DET_TH_HI (volatile uint32_t *)(0xff642000 + (0x182 << 2))
#define EE_AUDIO_POW_DET_TH_LO (0xff642000 + (0x183 << 2))
#define SEC_EE_AUDIO_POW_DET_TH_LO (0xff642000 + (0x183 << 2))
#define P_EE_AUDIO_POW_DET_TH_LO (volatile uint32_t *)(0xff642000 + (0x183 << 2))
#define EE_AUDIO_POW_DET_VALUE (0xff642000 + (0x184 << 2))
#define SEC_EE_AUDIO_POW_DET_VALUE (0xff642000 + (0x184 << 2))
#define P_EE_AUDIO_POW_DET_VALUE (volatile uint32_t *)(0xff642000 + (0x184 << 2))
#define EE_AUDIO_SECURITY_CTRL (0xff642000 + (0x193 << 2))
#define SEC_EE_AUDIO_SECURITY_CTRL (0xff642000 + (0x193 << 2))
#define P_EE_AUDIO_SECURITY_CTRL (volatile uint32_t *)(0xff642000 + (0x193 << 2))
#define EE_AUDIO_SPDIFOUT_B_STAT (0xff642000 + (0x1a0 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_STAT (0xff642000 + (0x1a0 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_STAT (volatile uint32_t *)(0xff642000 + (0x1a0 << 2))
#define EE_AUDIO_SPDIFOUT_B_GAIN0 (0xff642000 + (0x1a1 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_GAIN0 (0xff642000 + (0x1a1 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_GAIN0 (volatile uint32_t *)(0xff642000 + (0x1a1 << 2))
#define EE_AUDIO_SPDIFOUT_B_GAIN1 (0xff642000 + (0x1a2 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_GAIN1 (0xff642000 + (0x1a2 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_GAIN1 (volatile uint32_t *)(0xff642000 + (0x1a2 << 2))
#define EE_AUDIO_SPDIFOUT_B_CTRL0 (0xff642000 + (0x1a3 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CTRL0 (0xff642000 + (0x1a3 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CTRL0 (volatile uint32_t *)(0xff642000 + (0x1a3 << 2))
#define EE_AUDIO_SPDIFOUT_B_CTRL1 (0xff642000 + (0x1a4 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CTRL1 (0xff642000 + (0x1a4 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CTRL1 (volatile uint32_t *)(0xff642000 + (0x1a4 << 2))
#define EE_AUDIO_SPDIFOUT_B_PREAMB (0xff642000 + (0x1a5 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_PREAMB (0xff642000 + (0x1a5 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_PREAMB (volatile uint32_t *)(0xff642000 + (0x1a5 << 2))
#define EE_AUDIO_SPDIFOUT_B_SWAP (0xff642000 + (0x1a6 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_SWAP (0xff642000 + (0x1a6 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_SWAP (volatile uint32_t *)(0xff642000 + (0x1a6 << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTS0 (0xff642000 + (0x1a7 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS0 (0xff642000 + (0x1a7 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTS0 (volatile uint32_t *)(0xff642000 + (0x1a7 << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTS1 (0xff642000 + (0x1a8 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS1 (0xff642000 + (0x1a8 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTS1 (volatile uint32_t *)(0xff642000 + (0x1a8 << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTS2 (0xff642000 + (0x1a9 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS2 (0xff642000 + (0x1a9 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTS2 (volatile uint32_t *)(0xff642000 + (0x1a9 << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTS3 (0xff642000 + (0x1aa << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS3 (0xff642000 + (0x1aa << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTS3 (volatile uint32_t *)(0xff642000 + (0x1aa << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTS4 (0xff642000 + (0x1ab << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS4 (0xff642000 + (0x1ab << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTS4 (volatile uint32_t *)(0xff642000 + (0x1ab << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTS5 (0xff642000 + (0x1ac << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS5 (0xff642000 + (0x1ac << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTS5 (volatile uint32_t *)(0xff642000 + (0x1ac << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTS6 (0xff642000 + (0x1ad << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS6 (0xff642000 + (0x1ad << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTS6 (volatile uint32_t *)(0xff642000 + (0x1ad << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTS7 (0xff642000 + (0x1ae << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS7 (0xff642000 + (0x1ae << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTS7 (volatile uint32_t *)(0xff642000 + (0x1ae << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTS8 (0xff642000 + (0x1af << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS8 (0xff642000 + (0x1af << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTS8 (volatile uint32_t *)(0xff642000 + (0x1af << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTS9 (0xff642000 + (0x1b0 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS9 (0xff642000 + (0x1b0 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTS9 (volatile uint32_t *)(0xff642000 + (0x1b0 << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTSA (0xff642000 + (0x1b1 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTSA (0xff642000 + (0x1b1 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTSA (volatile uint32_t *)(0xff642000 + (0x1b1 << 2))
#define EE_AUDIO_SPDIFOUT_B_CHSTSB (0xff642000 + (0x1b2 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_CHSTSB (0xff642000 + (0x1b2 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_CHSTSB (volatile uint32_t *)(0xff642000 + (0x1b2 << 2))
#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL (0xff642000 + (0x1b3 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_B_MUTE_VAL (0xff642000 + (0x1b3 << 2))
#define P_EE_AUDIO_SPDIFOUT_B_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x1b3 << 2))
#define EE_AUDIO_TORAM_CTRL0 (0xff642000 + (0x1c0 << 2))
#define SEC_EE_AUDIO_TORAM_CTRL0 (0xff642000 + (0x1c0 << 2))
#define P_EE_AUDIO_TORAM_CTRL0 (volatile uint32_t *)(0xff642000 + (0x1c0 << 2))
#define EE_AUDIO_TORAM_CTRL1 (0xff642000 + (0x1c1 << 2))
#define SEC_EE_AUDIO_TORAM_CTRL1 (0xff642000 + (0x1c1 << 2))
#define P_EE_AUDIO_TORAM_CTRL1 (volatile uint32_t *)(0xff642000 + (0x1c1 << 2))
#define EE_AUDIO_TORAM_START_ADDR (0xff642000 + (0x1c2 << 2))
#define SEC_EE_AUDIO_TORAM_START_ADDR (0xff642000 + (0x1c2 << 2))
#define P_EE_AUDIO_TORAM_START_ADDR (volatile uint32_t *)(0xff642000 + (0x1c2 << 2))
#define EE_AUDIO_TORAM_FINISH_ADDR (0xff642000 + (0x1c3 << 2))
#define SEC_EE_AUDIO_TORAM_FINISH_ADDR (0xff642000 + (0x1c3 << 2))
#define P_EE_AUDIO_TORAM_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x1c3 << 2))
#define EE_AUDIO_TORAM_INT_ADDR (0xff642000 + (0x1c4 << 2))
#define SEC_EE_AUDIO_TORAM_INT_ADDR (0xff642000 + (0x1c4 << 2))
#define P_EE_AUDIO_TORAM_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x1c4 << 2))
#define EE_AUDIO_TORAM_STATUS1 (0xff642000 + (0x1c5 << 2))
#define SEC_EE_AUDIO_TORAM_STATUS1 (0xff642000 + (0x1c5 << 2))
#define P_EE_AUDIO_TORAM_STATUS1 (volatile uint32_t *)(0xff642000 + (0x1c5 << 2))
#define EE_AUDIO_TORAM_STATUS2 (0xff642000 + (0x1c6 << 2))
#define SEC_EE_AUDIO_TORAM_STATUS2 (0xff642000 + (0x1c6 << 2))
#define P_EE_AUDIO_TORAM_STATUS2 (volatile uint32_t *)(0xff642000 + (0x1c6 << 2))
#define EE_AUDIO_TORAM_INIT_ADDR (0xff642000 + (0x1c7 << 2))
#define SEC_EE_AUDIO_TORAM_INIT_ADDR (0xff642000 + (0x1c7 << 2))
#define P_EE_AUDIO_TORAM_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x1c7 << 2))
#define EE_AUDIO_TOACODEC_CTRL0 (0xff642000 + (0x1d0 << 2))
#define SEC_EE_AUDIO_TOACODEC_CTRL0 (0xff642000 + (0x1d0 << 2))
#define P_EE_AUDIO_TOACODEC_CTRL0 (volatile uint32_t *)(0xff642000 + (0x1d0 << 2))
#define EE_AUDIO_TOHDMITX_CTRL0 (0xff642000 + (0x1d1 << 2))
#define SEC_EE_AUDIO_TOHDMITX_CTRL0 (0xff642000 + (0x1d1 << 2))
#define P_EE_AUDIO_TOHDMITX_CTRL0 (volatile uint32_t *)(0xff642000 + (0x1d1 << 2))
//eq drc register
#define AED_EQ_CH1_COEF00 (0xff642000 + (0x200 << 2))
#define SEC_AED_EQ_CH1_COEF00 (0xff642000 + (0x200 << 2))
#define P_AED_EQ_CH1_COEF00 (volatile uint32_t *)(0xff642000 + (0x200 << 2))
#define AED_EQ_CH1_COEF01 (0xff642000 + (0x201 << 2))
#define SEC_AED_EQ_CH1_COEF01 (0xff642000 + (0x201 << 2))
#define P_AED_EQ_CH1_COEF01 (volatile uint32_t *)(0xff642000 + (0x201 << 2))
#define AED_EQ_CH1_COEF02 (0xff642000 + (0x202 << 2))
#define SEC_AED_EQ_CH1_COEF02 (0xff642000 + (0x202 << 2))
#define P_AED_EQ_CH1_COEF02 (volatile uint32_t *)(0xff642000 + (0x202 << 2))
#define AED_EQ_CH1_COEF03 (0xff642000 + (0x203 << 2))
#define SEC_AED_EQ_CH1_COEF03 (0xff642000 + (0x203 << 2))
#define P_AED_EQ_CH1_COEF03 (volatile uint32_t *)(0xff642000 + (0x203 << 2))
#define AED_EQ_CH1_COEF04 (0xff642000 + (0x204 << 2))
#define SEC_AED_EQ_CH1_COEF04 (0xff642000 + (0x204 << 2))
#define P_AED_EQ_CH1_COEF04 (volatile uint32_t *)(0xff642000 + (0x204 << 2))
#define AED_EQ_CH1_COEF10 (0xff642000 + (0x205 << 2))
#define SEC_AED_EQ_CH1_COEF10 (0xff642000 + (0x205 << 2))
#define P_AED_EQ_CH1_COEF10 (volatile uint32_t *)(0xff642000 + (0x205 << 2))
#define AED_EQ_CH1_COEF11 (0xff642000 + (0x206 << 2))
#define SEC_AED_EQ_CH1_COEF11 (0xff642000 + (0x206 << 2))
#define P_AED_EQ_CH1_COEF11 (volatile uint32_t *)(0xff642000 + (0x206 << 2))
#define AED_EQ_CH1_COEF12 (0xff642000 + (0x207 << 2))
#define SEC_AED_EQ_CH1_COEF12 (0xff642000 + (0x207 << 2))
#define P_AED_EQ_CH1_COEF12 (volatile uint32_t *)(0xff642000 + (0x207 << 2))
#define AED_EQ_CH1_COEF13 (0xff642000 + (0x208 << 2))
#define SEC_AED_EQ_CH1_COEF13 (0xff642000 + (0x208 << 2))
#define P_AED_EQ_CH1_COEF13 (volatile uint32_t *)(0xff642000 + (0x208 << 2))
#define AED_EQ_CH1_COEF14 (0xff642000 + (0x209 << 2))
#define SEC_AED_EQ_CH1_COEF14 (0xff642000 + (0x209 << 2))
#define P_AED_EQ_CH1_COEF14 (volatile uint32_t *)(0xff642000 + (0x209 << 2))
#define AED_EQ_CH1_COEF20 (0xff642000 + (0x20a << 2))
#define SEC_AED_EQ_CH1_COEF20 (0xff642000 + (0x20a << 2))
#define P_AED_EQ_CH1_COEF20 (volatile uint32_t *)(0xff642000 + (0x20a << 2))
#define AED_EQ_CH1_COEF21 (0xff642000 + (0x20b << 2))
#define SEC_AED_EQ_CH1_COEF21 (0xff642000 + (0x20b << 2))
#define P_AED_EQ_CH1_COEF21 (volatile uint32_t *)(0xff642000 + (0x20b << 2))
#define AED_EQ_CH1_COEF22 (0xff642000 + (0x20c << 2))
#define SEC_AED_EQ_CH1_COEF22 (0xff642000 + (0x20c << 2))
#define P_AED_EQ_CH1_COEF22 (volatile uint32_t *)(0xff642000 + (0x20c << 2))
#define AED_EQ_CH1_COEF23 (0xff642000 + (0x20d << 2))
#define SEC_AED_EQ_CH1_COEF23 (0xff642000 + (0x20d << 2))
#define P_AED_EQ_CH1_COEF23 (volatile uint32_t *)(0xff642000 + (0x20d << 2))
#define AED_EQ_CH1_COEF24 (0xff642000 + (0x20e << 2))
#define SEC_AED_EQ_CH1_COEF24 (0xff642000 + (0x20e << 2))
#define P_AED_EQ_CH1_COEF24 (volatile uint32_t *)(0xff642000 + (0x20e << 2))
#define AED_EQ_CH1_COEF30 (0xff642000 + (0x20f << 2))
#define SEC_AED_EQ_CH1_COEF30 (0xff642000 + (0x20f << 2))
#define P_AED_EQ_CH1_COEF30 (volatile uint32_t *)(0xff642000 + (0x20f << 2))
#define AED_EQ_CH1_COEF31 (0xff642000 + (0x210 << 2))
#define SEC_AED_EQ_CH1_COEF31 (0xff642000 + (0x210 << 2))
#define P_AED_EQ_CH1_COEF31 (volatile uint32_t *)(0xff642000 + (0x210 << 2))
#define AED_EQ_CH1_COEF32 (0xff642000 + (0x211 << 2))
#define SEC_AED_EQ_CH1_COEF32 (0xff642000 + (0x211 << 2))
#define P_AED_EQ_CH1_COEF32 (volatile uint32_t *)(0xff642000 + (0x211 << 2))
#define AED_EQ_CH1_COEF33 (0xff642000 + (0x212 << 2))
#define SEC_AED_EQ_CH1_COEF33 (0xff642000 + (0x212 << 2))
#define P_AED_EQ_CH1_COEF33 (volatile uint32_t *)(0xff642000 + (0x212 << 2))
#define AED_EQ_CH1_COEF34 (0xff642000 + (0x213 << 2))
#define SEC_AED_EQ_CH1_COEF34 (0xff642000 + (0x213 << 2))
#define P_AED_EQ_CH1_COEF34 (volatile uint32_t *)(0xff642000 + (0x213 << 2))
#define AED_EQ_CH1_COEF40 (0xff642000 + (0x214 << 2))
#define SEC_AED_EQ_CH1_COEF40 (0xff642000 + (0x214 << 2))
#define P_AED_EQ_CH1_COEF40 (volatile uint32_t *)(0xff642000 + (0x214 << 2))
#define AED_EQ_CH1_COEF41 (0xff642000 + (0x215 << 2))
#define SEC_AED_EQ_CH1_COEF41 (0xff642000 + (0x215 << 2))
#define P_AED_EQ_CH1_COEF41 (volatile uint32_t *)(0xff642000 + (0x215 << 2))
#define AED_EQ_CH1_COEF42 (0xff642000 + (0x216 << 2))
#define SEC_AED_EQ_CH1_COEF42 (0xff642000 + (0x216 << 2))
#define P_AED_EQ_CH1_COEF42 (volatile uint32_t *)(0xff642000 + (0x216 << 2))
#define AED_EQ_CH1_COEF43 (0xff642000 + (0x217 << 2))
#define SEC_AED_EQ_CH1_COEF43 (0xff642000 + (0x217 << 2))
#define P_AED_EQ_CH1_COEF43 (volatile uint32_t *)(0xff642000 + (0x217 << 2))
#define AED_EQ_CH1_COEF44 (0xff642000 + (0x218 << 2))
#define SEC_AED_EQ_CH1_COEF44 (0xff642000 + (0x218 << 2))
#define P_AED_EQ_CH1_COEF44 (volatile uint32_t *)(0xff642000 + (0x218 << 2))
#define AED_EQ_CH1_COEF50 (0xff642000 + (0x219 << 2))
#define SEC_AED_EQ_CH1_COEF50 (0xff642000 + (0x219 << 2))
#define P_AED_EQ_CH1_COEF50 (volatile uint32_t *)(0xff642000 + (0x219 << 2))
#define AED_EQ_CH1_COEF51 (0xff642000 + (0x21a << 2))
#define SEC_AED_EQ_CH1_COEF51 (0xff642000 + (0x21a << 2))
#define P_AED_EQ_CH1_COEF51 (volatile uint32_t *)(0xff642000 + (0x21a << 2))
#define AED_EQ_CH1_COEF52 (0xff642000 + (0x21b << 2))
#define SEC_AED_EQ_CH1_COEF52 (0xff642000 + (0x21b << 2))
#define P_AED_EQ_CH1_COEF52 (volatile uint32_t *)(0xff642000 + (0x21b << 2))
#define AED_EQ_CH1_COEF53 (0xff642000 + (0x21c << 2))
#define SEC_AED_EQ_CH1_COEF53 (0xff642000 + (0x21c << 2))
#define P_AED_EQ_CH1_COEF53 (volatile uint32_t *)(0xff642000 + (0x21c << 2))
#define AED_EQ_CH1_COEF54 (0xff642000 + (0x21d << 2))
#define SEC_AED_EQ_CH1_COEF54 (0xff642000 + (0x21d << 2))
#define P_AED_EQ_CH1_COEF54 (volatile uint32_t *)(0xff642000 + (0x21d << 2))
#define AED_EQ_CH1_COEF60 (0xff642000 + (0x21e << 2))
#define SEC_AED_EQ_CH1_COEF60 (0xff642000 + (0x21e << 2))
#define P_AED_EQ_CH1_COEF60 (volatile uint32_t *)(0xff642000 + (0x21e << 2))
#define AED_EQ_CH1_COEF61 (0xff642000 + (0x21f << 2))
#define SEC_AED_EQ_CH1_COEF61 (0xff642000 + (0x21f << 2))
#define P_AED_EQ_CH1_COEF61 (volatile uint32_t *)(0xff642000 + (0x21f << 2))
#define AED_EQ_CH1_COEF62 (0xff642000 + (0x220 << 2))
#define SEC_AED_EQ_CH1_COEF62 (0xff642000 + (0x220 << 2))
#define P_AED_EQ_CH1_COEF62 (volatile uint32_t *)(0xff642000 + (0x220 << 2))
#define AED_EQ_CH1_COEF63 (0xff642000 + (0x221 << 2))
#define SEC_AED_EQ_CH1_COEF63 (0xff642000 + (0x221 << 2))
#define P_AED_EQ_CH1_COEF63 (volatile uint32_t *)(0xff642000 + (0x221 << 2))
#define AED_EQ_CH1_COEF64 (0xff642000 + (0x222 << 2))
#define SEC_AED_EQ_CH1_COEF64 (0xff642000 + (0x222 << 2))
#define P_AED_EQ_CH1_COEF64 (volatile uint32_t *)(0xff642000 + (0x222 << 2))
#define AED_EQ_CH1_COEF70 (0xff642000 + (0x223 << 2))
#define SEC_AED_EQ_CH1_COEF70 (0xff642000 + (0x223 << 2))
#define P_AED_EQ_CH1_COEF70 (volatile uint32_t *)(0xff642000 + (0x223 << 2))
#define AED_EQ_CH1_COEF71 (0xff642000 + (0x224 << 2))
#define SEC_AED_EQ_CH1_COEF71 (0xff642000 + (0x224 << 2))
#define P_AED_EQ_CH1_COEF71 (volatile uint32_t *)(0xff642000 + (0x224 << 2))
#define AED_EQ_CH1_COEF72 (0xff642000 + (0x225 << 2))
#define SEC_AED_EQ_CH1_COEF72 (0xff642000 + (0x225 << 2))
#define P_AED_EQ_CH1_COEF72 (volatile uint32_t *)(0xff642000 + (0x225 << 2))
#define AED_EQ_CH1_COEF73 (0xff642000 + (0x226 << 2))
#define SEC_AED_EQ_CH1_COEF73 (0xff642000 + (0x226 << 2))
#define P_AED_EQ_CH1_COEF73 (volatile uint32_t *)(0xff642000 + (0x226 << 2))
#define AED_EQ_CH1_COEF74 (0xff642000 + (0x227 << 2))
#define SEC_AED_EQ_CH1_COEF74 (0xff642000 + (0x227 << 2))
#define P_AED_EQ_CH1_COEF74 (volatile uint32_t *)(0xff642000 + (0x227 << 2))
#define AED_EQ_CH1_COEF80 (0xff642000 + (0x228 << 2))
#define SEC_AED_EQ_CH1_COEF80 (0xff642000 + (0x228 << 2))
#define P_AED_EQ_CH1_COEF80 (volatile uint32_t *)(0xff642000 + (0x228 << 2))
#define AED_EQ_CH1_COEF81 (0xff642000 + (0x229 << 2))
#define SEC_AED_EQ_CH1_COEF81 (0xff642000 + (0x229 << 2))
#define P_AED_EQ_CH1_COEF81 (volatile uint32_t *)(0xff642000 + (0x229 << 2))
#define AED_EQ_CH1_COEF82 (0xff642000 + (0x22a << 2))
#define SEC_AED_EQ_CH1_COEF82 (0xff642000 + (0x22a << 2))
#define P_AED_EQ_CH1_COEF82 (volatile uint32_t *)(0xff642000 + (0x22a << 2))
#define AED_EQ_CH1_COEF83 (0xff642000 + (0x22b << 2))
#define SEC_AED_EQ_CH1_COEF83 (0xff642000 + (0x22b << 2))
#define P_AED_EQ_CH1_COEF83 (volatile uint32_t *)(0xff642000 + (0x22b << 2))
#define AED_EQ_CH1_COEF84 (0xff642000 + (0x22c << 2))
#define SEC_AED_EQ_CH1_COEF84 (0xff642000 + (0x22c << 2))
#define P_AED_EQ_CH1_COEF84 (volatile uint32_t *)(0xff642000 + (0x22c << 2))
#define AED_EQ_CH1_COEF90 (0xff642000 + (0x22d << 2))
#define SEC_AED_EQ_CH1_COEF90 (0xff642000 + (0x22d << 2))
#define P_AED_EQ_CH1_COEF90 (volatile uint32_t *)(0xff642000 + (0x22d << 2))
#define AED_EQ_CH1_COEF91 (0xff642000 + (0x22e << 2))
#define SEC_AED_EQ_CH1_COEF91 (0xff642000 + (0x22e << 2))
#define P_AED_EQ_CH1_COEF91 (volatile uint32_t *)(0xff642000 + (0x22e << 2))
#define AED_EQ_CH1_COEF92 (0xff642000 + (0x22f << 2))
#define SEC_AED_EQ_CH1_COEF92 (0xff642000 + (0x22f << 2))
#define P_AED_EQ_CH1_COEF92 (volatile uint32_t *)(0xff642000 + (0x22f << 2))
#define AED_EQ_CH1_COEF93 (0xff642000 + (0x230 << 2))
#define SEC_AED_EQ_CH1_COEF93 (0xff642000 + (0x230 << 2))
#define P_AED_EQ_CH1_COEF93 (volatile uint32_t *)(0xff642000 + (0x230 << 2))
#define AED_EQ_CH1_COEF94 (0xff642000 + (0x231 << 2))
#define SEC_AED_EQ_CH1_COEF94 (0xff642000 + (0x231 << 2))
#define P_AED_EQ_CH1_COEF94 (volatile uint32_t *)(0xff642000 + (0x231 << 2))
#define AED_EQ_CH2_COEF00 (0xff642000 + (0x232 << 2))
#define SEC_AED_EQ_CH2_COEF00 (0xff642000 + (0x232 << 2))
#define P_AED_EQ_CH2_COEF00 (volatile uint32_t *)(0xff642000 + (0x232 << 2))
#define AED_EQ_CH2_COEF01 (0xff642000 + (0x233 << 2))
#define SEC_AED_EQ_CH2_COEF01 (0xff642000 + (0x233 << 2))
#define P_AED_EQ_CH2_COEF01 (volatile uint32_t *)(0xff642000 + (0x233 << 2))
#define AED_EQ_CH2_COEF02 (0xff642000 + (0x234 << 2))
#define SEC_AED_EQ_CH2_COEF02 (0xff642000 + (0x234 << 2))
#define P_AED_EQ_CH2_COEF02 (volatile uint32_t *)(0xff642000 + (0x234 << 2))
#define AED_EQ_CH2_COEF03 (0xff642000 + (0x235 << 2))
#define SEC_AED_EQ_CH2_COEF03 (0xff642000 + (0x235 << 2))
#define P_AED_EQ_CH2_COEF03 (volatile uint32_t *)(0xff642000 + (0x235 << 2))
#define AED_EQ_CH2_COEF04 (0xff642000 + (0x236 << 2))
#define SEC_AED_EQ_CH2_COEF04 (0xff642000 + (0x236 << 2))
#define P_AED_EQ_CH2_COEF04 (volatile uint32_t *)(0xff642000 + (0x236 << 2))
#define AED_EQ_CH2_COEF10 (0xff642000 + (0x237 << 2))
#define SEC_AED_EQ_CH2_COEF10 (0xff642000 + (0x237 << 2))
#define P_AED_EQ_CH2_COEF10 (volatile uint32_t *)(0xff642000 + (0x237 << 2))
#define AED_EQ_CH2_COEF11 (0xff642000 + (0x238 << 2))
#define SEC_AED_EQ_CH2_COEF11 (0xff642000 + (0x238 << 2))
#define P_AED_EQ_CH2_COEF11 (volatile uint32_t *)(0xff642000 + (0x238 << 2))
#define AED_EQ_CH2_COEF12 (0xff642000 + (0x239 << 2))
#define SEC_AED_EQ_CH2_COEF12 (0xff642000 + (0x239 << 2))
#define P_AED_EQ_CH2_COEF12 (volatile uint32_t *)(0xff642000 + (0x239 << 2))
#define AED_EQ_CH2_COEF13 (0xff642000 + (0x23a << 2))
#define SEC_AED_EQ_CH2_COEF13 (0xff642000 + (0x23a << 2))
#define P_AED_EQ_CH2_COEF13 (volatile uint32_t *)(0xff642000 + (0x23a << 2))
#define AED_EQ_CH2_COEF14 (0xff642000 + (0x23b << 2))
#define SEC_AED_EQ_CH2_COEF14 (0xff642000 + (0x23b << 2))
#define P_AED_EQ_CH2_COEF14 (volatile uint32_t *)(0xff642000 + (0x23b << 2))
#define AED_EQ_CH2_COEF20 (0xff642000 + (0x23c << 2))
#define SEC_AED_EQ_CH2_COEF20 (0xff642000 + (0x23c << 2))
#define P_AED_EQ_CH2_COEF20 (volatile uint32_t *)(0xff642000 + (0x23c << 2))
#define AED_EQ_CH2_COEF21 (0xff642000 + (0x23d << 2))
#define SEC_AED_EQ_CH2_COEF21 (0xff642000 + (0x23d << 2))
#define P_AED_EQ_CH2_COEF21 (volatile uint32_t *)(0xff642000 + (0x23d << 2))
#define AED_EQ_CH2_COEF22 (0xff642000 + (0x23e << 2))
#define SEC_AED_EQ_CH2_COEF22 (0xff642000 + (0x23e << 2))
#define P_AED_EQ_CH2_COEF22 (volatile uint32_t *)(0xff642000 + (0x23e << 2))
#define AED_EQ_CH2_COEF23 (0xff642000 + (0x23f << 2))
#define SEC_AED_EQ_CH2_COEF23 (0xff642000 + (0x23f << 2))
#define P_AED_EQ_CH2_COEF23 (volatile uint32_t *)(0xff642000 + (0x23f << 2))
#define AED_EQ_CH2_COEF24 (0xff642000 + (0x240 << 2))
#define SEC_AED_EQ_CH2_COEF24 (0xff642000 + (0x240 << 2))
#define P_AED_EQ_CH2_COEF24 (volatile uint32_t *)(0xff642000 + (0x240 << 2))
#define AED_EQ_CH2_COEF30 (0xff642000 + (0x241 << 2))
#define SEC_AED_EQ_CH2_COEF30 (0xff642000 + (0x241 << 2))
#define P_AED_EQ_CH2_COEF30 (volatile uint32_t *)(0xff642000 + (0x241 << 2))
#define AED_EQ_CH2_COEF31 (0xff642000 + (0x242 << 2))
#define SEC_AED_EQ_CH2_COEF31 (0xff642000 + (0x242 << 2))
#define P_AED_EQ_CH2_COEF31 (volatile uint32_t *)(0xff642000 + (0x242 << 2))
#define AED_EQ_CH2_COEF32 (0xff642000 + (0x243 << 2))
#define SEC_AED_EQ_CH2_COEF32 (0xff642000 + (0x243 << 2))
#define P_AED_EQ_CH2_COEF32 (volatile uint32_t *)(0xff642000 + (0x243 << 2))
#define AED_EQ_CH2_COEF33 (0xff642000 + (0x244 << 2))
#define SEC_AED_EQ_CH2_COEF33 (0xff642000 + (0x244 << 2))
#define P_AED_EQ_CH2_COEF33 (volatile uint32_t *)(0xff642000 + (0x244 << 2))
#define AED_EQ_CH2_COEF34 (0xff642000 + (0x245 << 2))
#define SEC_AED_EQ_CH2_COEF34 (0xff642000 + (0x245 << 2))
#define P_AED_EQ_CH2_COEF34 (volatile uint32_t *)(0xff642000 + (0x245 << 2))
#define AED_EQ_CH2_COEF40 (0xff642000 + (0x246 << 2))
#define SEC_AED_EQ_CH2_COEF40 (0xff642000 + (0x246 << 2))
#define P_AED_EQ_CH2_COEF40 (volatile uint32_t *)(0xff642000 + (0x246 << 2))
#define AED_EQ_CH2_COEF41 (0xff642000 + (0x247 << 2))
#define SEC_AED_EQ_CH2_COEF41 (0xff642000 + (0x247 << 2))
#define P_AED_EQ_CH2_COEF41 (volatile uint32_t *)(0xff642000 + (0x247 << 2))
#define AED_EQ_CH2_COEF42 (0xff642000 + (0x248 << 2))
#define SEC_AED_EQ_CH2_COEF42 (0xff642000 + (0x248 << 2))
#define P_AED_EQ_CH2_COEF42 (volatile uint32_t *)(0xff642000 + (0x248 << 2))
#define AED_EQ_CH2_COEF43 (0xff642000 + (0x249 << 2))
#define SEC_AED_EQ_CH2_COEF43 (0xff642000 + (0x249 << 2))
#define P_AED_EQ_CH2_COEF43 (volatile uint32_t *)(0xff642000 + (0x249 << 2))
#define AED_EQ_CH2_COEF44 (0xff642000 + (0x24a << 2))
#define SEC_AED_EQ_CH2_COEF44 (0xff642000 + (0x24a << 2))
#define P_AED_EQ_CH2_COEF44 (volatile uint32_t *)(0xff642000 + (0x24a << 2))
#define AED_EQ_CH2_COEF50 (0xff642000 + (0x24b << 2))
#define SEC_AED_EQ_CH2_COEF50 (0xff642000 + (0x24b << 2))
#define P_AED_EQ_CH2_COEF50 (volatile uint32_t *)(0xff642000 + (0x24b << 2))
#define AED_EQ_CH2_COEF51 (0xff642000 + (0x24c << 2))
#define SEC_AED_EQ_CH2_COEF51 (0xff642000 + (0x24c << 2))
#define P_AED_EQ_CH2_COEF51 (volatile uint32_t *)(0xff642000 + (0x24c << 2))
#define AED_EQ_CH2_COEF52 (0xff642000 + (0x24d << 2))
#define SEC_AED_EQ_CH2_COEF52 (0xff642000 + (0x24d << 2))
#define P_AED_EQ_CH2_COEF52 (volatile uint32_t *)(0xff642000 + (0x24d << 2))
#define AED_EQ_CH2_COEF53 (0xff642000 + (0x24e << 2))
#define SEC_AED_EQ_CH2_COEF53 (0xff642000 + (0x24e << 2))
#define P_AED_EQ_CH2_COEF53 (volatile uint32_t *)(0xff642000 + (0x24e << 2))
#define AED_EQ_CH2_COEF54 (0xff642000 + (0x24f << 2))
#define SEC_AED_EQ_CH2_COEF54 (0xff642000 + (0x24f << 2))
#define P_AED_EQ_CH2_COEF54 (volatile uint32_t *)(0xff642000 + (0x24f << 2))
#define AED_EQ_CH2_COEF60 (0xff642000 + (0x250 << 2))
#define SEC_AED_EQ_CH2_COEF60 (0xff642000 + (0x250 << 2))
#define P_AED_EQ_CH2_COEF60 (volatile uint32_t *)(0xff642000 + (0x250 << 2))
#define AED_EQ_CH2_COEF61 (0xff642000 + (0x251 << 2))
#define SEC_AED_EQ_CH2_COEF61 (0xff642000 + (0x251 << 2))
#define P_AED_EQ_CH2_COEF61 (volatile uint32_t *)(0xff642000 + (0x251 << 2))
#define AED_EQ_CH2_COEF62 (0xff642000 + (0x252 << 2))
#define SEC_AED_EQ_CH2_COEF62 (0xff642000 + (0x252 << 2))
#define P_AED_EQ_CH2_COEF62 (volatile uint32_t *)(0xff642000 + (0x252 << 2))
#define AED_EQ_CH2_COEF63 (0xff642000 + (0x253 << 2))
#define SEC_AED_EQ_CH2_COEF63 (0xff642000 + (0x253 << 2))
#define P_AED_EQ_CH2_COEF63 (volatile uint32_t *)(0xff642000 + (0x253 << 2))
#define AED_EQ_CH2_COEF64 (0xff642000 + (0x254 << 2))
#define SEC_AED_EQ_CH2_COEF64 (0xff642000 + (0x254 << 2))
#define P_AED_EQ_CH2_COEF64 (volatile uint32_t *)(0xff642000 + (0x254 << 2))
#define AED_EQ_CH2_COEF70 (0xff642000 + (0x255 << 2))
#define SEC_AED_EQ_CH2_COEF70 (0xff642000 + (0x255 << 2))
#define P_AED_EQ_CH2_COEF70 (volatile uint32_t *)(0xff642000 + (0x255 << 2))
#define AED_EQ_CH2_COEF71 (0xff642000 + (0x256 << 2))
#define SEC_AED_EQ_CH2_COEF71 (0xff642000 + (0x256 << 2))
#define P_AED_EQ_CH2_COEF71 (volatile uint32_t *)(0xff642000 + (0x256 << 2))
#define AED_EQ_CH2_COEF72 (0xff642000 + (0x257 << 2))
#define SEC_AED_EQ_CH2_COEF72 (0xff642000 + (0x257 << 2))
#define P_AED_EQ_CH2_COEF72 (volatile uint32_t *)(0xff642000 + (0x257 << 2))
#define AED_EQ_CH2_COEF73 (0xff642000 + (0x258 << 2))
#define SEC_AED_EQ_CH2_COEF73 (0xff642000 + (0x258 << 2))
#define P_AED_EQ_CH2_COEF73 (volatile uint32_t *)(0xff642000 + (0x258 << 2))
#define AED_EQ_CH2_COEF74 (0xff642000 + (0x259 << 2))
#define SEC_AED_EQ_CH2_COEF74 (0xff642000 + (0x259 << 2))
#define P_AED_EQ_CH2_COEF74 (volatile uint32_t *)(0xff642000 + (0x259 << 2))
#define AED_EQ_CH2_COEF80 (0xff642000 + (0x25a << 2))
#define SEC_AED_EQ_CH2_COEF80 (0xff642000 + (0x25a << 2))
#define P_AED_EQ_CH2_COEF80 (volatile uint32_t *)(0xff642000 + (0x25a << 2))
#define AED_EQ_CH2_COEF81 (0xff642000 + (0x25b << 2))
#define SEC_AED_EQ_CH2_COEF81 (0xff642000 + (0x25b << 2))
#define P_AED_EQ_CH2_COEF81 (volatile uint32_t *)(0xff642000 + (0x25b << 2))
#define AED_EQ_CH2_COEF82 (0xff642000 + (0x25c << 2))
#define SEC_AED_EQ_CH2_COEF82 (0xff642000 + (0x25c << 2))
#define P_AED_EQ_CH2_COEF82 (volatile uint32_t *)(0xff642000 + (0x25c << 2))
#define AED_EQ_CH2_COEF83 (0xff642000 + (0x25d << 2))
#define SEC_AED_EQ_CH2_COEF83 (0xff642000 + (0x25d << 2))
#define P_AED_EQ_CH2_COEF83 (volatile uint32_t *)(0xff642000 + (0x25d << 2))
#define AED_EQ_CH2_COEF84 (0xff642000 + (0x25e << 2))
#define SEC_AED_EQ_CH2_COEF84 (0xff642000 + (0x25e << 2))
#define P_AED_EQ_CH2_COEF84 (volatile uint32_t *)(0xff642000 + (0x25e << 2))
#define AED_EQ_CH2_COEF90 (0xff642000 + (0x25f << 2))
#define SEC_AED_EQ_CH2_COEF90 (0xff642000 + (0x25f << 2))
#define P_AED_EQ_CH2_COEF90 (volatile uint32_t *)(0xff642000 + (0x25f << 2))
#define AED_EQ_CH2_COEF91 (0xff642000 + (0x260 << 2))
#define SEC_AED_EQ_CH2_COEF91 (0xff642000 + (0x260 << 2))
#define P_AED_EQ_CH2_COEF91 (volatile uint32_t *)(0xff642000 + (0x260 << 2))
#define AED_EQ_CH2_COEF92 (0xff642000 + (0x261 << 2))
#define SEC_AED_EQ_CH2_COEF92 (0xff642000 + (0x261 << 2))
#define P_AED_EQ_CH2_COEF92 (volatile uint32_t *)(0xff642000 + (0x261 << 2))
#define AED_EQ_CH2_COEF93 (0xff642000 + (0x262 << 2))
#define SEC_AED_EQ_CH2_COEF93 (0xff642000 + (0x262 << 2))
#define P_AED_EQ_CH2_COEF93 (volatile uint32_t *)(0xff642000 + (0x262 << 2))
#define AED_EQ_CH2_COEF94 (0xff642000 + (0x263 << 2))
#define SEC_AED_EQ_CH2_COEF94 (0xff642000 + (0x263 << 2))
#define P_AED_EQ_CH2_COEF94 (volatile uint32_t *)(0xff642000 + (0x263 << 2))
#define AED_EQ_EN (0xff642000 + (0x264 << 2))
#define SEC_AED_EQ_EN (0xff642000 + (0x264 << 2))
#define P_AED_EQ_EN (volatile uint32_t *)(0xff642000 + (0x264 << 2))
#define AED_EQ_VOLUME (0xff642000 + (0x265 << 2))
#define SEC_AED_EQ_VOLUME (0xff642000 + (0x265 << 2))
#define P_AED_EQ_VOLUME (volatile uint32_t *)(0xff642000 + (0x265 << 2))
#define AED_EQ_VOLUME_SLEW_CNT (0xff642000 + (0x266 << 2))
#define SEC_AED_EQ_VOLUME_SLEW_CNT (0xff642000 + (0x266 << 2))
#define P_AED_EQ_VOLUME_SLEW_CNT (volatile uint32_t *)(0xff642000 + (0x266 << 2))
#define AED_MUTE (0xff642000 + (0x267 << 2))
#define SEC_AED_MUTE (0xff642000 + (0x267 << 2))
#define P_AED_MUTE (volatile uint32_t *)(0xff642000 + (0x267 << 2))
#define AED_DRC_EN (0xff642000 + (0x268 << 2))
#define SEC_AED_DRC_EN (0xff642000 + (0x268 << 2))
#define P_AED_DRC_EN (volatile uint32_t *)(0xff642000 + (0x268 << 2))
#define AED_DRC_AE (0xff642000 + (0x269 << 2))
#define SEC_AED_DRC_AE (0xff642000 + (0x269 << 2))
#define P_AED_DRC_AE (volatile uint32_t *)(0xff642000 + (0x269 << 2))
#define AED_DRC_AA (0xff642000 + (0x26a << 2))
#define SEC_AED_DRC_AA (0xff642000 + (0x26a << 2))
#define P_AED_DRC_AA (volatile uint32_t *)(0xff642000 + (0x26a << 2))
#define AED_DRC_AD (0xff642000 + (0x26b << 2))
#define SEC_AED_DRC_AD (0xff642000 + (0x26b << 2))
#define P_AED_DRC_AD (volatile uint32_t *)(0xff642000 + (0x26b << 2))
#define AED_DRC_AE_1M (0xff642000 + (0x26c << 2))
#define SEC_AED_DRC_AE_1M (0xff642000 + (0x26c << 2))
#define P_AED_DRC_AE_1M (volatile uint32_t *)(0xff642000 + (0x26c << 2))
#define AED_DRC_AA_1M (0xff642000 + (0x26d << 2))
#define SEC_AED_DRC_AA_1M (0xff642000 + (0x26d << 2))
#define P_AED_DRC_AA_1M (volatile uint32_t *)(0xff642000 + (0x26d << 2))
#define AED_DRC_AD_1M (0xff642000 + (0x26e << 2))
#define SEC_AED_DRC_AD_1M (0xff642000 + (0x26e << 2))
#define P_AED_DRC_AD_1M (volatile uint32_t *)(0xff642000 + (0x26e << 2))
#define AED_DRC_OFFSET0 (0xff642000 + (0x26f << 2))
#define SEC_AED_DRC_OFFSET0 (0xff642000 + (0x26f << 2))
#define P_AED_DRC_OFFSET0 (volatile uint32_t *)(0xff642000 + (0x26f << 2))
#define AED_DRC_OFFSET1 (0xff642000 + (0x270 << 2))
#define SEC_AED_DRC_OFFSET1 (0xff642000 + (0x270 << 2))
#define P_AED_DRC_OFFSET1 (volatile uint32_t *)(0xff642000 + (0x270 << 2))
#define AED_DRC_THD0 (0xff642000 + (0x271 << 2))
#define SEC_AED_DRC_THD0 (0xff642000 + (0x271 << 2))
#define P_AED_DRC_THD0 (volatile uint32_t *)(0xff642000 + (0x271 << 2))
#define AED_DRC_THD1 (0xff642000 + (0x272 << 2))
#define SEC_AED_DRC_THD1 (0xff642000 + (0x272 << 2))
#define P_AED_DRC_THD1 (volatile uint32_t *)(0xff642000 + (0x272 << 2))
#define AED_DRC_K0 (0xff642000 + (0x273 << 2))
#define SEC_AED_DRC_K0 (0xff642000 + (0x273 << 2))
#define P_AED_DRC_K0 (volatile uint32_t *)(0xff642000 + (0x273 << 2))
#define AED_DRC_K1 (0xff642000 + (0x274 << 2))
#define SEC_AED_DRC_K1 (0xff642000 + (0x274 << 2))
#define P_AED_DRC_K1 (volatile uint32_t *)(0xff642000 + (0x274 << 2))
#define AED_CLIP_THD (0xff642000 + (0x275 << 2))
#define SEC_AED_CLIP_THD (0xff642000 + (0x275 << 2))
#define P_AED_CLIP_THD (volatile uint32_t *)(0xff642000 + (0x275 << 2))
#define AED_NG_THD0 (0xff642000 + (0x276 << 2))
#define SEC_AED_NG_THD0 (0xff642000 + (0x276 << 2))
#define P_AED_NG_THD0 (volatile uint32_t *)(0xff642000 + (0x276 << 2))
#define AED_NG_THD1 (0xff642000 + (0x277 << 2))
#define SEC_AED_NG_THD1 (0xff642000 + (0x277 << 2))
#define P_AED_NG_THD1 (volatile uint32_t *)(0xff642000 + (0x277 << 2))
#define AED_NG_CNT_THD (0xff642000 + (0x278 << 2))
#define SEC_AED_NG_CNT_THD (0xff642000 + (0x278 << 2))
#define P_AED_NG_CNT_THD (volatile uint32_t *)(0xff642000 + (0x278 << 2))
#define AED_NG_CTL (0xff642000 + (0x279 << 2))
#define SEC_AED_NG_CTL (0xff642000 + (0x279 << 2))
#define P_AED_NG_CTL (volatile uint32_t *)(0xff642000 + (0x279 << 2))
#define AED_ED_CTL (0xff642000 + (0x27a << 2))
#define SEC_AED_ED_CTL (0xff642000 + (0x27a << 2))
#define P_AED_ED_CTL (volatile uint32_t *)(0xff642000 + (0x27a << 2))
#define AED_DEBUG0 (0xff642000 + (0x27b << 2))
#define SEC_AED_DEBUG0 (0xff642000 + (0x27b << 2))
#define P_AED_DEBUG0 (volatile uint32_t *)(0xff642000 + (0x27b << 2))
#define AED_DEBUG1 (0xff642000 + (0x27c << 2))
#define SEC_AED_DEBUG1 (0xff642000 + (0x27c << 2))
#define P_AED_DEBUG1 (volatile uint32_t *)(0xff642000 + (0x27c << 2))
#define AED_DEBUG2 (0xff642000 + (0x27d << 2))
#define SEC_AED_DEBUG2 (0xff642000 + (0x27d << 2))
#define P_AED_DEBUG2 (volatile uint32_t *)(0xff642000 + (0x27d << 2))
#define AED_DEBUG3 (0xff642000 + (0x27e << 2))
#define SEC_AED_DEBUG3 (0xff642000 + (0x27e << 2))
#define P_AED_DEBUG3 (volatile uint32_t *)(0xff642000 + (0x27e << 2))
#define AED_DEBUG4 (0xff642000 + (0x27f << 2))
#define SEC_AED_DEBUG4 (0xff642000 + (0x27f << 2))
#define P_AED_DEBUG4 (volatile uint32_t *)(0xff642000 + (0x27f << 2))
#define AED_DEBUG5 (0xff642000 + (0x280 << 2))
#define SEC_AED_DEBUG5 (0xff642000 + (0x280 << 2))
#define P_AED_DEBUG5 (volatile uint32_t *)(0xff642000 + (0x280 << 2))
#define AED_DEBUG6 (0xff642000 + (0x281 << 2))
#define SEC_AED_DEBUG6 (0xff642000 + (0x281 << 2))
#define P_AED_DEBUG6 (volatile uint32_t *)(0xff642000 + (0x281 << 2))
#define AED_DRC_AA_H (0xff642000 + (0x282 << 2))
#define SEC_AED_DRC_AA_H (0xff642000 + (0x282 << 2))
#define P_AED_DRC_AA_H (volatile uint32_t *)(0xff642000 + (0x282 << 2))
#define AED_DRC_AD_H (0xff642000 + (0x283 << 2))
#define SEC_AED_DRC_AD_H (0xff642000 + (0x283 << 2))
#define P_AED_DRC_AD_H (volatile uint32_t *)(0xff642000 + (0x283 << 2))
#define AED_DRC_AA_1M_H (0xff642000 + (0x284 << 2))
#define SEC_AED_DRC_AA_1M_H (0xff642000 + (0x284 << 2))
#define P_AED_DRC_AA_1M_H (volatile uint32_t *)(0xff642000 + (0x284 << 2))
#define AED_DRC_AD_1M_H (0xff642000 + (0x285 << 2))
#define SEC_AED_DRC_AD_1M_H (0xff642000 + (0x285 << 2))
#define P_AED_DRC_AD_1M_H (volatile uint32_t *)(0xff642000 + (0x285 << 2))
#define AED_NG_CNT (0xff642000 + (0x286 << 2))
#define SEC_AED_NG_CNT (0xff642000 + (0x286 << 2))
#define P_AED_NG_CNT (volatile uint32_t *)(0xff642000 + (0x286 << 2))
#define AED_NG_STEP (0xff642000 + (0x287 << 2))
#define SEC_AED_NG_STEP (0xff642000 + (0x287 << 2))
#define P_AED_NG_STEP (volatile uint32_t *)(0xff642000 + (0x287 << 2))
#define AED_TOP_CTL (0xff642000 + (0x288 << 2))
#define SEC_AED_TOP_CTL (0xff642000 + (0x288 << 2))
#define P_AED_TOP_CTL (volatile uint32_t *)(0xff642000 + (0x288 << 2))
#define AED_TOP_REQ_CTL (0xff642000 + (0x289 << 2))
#define SEC_AED_TOP_REQ_CTL (0xff642000 + (0x289 << 2))
#define P_AED_TOP_REQ_CTL (volatile uint32_t *)(0xff642000 + (0x289 << 2))
//========================================================================
// HIU - Registers
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF63C000
// APB4_DECODER_SECURE_BASE 32'hFF63C000
#define HHI_MIPI_CNTL0 (0xff63c000 + (0x000 << 2))
#define SEC_HHI_MIPI_CNTL0 (0xff63c000 + (0x000 << 2))
#define P_HHI_MIPI_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x000 << 2))
#define HHI_MIPI_CNTL1 (0xff63c000 + (0x001 << 2))
#define SEC_HHI_MIPI_CNTL1 (0xff63c000 + (0x001 << 2))
#define P_HHI_MIPI_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x001 << 2))
#define HHI_MIPI_CNTL2 (0xff63c000 + (0x002 << 2))
#define SEC_HHI_MIPI_CNTL2 (0xff63c000 + (0x002 << 2))
#define P_HHI_MIPI_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x002 << 2))
#define HHI_MIPI_STS (0xff63c000 + (0x003 << 2))
#define SEC_HHI_MIPI_STS (0xff63c000 + (0x003 << 2))
#define P_HHI_MIPI_STS (volatile uint32_t *)(0xff63c000 + (0x003 << 2))
#define HHI_CHECK_CLK_RESULT (0xff63c000 + (0x004 << 2))
#define SEC_HHI_CHECK_CLK_RESULT (0xff63c000 + (0x004 << 2))
#define P_HHI_CHECK_CLK_RESULT (volatile uint32_t *)(0xff63c000 + (0x004 << 2))
#define SCR_HIU (0xff63c000 + (0x00b << 2))
#define SEC_SCR_HIU (0xff63c000 + (0x00b << 2))
#define P_SCR_HIU (volatile uint32_t *)(0xff63c000 + (0x00b << 2))
//`define HHI_SYS_STS 8'h0c
#define HPG_TIMER (0xff63c000 + (0x00f << 2))
#define SEC_HPG_TIMER (0xff63c000 + (0x00f << 2))
#define P_HPG_TIMER (volatile uint32_t *)(0xff63c000 + (0x00f << 2))
#define HHI_GP0_PLL_CNTL0 (0xff63c000 + (0x010 << 2))
#define SEC_HHI_GP0_PLL_CNTL0 (0xff63c000 + (0x010 << 2))
#define P_HHI_GP0_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x010 << 2))
#define HHI_GP0_PLL_CNTL1 (0xff63c000 + (0x011 << 2))
#define SEC_HHI_GP0_PLL_CNTL1 (0xff63c000 + (0x011 << 2))
#define P_HHI_GP0_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x011 << 2))
#define HHI_GP0_PLL_CNTL2 (0xff63c000 + (0x012 << 2))
#define SEC_HHI_GP0_PLL_CNTL2 (0xff63c000 + (0x012 << 2))
#define P_HHI_GP0_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x012 << 2))
#define HHI_GP0_PLL_CNTL3 (0xff63c000 + (0x013 << 2))
#define SEC_HHI_GP0_PLL_CNTL3 (0xff63c000 + (0x013 << 2))
#define P_HHI_GP0_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x013 << 2))
#define HHI_GP0_PLL_CNTL4 (0xff63c000 + (0x014 << 2))
#define SEC_HHI_GP0_PLL_CNTL4 (0xff63c000 + (0x014 << 2))
#define P_HHI_GP0_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x014 << 2))
#define HHI_GP0_PLL_CNTL5 (0xff63c000 + (0x015 << 2))
#define SEC_HHI_GP0_PLL_CNTL5 (0xff63c000 + (0x015 << 2))
#define P_HHI_GP0_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x015 << 2))
#define HHI_GP0_PLL_CNTL6 (0xff63c000 + (0x016 << 2))
#define SEC_HHI_GP0_PLL_CNTL6 (0xff63c000 + (0x016 << 2))
#define P_HHI_GP0_PLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x016 << 2))
#define HHI_GP0_PLL_STS (0xff63c000 + (0x017 << 2))
#define SEC_HHI_GP0_PLL_STS (0xff63c000 + (0x017 << 2))
#define P_HHI_GP0_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x017 << 2))
//`define HHI_GP1_PLL_CNTL0 8'h18
//`define HHI_GP1_PLL_CNTL1 8'h19
//`define HHI_GP1_PLL_CNTL2 8'h1a
//`define HHI_GP1_PLL_CNTL3 8'h1b
//`define HHI_GP1_PLL_CNTL4 8'h1c
//`define HHI_GP1_PLL_CNTL5 8'h1d
//`define HHI_GP1_PLL_CNTL6 8'h1e
//`define HHI_GP1_PLL_STS 8'h1f
//`define HHI_CADC_CNTL 8'h20
//`define HHI_CADC_CNTL2 8'h21
//`define HHI_CADC_CNTL3 8'h22
//`define HHI_CADC_CNTL4 8'h23
//`define HHI_CADC_CNTL5 8'h24
//`define HHI_CADC_CNTL6 8'h25
#define HHI_PCIE_PLL_CNTL0 (0xff63c000 + (0x026 << 2))
#define SEC_HHI_PCIE_PLL_CNTL0 (0xff63c000 + (0x026 << 2))
#define P_HHI_PCIE_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x026 << 2))
#define HHI_PCIE_PLL_CNTL1 (0xff63c000 + (0x027 << 2))
#define SEC_HHI_PCIE_PLL_CNTL1 (0xff63c000 + (0x027 << 2))
#define P_HHI_PCIE_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x027 << 2))
#define HHI_PCIE_PLL_CNTL2 (0xff63c000 + (0x028 << 2))
#define SEC_HHI_PCIE_PLL_CNTL2 (0xff63c000 + (0x028 << 2))
#define P_HHI_PCIE_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x028 << 2))
#define HHI_PCIE_PLL_CNTL3 (0xff63c000 + (0x029 << 2))
#define SEC_HHI_PCIE_PLL_CNTL3 (0xff63c000 + (0x029 << 2))
#define P_HHI_PCIE_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x029 << 2))
#define HHI_PCIE_PLL_CNTL4 (0xff63c000 + (0x02a << 2))
#define SEC_HHI_PCIE_PLL_CNTL4 (0xff63c000 + (0x02a << 2))
#define P_HHI_PCIE_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x02a << 2))
#define HHI_PCIE_PLL_CNTL5 (0xff63c000 + (0x02b << 2))
#define SEC_HHI_PCIE_PLL_CNTL5 (0xff63c000 + (0x02b << 2))
#define P_HHI_PCIE_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x02b << 2))
#define HHI_PCIE_PLL_STS (0xff63c000 + (0x02c << 2))
#define SEC_HHI_PCIE_PLL_STS (0xff63c000 + (0x02c << 2))
#define P_HHI_PCIE_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x02c << 2))
//`define HHI_DADC_CNTL 8'h27
//`define HHI_DADC_CNTL2 8'h28
//`define HHI_DADC_RDBK0_I 8'h29
//`define HHI_DADC_CNTL3 8'h2a
//`define HHI_DADC_CNTL4 8'h2b
//`define HHI_AFE_TUNNING_CNTL 8'h2c
//`define HHI_AFE_TUNNING_CNTL_I 8'h2d
//`define HHI_CVBS_DETECT_CNTL 8'h2e
#define HHI_XTAL_DIVN_CNTL (0xff63c000 + (0x02f << 2))
#define SEC_HHI_XTAL_DIVN_CNTL (0xff63c000 + (0x02f << 2))
#define P_HHI_XTAL_DIVN_CNTL (volatile uint32_t *)(0xff63c000 + (0x02f << 2))
#define HHI_GCLK2_MPEG0 (0xff63c000 + (0x030 << 2))
#define SEC_HHI_GCLK2_MPEG0 (0xff63c000 + (0x030 << 2))
#define P_HHI_GCLK2_MPEG0 (volatile uint32_t *)(0xff63c000 + (0x030 << 2))
#define HHI_GCLK2_MPEG1 (0xff63c000 + (0x031 << 2))
#define SEC_HHI_GCLK2_MPEG1 (0xff63c000 + (0x031 << 2))
#define P_HHI_GCLK2_MPEG1 (volatile uint32_t *)(0xff63c000 + (0x031 << 2))
#define HHI_GCLK2_MPEG2 (0xff63c000 + (0x032 << 2))
#define SEC_HHI_GCLK2_MPEG2 (0xff63c000 + (0x032 << 2))
#define P_HHI_GCLK2_MPEG2 (volatile uint32_t *)(0xff63c000 + (0x032 << 2))
#define HHI_GCLK2_OTHER (0xff63c000 + (0x034 << 2))
#define SEC_HHI_GCLK2_OTHER (0xff63c000 + (0x034 << 2))
#define P_HHI_GCLK2_OTHER (volatile uint32_t *)(0xff63c000 + (0x034 << 2))
//`define HHI_GCLK2_AO 8'h35
#define HHI_HIFI_PLL_CNTL0 (0xff63c000 + (0x036 << 2))
#define SEC_HHI_HIFI_PLL_CNTL0 (0xff63c000 + (0x036 << 2))
#define P_HHI_HIFI_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x036 << 2))
#define HHI_HIFI_PLL_CNTL1 (0xff63c000 + (0x037 << 2))
#define SEC_HHI_HIFI_PLL_CNTL1 (0xff63c000 + (0x037 << 2))
#define P_HHI_HIFI_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x037 << 2))
#define HHI_HIFI_PLL_CNTL2 (0xff63c000 + (0x038 << 2))
#define SEC_HHI_HIFI_PLL_CNTL2 (0xff63c000 + (0x038 << 2))
#define P_HHI_HIFI_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x038 << 2))
#define HHI_HIFI_PLL_CNTL3 (0xff63c000 + (0x039 << 2))
#define SEC_HHI_HIFI_PLL_CNTL3 (0xff63c000 + (0x039 << 2))
#define P_HHI_HIFI_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x039 << 2))
#define HHI_HIFI_PLL_CNTL4 (0xff63c000 + (0x03a << 2))
#define SEC_HHI_HIFI_PLL_CNTL4 (0xff63c000 + (0x03a << 2))
#define P_HHI_HIFI_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x03a << 2))
#define HHI_HIFI_PLL_CNTL5 (0xff63c000 + (0x03b << 2))
#define SEC_HHI_HIFI_PLL_CNTL5 (0xff63c000 + (0x03b << 2))
#define P_HHI_HIFI_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x03b << 2))
#define HHI_HIFI_PLL_CNTL6 (0xff63c000 + (0x03c << 2))
#define SEC_HHI_HIFI_PLL_CNTL6 (0xff63c000 + (0x03c << 2))
#define P_HHI_HIFI_PLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x03c << 2))
#define HHI_HIFI_PLL_STS (0xff63c000 + (0x03d << 2))
#define SEC_HHI_HIFI_PLL_STS (0xff63c000 + (0x03d << 2))
#define P_HHI_HIFI_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x03d << 2))
#define HHI_TIMER90K (0xff63c000 + (0x03f << 2))
#define SEC_HHI_TIMER90K (0xff63c000 + (0x03f << 2))
#define P_HHI_TIMER90K (volatile uint32_t *)(0xff63c000 + (0x03f << 2))
#define HHI_MEM_PD_REG0 (0xff63c000 + (0x040 << 2))
#define SEC_HHI_MEM_PD_REG0 (0xff63c000 + (0x040 << 2))
#define P_HHI_MEM_PD_REG0 (volatile uint32_t *)(0xff63c000 + (0x040 << 2))
//VIU1
//bit 29:28 mem_pd_vi_sharp, 2'b00: Sharpness line buffer memory power on, 2'b11: power down
//bit 29:28 mem_pd_vi_dipost, 2'b00: Deinterlace - di_post memory power on, 2'b11: power down
//bit 27:26 mem_pd_vi_dipre, 2'b00: Deinterlace - di_pre memory power on, 2'b11: power down
//bit 25:24 mem_pd_vi_prot3, 2'b00: picture rotation3 memory power on, 2'b11: power down
//bit 23:22 mem_pd_vi_prot2, 2'b00: picture rotation2 memory power on, 2'b11: power down
//bit 21:20 mem_pd_vi_prot1, 2'b00: picture rotation1 memory power on, 2'b11: power down
//bit 19:18 mem_pd_vi_vdin1, 2'b00: vdin1 memory power on, 2'b11: power down
//bit 17:16 mem_pd_vi_vdin0, 2'b00: vdin0 memory power on, 2'b11: power down
//bit 15:14 mem_pd_vi_osd_sc, 2'b00: osd_scaler memory power on, 2'b11: power down
//bit 13:12 mem_pd_vi_scale, 2'b00: scaler memory power on, 2'b11: power down
//bit 11:10 mem_pd_vi_ofifo, 2'b00: vpp output fifo memory power on, 2'b11: power down
//bit 9:8 mem_pd_vi_chroma, 2'b00: color management module memory power on, 2'b11: power down
//bit 7:6 mem_pd_vi_vd2, 2'b00: vd2 memory power on, 2'b11: power down
//bit 5:4 mem_pd_vi_vd1, 2'b00: vd1 memory power on, 2'b11: power down
//bit 3:2 mem_pd_vi_osd2, 2'b00: osd2 memory power on, 2'b11: power down
//bit 1:0 mem_pd_vi_osd1, 2'b00: osd1 memory power on, 2'b11: power down
#define HHI_VPU_MEM_PD_REG0 (0xff63c000 + (0x041 << 2))
#define SEC_HHI_VPU_MEM_PD_REG0 (0xff63c000 + (0x041 << 2))
#define P_HHI_VPU_MEM_PD_REG0 (volatile uint32_t *)(0xff63c000 + (0x041 << 2))
//bit 29:28 mem_pd_atv_dmd, 2'b00: ATV DMD memory power on, 2'b11: power down
//bit 29:28 mem_pd_cvd2, 2'b00: CVD2 memory power on, 2'b11: power down
//bit 27:26 mem_pd_isp, 2'b00: ISP memory power on, 2'b11: power down
//bit 25:24 mem_pd_venci_int, 2'b00: cvbs- enci interface memory power on, 2'b11: power down
//bit 23:22 mem_pd_venc_l_top,2'b00: panel - encl top memory power on, 2'b11: power down
//bit 21:20 mem_pd_vencp_int, 2'b00: hdmi - encp interface memory power on, 2'b11: power down
//bit 13:12 mem_pd_vi2_osd_sc,2'b00: viu2 OSD scaler memory power on, 2'b11: power down
//bit 11:10 mem_pd_vi2_scale, 2'b00: viu2 scaler memory power on, 2'b11: power down
//bit 9:8 mem_pd_vi2_ofifo, 2'b00: viu2 vpp output fifo memory power on, 2'b11: power down
//bit 7:6 mem_pd_vi2_chroma,2'b00: viu2 color management module memory power on, 2'b11: power down
//bit 5:4 mem_pd_vi2_vd1, 2'b00: viu2 vd1 memory power on, 2'b11: power down
//bit 3:2 mem_pd_vi2_osd2, 2'b00: viu2 osd2 memory power on, 2'b11: power down
//bit 1:0 mem_pd_vi2_osd1, 2'b00: viu2 osd1 memory power on, 2'b11: power down
#define HHI_VPU_MEM_PD_REG1 (0xff63c000 + (0x042 << 2))
#define SEC_HHI_VPU_MEM_PD_REG1 (0xff63c000 + (0x042 << 2))
#define P_HHI_VPU_MEM_PD_REG1 (volatile uint32_t *)(0xff63c000 + (0x042 << 2))
//`define HHI_DEMOD_MEM_PD_REG 8'h43
//`define HHI_AUD_DAC_CTRL 8'h44
// `define HHI_VIID_PLL_CNTL4 8'h46 // video PLL read back
// `define HHI_VIID_PLL_CNTL 8'h47 // Video PLL control, word 1
// `define HHI_VIID_PLL_CNTL2 8'h48 // Video PLL control, word 2
// `define HHI_VIID_PLL_CNTL3 8'h49 // Video PLL control, word 3
#define HHI_VIID_CLK_DIV (0xff63c000 + (0x04a << 2))
#define SEC_HHI_VIID_CLK_DIV (0xff63c000 + (0x04a << 2))
#define P_HHI_VIID_CLK_DIV (volatile uint32_t *)(0xff63c000 + (0x04a << 2))
#define HHI_VIID_CLK_CNTL (0xff63c000 + (0x04b << 2))
#define SEC_HHI_VIID_CLK_CNTL (0xff63c000 + (0x04b << 2))
#define P_HHI_VIID_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x04b << 2))
//`define HHI_VIID_DIVIDER_CNTL 8'h4c
//bit 1:0 mem_pd_vi_wm, 2'b00: viu1 wm memory power on, 2'b11: power down
#define HHI_VPU_MEM_PD_REG2 (0xff63c000 + (0x04d << 2))
#define SEC_HHI_VPU_MEM_PD_REG2 (0xff63c000 + (0x04d << 2))
#define P_HHI_VPU_MEM_PD_REG2 (volatile uint32_t *)(0xff63c000 + (0x04d << 2))
// Gated clock enables. There are 64 enables for the MPEG clocks and 32 enables for other clock domains
#define HHI_GCLK_LOCK (0xff63c000 + (0x04f << 2))
#define SEC_HHI_GCLK_LOCK (0xff63c000 + (0x04f << 2))
#define P_HHI_GCLK_LOCK (volatile uint32_t *)(0xff63c000 + (0x04f << 2))
#define HHI_GCLK_MPEG0 (0xff63c000 + (0x050 << 2))
#define SEC_HHI_GCLK_MPEG0 (0xff63c000 + (0x050 << 2))
#define P_HHI_GCLK_MPEG0 (volatile uint32_t *)(0xff63c000 + (0x050 << 2))
#define HHI_GCLK_MPEG1 (0xff63c000 + (0x051 << 2))
#define SEC_HHI_GCLK_MPEG1 (0xff63c000 + (0x051 << 2))
#define P_HHI_GCLK_MPEG1 (volatile uint32_t *)(0xff63c000 + (0x051 << 2))
#define HHI_GCLK_MPEG2 (0xff63c000 + (0x052 << 2))
#define SEC_HHI_GCLK_MPEG2 (0xff63c000 + (0x052 << 2))
#define P_HHI_GCLK_MPEG2 (volatile uint32_t *)(0xff63c000 + (0x052 << 2))
#define HHI_GCLK_OTHER (0xff63c000 + (0x054 << 2))
#define SEC_HHI_GCLK_OTHER (0xff63c000 + (0x054 << 2))
#define P_HHI_GCLK_OTHER (volatile uint32_t *)(0xff63c000 + (0x054 << 2))
#define HHI_GCLK_SP_MPEG (0xff63c000 + (0x055 << 2))
#define SEC_HHI_GCLK_SP_MPEG (0xff63c000 + (0x055 << 2))
#define P_HHI_GCLK_SP_MPEG (volatile uint32_t *)(0xff63c000 + (0x055 << 2))
//`define HHI_SYS_OSCIN_CNTL 8'h56
#define HHI_SYS_CPU_CLK_CNTL1 (0xff63c000 + (0x057 << 2))
#define SEC_HHI_SYS_CPU_CLK_CNTL1 (0xff63c000 + (0x057 << 2))
#define P_HHI_SYS_CPU_CLK_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x057 << 2))
#define HHI_SYS_CPU_RESET_CNTL (0xff63c000 + (0x058 << 2))
#define SEC_HHI_SYS_CPU_RESET_CNTL (0xff63c000 + (0x058 << 2))
#define P_HHI_SYS_CPU_RESET_CNTL (volatile uint32_t *)(0xff63c000 + (0x058 << 2))
// PLL Controls
#define HHI_VID_CLK_DIV (0xff63c000 + (0x059 << 2))
#define SEC_HHI_VID_CLK_DIV (0xff63c000 + (0x059 << 2))
#define P_HHI_VID_CLK_DIV (volatile uint32_t *)(0xff63c000 + (0x059 << 2))
#define HHI_MPEG_CLK_CNTL (0xff63c000 + (0x05d << 2))
#define SEC_HHI_MPEG_CLK_CNTL (0xff63c000 + (0x05d << 2))
#define P_HHI_MPEG_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x05d << 2))
#define HHI_VID_CLK_CNTL (0xff63c000 + (0x05f << 2))
#define SEC_HHI_VID_CLK_CNTL (0xff63c000 + (0x05f << 2))
#define P_HHI_VID_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x05f << 2))
//`define HHI_WIFI_CLK_CNTL 8'h60 // MPEG clock control
//`define HHI_WIFI_PLL_CNTL 8'h61 // WIFI PLL control, word 1
//`define HHI_WIFI_PLL_CNTL2 8'h62 // WIFI PLL control, word 2
//`define HHI_WIFI_PLL_CNTL3 8'h63 // WIFI PLL control, word 3
#define HHI_TS_CLK_CNTL (0xff63c000 + (0x064 << 2))
#define SEC_HHI_TS_CLK_CNTL (0xff63c000 + (0x064 << 2))
#define P_HHI_TS_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x064 << 2))
#define HHI_VID_CLK_CNTL2 (0xff63c000 + (0x065 << 2))
#define SEC_HHI_VID_CLK_CNTL2 (0xff63c000 + (0x065 << 2))
#define P_HHI_VID_CLK_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x065 << 2))
//`define HHI_VID_DIVIDER_CNTL 8'h66
#define HHI_SYS_CPU_CLK_CNTL (0xff63c000 + (0x067 << 2))
#define SEC_HHI_SYS_CPU_CLK_CNTL (0xff63c000 + (0x067 << 2))
#define P_HHI_SYS_CPU_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x067 << 2))
#define HHI_VID_PLL_CLK_DIV (0xff63c000 + (0x068 << 2))
#define SEC_HHI_VID_PLL_CLK_DIV (0xff63c000 + (0x068 << 2))
#define P_HHI_VID_PLL_CLK_DIV (volatile uint32_t *)(0xff63c000 + (0x068 << 2))
// Moved to Martin's domain `define HHI_DDR_PLL_CNTL 8'h68 // DDR PLL control, word 1
// Moved to Martin's domain `define HHI_DDR_PLL_CNTL2 8'h69 // DDR PLL control, word 2
// Moved to Martin's domain `define HHI_DDR_PLL_CNTL3 8'h6a // DDR PLL control, word 3
// Moved to Martin's domain `define HHI_DDR_PLL_CNTL4 8'h6b // DDR PLL control, word 3
#define HHI_MALI_CLK_CNTL (0xff63c000 + (0x06c << 2))
#define SEC_HHI_MALI_CLK_CNTL (0xff63c000 + (0x06c << 2))
#define P_HHI_MALI_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x06c << 2))
#define HHI_VPU_CLKC_CNTL (0xff63c000 + (0x06d << 2))
#define SEC_HHI_VPU_CLKC_CNTL (0xff63c000 + (0x06d << 2))
#define P_HHI_VPU_CLKC_CNTL (volatile uint32_t *)(0xff63c000 + (0x06d << 2))
//`define HHI_MIPI_PHY_CLK_CNTL 8'h6e
#define HHI_VPU_CLK_CNTL (0xff63c000 + (0x06f << 2))
#define SEC_HHI_VPU_CLK_CNTL (0xff63c000 + (0x06f << 2))
#define P_HHI_VPU_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x06f << 2))
//`define HHI_OTHER_PLL_CNTL 8'h70 // OTHER PLL control, word 1
//`define HHI_OTHER_PLL_CNTL2 8'h71 // OTHER PLL control, word 2
//`define HHI_OTHER_PLL_CNTL3 8'h72 // OTHER PLL control, word 3
#define HHI_HDMI_CLK_CNTL (0xff63c000 + (0x073 << 2))
#define SEC_HHI_HDMI_CLK_CNTL (0xff63c000 + (0x073 << 2))
#define P_HHI_HDMI_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x073 << 2))
//`define HHI_DEMOD_CLK_CNTL 8'h74 // DEMOD clock control
//`define HHI_SATA_CLK_CNTL 8'h75 // SATA clock control
#define HHI_ETH_CLK_CNTL (0xff63c000 + (0x076 << 2))
#define SEC_HHI_ETH_CLK_CNTL (0xff63c000 + (0x076 << 2))
#define P_HHI_ETH_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x076 << 2))
//`define HHI_CLK_DOUBLE_CNTL 8'h77 // Ethernet clock control
#define HHI_VDEC_CLK_CNTL (0xff63c000 + (0x078 << 2))
#define SEC_HHI_VDEC_CLK_CNTL (0xff63c000 + (0x078 << 2))
#define P_HHI_VDEC_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x078 << 2))
#define HHI_VDEC2_CLK_CNTL (0xff63c000 + (0x079 << 2))
#define SEC_HHI_VDEC2_CLK_CNTL (0xff63c000 + (0x079 << 2))
#define P_HHI_VDEC2_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x079 << 2))
#define HHI_VDEC3_CLK_CNTL (0xff63c000 + (0x07a << 2))
#define SEC_HHI_VDEC3_CLK_CNTL (0xff63c000 + (0x07a << 2))
#define P_HHI_VDEC3_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x07a << 2))
#define HHI_VDEC4_CLK_CNTL (0xff63c000 + (0x07b << 2))
#define SEC_HHI_VDEC4_CLK_CNTL (0xff63c000 + (0x07b << 2))
#define P_HHI_VDEC4_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x07b << 2))
#define HHI_HDCP22_CLK_CNTL (0xff63c000 + (0x07c << 2))
#define SEC_HHI_HDCP22_CLK_CNTL (0xff63c000 + (0x07c << 2))
#define P_HHI_HDCP22_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x07c << 2))
#define HHI_VAPBCLK_CNTL (0xff63c000 + (0x07d << 2))
#define SEC_HHI_VAPBCLK_CNTL (0xff63c000 + (0x07d << 2))
#define P_HHI_VAPBCLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x07d << 2))
//`define HHI_VP9DEC_CLK_CNTL 8'h7e
// `define HHI_SYS_CPU_AUTO_CLK0 8'h78 never used
// `define HHI_SYS_CPU_AUTO_CLK1 8'h79 never used
// `define HHI_MEDIA_CPU_AUTO_CLK0 8'h7a never used
// `define HHI_MEDIA_CPU_AUTO_CLK1 8'h7b never used
//`define HHI_HDMI_AFC_CNTL 8'h7f
//`define HHI_HDMIRX_CLK_CNTL 8'h80
//`define HHI_HDMIRX_AUD_CLK_CNTL 8'h81
//`define HHI_EDP_APB_CLK_CNTL 8'h82
#define HHI_VPU_CLKB_CNTL (0xff63c000 + (0x083 << 2))
#define SEC_HHI_VPU_CLKB_CNTL (0xff63c000 + (0x083 << 2))
#define P_HHI_VPU_CLKB_CNTL (volatile uint32_t *)(0xff63c000 + (0x083 << 2))
//`define HHI_VID_PLL_MOD_CNTL0 8'h84
//`define HHI_VID_PLL_MOD_LOW_TCNT 8'h85
//`define HHI_VID_PLL_MOD_HIGH_TCNT 8'h86
//`define HHI_VID_PLL_MOD_NOM_TCNT 8'h87
// Removed `define HHI_DDR_CLK_CNTL 8'h88
//`define HHI_32K_CLK_CNTL 8'h89
#define HHI_GEN_CLK_CNTL (0xff63c000 + (0x08a << 2))
#define SEC_HHI_GEN_CLK_CNTL (0xff63c000 + (0x08a << 2))
#define P_HHI_GEN_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x08a << 2))
//`define HHI_GEN_CLK_CNTL2 8'h8b
//`define HHI_AUDPLL_CLK_OUT_CNTL 8'h8c
//`define HHI_JTAG_CONFIG 8'h8e
//`define HHI_VAFE_CLKXTALIN_CNTL 8'h8f
//`define HHI_VAFE_CLKOSCIN_CNTL 8'h90
//`define HHI_VAFE_CLKIN_CNTL 8'h91
//`define HHI_TVFE_AUTOMODE_CLK_CNTL 8'h92
//`define HHI_VAFE_CLKPI_CNTL 8'h93
#define HHI_VDIN_MEAS_CLK_CNTL (0xff63c000 + (0x094 << 2))
#define SEC_HHI_VDIN_MEAS_CLK_CNTL (0xff63c000 + (0x094 << 2))
#define P_HHI_VDIN_MEAS_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x094 << 2))
#define HHI_MIPIDSI_PHY_CLK_CNTL (0xff63c000 + (0x095 << 2))
#define SEC_HHI_MIPIDSI_PHY_CLK_CNTL (0xff63c000 + (0x095 << 2))
#define P_HHI_MIPIDSI_PHY_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x095 << 2))
#define HHI_NAND_CLK_CNTL (0xff63c000 + (0x097 << 2))
#define SEC_HHI_NAND_CLK_CNTL (0xff63c000 + (0x097 << 2))
#define P_HHI_NAND_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x097 << 2))
//`define HHI_ISP_LED_CLK_CNTL 8'h98
#define HHI_SD_EMMC_CLK_CNTL (0xff63c000 + (0x099 << 2))
#define SEC_HHI_SD_EMMC_CLK_CNTL (0xff63c000 + (0x099 << 2))
#define P_HHI_SD_EMMC_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x099 << 2))
#define HHI_WAVE420L_CLK_CNTL (0xff63c000 + (0x09a << 2))
#define SEC_HHI_WAVE420L_CLK_CNTL (0xff63c000 + (0x09a << 2))
#define P_HHI_WAVE420L_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x09a << 2))
#define HHI_WAVE420L_CLK_CNTL2 (0xff63c000 + (0x09b << 2))
#define SEC_HHI_WAVE420L_CLK_CNTL2 (0xff63c000 + (0x09b << 2))
#define P_HHI_WAVE420L_CLK_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x09b << 2))
//`define HHI_EDP_TX_PHY_CNTL0 8'h9c
//`define HHI_EDP_TX_PHY_CNTL1 8'h9d
//`define HHI_ADC_PLL_CNTL5 8'h9e
//`define HHI_ADC_PLL_CNTL6 8'h9f
#define HHI_MPLL_CNTL0 (0xff63c000 + (0x09e << 2))
#define SEC_HHI_MPLL_CNTL0 (0xff63c000 + (0x09e << 2))
#define P_HHI_MPLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x09e << 2))
#define HHI_MPLL_CNTL1 (0xff63c000 + (0x09f << 2))
#define SEC_HHI_MPLL_CNTL1 (0xff63c000 + (0x09f << 2))
#define P_HHI_MPLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x09f << 2))
#define HHI_MPLL_CNTL2 (0xff63c000 + (0x0a0 << 2))
#define SEC_HHI_MPLL_CNTL2 (0xff63c000 + (0x0a0 << 2))
#define P_HHI_MPLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x0a0 << 2))
#define HHI_MPLL_CNTL3 (0xff63c000 + (0x0a1 << 2))
#define SEC_HHI_MPLL_CNTL3 (0xff63c000 + (0x0a1 << 2))
#define P_HHI_MPLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x0a1 << 2))
#define HHI_MPLL_CNTL4 (0xff63c000 + (0x0a2 << 2))
#define SEC_HHI_MPLL_CNTL4 (0xff63c000 + (0x0a2 << 2))
#define P_HHI_MPLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x0a2 << 2))
#define HHI_MPLL_CNTL5 (0xff63c000 + (0x0a3 << 2))
#define SEC_HHI_MPLL_CNTL5 (0xff63c000 + (0x0a3 << 2))
#define P_HHI_MPLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x0a3 << 2))
#define HHI_MPLL_CNTL6 (0xff63c000 + (0x0a4 << 2))
#define SEC_HHI_MPLL_CNTL6 (0xff63c000 + (0x0a4 << 2))
#define P_HHI_MPLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x0a4 << 2))
#define HHI_MPLL_CNTL7 (0xff63c000 + (0x0a5 << 2))
#define SEC_HHI_MPLL_CNTL7 (0xff63c000 + (0x0a5 << 2))
#define P_HHI_MPLL_CNTL7 (volatile uint32_t *)(0xff63c000 + (0x0a5 << 2))
#define HHI_MPLL_CNTL8 (0xff63c000 + (0x0a6 << 2))
#define SEC_HHI_MPLL_CNTL8 (0xff63c000 + (0x0a6 << 2))
#define P_HHI_MPLL_CNTL8 (volatile uint32_t *)(0xff63c000 + (0x0a6 << 2))
#define HHI_MPLL_STS (0xff63c000 + (0x0a7 << 2))
#define SEC_HHI_MPLL_STS (0xff63c000 + (0x0a7 << 2))
#define P_HHI_MPLL_STS (volatile uint32_t *)(0xff63c000 + (0x0a7 << 2))
#define HHI_FIX_PLL_CNTL0 (0xff63c000 + (0x0a8 << 2))
#define SEC_HHI_FIX_PLL_CNTL0 (0xff63c000 + (0x0a8 << 2))
#define P_HHI_FIX_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x0a8 << 2))
#define HHI_FIX_PLL_CNTL1 (0xff63c000 + (0x0a9 << 2))
#define SEC_HHI_FIX_PLL_CNTL1 (0xff63c000 + (0x0a9 << 2))
#define P_HHI_FIX_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x0a9 << 2))
#define HHI_FIX_PLL_CNTL2 (0xff63c000 + (0x0aa << 2))
#define SEC_HHI_FIX_PLL_CNTL2 (0xff63c000 + (0x0aa << 2))
#define P_HHI_FIX_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x0aa << 2))
#define HHI_FIX_PLL_CNTL3 (0xff63c000 + (0x0ab << 2))
#define SEC_HHI_FIX_PLL_CNTL3 (0xff63c000 + (0x0ab << 2))
#define P_HHI_FIX_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x0ab << 2))
#define HHI_FIX_PLL_CNTL4 (0xff63c000 + (0x0ac << 2))
#define SEC_HHI_FIX_PLL_CNTL4 (0xff63c000 + (0x0ac << 2))
#define P_HHI_FIX_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x0ac << 2))
#define HHI_FIX_PLL_CNTL5 (0xff63c000 + (0x0ad << 2))
#define SEC_HHI_FIX_PLL_CNTL5 (0xff63c000 + (0x0ad << 2))
#define P_HHI_FIX_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x0ad << 2))
#define HHI_FIX_PLL_CNTL6 (0xff63c000 + (0x0ae << 2))
#define SEC_HHI_FIX_PLL_CNTL6 (0xff63c000 + (0x0ae << 2))
#define P_HHI_FIX_PLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x0ae << 2))
#define HHI_FIX_PLL_STS (0xff63c000 + (0x0af << 2))
#define SEC_HHI_FIX_PLL_STS (0xff63c000 + (0x0af << 2))
#define P_HHI_FIX_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x0af << 2))
//`define HHI_ADC_PLL_CNTL 8'haa
//`define HHI_ADC_PLL_CNTL2 8'hab
//`define HHI_ADC_PLL_CNTL3 8'hac
//`define HHI_ADC_PLL_CNTL4 8'had
//`define HHI_ADC_PLL_STS 8'hae
//`define HHI_ADC_PLL_CNTL1 8'haf
//`define HHI_AUDCLK_PLL_CNTL 8'hb0
//`define HHI_AUDCLK_PLL_CNTL2 8'hb1
//`define HHI_AUDCLK_PLL_CNTL3 8'hb2
//`define HHI_AUDCLK_PLL_CNTL4 8'hb3
//`define HHI_AUDCLK_PLL_CNTL5 8'hb4
//`define HHI_AUDCLK_PLL_CNTL6 8'hb5
//`define HHI_L2_DDR_CLK_CNTL 8'hb6
//`define HHI_PLL_TOP_MISC 8'hba
#define HHI_VDAC_CNTL0 (0xff63c000 + (0x0bb << 2))
#define SEC_HHI_VDAC_CNTL0 (0xff63c000 + (0x0bb << 2))
#define P_HHI_VDAC_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x0bb << 2))
#define HHI_VDAC_CNTL1 (0xff63c000 + (0x0bc << 2))
#define SEC_HHI_VDAC_CNTL1 (0xff63c000 + (0x0bc << 2))
#define P_HHI_VDAC_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x0bc << 2))
#define HHI_SYS_PLL_CNTL0 (0xff63c000 + (0x0bd << 2))
#define SEC_HHI_SYS_PLL_CNTL0 (0xff63c000 + (0x0bd << 2))
#define P_HHI_SYS_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x0bd << 2))
#define HHI_SYS_PLL_CNTL1 (0xff63c000 + (0x0be << 2))
#define SEC_HHI_SYS_PLL_CNTL1 (0xff63c000 + (0x0be << 2))
#define P_HHI_SYS_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x0be << 2))
#define HHI_SYS_PLL_CNTL2 (0xff63c000 + (0x0bf << 2))
#define SEC_HHI_SYS_PLL_CNTL2 (0xff63c000 + (0x0bf << 2))
#define P_HHI_SYS_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x0bf << 2))
#define HHI_SYS_PLL_CNTL3 (0xff63c000 + (0x0c0 << 2))
#define SEC_HHI_SYS_PLL_CNTL3 (0xff63c000 + (0x0c0 << 2))
#define P_HHI_SYS_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x0c0 << 2))
#define HHI_SYS_PLL_CNTL4 (0xff63c000 + (0x0c1 << 2))
#define SEC_HHI_SYS_PLL_CNTL4 (0xff63c000 + (0x0c1 << 2))
#define P_HHI_SYS_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x0c1 << 2))
#define HHI_SYS_PLL_CNTL5 (0xff63c000 + (0x0c2 << 2))
#define SEC_HHI_SYS_PLL_CNTL5 (0xff63c000 + (0x0c2 << 2))
#define P_HHI_SYS_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x0c2 << 2))
#define HHI_SYS_PLL_CNTL6 (0xff63c000 + (0x0c3 << 2))
#define SEC_HHI_SYS_PLL_CNTL6 (0xff63c000 + (0x0c3 << 2))
#define P_HHI_SYS_PLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x0c3 << 2))
#define HHI_SYS_PLL_STS (0xff63c000 + (0x0c4 << 2))
#define SEC_HHI_SYS_PLL_STS (0xff63c000 + (0x0c4 << 2))
#define P_HHI_SYS_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x0c4 << 2))
#define HHI_HDMI_PLL_CNTL0 (0xff63c000 + (0x0c8 << 2))
#define SEC_HHI_HDMI_PLL_CNTL0 (0xff63c000 + (0x0c8 << 2))
#define P_HHI_HDMI_PLL_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x0c8 << 2))
#define HHI_HDMI_PLL_CNTL1 (0xff63c000 + (0x0c9 << 2))
#define SEC_HHI_HDMI_PLL_CNTL1 (0xff63c000 + (0x0c9 << 2))
#define P_HHI_HDMI_PLL_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x0c9 << 2))
#define HHI_HDMI_PLL_CNTL2 (0xff63c000 + (0x0ca << 2))
#define SEC_HHI_HDMI_PLL_CNTL2 (0xff63c000 + (0x0ca << 2))
#define P_HHI_HDMI_PLL_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x0ca << 2))
#define HHI_HDMI_PLL_CNTL3 (0xff63c000 + (0x0cb << 2))
#define SEC_HHI_HDMI_PLL_CNTL3 (0xff63c000 + (0x0cb << 2))
#define P_HHI_HDMI_PLL_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x0cb << 2))
#define HHI_HDMI_PLL_CNTL4 (0xff63c000 + (0x0cc << 2))
#define SEC_HHI_HDMI_PLL_CNTL4 (0xff63c000 + (0x0cc << 2))
#define P_HHI_HDMI_PLL_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x0cc << 2))
#define HHI_HDMI_PLL_CNTL5 (0xff63c000 + (0x0cd << 2))
#define SEC_HHI_HDMI_PLL_CNTL5 (0xff63c000 + (0x0cd << 2))
#define P_HHI_HDMI_PLL_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x0cd << 2))
#define HHI_HDMI_PLL_CNTL6 (0xff63c000 + (0x0ce << 2))
#define SEC_HHI_HDMI_PLL_CNTL6 (0xff63c000 + (0x0ce << 2))
#define P_HHI_HDMI_PLL_CNTL6 (volatile uint32_t *)(0xff63c000 + (0x0ce << 2))
#define HHI_HDMI_PLL_STS (0xff63c000 + (0x0cf << 2))
#define SEC_HHI_HDMI_PLL_STS (0xff63c000 + (0x0cf << 2))
#define P_HHI_HDMI_PLL_STS (volatile uint32_t *)(0xff63c000 + (0x0cf << 2))
//`define HHI_MIPI_CSI_PHY_CLK_CNTL 8'hd0
//`define HHI_DSI_LVDS_EDP_CNTL0 8'hd1
//`define HHI_DSI_LVDS_EDP_CNTL1 8'hd2
//`define HHI_CSI_PHY_CNTL0 8'hd3
//`define HHI_CSI_PHY_CNTL1 8'hd4
//`define HHI_CSI_PHY_CNTL2 8'hd5
//`define HHI_CSI_PHY_CNTL3 8'hd6
//`define HHI_CSI_PHY_CNTL4 8'hd7
//`define HHI_DIF_CSI_PHY_CNTL0 8'hd8
//`define HHI_DIF_CSI_PHY_CNTL1 8'hd9
//`define HHI_DIF_CSI_PHY_CNTL2 8'hda
//`define HHI_DIF_CSI_PHY_CNTL3 8'hdb
//`define HHI_DIF_CSI_PHY_CNTL4 8'hdc
//`define HHI_DIF_CSI_PHY_CNTL5 8'hdd
//`define HHI_LVDS_TX_PHY_CNTL0 8'hde
//`define HHI_LVDS_TX_PHY_CNTL1 8'hdf
//`define HHI_VID2_PLL_CNTL 8'he0
//`define HHI_VID2_PLL_CNTL2 8'he1
//`define HHI_VID2_PLL_CNTL3 8'he2
//`define HHI_VID2_PLL_CNTL4 8'he3
//`define HHI_VID2_PLL_CNTL5 8'he4
//`define HHI_VID2_PLL_CNTL_I 8'he5
#define HHI_HDMI_PHY_CNTL0 (0xff63c000 + (0x0e8 << 2))
#define SEC_HHI_HDMI_PHY_CNTL0 (0xff63c000 + (0x0e8 << 2))
#define P_HHI_HDMI_PHY_CNTL0 (volatile uint32_t *)(0xff63c000 + (0x0e8 << 2))
#define HHI_HDMI_PHY_CNTL1 (0xff63c000 + (0x0e9 << 2))
#define SEC_HHI_HDMI_PHY_CNTL1 (0xff63c000 + (0x0e9 << 2))
#define P_HHI_HDMI_PHY_CNTL1 (volatile uint32_t *)(0xff63c000 + (0x0e9 << 2))
#define HHI_HDMI_PHY_CNTL2 (0xff63c000 + (0x0ea << 2))
#define SEC_HHI_HDMI_PHY_CNTL2 (0xff63c000 + (0x0ea << 2))
#define P_HHI_HDMI_PHY_CNTL2 (volatile uint32_t *)(0xff63c000 + (0x0ea << 2))
#define HHI_HDMI_PHY_CNTL3 (0xff63c000 + (0x0eb << 2))
#define SEC_HHI_HDMI_PHY_CNTL3 (0xff63c000 + (0x0eb << 2))
#define P_HHI_HDMI_PHY_CNTL3 (volatile uint32_t *)(0xff63c000 + (0x0eb << 2))
#define HHI_HDMI_PHY_CNTL4 (0xff63c000 + (0x0ec << 2))
#define SEC_HHI_HDMI_PHY_CNTL4 (0xff63c000 + (0x0ec << 2))
#define P_HHI_HDMI_PHY_CNTL4 (volatile uint32_t *)(0xff63c000 + (0x0ec << 2))
#define HHI_HDMI_PHY_CNTL5 (0xff63c000 + (0x0ed << 2))
#define SEC_HHI_HDMI_PHY_CNTL5 (0xff63c000 + (0x0ed << 2))
#define P_HHI_HDMI_PHY_CNTL5 (volatile uint32_t *)(0xff63c000 + (0x0ed << 2))
#define HHI_HDMI_PHY_STATUS (0xff63c000 + (0x0ee << 2))
#define SEC_HHI_HDMI_PHY_STATUS (0xff63c000 + (0x0ee << 2))
#define P_HHI_HDMI_PHY_STATUS (volatile uint32_t *)(0xff63c000 + (0x0ee << 2))
//`define HHI_ADEC_SYS_CLK_CNTL 8'hf1
#define HHI_VID_LOCK_CLK_CNTL (0xff63c000 + (0x0f2 << 2))
#define SEC_HHI_VID_LOCK_CLK_CNTL (0xff63c000 + (0x0f2 << 2))
#define P_HHI_VID_LOCK_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x0f2 << 2))
//`define HHI_ATV_DMD_SYS_CLK_CNTL 8'hf3
#define HHI_AXI_PIPEL_CNTL (0xff63c000 + (0x0f4 << 2))
#define SEC_HHI_AXI_PIPEL_CNTL (0xff63c000 + (0x0f4 << 2))
#define P_HHI_AXI_PIPEL_CNTL (volatile uint32_t *)(0xff63c000 + (0x0f4 << 2))
#define HHI_BT656_CLK_CNTL (0xff63c000 + (0x0f5 << 2))
#define SEC_HHI_BT656_CLK_CNTL (0xff63c000 + (0x0f5 << 2))
#define P_HHI_BT656_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x0f5 << 2))
#define HHI_CDAC_CLK_CNTL (0xff63c000 + (0x0f6 << 2))
#define SEC_HHI_CDAC_CLK_CNTL (0xff63c000 + (0x0f6 << 2))
#define P_HHI_CDAC_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x0f6 << 2))
#define HHI_SPICC_CLK_CNTL (0xff63c000 + (0x0f7 << 2))
#define SEC_HHI_SPICC_CLK_CNTL (0xff63c000 + (0x0f7 << 2))
#define P_HHI_SPICC_CLK_CNTL (volatile uint32_t *)(0xff63c000 + (0x0f7 << 2))
//`define HHI_HDMIRX_AUD_PLL_CNTL 8'hf8
//`define HHI_HDMIRX_AUD_PLL_CNTL2 8'hf9
//`define HHI_HDMIRX_AUD_PLL_CNTL3 8'hfa
//`define HHI_HDMIRX_AUD_PLL_CNTL4 8'hfb
//`define HHI_HDMIRX_AUD_PLL_CNTL5 8'hfc
//`define HHI_HDMIRX_AUD_PLL_CNTL6 8'hfd
//`define HHI_HDMIRX_AUD_PLL_CNTL_I 8'hfe
//========================================================================
// HIU - Mailbox
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF63C400
// APB4_DECODER_SECURE_BASE 32'hFF63C400
#define HIU_MAILBOX_SET_0 (0xff63c400 + (0x001 << 2))
#define SEC_HIU_MAILBOX_SET_0 (0xff63c400 + (0x001 << 2))
#define P_HIU_MAILBOX_SET_0 (volatile uint32_t *)(0xff63c400 + (0x001 << 2))
#define HIU_MAILBOX_STAT_0 (0xff63c400 + (0x002 << 2))
#define SEC_HIU_MAILBOX_STAT_0 (0xff63c400 + (0x002 << 2))
#define P_HIU_MAILBOX_STAT_0 (volatile uint32_t *)(0xff63c400 + (0x002 << 2))
#define HIU_MAILBOX_CLR_0 (0xff63c400 + (0x003 << 2))
#define SEC_HIU_MAILBOX_CLR_0 (0xff63c400 + (0x003 << 2))
#define P_HIU_MAILBOX_CLR_0 (volatile uint32_t *)(0xff63c400 + (0x003 << 2))
#define HIU_MAILBOX_SET_1 (0xff63c400 + (0x004 << 2))
#define SEC_HIU_MAILBOX_SET_1 (0xff63c400 + (0x004 << 2))
#define P_HIU_MAILBOX_SET_1 (volatile uint32_t *)(0xff63c400 + (0x004 << 2))
#define HIU_MAILBOX_STAT_1 (0xff63c400 + (0x005 << 2))
#define SEC_HIU_MAILBOX_STAT_1 (0xff63c400 + (0x005 << 2))
#define P_HIU_MAILBOX_STAT_1 (volatile uint32_t *)(0xff63c400 + (0x005 << 2))
#define HIU_MAILBOX_CLR_1 (0xff63c400 + (0x006 << 2))
#define SEC_HIU_MAILBOX_CLR_1 (0xff63c400 + (0x006 << 2))
#define P_HIU_MAILBOX_CLR_1 (volatile uint32_t *)(0xff63c400 + (0x006 << 2))
#define HIU_MAILBOX_SET_2 (0xff63c400 + (0x007 << 2))
#define SEC_HIU_MAILBOX_SET_2 (0xff63c400 + (0x007 << 2))
#define P_HIU_MAILBOX_SET_2 (volatile uint32_t *)(0xff63c400 + (0x007 << 2))
#define HIU_MAILBOX_STAT_2 (0xff63c400 + (0x008 << 2))
#define SEC_HIU_MAILBOX_STAT_2 (0xff63c400 + (0x008 << 2))
#define P_HIU_MAILBOX_STAT_2 (volatile uint32_t *)(0xff63c400 + (0x008 << 2))
#define HIU_MAILBOX_CLR_2 (0xff63c400 + (0x009 << 2))
#define SEC_HIU_MAILBOX_CLR_2 (0xff63c400 + (0x009 << 2))
#define P_HIU_MAILBOX_CLR_2 (volatile uint32_t *)(0xff63c400 + (0x009 << 2))
#define HIU_MAILBOX_SET_3 (0xff63c400 + (0x00a << 2))
#define SEC_HIU_MAILBOX_SET_3 (0xff63c400 + (0x00a << 2))
#define P_HIU_MAILBOX_SET_3 (volatile uint32_t *)(0xff63c400 + (0x00a << 2))
#define HIU_MAILBOX_STAT_3 (0xff63c400 + (0x00b << 2))
#define SEC_HIU_MAILBOX_STAT_3 (0xff63c400 + (0x00b << 2))
#define P_HIU_MAILBOX_STAT_3 (volatile uint32_t *)(0xff63c400 + (0x00b << 2))
#define HIU_MAILBOX_CLR_3 (0xff63c400 + (0x00c << 2))
#define SEC_HIU_MAILBOX_CLR_3 (0xff63c400 + (0x00c << 2))
#define P_HIU_MAILBOX_CLR_3 (volatile uint32_t *)(0xff63c400 + (0x00c << 2))
#define HIU_MAILBOX_SET_4 (0xff63c400 + (0x00d << 2))
#define SEC_HIU_MAILBOX_SET_4 (0xff63c400 + (0x00d << 2))
#define P_HIU_MAILBOX_SET_4 (volatile uint32_t *)(0xff63c400 + (0x00d << 2))
#define HIU_MAILBOX_STAT_4 (0xff63c400 + (0x00e << 2))
#define SEC_HIU_MAILBOX_STAT_4 (0xff63c400 + (0x00e << 2))
#define P_HIU_MAILBOX_STAT_4 (volatile uint32_t *)(0xff63c400 + (0x00e << 2))
#define HIU_MAILBOX_CLR_4 (0xff63c400 + (0x00f << 2))
#define SEC_HIU_MAILBOX_CLR_4 (0xff63c400 + (0x00f << 2))
#define P_HIU_MAILBOX_CLR_4 (volatile uint32_t *)(0xff63c400 + (0x00f << 2))
#define HIU_MAILBOX_SET_5 (0xff63c400 + (0x010 << 2))
#define SEC_HIU_MAILBOX_SET_5 (0xff63c400 + (0x010 << 2))
#define P_HIU_MAILBOX_SET_5 (volatile uint32_t *)(0xff63c400 + (0x010 << 2))
#define HIU_MAILBOX_STAT_5 (0xff63c400 + (0x011 << 2))
#define SEC_HIU_MAILBOX_STAT_5 (0xff63c400 + (0x011 << 2))
#define P_HIU_MAILBOX_STAT_5 (volatile uint32_t *)(0xff63c400 + (0x011 << 2))
#define HIU_MAILBOX_CLR_5 (0xff63c400 + (0x012 << 2))
#define SEC_HIU_MAILBOX_CLR_5 (0xff63c400 + (0x012 << 2))
#define P_HIU_MAILBOX_CLR_5 (volatile uint32_t *)(0xff63c400 + (0x012 << 2))
#define HIU_MAILBOX_SET_6 (0xff63c400 + (0x013 << 2))
#define SEC_HIU_MAILBOX_SET_6 (0xff63c400 + (0x013 << 2))
#define P_HIU_MAILBOX_SET_6 (volatile uint32_t *)(0xff63c400 + (0x013 << 2))
#define HIU_MAILBOX_STAT_6 (0xff63c400 + (0x014 << 2))
#define SEC_HIU_MAILBOX_STAT_6 (0xff63c400 + (0x014 << 2))
#define P_HIU_MAILBOX_STAT_6 (volatile uint32_t *)(0xff63c400 + (0x014 << 2))
#define HIU_MAILBOX_CLR_6 (0xff63c400 + (0x015 << 2))
#define SEC_HIU_MAILBOX_CLR_6 (0xff63c400 + (0x015 << 2))
#define P_HIU_MAILBOX_CLR_6 (volatile uint32_t *)(0xff63c400 + (0x015 << 2))
#define HIU_MAILBOX_SET_7 (0xff63c400 + (0x016 << 2))
#define SEC_HIU_MAILBOX_SET_7 (0xff63c400 + (0x016 << 2))
#define P_HIU_MAILBOX_SET_7 (volatile uint32_t *)(0xff63c400 + (0x016 << 2))
#define HIU_MAILBOX_STAT_7 (0xff63c400 + (0x017 << 2))
#define SEC_HIU_MAILBOX_STAT_7 (0xff63c400 + (0x017 << 2))
#define P_HIU_MAILBOX_STAT_7 (volatile uint32_t *)(0xff63c400 + (0x017 << 2))
#define HIU_MAILBOX_CLR_7 (0xff63c400 + (0x018 << 2))
#define SEC_HIU_MAILBOX_CLR_7 (0xff63c400 + (0x018 << 2))
#define P_HIU_MAILBOX_CLR_7 (volatile uint32_t *)(0xff63c400 + (0x018 << 2))
//========================================================================
// EFUSE
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF630000
// APB4_DECODER_SECURE_BASE 32'hFF630000
#define EFUSE_CLR (0xff630000 + (0x000 << 2))
#define SEC_EFUSE_CLR (0xff630000 + (0x000 << 2))
#define P_EFUSE_CLR (volatile uint32_t *)(0xff630000 + (0x000 << 2))
#define EFUSE_START (0xff630000 + (0x001 << 2))
#define SEC_EFUSE_START (0xff630000 + (0x001 << 2))
#define P_EFUSE_START (volatile uint32_t *)(0xff630000 + (0x001 << 2))
#define EFUSE_WDATA0 (0xff630000 + (0x004 << 2))
#define SEC_EFUSE_WDATA0 (0xff630000 + (0x004 << 2))
#define P_EFUSE_WDATA0 (volatile uint32_t *)(0xff630000 + (0x004 << 2))
#define EFUSE_WDATA1 (0xff630000 + (0x005 << 2))
#define SEC_EFUSE_WDATA1 (0xff630000 + (0x005 << 2))
#define P_EFUSE_WDATA1 (volatile uint32_t *)(0xff630000 + (0x005 << 2))
#define EFUSE_WDATA2 (0xff630000 + (0x006 << 2))
#define SEC_EFUSE_WDATA2 (0xff630000 + (0x006 << 2))
#define P_EFUSE_WDATA2 (volatile uint32_t *)(0xff630000 + (0x006 << 2))
#define EFUSE_WDATA3 (0xff630000 + (0x007 << 2))
#define SEC_EFUSE_WDATA3 (0xff630000 + (0x007 << 2))
#define P_EFUSE_WDATA3 (volatile uint32_t *)(0xff630000 + (0x007 << 2))
#define EFUSE_RDATA0 (0xff630000 + (0x008 << 2))
#define SEC_EFUSE_RDATA0 (0xff630000 + (0x008 << 2))
#define P_EFUSE_RDATA0 (volatile uint32_t *)(0xff630000 + (0x008 << 2))
#define EFUSE_RDATA1 (0xff630000 + (0x009 << 2))
#define SEC_EFUSE_RDATA1 (0xff630000 + (0x009 << 2))
#define P_EFUSE_RDATA1 (volatile uint32_t *)(0xff630000 + (0x009 << 2))
#define EFUSE_RDATA2 (0xff630000 + (0x00a << 2))
#define SEC_EFUSE_RDATA2 (0xff630000 + (0x00a << 2))
#define P_EFUSE_RDATA2 (volatile uint32_t *)(0xff630000 + (0x00a << 2))
#define EFUSE_RDATA3 (0xff630000 + (0x00b << 2))
#define SEC_EFUSE_RDATA3 (0xff630000 + (0x00b << 2))
#define P_EFUSE_RDATA3 (volatile uint32_t *)(0xff630000 + (0x00b << 2))
#define EFUSE_LIC0 (0xff630000 + (0x00c << 2))
#define SEC_EFUSE_LIC0 (0xff630000 + (0x00c << 2))
#define P_EFUSE_LIC0 (volatile uint32_t *)(0xff630000 + (0x00c << 2))
#define EFUSE_LIC1 (0xff630000 + (0x00d << 2))
#define SEC_EFUSE_LIC1 (0xff630000 + (0x00d << 2))
#define P_EFUSE_LIC1 (volatile uint32_t *)(0xff630000 + (0x00d << 2))
#define EFUSE_LIC2 (0xff630000 + (0x00e << 2))
#define SEC_EFUSE_LIC2 (0xff630000 + (0x00e << 2))
#define P_EFUSE_LIC2 (volatile uint32_t *)(0xff630000 + (0x00e << 2))
#define EFUSE_LIC3 (0xff630000 + (0x00f << 2))
#define SEC_EFUSE_LIC3 (0xff630000 + (0x00f << 2))
#define P_EFUSE_LIC3 (volatile uint32_t *)(0xff630000 + (0x00f << 2))
#define KL_START0 (0xff630000 + (0x020 << 2))
#define SEC_KL_START0 (0xff630000 + (0x020 << 2))
#define P_KL_START0 (volatile uint32_t *)(0xff630000 + (0x020 << 2))
#define KL_START1 (0xff630000 + (0x021 << 2))
#define SEC_KL_START1 (0xff630000 + (0x021 << 2))
#define P_KL_START1 (volatile uint32_t *)(0xff630000 + (0x021 << 2))
#define KL_RESP0_0 (0xff630000 + (0x024 << 2))
#define SEC_KL_RESP0_0 (0xff630000 + (0x024 << 2))
#define P_KL_RESP0_0 (volatile uint32_t *)(0xff630000 + (0x024 << 2))
#define KL_RESP0_1 (0xff630000 + (0x025 << 2))
#define SEC_KL_RESP0_1 (0xff630000 + (0x025 << 2))
#define P_KL_RESP0_1 (volatile uint32_t *)(0xff630000 + (0x025 << 2))
#define KL_RESP0_2 (0xff630000 + (0x026 << 2))
#define SEC_KL_RESP0_2 (0xff630000 + (0x026 << 2))
#define P_KL_RESP0_2 (volatile uint32_t *)(0xff630000 + (0x026 << 2))
#define KL_RESP0_3 (0xff630000 + (0x027 << 2))
#define SEC_KL_RESP0_3 (0xff630000 + (0x027 << 2))
#define P_KL_RESP0_3 (volatile uint32_t *)(0xff630000 + (0x027 << 2))
#define KL_RESP1_0 (0xff630000 + (0x028 << 2))
#define SEC_KL_RESP1_0 (0xff630000 + (0x028 << 2))
#define P_KL_RESP1_0 (volatile uint32_t *)(0xff630000 + (0x028 << 2))
#define KL_RESP1_1 (0xff630000 + (0x029 << 2))
#define SEC_KL_RESP1_1 (0xff630000 + (0x029 << 2))
#define P_KL_RESP1_1 (volatile uint32_t *)(0xff630000 + (0x029 << 2))
#define KL_RESP1_2 (0xff630000 + (0x02a << 2))
#define SEC_KL_RESP1_2 (0xff630000 + (0x02a << 2))
#define P_KL_RESP1_2 (volatile uint32_t *)(0xff630000 + (0x02a << 2))
#define KL_RESP1_3 (0xff630000 + (0x02b << 2))
#define SEC_KL_RESP1_3 (0xff630000 + (0x02b << 2))
#define P_KL_RESP1_3 (volatile uint32_t *)(0xff630000 + (0x02b << 2))
#define KL_RAM (0xff630000 + (0x040 << 2))
#define SEC_KL_RAM (0xff630000 + (0x040 << 2))
#define P_KL_RAM (volatile uint32_t *)(0xff630000 + (0x040 << 2))
#define RNG_SEC_CONFIG_REG1 (0xff630000 + (0x081 << 2))
#define SEC_RNG_SEC_CONFIG_REG1 (0xff630000 + (0x081 << 2))
#define P_RNG_SEC_CONFIG_REG1 (volatile uint32_t *)(0xff630000 + (0x081 << 2))
#define RNG_SEC_CONFIG_REG2 (0xff630000 + (0x082 << 2))
#define SEC_RNG_SEC_CONFIG_REG2 (0xff630000 + (0x082 << 2))
#define P_RNG_SEC_CONFIG_REG2 (volatile uint32_t *)(0xff630000 + (0x082 << 2))
#define RNG_SEC_DATA (0xff630000 + (0x084 << 2))
#define SEC_RNG_SEC_DATA (0xff630000 + (0x084 << 2))
#define P_RNG_SEC_DATA (volatile uint32_t *)(0xff630000 + (0x084 << 2))
#define RNG_SEC_STS (0xff630000 + (0x085 << 2))
#define SEC_RNG_SEC_STS (0xff630000 + (0x085 << 2))
#define P_RNG_SEC_STS (volatile uint32_t *)(0xff630000 + (0x085 << 2))
#define RNG_USR_DATA (0xff630000 + (0x086 << 2))
#define SEC_RNG_USR_DATA (0xff630000 + (0x086 << 2))
#define P_RNG_USR_DATA (volatile uint32_t *)(0xff630000 + (0x086 << 2))
#define RNG_USR_STS (0xff630000 + (0x087 << 2))
#define SEC_RNG_USR_STS (0xff630000 + (0x087 << 2))
#define P_RNG_USR_STS (volatile uint32_t *)(0xff630000 + (0x087 << 2))
//========================================================================
// Ethernet Phy
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF64C000
// APB4_DECODER_SECURE_BASE 32'hFF64C000
#define ETH_PHY_DBG_CTL0 (0xff64c000 + (0x000 << 2))
#define SEC_ETH_PHY_DBG_CTL0 (0xff64c000 + (0x000 << 2))
#define P_ETH_PHY_DBG_CTL0 (volatile uint32_t *)(0xff64c000 + (0x000 << 2))
#define ETH_PHY_DBG_CTL1 (0xff64c000 + (0x001 << 2))
#define SEC_ETH_PHY_DBG_CTL1 (0xff64c000 + (0x001 << 2))
#define P_ETH_PHY_DBG_CTL1 (volatile uint32_t *)(0xff64c000 + (0x001 << 2))
#define ETH_PHY_DBG_CFG0 (0xff64c000 + (0x002 << 2))
#define SEC_ETH_PHY_DBG_CFG0 (0xff64c000 + (0x002 << 2))
#define P_ETH_PHY_DBG_CFG0 (volatile uint32_t *)(0xff64c000 + (0x002 << 2))
#define ETH_PHY_DBG_CFG1 (0xff64c000 + (0x003 << 2))
#define SEC_ETH_PHY_DBG_CFG1 (0xff64c000 + (0x003 << 2))
#define P_ETH_PHY_DBG_CFG1 (volatile uint32_t *)(0xff64c000 + (0x003 << 2))
#define ETH_PHY_DBG_CFG2 (0xff64c000 + (0x004 << 2))
#define SEC_ETH_PHY_DBG_CFG2 (0xff64c000 + (0x004 << 2))
#define P_ETH_PHY_DBG_CFG2 (volatile uint32_t *)(0xff64c000 + (0x004 << 2))
#define ETH_PHY_DBG_CFG3 (0xff64c000 + (0x005 << 2))
#define SEC_ETH_PHY_DBG_CFG3 (0xff64c000 + (0x005 << 2))
#define P_ETH_PHY_DBG_CFG3 (volatile uint32_t *)(0xff64c000 + (0x005 << 2))
#define ETH_PHY_DBG_CFG4 (0xff64c000 + (0x006 << 2))
#define SEC_ETH_PHY_DBG_CFG4 (0xff64c000 + (0x006 << 2))
#define P_ETH_PHY_DBG_CFG4 (volatile uint32_t *)(0xff64c000 + (0x006 << 2))
#define ETH_PLL_STS (0xff64c000 + (0x010 << 2))
#define SEC_ETH_PLL_STS (0xff64c000 + (0x010 << 2))
#define P_ETH_PLL_STS (volatile uint32_t *)(0xff64c000 + (0x010 << 2))
#define ETH_PLL_CTL0 (0xff64c000 + (0x011 << 2))
#define SEC_ETH_PLL_CTL0 (0xff64c000 + (0x011 << 2))
#define P_ETH_PLL_CTL0 (volatile uint32_t *)(0xff64c000 + (0x011 << 2))
#define ETH_PLL_CTL1 (0xff64c000 + (0x012 << 2))
#define SEC_ETH_PLL_CTL1 (0xff64c000 + (0x012 << 2))
#define P_ETH_PLL_CTL1 (volatile uint32_t *)(0xff64c000 + (0x012 << 2))
#define ETH_PLL_CTL2 (0xff64c000 + (0x013 << 2))
#define SEC_ETH_PLL_CTL2 (0xff64c000 + (0x013 << 2))
#define P_ETH_PLL_CTL2 (volatile uint32_t *)(0xff64c000 + (0x013 << 2))
#define ETH_PLL_CTL3 (0xff64c000 + (0x014 << 2))
#define SEC_ETH_PLL_CTL3 (0xff64c000 + (0x014 << 2))
#define P_ETH_PLL_CTL3 (volatile uint32_t *)(0xff64c000 + (0x014 << 2))
#define ETH_PLL_CTL4 (0xff64c000 + (0x015 << 2))
#define SEC_ETH_PLL_CTL4 (0xff64c000 + (0x015 << 2))
#define P_ETH_PLL_CTL4 (volatile uint32_t *)(0xff64c000 + (0x015 << 2))
#define ETH_PLL_CTL5 (0xff64c000 + (0x016 << 2))
#define SEC_ETH_PLL_CTL5 (0xff64c000 + (0x016 << 2))
#define P_ETH_PLL_CTL5 (volatile uint32_t *)(0xff64c000 + (0x016 << 2))
#define ETH_PLL_CTL6 (0xff64c000 + (0x017 << 2))
#define SEC_ETH_PLL_CTL6 (0xff64c000 + (0x017 << 2))
#define P_ETH_PLL_CTL6 (volatile uint32_t *)(0xff64c000 + (0x017 << 2))
#define ETH_PLL_CTL7 (0xff64c000 + (0x018 << 2))
#define SEC_ETH_PLL_CTL7 (0xff64c000 + (0x018 << 2))
#define P_ETH_PLL_CTL7 (volatile uint32_t *)(0xff64c000 + (0x018 << 2))
#define ETH_PHY_CNTL0 (0xff64c000 + (0x020 << 2))
#define SEC_ETH_PHY_CNTL0 (0xff64c000 + (0x020 << 2))
#define P_ETH_PHY_CNTL0 (volatile uint32_t *)(0xff64c000 + (0x020 << 2))
#define ETH_PHY_CNTL1 (0xff64c000 + (0x021 << 2))
#define SEC_ETH_PHY_CNTL1 (0xff64c000 + (0x021 << 2))
#define P_ETH_PHY_CNTL1 (volatile uint32_t *)(0xff64c000 + (0x021 << 2))
#define ETH_PHY_CNTL2 (0xff64c000 + (0x022 << 2))
#define SEC_ETH_PHY_CNTL2 (0xff64c000 + (0x022 << 2))
#define P_ETH_PHY_CNTL2 (volatile uint32_t *)(0xff64c000 + (0x022 << 2))
#define ETH_PHY_STS0 (0xff64c000 + (0x025 << 2))
#define SEC_ETH_PHY_STS0 (0xff64c000 + (0x025 << 2))
#define P_ETH_PHY_STS0 (volatile uint32_t *)(0xff64c000 + (0x025 << 2))
#define ETH_PHY_STS1 (0xff64c000 + (0x026 << 2))
#define SEC_ETH_PHY_STS1 (0xff64c000 + (0x026 << 2))
#define P_ETH_PHY_STS1 (volatile uint32_t *)(0xff64c000 + (0x026 << 2))
#define ETH_PHY_STS2 (0xff64c000 + (0x027 << 2))
#define SEC_ETH_PHY_STS2 (0xff64c000 + (0x027 << 2))
#define P_ETH_PHY_STS2 (volatile uint32_t *)(0xff64c000 + (0x027 << 2))
#define ETH_PHY_DBG_REG (0xff64c000 + (0x028 << 2))
#define SEC_ETH_PHY_DBG_REG (0xff64c000 + (0x028 << 2))
#define P_ETH_PHY_DBG_REG (volatile uint32_t *)(0xff64c000 + (0x028 << 2))
//========================================================================
// PDM
//========================================================================
//
// Reading file: ../audio/rtl/pdm_reg.vh
//
// APB4_DECODER_NON_SECURE_BASE 32'hFF640000
// APB4_DECODER_SECURE_BASE 32'hFF640000
#define PDM_CTRL (0xff640000 + (0x000 << 2))
#define SEC_PDM_CTRL (0xff640000 + (0x000 << 2))
#define P_PDM_CTRL (volatile uint32_t *)(0xff640000 + (0x000 << 2))
#define PDM_HCIC_CTRL1 (0xff640000 + (0x001 << 2))
#define SEC_PDM_HCIC_CTRL1 (0xff640000 + (0x001 << 2))
#define P_PDM_HCIC_CTRL1 (volatile uint32_t *)(0xff640000 + (0x001 << 2))
#define PDM_HCIC_CTRL2 (0xff640000 + (0x002 << 2))
#define SEC_PDM_HCIC_CTRL2 (0xff640000 + (0x002 << 2))
#define P_PDM_HCIC_CTRL2 (volatile uint32_t *)(0xff640000 + (0x002 << 2))
#define PDM_F1_CTRL (0xff640000 + (0x003 << 2))
#define SEC_PDM_F1_CTRL (0xff640000 + (0x003 << 2))
#define P_PDM_F1_CTRL (volatile uint32_t *)(0xff640000 + (0x003 << 2))
#define PDM_F2_CTRL (0xff640000 + (0x004 << 2))
#define SEC_PDM_F2_CTRL (0xff640000 + (0x004 << 2))
#define P_PDM_F2_CTRL (volatile uint32_t *)(0xff640000 + (0x004 << 2))
#define PDM_F3_CTRL (0xff640000 + (0x005 << 2))
#define SEC_PDM_F3_CTRL (0xff640000 + (0x005 << 2))
#define P_PDM_F3_CTRL (volatile uint32_t *)(0xff640000 + (0x005 << 2))
#define PDM_HPF_CTRL (0xff640000 + (0x006 << 2))
#define SEC_PDM_HPF_CTRL (0xff640000 + (0x006 << 2))
#define P_PDM_HPF_CTRL (volatile uint32_t *)(0xff640000 + (0x006 << 2))
#define PDM_CHAN_CTRL (0xff640000 + (0x007 << 2))
#define SEC_PDM_CHAN_CTRL (0xff640000 + (0x007 << 2))
#define P_PDM_CHAN_CTRL (volatile uint32_t *)(0xff640000 + (0x007 << 2))
#define PDM_CHAN_CTRL1 (0xff640000 + (0x008 << 2))
#define SEC_PDM_CHAN_CTRL1 (0xff640000 + (0x008 << 2))
#define P_PDM_CHAN_CTRL1 (volatile uint32_t *)(0xff640000 + (0x008 << 2))
#define PDM_COEFF_ADDR (0xff640000 + (0x009 << 2))
#define SEC_PDM_COEFF_ADDR (0xff640000 + (0x009 << 2))
#define P_PDM_COEFF_ADDR (volatile uint32_t *)(0xff640000 + (0x009 << 2))
#define PDM_COEFF_DATA (0xff640000 + (0x00a << 2))
#define SEC_PDM_COEFF_DATA (0xff640000 + (0x00a << 2))
#define P_PDM_COEFF_DATA (volatile uint32_t *)(0xff640000 + (0x00a << 2))
#define PDM_CLKG_CTRL (0xff640000 + (0x00b << 2))
#define SEC_PDM_CLKG_CTRL (0xff640000 + (0x00b << 2))
#define P_PDM_CLKG_CTRL (volatile uint32_t *)(0xff640000 + (0x00b << 2))
#define PDM_STS (0xff640000 + (0x00c << 2))
#define SEC_PDM_STS (0xff640000 + (0x00c << 2))
#define P_PDM_STS (volatile uint32_t *)(0xff640000 + (0x00c << 2))
//bit 1 HPF filter output overflow. means the PCLK is too slow.
//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function.
#define PDM_MUTE_VALUE (0xff640000 + (0x00d << 2))
#define SEC_PDM_MUTE_VALUE (0xff640000 + (0x00d << 2))
#define P_PDM_MUTE_VALUE (volatile uint32_t *)(0xff640000 + (0x00d << 2))
//
// Closing file: ../audio/rtl/pdm_reg.vh
//
// synopsys translate_off
// synopsys translate_on
//
// Closing file: ./secure_apb4_ee.h
//
//
// Reading file: ./ao_rti_reg.h
//
//#define AO_RTI_REG_BASE 0x00
// APB4_DECODER_NON_SECURE_BASE 32'hFF800000
// APB4_DECODER_SECURE_BASE 32'hFF800000
// Registers not affected by the Watchdog timer
#define AO_RTI_STATUS_REG0 (0xff800000 + (0x000 << 2))
#define SEC_AO_RTI_STATUS_REG0 (0xff800000 + (0x000 << 2))
#define P_AO_RTI_STATUS_REG0 (volatile uint32_t *)(0xff800000 + (0x000 << 2))
#define AO_RTI_STATUS_REG1 (0xff800000 + (0x001 << 2))
#define SEC_AO_RTI_STATUS_REG1 (0xff800000 + (0x001 << 2))
#define P_AO_RTI_STATUS_REG1 (volatile uint32_t *)(0xff800000 + (0x001 << 2))
#define AO_RTI_STATUS_REG2 (0xff800000 + (0x002 << 2))
#define SEC_AO_RTI_STATUS_REG2 (0xff800000 + (0x002 << 2))
#define P_AO_RTI_STATUS_REG2 (volatile uint32_t *)(0xff800000 + (0x002 << 2))
#define AO_RTI_STATUS_REG3 (0xff800000 + (0x003 << 2))
#define SEC_AO_RTI_STATUS_REG3 (0xff800000 + (0x003 << 2))
#define P_AO_RTI_STATUS_REG3 (volatile uint32_t *)(0xff800000 + (0x003 << 2))
//`define AO_RTI_PWR_CNTL_REG1 8'h03
#define AO_RTI_PWR_CNTL_REG0 (0xff800000 + (0x004 << 2))
#define SEC_AO_RTI_PWR_CNTL_REG0 (0xff800000 + (0x004 << 2))
#define P_AO_RTI_PWR_CNTL_REG0 (volatile uint32_t *)(0xff800000 + (0x004 << 2))
#define AO_RTI_PINMUX_REG0 (0xff800000 + (0x005 << 2))
#define SEC_AO_RTI_PINMUX_REG0 (0xff800000 + (0x005 << 2))
#define P_AO_RTI_PINMUX_REG0 (volatile uint32_t *)(0xff800000 + (0x005 << 2))
#define AO_RTI_PINMUX_REG1 (0xff800000 + (0x006 << 2))
#define SEC_AO_RTI_PINMUX_REG1 (0xff800000 + (0x006 << 2))
#define P_AO_RTI_PINMUX_REG1 (volatile uint32_t *)(0xff800000 + (0x006 << 2))
//`define AO_REMAP_REG1 8'h08
#define AO_PAD_DS_A (0xff800000 + (0x007 << 2))
#define SEC_AO_PAD_DS_A (0xff800000 + (0x007 << 2))
#define P_AO_PAD_DS_A (volatile uint32_t *)(0xff800000 + (0x007 << 2))
#define AO_PAD_DS_B (0xff800000 + (0x008 << 2))
#define SEC_AO_PAD_DS_B (0xff800000 + (0x008 << 2))
#define P_AO_PAD_DS_B (volatile uint32_t *)(0xff800000 + (0x008 << 2))
#define AO_GPIO_O_EN_N (0xff800000 + (0x009 << 2))
#define SEC_AO_GPIO_O_EN_N (0xff800000 + (0x009 << 2))
#define P_AO_GPIO_O_EN_N (volatile uint32_t *)(0xff800000 + (0x009 << 2))
#define AO_GPIO_I (0xff800000 + (0x00a << 2))
#define SEC_AO_GPIO_I (0xff800000 + (0x00a << 2))
#define P_AO_GPIO_I (volatile uint32_t *)(0xff800000 + (0x00a << 2))
#define AO_RTI_PULL_UP_REG (0xff800000 + (0x00b << 2))
#define SEC_AO_RTI_PULL_UP_REG (0xff800000 + (0x00b << 2))
#define P_AO_RTI_PULL_UP_REG (volatile uint32_t *)(0xff800000 + (0x00b << 2))
#define AO_RTI_PULL_UP_EN_REG (0xff800000 + (0x00c << 2))
#define SEC_AO_RTI_PULL_UP_EN_REG (0xff800000 + (0x00c << 2))
#define P_AO_RTI_PULL_UP_EN_REG (volatile uint32_t *)(0xff800000 + (0x00c << 2))
#define AO_GPIO_O (0xff800000 + (0x00d << 2))
#define SEC_AO_GPIO_O (0xff800000 + (0x00d << 2))
#define P_AO_GPIO_O (volatile uint32_t *)(0xff800000 + (0x00d << 2))
//`define AO_RTI_JTAG_CONFIG_REG 8'h0C
//`define AO_RTI_WD_MARK 8'h0D
#define AO_CPU_CNTL (0xff800000 + (0x00e << 2))
#define SEC_AO_CPU_CNTL (0xff800000 + (0x00e << 2))
#define P_AO_CPU_CNTL (volatile uint32_t *)(0xff800000 + (0x00e << 2))
#define AO_CPU_CNTL2 (0xff800000 + (0x00f << 2))
#define SEC_AO_CPU_CNTL2 (0xff800000 + (0x00f << 2))
#define P_AO_CPU_CNTL2 (volatile uint32_t *)(0xff800000 + (0x00f << 2))
#define AO_RTI_GEN_CNTL_REG0 (0xff800000 + (0x010 << 2))
#define SEC_AO_RTI_GEN_CNTL_REG0 (0xff800000 + (0x010 << 2))
#define P_AO_RTI_GEN_CNTL_REG0 (volatile uint32_t *)(0xff800000 + (0x010 << 2))
#define AO_CPU_CNTL_NS (0xff800000 + (0x011 << 2))
#define SEC_AO_CPU_CNTL_NS (0xff800000 + (0x011 << 2))
#define P_AO_CPU_CNTL_NS (volatile uint32_t *)(0xff800000 + (0x011 << 2))
#define AO_METAL_REVISION_1 (0xff800000 + (0x012 << 2))
#define SEC_AO_METAL_REVISION_1 (0xff800000 + (0x012 << 2))
#define P_AO_METAL_REVISION_1 (volatile uint32_t *)(0xff800000 + (0x012 << 2))
#define AO_CLK_GATE0 (0xff800000 + (0x013 << 2))
#define SEC_AO_CLK_GATE0 (0xff800000 + (0x013 << 2))
#define P_AO_CLK_GATE0 (volatile uint32_t *)(0xff800000 + (0x013 << 2))
#define AO_CLK_GATE0_SP (0xff800000 + (0x014 << 2))
#define SEC_AO_CLK_GATE0_SP (0xff800000 + (0x014 << 2))
#define P_AO_CLK_GATE0_SP (volatile uint32_t *)(0xff800000 + (0x014 << 2))
#define AO_TIMEBASE_CNTL1 (0xff800000 + (0x015 << 2))
#define SEC_AO_TIMEBASE_CNTL1 (0xff800000 + (0x015 << 2))
#define P_AO_TIMEBASE_CNTL1 (volatile uint32_t *)(0xff800000 + (0x015 << 2))
#define AO_OSCIN_CNTL (0xff800000 + (0x016 << 2))
#define SEC_AO_OSCIN_CNTL (0xff800000 + (0x016 << 2))
#define P_AO_OSCIN_CNTL (volatile uint32_t *)(0xff800000 + (0x016 << 2))
#define AO_PINMUX_LOCK (0xff800000 + (0x017 << 2))
#define SEC_AO_PINMUX_LOCK (0xff800000 + (0x017 << 2))
#define P_AO_PINMUX_LOCK (volatile uint32_t *)(0xff800000 + (0x017 << 2))
#define AO_AHB2DDR_CNTL (0xff800000 + (0x018 << 2))
#define SEC_AO_AHB2DDR_CNTL (0xff800000 + (0x018 << 2))
#define P_AO_AHB2DDR_CNTL (volatile uint32_t *)(0xff800000 + (0x018 << 2))
#define AO_TIMEBASE_CNTL (0xff800000 + (0x019 << 2))
#define SEC_AO_TIMEBASE_CNTL (0xff800000 + (0x019 << 2))
#define P_AO_TIMEBASE_CNTL (volatile uint32_t *)(0xff800000 + (0x019 << 2))
#define AO_GEN_CLK_CNTL (0xff800000 + (0x01a << 2))
#define SEC_AO_GEN_CLK_CNTL (0xff800000 + (0x01a << 2))
#define P_AO_GEN_CLK_CNTL (volatile uint32_t *)(0xff800000 + (0x01a << 2))
//`define AO_RTI_INTER_OSC_CTL0 8'h1b
//`define AO_RTI_INTER_OSC_CTL1 8'h1c
#define AO_CEC_CLK_CNTL_REG0 (0xff800000 + (0x01d << 2))
#define SEC_AO_CEC_CLK_CNTL_REG0 (0xff800000 + (0x01d << 2))
#define P_AO_CEC_CLK_CNTL_REG0 (volatile uint32_t *)(0xff800000 + (0x01d << 2))
#define AO_CEC_CLK_CNTL_REG1 (0xff800000 + (0x01e << 2))
#define SEC_AO_CEC_CLK_CNTL_REG1 (0xff800000 + (0x01e << 2))
#define P_AO_CEC_CLK_CNTL_REG1 (volatile uint32_t *)(0xff800000 + (0x01e << 2))
#define AO_METAL_REVISION (0xff800000 + (0x01f << 2))
#define SEC_AO_METAL_REVISION (0xff800000 + (0x01f << 2))
#define P_AO_METAL_REVISION (volatile uint32_t *)(0xff800000 + (0x01f << 2))
//`define AO_IRQ_MASK_FIQ_SEL 8'h20
#define AO_IRQ_GPIO_REG (0xff800000 + (0x021 << 2))
#define SEC_AO_IRQ_GPIO_REG (0xff800000 + (0x021 << 2))
#define P_AO_IRQ_GPIO_REG (volatile uint32_t *)(0xff800000 + (0x021 << 2))
//`define AO_IRQ_STAT 8'h22
//`define AO_IRQ_STAT_CLR 8'h23
#define AO_SAR_CLK (0xff800000 + (0x024 << 2))
#define SEC_AO_SAR_CLK (0xff800000 + (0x024 << 2))
#define P_AO_SAR_CLK (volatile uint32_t *)(0xff800000 + (0x024 << 2))
#define AO_RTC_ALT_CLK_CNTL0 (0xff800000 + (0x025 << 2))
#define SEC_AO_RTC_ALT_CLK_CNTL0 (0xff800000 + (0x025 << 2))
#define P_AO_RTC_ALT_CLK_CNTL0 (volatile uint32_t *)(0xff800000 + (0x025 << 2))
#define AO_RTC_ALT_CLK_CNTL1 (0xff800000 + (0x026 << 2))
#define SEC_AO_RTC_ALT_CLK_CNTL1 (0xff800000 + (0x026 << 2))
#define P_AO_RTC_ALT_CLK_CNTL1 (volatile uint32_t *)(0xff800000 + (0x026 << 2))
#define AO_TIMESTAMP_CNTL2 (0xff800000 + (0x027 << 2))
#define SEC_AO_TIMESTAMP_CNTL2 (0xff800000 + (0x027 << 2))
#define P_AO_TIMESTAMP_CNTL2 (volatile uint32_t *)(0xff800000 + (0x027 << 2))
#define AO_DEBUG_REG0 (0xff800000 + (0x028 << 2))
#define SEC_AO_DEBUG_REG0 (0xff800000 + (0x028 << 2))
#define P_AO_DEBUG_REG0 (volatile uint32_t *)(0xff800000 + (0x028 << 2))
#define AO_DEBUG_REG1 (0xff800000 + (0x029 << 2))
#define SEC_AO_DEBUG_REG1 (0xff800000 + (0x029 << 2))
#define P_AO_DEBUG_REG1 (volatile uint32_t *)(0xff800000 + (0x029 << 2))
#define AO_DEBUG_REG2 (0xff800000 + (0x02a << 2))
#define SEC_AO_DEBUG_REG2 (0xff800000 + (0x02a << 2))
#define P_AO_DEBUG_REG2 (volatile uint32_t *)(0xff800000 + (0x02a << 2))
#define AO_DEBUG_REG3 (0xff800000 + (0x02b << 2))
#define SEC_AO_DEBUG_REG3 (0xff800000 + (0x02b << 2))
#define P_AO_DEBUG_REG3 (volatile uint32_t *)(0xff800000 + (0x02b << 2))
#define AO_TIMESTAMP_CNTL1 (0xff800000 + (0x02c << 2))
#define SEC_AO_TIMESTAMP_CNTL1 (0xff800000 + (0x02c << 2))
#define P_AO_TIMESTAMP_CNTL1 (volatile uint32_t *)(0xff800000 + (0x02c << 2))
#define AO_TIMESTAMP_CNTL (0xff800000 + (0x02d << 2))
#define SEC_AO_TIMESTAMP_CNTL (0xff800000 + (0x02d << 2))
#define P_AO_TIMESTAMP_CNTL (volatile uint32_t *)(0xff800000 + (0x02d << 2))
#define AO_TIMESTAMP_RD0 (0xff800000 + (0x02e << 2))
#define SEC_AO_TIMESTAMP_RD0 (0xff800000 + (0x02e << 2))
#define P_AO_TIMESTAMP_RD0 (volatile uint32_t *)(0xff800000 + (0x02e << 2))
#define AO_TIMESTAMP_RD1 (0xff800000 + (0x02f << 2))
#define SEC_AO_TIMESTAMP_RD1 (0xff800000 + (0x02f << 2))
#define P_AO_TIMESTAMP_RD1 (volatile uint32_t *)(0xff800000 + (0x02f << 2))
#define SP_HOLD_CTRL (0xff800000 + (0x031 << 2))
#define SEC_SP_HOLD_CTRL (0xff800000 + (0x031 << 2))
#define P_SP_HOLD_CTRL (volatile uint32_t *)(0xff800000 + (0x031 << 2))
#define AO_FR_EE_WR_ONCE (0xff800000 + (0x032 << 2))
#define SEC_AO_FR_EE_WR_ONCE (0xff800000 + (0x032 << 2))
#define P_AO_FR_EE_WR_ONCE (volatile uint32_t *)(0xff800000 + (0x032 << 2))
#define AO_CPU_STAT1 (0xff800000 + (0x033 << 2))
#define SEC_AO_CPU_STAT1 (0xff800000 + (0x033 << 2))
#define P_AO_CPU_STAT1 (volatile uint32_t *)(0xff800000 + (0x033 << 2))
#define AO_CPU_STAT2 (0xff800000 + (0x034 << 2))
#define SEC_AO_CPU_STAT2 (0xff800000 + (0x034 << 2))
#define P_AO_CPU_STAT2 (volatile uint32_t *)(0xff800000 + (0x034 << 2))
#define AO_CPU_TIMESTAMP (0xff800000 + (0x035 << 2))
#define SEC_AO_CPU_TIMESTAMP (0xff800000 + (0x035 << 2))
#define P_AO_CPU_TIMESTAMP (volatile uint32_t *)(0xff800000 + (0x035 << 2))
#define AO_CPU_TIMESTAMP2 (0xff800000 + (0x036 << 2))
#define SEC_AO_CPU_TIMESTAMP2 (0xff800000 + (0x036 << 2))
#define P_AO_CPU_TIMESTAMP2 (volatile uint32_t *)(0xff800000 + (0x036 << 2))
#define AO_CPU_CNTL3 (0xff800000 + (0x037 << 2))
#define SEC_AO_CPU_CNTL3 (0xff800000 + (0x037 << 2))
#define P_AO_CPU_CNTL3 (volatile uint32_t *)(0xff800000 + (0x037 << 2))
// general Power control
#define AO_RTI_PWR_SYS_CPU_CNTL0 (0xff800000 + (0x038 << 2))
#define SEC_AO_RTI_PWR_SYS_CPU_CNTL0 (0xff800000 + (0x038 << 2))
#define P_AO_RTI_PWR_SYS_CPU_CNTL0 (volatile uint32_t *)(0xff800000 + (0x038 << 2))
#define AO_RTI_PWR_SYS_CPU_CNTL1 (0xff800000 + (0x039 << 2))
#define SEC_AO_RTI_PWR_SYS_CPU_CNTL1 (0xff800000 + (0x039 << 2))
#define P_AO_RTI_PWR_SYS_CPU_CNTL1 (volatile uint32_t *)(0xff800000 + (0x039 << 2))
#define AO_RTI_GEN_PWR_SLEEP0 (0xff800000 + (0x03a << 2))
#define SEC_AO_RTI_GEN_PWR_SLEEP0 (0xff800000 + (0x03a << 2))
#define P_AO_RTI_GEN_PWR_SLEEP0 (volatile uint32_t *)(0xff800000 + (0x03a << 2))
#define AO_RTI_GEN_PWR_ISO0 (0xff800000 + (0x03b << 2))
#define SEC_AO_RTI_GEN_PWR_ISO0 (0xff800000 + (0x03b << 2))
#define P_AO_RTI_GEN_PWR_ISO0 (volatile uint32_t *)(0xff800000 + (0x03b << 2))
#define AO_RTI_GEN_PWR_ACK0 (0xff800000 + (0x03c << 2))
#define SEC_AO_RTI_GEN_PWR_ACK0 (0xff800000 + (0x03c << 2))
#define P_AO_RTI_GEN_PWR_ACK0 (volatile uint32_t *)(0xff800000 + (0x03c << 2))
#define AO_RTI_PWR_SYS_CPU_MEM_PD0 (0xff800000 + (0x03d << 2))
#define SEC_AO_RTI_PWR_SYS_CPU_MEM_PD0 (0xff800000 + (0x03d << 2))
#define P_AO_RTI_PWR_SYS_CPU_MEM_PD0 (volatile uint32_t *)(0xff800000 + (0x03d << 2))
#define AO_RTI_PWR_SYS_CPU_MEM_PD1 (0xff800000 + (0x03e << 2))
#define SEC_AO_RTI_PWR_SYS_CPU_MEM_PD1 (0xff800000 + (0x03e << 2))
#define P_AO_RTI_PWR_SYS_CPU_MEM_PD1 (volatile uint32_t *)(0xff800000 + (0x03e << 2))
#define AO_CPU_CNTL4 (0xff800000 + (0x03f << 2))
#define SEC_AO_CPU_CNTL4 (0xff800000 + (0x03f << 2))
#define P_AO_CPU_CNTL4 (volatile uint32_t *)(0xff800000 + (0x03f << 2))
#define AO_CEC_GEN_CNTL (0xff800000 + (0x040 << 2))
#define SEC_AO_CEC_GEN_CNTL (0xff800000 + (0x040 << 2))
#define P_AO_CEC_GEN_CNTL (volatile uint32_t *)(0xff800000 + (0x040 << 2))
#define AO_CEC_RW_REG (0xff800000 + (0x041 << 2))
#define SEC_AO_CEC_RW_REG (0xff800000 + (0x041 << 2))
#define P_AO_CEC_RW_REG (volatile uint32_t *)(0xff800000 + (0x041 << 2))
#define AO_CEC_INTR_MASKN (0xff800000 + (0x042 << 2))
#define SEC_AO_CEC_INTR_MASKN (0xff800000 + (0x042 << 2))
#define P_AO_CEC_INTR_MASKN (volatile uint32_t *)(0xff800000 + (0x042 << 2))
#define AO_CEC_INTR_CLR (0xff800000 + (0x043 << 2))
#define SEC_AO_CEC_INTR_CLR (0xff800000 + (0x043 << 2))
#define P_AO_CEC_INTR_CLR (volatile uint32_t *)(0xff800000 + (0x043 << 2))
#define AO_CEC_INTR_STAT (0xff800000 + (0x044 << 2))
#define SEC_AO_CEC_INTR_STAT (0xff800000 + (0x044 << 2))
#define P_AO_CEC_INTR_STAT (volatile uint32_t *)(0xff800000 + (0x044 << 2))
#define AO_CPU_CNTL5 (0xff800000 + (0x045 << 2))
#define SEC_AO_CPU_CNTL5 (0xff800000 + (0x045 << 2))
#define P_AO_CPU_CNTL5 (volatile uint32_t *)(0xff800000 + (0x045 << 2))
#define AO_WATCHDOG_CNTL (0xff800000 + (0x048 << 2))
#define SEC_AO_WATCHDOG_CNTL (0xff800000 + (0x048 << 2))
#define P_AO_WATCHDOG_CNTL (volatile uint32_t *)(0xff800000 + (0x048 << 2))
#define AO_WATCHDOG_CNTL1 (0xff800000 + (0x049 << 2))
#define SEC_AO_WATCHDOG_CNTL1 (0xff800000 + (0x049 << 2))
#define P_AO_WATCHDOG_CNTL1 (volatile uint32_t *)(0xff800000 + (0x049 << 2))
#define AO_WATCHDOG_TCNT (0xff800000 + (0x04a << 2))
#define SEC_AO_WATCHDOG_TCNT (0xff800000 + (0x04a << 2))
#define P_AO_WATCHDOG_TCNT (volatile uint32_t *)(0xff800000 + (0x04a << 2))
#define AO_WATCHDOG_RESET (0xff800000 + (0x04b << 2))
#define SEC_AO_WATCHDOG_RESET (0xff800000 + (0x04b << 2))
#define P_AO_WATCHDOG_RESET (volatile uint32_t *)(0xff800000 + (0x04b << 2))
#define AO_RTI_STICKY_REG0 (0xff800000 + (0x04c << 2))
#define SEC_AO_RTI_STICKY_REG0 (0xff800000 + (0x04c << 2))
#define P_AO_RTI_STICKY_REG0 (volatile uint32_t *)(0xff800000 + (0x04c << 2))
#define AO_RTI_STICKY_REG1 (0xff800000 + (0x04d << 2))
#define SEC_AO_RTI_STICKY_REG1 (0xff800000 + (0x04d << 2))
#define P_AO_RTI_STICKY_REG1 (volatile uint32_t *)(0xff800000 + (0x04d << 2))
#define AO_RTI_STICKY_REG2 (0xff800000 + (0x04e << 2))
#define SEC_AO_RTI_STICKY_REG2 (0xff800000 + (0x04e << 2))
#define P_AO_RTI_STICKY_REG2 (volatile uint32_t *)(0xff800000 + (0x04e << 2))
#define AO_RTI_STICKY_REG3 (0xff800000 + (0x04f << 2))
#define SEC_AO_RTI_STICKY_REG3 (0xff800000 + (0x04f << 2))
#define P_AO_RTI_STICKY_REG3 (volatile uint32_t *)(0xff800000 + (0x04f << 2))
//
// Secure APB3 Slot 2 registers
//
#define AO_SEC_REG0 (0xff800000 + (0x050 << 2))
#define SEC_AO_SEC_REG0 (0xff800000 + (0x050 << 2))
#define P_AO_SEC_REG0 (volatile uint32_t *)(0xff800000 + (0x050 << 2))
//`define AO_SEC_REG1 8'h51
#define AO_IR_BLASTER_ADDR0 (0xff800000 + (0x053 << 2))
#define SEC_AO_IR_BLASTER_ADDR0 (0xff800000 + (0x053 << 2))
#define P_AO_IR_BLASTER_ADDR0 (volatile uint32_t *)(0xff800000 + (0x053 << 2))
#define AO_IR_BLASTER_ADDR1 (0xff800000 + (0x054 << 2))
#define SEC_AO_IR_BLASTER_ADDR1 (0xff800000 + (0x054 << 2))
#define P_AO_IR_BLASTER_ADDR1 (volatile uint32_t *)(0xff800000 + (0x054 << 2))
#define AO_IR_BLASTER_ADDR2 (0xff800000 + (0x055 << 2))
#define SEC_AO_IR_BLASTER_ADDR2 (0xff800000 + (0x055 << 2))
#define P_AO_IR_BLASTER_ADDR2 (volatile uint32_t *)(0xff800000 + (0x055 << 2))
#define AO_IR_BLASTER_ADDR3 (0xff800000 + (0x056 << 2))
#define SEC_AO_IR_BLASTER_ADDR3 (0xff800000 + (0x056 << 2))
#define P_AO_IR_BLASTER_ADDR3 (volatile uint32_t *)(0xff800000 + (0x056 << 2))
#define AO_SEC_TMODE_PWD0 (0xff800000 + (0x058 << 2))
#define SEC_AO_SEC_TMODE_PWD0 (0xff800000 + (0x058 << 2))
#define P_AO_SEC_TMODE_PWD0 (volatile uint32_t *)(0xff800000 + (0x058 << 2))
#define AO_SEC_TMODE_PWD1 (0xff800000 + (0x059 << 2))
#define SEC_AO_SEC_TMODE_PWD1 (0xff800000 + (0x059 << 2))
#define P_AO_SEC_TMODE_PWD1 (volatile uint32_t *)(0xff800000 + (0x059 << 2))
#define AO_SEC_TMODE_PWD2 (0xff800000 + (0x05a << 2))
#define SEC_AO_SEC_TMODE_PWD2 (0xff800000 + (0x05a << 2))
#define P_AO_SEC_TMODE_PWD2 (volatile uint32_t *)(0xff800000 + (0x05a << 2))
#define AO_SEC_TMODE_PWD3 (0xff800000 + (0x05b << 2))
#define SEC_AO_SEC_TMODE_PWD3 (0xff800000 + (0x05b << 2))
#define P_AO_SEC_TMODE_PWD3 (volatile uint32_t *)(0xff800000 + (0x05b << 2))
#define AO_WRITE_ONCE0 (0xff800000 + (0x05c << 2))
#define SEC_AO_WRITE_ONCE0 (0xff800000 + (0x05c << 2))
#define P_AO_WRITE_ONCE0 (volatile uint32_t *)(0xff800000 + (0x05c << 2))
#define AO_WRITE_ONCE1 (0xff800000 + (0x05d << 2))
#define SEC_AO_WRITE_ONCE1 (0xff800000 + (0x05d << 2))
#define P_AO_WRITE_ONCE1 (volatile uint32_t *)(0xff800000 + (0x05d << 2))
#define AO_WRITE_ONCE2 (0xff800000 + (0x05e << 2))
#define SEC_AO_WRITE_ONCE2 (0xff800000 + (0x05e << 2))
#define P_AO_WRITE_ONCE2 (volatile uint32_t *)(0xff800000 + (0x05e << 2))
#define AO_SEC_SCRATCH (0xff800000 + (0x05f << 2))
#define SEC_AO_SEC_SCRATCH (0xff800000 + (0x05f << 2))
#define P_AO_SEC_SCRATCH (volatile uint32_t *)(0xff800000 + (0x05f << 2))
#define AO_MSG_INDEX0 (0xff800000 + (0x060 << 2))
#define SEC_AO_MSG_INDEX0 (0xff800000 + (0x060 << 2))
#define P_AO_MSG_INDEX0 (volatile uint32_t *)(0xff800000 + (0x060 << 2))
#define AO_MSG_INDEX1 (0xff800000 + (0x061 << 2))
#define SEC_AO_MSG_INDEX1 (0xff800000 + (0x061 << 2))
#define P_AO_MSG_INDEX1 (volatile uint32_t *)(0xff800000 + (0x061 << 2))
#define AO_MSG_INDEX2 (0xff800000 + (0x062 << 2))
#define SEC_AO_MSG_INDEX2 (0xff800000 + (0x062 << 2))
#define P_AO_MSG_INDEX2 (volatile uint32_t *)(0xff800000 + (0x062 << 2))
#define AO_MSG_INDEX3 (0xff800000 + (0x063 << 2))
#define SEC_AO_MSG_INDEX3 (0xff800000 + (0x063 << 2))
#define P_AO_MSG_INDEX3 (volatile uint32_t *)(0xff800000 + (0x063 << 2))
#define AO_SEC_SHARED_AHB_SRAM_MASK_0 (0xff800000 + (0x066 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_MASK_0 (0xff800000 + (0x066 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_MASK_0 (volatile uint32_t *)(0xff800000 + (0x066 << 2))
#define AO_SEC_SHARED_AHB_SRAM_MASK_1 (0xff800000 + (0x067 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_MASK_1 (0xff800000 + (0x067 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_MASK_1 (volatile uint32_t *)(0xff800000 + (0x067 << 2))
#define AO_SEC_SHARED_AHB_SRAM_MASK_2 (0xff800000 + (0x068 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_MASK_2 (0xff800000 + (0x068 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_MASK_2 (volatile uint32_t *)(0xff800000 + (0x068 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG0_0 (0xff800000 + (0x069 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG0_0 (0xff800000 + (0x069 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG0_0 (volatile uint32_t *)(0xff800000 + (0x069 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG0_1 (0xff800000 + (0x06a << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG0_1 (0xff800000 + (0x06a << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG0_1 (volatile uint32_t *)(0xff800000 + (0x06a << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG0_2 (0xff800000 + (0x06b << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG0_2 (0xff800000 + (0x06b << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG0_2 (volatile uint32_t *)(0xff800000 + (0x06b << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG1_0 (0xff800000 + (0x06c << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG1_0 (0xff800000 + (0x06c << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG1_0 (volatile uint32_t *)(0xff800000 + (0x06c << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG1_1 (0xff800000 + (0x06d << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG1_1 (0xff800000 + (0x06d << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG1_1 (volatile uint32_t *)(0xff800000 + (0x06d << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG1_2 (0xff800000 + (0x06e << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG1_2 (0xff800000 + (0x06e << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG1_2 (volatile uint32_t *)(0xff800000 + (0x06e << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG2_0 (0xff800000 + (0x06f << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG2_0 (0xff800000 + (0x06f << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG2_0 (volatile uint32_t *)(0xff800000 + (0x06f << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG2_1 (0xff800000 + (0x070 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG2_1 (0xff800000 + (0x070 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG2_1 (volatile uint32_t *)(0xff800000 + (0x070 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG2_2 (0xff800000 + (0x071 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG2_2 (0xff800000 + (0x071 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG2_2 (volatile uint32_t *)(0xff800000 + (0x071 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG3_0 (0xff800000 + (0x072 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG3_0 (0xff800000 + (0x072 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG3_0 (volatile uint32_t *)(0xff800000 + (0x072 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG3_1 (0xff800000 + (0x073 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG3_1 (0xff800000 + (0x073 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG3_1 (volatile uint32_t *)(0xff800000 + (0x073 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG3_2 (0xff800000 + (0x074 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG3_2 (0xff800000 + (0x074 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG3_2 (volatile uint32_t *)(0xff800000 + (0x074 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG4_0 (0xff800000 + (0x075 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG4_0 (0xff800000 + (0x075 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG4_0 (volatile uint32_t *)(0xff800000 + (0x075 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG4_1 (0xff800000 + (0x076 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG4_1 (0xff800000 + (0x076 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG4_1 (volatile uint32_t *)(0xff800000 + (0x076 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG4_2 (0xff800000 + (0x077 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG4_2 (0xff800000 + (0x077 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG4_2 (volatile uint32_t *)(0xff800000 + (0x077 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG5_0 (0xff800000 + (0x078 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG5_0 (0xff800000 + (0x078 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG5_0 (volatile uint32_t *)(0xff800000 + (0x078 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG5_1 (0xff800000 + (0x079 << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG5_1 (0xff800000 + (0x079 << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG5_1 (volatile uint32_t *)(0xff800000 + (0x079 << 2))
#define AO_SEC_SHARED_AHB_SRAM_REG5_2 (0xff800000 + (0x07a << 2))
#define SEC_AO_SEC_SHARED_AHB_SRAM_REG5_2 (0xff800000 + (0x07a << 2))
#define P_AO_SEC_SHARED_AHB_SRAM_REG5_2 (volatile uint32_t *)(0xff800000 + (0x07a << 2))
#define AO_SEC_AO_CPU_SRAM_REG0_0 (0xff800000 + (0x07c << 2))
#define SEC_AO_SEC_AO_CPU_SRAM_REG0_0 (0xff800000 + (0x07c << 2))
#define P_AO_SEC_AO_CPU_SRAM_REG0_0 (volatile uint32_t *)(0xff800000 + (0x07c << 2))
#define AO_SEC_AO_CPU_SRAM_REG0_1 (0xff800000 + (0x07d << 2))
#define SEC_AO_SEC_AO_CPU_SRAM_REG0_1 (0xff800000 + (0x07d << 2))
#define P_AO_SEC_AO_CPU_SRAM_REG0_1 (volatile uint32_t *)(0xff800000 + (0x07d << 2))
#define AO_SEC_AO_CPU_SRAM_REG1_0 (0xff800000 + (0x07e << 2))
#define SEC_AO_SEC_AO_CPU_SRAM_REG1_0 (0xff800000 + (0x07e << 2))
#define P_AO_SEC_AO_CPU_SRAM_REG1_0 (volatile uint32_t *)(0xff800000 + (0x07e << 2))
#define AO_SEC_AO_CPU_SRAM_REG1_1 (0xff800000 + (0x07f << 2))
#define SEC_AO_SEC_AO_CPU_SRAM_REG1_1 (0xff800000 + (0x07f << 2))
#define P_AO_SEC_AO_CPU_SRAM_REG1_1 (volatile uint32_t *)(0xff800000 + (0x07f << 2))
#define AO_SEC_SD_CFG0 (0xff800000 + (0x080 << 2))
#define SEC_AO_SEC_SD_CFG0 (0xff800000 + (0x080 << 2))
#define P_AO_SEC_SD_CFG0 (volatile uint32_t *)(0xff800000 + (0x080 << 2))
#define AO_SEC_SD_CFG1 (0xff800000 + (0x081 << 2))
#define SEC_AO_SEC_SD_CFG1 (0xff800000 + (0x081 << 2))
#define P_AO_SEC_SD_CFG1 (volatile uint32_t *)(0xff800000 + (0x081 << 2))
#define AO_SEC_SD_CFG2 (0xff800000 + (0x082 << 2))
#define SEC_AO_SEC_SD_CFG2 (0xff800000 + (0x082 << 2))
#define P_AO_SEC_SD_CFG2 (volatile uint32_t *)(0xff800000 + (0x082 << 2))
#define AO_SEC_SD_CFG3 (0xff800000 + (0x083 << 2))
#define SEC_AO_SEC_SD_CFG3 (0xff800000 + (0x083 << 2))
#define P_AO_SEC_SD_CFG3 (volatile uint32_t *)(0xff800000 + (0x083 << 2))
#define AO_SEC_SD_CFG4 (0xff800000 + (0x084 << 2))
#define SEC_AO_SEC_SD_CFG4 (0xff800000 + (0x084 << 2))
#define P_AO_SEC_SD_CFG4 (volatile uint32_t *)(0xff800000 + (0x084 << 2))
#define AO_SEC_SD_CFG5 (0xff800000 + (0x085 << 2))
#define SEC_AO_SEC_SD_CFG5 (0xff800000 + (0x085 << 2))
#define P_AO_SEC_SD_CFG5 (volatile uint32_t *)(0xff800000 + (0x085 << 2))
#define AO_SEC_SD_CFG6 (0xff800000 + (0x086 << 2))
#define SEC_AO_SEC_SD_CFG6 (0xff800000 + (0x086 << 2))
#define P_AO_SEC_SD_CFG6 (volatile uint32_t *)(0xff800000 + (0x086 << 2))
#define AO_SEC_SD_CFG7 (0xff800000 + (0x087 << 2))
#define SEC_AO_SEC_SD_CFG7 (0xff800000 + (0x087 << 2))
#define P_AO_SEC_SD_CFG7 (volatile uint32_t *)(0xff800000 + (0x087 << 2))
#define AO_SEC_SD_CFG8 (0xff800000 + (0x088 << 2))
#define SEC_AO_SEC_SD_CFG8 (0xff800000 + (0x088 << 2))
#define P_AO_SEC_SD_CFG8 (volatile uint32_t *)(0xff800000 + (0x088 << 2))
#define AO_SEC_SD_CFG9 (0xff800000 + (0x089 << 2))
#define SEC_AO_SEC_SD_CFG9 (0xff800000 + (0x089 << 2))
#define P_AO_SEC_SD_CFG9 (volatile uint32_t *)(0xff800000 + (0x089 << 2))
#define AO_SEC_SD_CFG10 (0xff800000 + (0x08a << 2))
#define SEC_AO_SEC_SD_CFG10 (0xff800000 + (0x08a << 2))
#define P_AO_SEC_SD_CFG10 (volatile uint32_t *)(0xff800000 + (0x08a << 2))
#define AO_SEC_SD_CFG11 (0xff800000 + (0x08b << 2))
#define SEC_AO_SEC_SD_CFG11 (0xff800000 + (0x08b << 2))
#define P_AO_SEC_SD_CFG11 (volatile uint32_t *)(0xff800000 + (0x08b << 2))
#define AO_SEC_SD_CFG12 (0xff800000 + (0x08c << 2))
#define SEC_AO_SEC_SD_CFG12 (0xff800000 + (0x08c << 2))
#define P_AO_SEC_SD_CFG12 (volatile uint32_t *)(0xff800000 + (0x08c << 2))
#define AO_SEC_SD_CFG13 (0xff800000 + (0x08d << 2))
#define SEC_AO_SEC_SD_CFG13 (0xff800000 + (0x08d << 2))
#define P_AO_SEC_SD_CFG13 (volatile uint32_t *)(0xff800000 + (0x08d << 2))
#define AO_SEC_SD_CFG14 (0xff800000 + (0x08e << 2))
#define SEC_AO_SEC_SD_CFG14 (0xff800000 + (0x08e << 2))
#define P_AO_SEC_SD_CFG14 (volatile uint32_t *)(0xff800000 + (0x08e << 2))
#define AO_SEC_SD_CFG15 (0xff800000 + (0x08f << 2))
#define SEC_AO_SEC_SD_CFG15 (0xff800000 + (0x08f << 2))
#define P_AO_SEC_SD_CFG15 (volatile uint32_t *)(0xff800000 + (0x08f << 2))
#define AO_SEC_GP_CFG0 (0xff800000 + (0x090 << 2))
#define SEC_AO_SEC_GP_CFG0 (0xff800000 + (0x090 << 2))
#define P_AO_SEC_GP_CFG0 (volatile uint32_t *)(0xff800000 + (0x090 << 2))
#define AO_SEC_GP_CFG1 (0xff800000 + (0x091 << 2))
#define SEC_AO_SEC_GP_CFG1 (0xff800000 + (0x091 << 2))
#define P_AO_SEC_GP_CFG1 (volatile uint32_t *)(0xff800000 + (0x091 << 2))
#define AO_SEC_GP_CFG2 (0xff800000 + (0x092 << 2))
#define SEC_AO_SEC_GP_CFG2 (0xff800000 + (0x092 << 2))
#define P_AO_SEC_GP_CFG2 (volatile uint32_t *)(0xff800000 + (0x092 << 2))
#define AO_SEC_GP_CFG3 (0xff800000 + (0x093 << 2))
#define SEC_AO_SEC_GP_CFG3 (0xff800000 + (0x093 << 2))
#define P_AO_SEC_GP_CFG3 (volatile uint32_t *)(0xff800000 + (0x093 << 2))
#define AO_SEC_GP_CFG4 (0xff800000 + (0x094 << 2))
#define SEC_AO_SEC_GP_CFG4 (0xff800000 + (0x094 << 2))
#define P_AO_SEC_GP_CFG4 (volatile uint32_t *)(0xff800000 + (0x094 << 2))
#define AO_SEC_GP_CFG5 (0xff800000 + (0x095 << 2))
#define SEC_AO_SEC_GP_CFG5 (0xff800000 + (0x095 << 2))
#define P_AO_SEC_GP_CFG5 (volatile uint32_t *)(0xff800000 + (0x095 << 2))
#define AO_SEC_GP_CFG6 (0xff800000 + (0x096 << 2))
#define SEC_AO_SEC_GP_CFG6 (0xff800000 + (0x096 << 2))
#define P_AO_SEC_GP_CFG6 (volatile uint32_t *)(0xff800000 + (0x096 << 2))
#define AO_SEC_GP_CFG7 (0xff800000 + (0x097 << 2))
#define SEC_AO_SEC_GP_CFG7 (0xff800000 + (0x097 << 2))
#define P_AO_SEC_GP_CFG7 (volatile uint32_t *)(0xff800000 + (0x097 << 2))
#define AO_SEC_GP_CFG8 (0xff800000 + (0x098 << 2))
#define SEC_AO_SEC_GP_CFG8 (0xff800000 + (0x098 << 2))
#define P_AO_SEC_GP_CFG8 (volatile uint32_t *)(0xff800000 + (0x098 << 2))
#define AO_SEC_GP_CFG9 (0xff800000 + (0x099 << 2))
#define SEC_AO_SEC_GP_CFG9 (0xff800000 + (0x099 << 2))
#define P_AO_SEC_GP_CFG9 (volatile uint32_t *)(0xff800000 + (0x099 << 2))
#define AO_SEC_GP_CFG10 (0xff800000 + (0x09a << 2))
#define SEC_AO_SEC_GP_CFG10 (0xff800000 + (0x09a << 2))
#define P_AO_SEC_GP_CFG10 (volatile uint32_t *)(0xff800000 + (0x09a << 2))
#define AO_SEC_GP_CFG11 (0xff800000 + (0x09b << 2))
#define SEC_AO_SEC_GP_CFG11 (0xff800000 + (0x09b << 2))
#define P_AO_SEC_GP_CFG11 (volatile uint32_t *)(0xff800000 + (0x09b << 2))
#define AO_SEC_GP_CFG12 (0xff800000 + (0x09c << 2))
#define SEC_AO_SEC_GP_CFG12 (0xff800000 + (0x09c << 2))
#define P_AO_SEC_GP_CFG12 (volatile uint32_t *)(0xff800000 + (0x09c << 2))
#define AO_SEC_GP_CFG13 (0xff800000 + (0x09d << 2))
#define SEC_AO_SEC_GP_CFG13 (0xff800000 + (0x09d << 2))
#define P_AO_SEC_GP_CFG13 (volatile uint32_t *)(0xff800000 + (0x09d << 2))
#define AO_SEC_GP_CFG14 (0xff800000 + (0x09e << 2))
#define SEC_AO_SEC_GP_CFG14 (0xff800000 + (0x09e << 2))
#define P_AO_SEC_GP_CFG14 (volatile uint32_t *)(0xff800000 + (0x09e << 2))
#define AO_SEC_GP_CFG15 (0xff800000 + (0x09f << 2))
#define SEC_AO_SEC_GP_CFG15 (0xff800000 + (0x09f << 2))
#define P_AO_SEC_GP_CFG15 (volatile uint32_t *)(0xff800000 + (0x09f << 2))
#define AO_CECB_CLK_CNTL_REG0 (0xff800000 + (0x0a0 << 2))
#define SEC_AO_CECB_CLK_CNTL_REG0 (0xff800000 + (0x0a0 << 2))
#define P_AO_CECB_CLK_CNTL_REG0 (volatile uint32_t *)(0xff800000 + (0x0a0 << 2))
#define AO_CECB_CLK_CNTL_REG1 (0xff800000 + (0x0a1 << 2))
#define SEC_AO_CECB_CLK_CNTL_REG1 (0xff800000 + (0x0a1 << 2))
#define P_AO_CECB_CLK_CNTL_REG1 (volatile uint32_t *)(0xff800000 + (0x0a1 << 2))
#define AO_CECB_GEN_CNTL (0xff800000 + (0x0a2 << 2))
#define SEC_AO_CECB_GEN_CNTL (0xff800000 + (0x0a2 << 2))
#define P_AO_CECB_GEN_CNTL (volatile uint32_t *)(0xff800000 + (0x0a2 << 2))
#define AO_CECB_RW_REG (0xff800000 + (0x0a3 << 2))
#define SEC_AO_CECB_RW_REG (0xff800000 + (0x0a3 << 2))
#define P_AO_CECB_RW_REG (volatile uint32_t *)(0xff800000 + (0x0a3 << 2))
#define AO_CECB_INTR_MASKN (0xff800000 + (0x0a4 << 2))
#define SEC_AO_CECB_INTR_MASKN (0xff800000 + (0x0a4 << 2))
#define P_AO_CECB_INTR_MASKN (volatile uint32_t *)(0xff800000 + (0x0a4 << 2))
#define AO_CECB_INTR_CLR (0xff800000 + (0x0a5 << 2))
#define SEC_AO_CECB_INTR_CLR (0xff800000 + (0x0a5 << 2))
#define P_AO_CECB_INTR_CLR (volatile uint32_t *)(0xff800000 + (0x0a5 << 2))
#define AO_CECB_INTR_STAT (0xff800000 + (0x0a6 << 2))
#define SEC_AO_CECB_INTR_STAT (0xff800000 + (0x0a6 << 2))
#define P_AO_CECB_INTR_STAT (volatile uint32_t *)(0xff800000 + (0x0a6 << 2))
#define AO_SEC_M4_CPU_SRAM_REG0_0 (0xff800000 + (0x0a7 << 2))
#define SEC_AO_SEC_M4_CPU_SRAM_REG0_0 (0xff800000 + (0x0a7 << 2))
#define P_AO_SEC_M4_CPU_SRAM_REG0_0 (volatile uint32_t *)(0xff800000 + (0x0a7 << 2))
#define AO_SEC_M4_CPU_SRAM_REG0_1 (0xff800000 + (0x0a8 << 2))
#define SEC_AO_SEC_M4_CPU_SRAM_REG0_1 (0xff800000 + (0x0a8 << 2))
#define P_AO_SEC_M4_CPU_SRAM_REG0_1 (volatile uint32_t *)(0xff800000 + (0x0a8 << 2))
#define AO_SEC_M4_CPU_SRAM_REG1_0 (0xff800000 + (0x0a9 << 2))
#define SEC_AO_SEC_M4_CPU_SRAM_REG1_0 (0xff800000 + (0x0a9 << 2))
#define P_AO_SEC_M4_CPU_SRAM_REG1_0 (volatile uint32_t *)(0xff800000 + (0x0a9 << 2))
#define AO_SEC_M4_CPU_SRAM_REG1_1 (0xff800000 + (0x0aa << 2))
#define SEC_AO_SEC_M4_CPU_SRAM_REG1_1 (0xff800000 + (0x0aa << 2))
#define P_AO_SEC_M4_CPU_SRAM_REG1_1 (volatile uint32_t *)(0xff800000 + (0x0aa << 2))
#define AO_SEC_M4_CPU_SRAM_REG2_0 (0xff800000 + (0x0ab << 2))
#define SEC_AO_SEC_M4_CPU_SRAM_REG2_0 (0xff800000 + (0x0ab << 2))
#define P_AO_SEC_M4_CPU_SRAM_REG2_0 (volatile uint32_t *)(0xff800000 + (0x0ab << 2))
//`define AO_RTC_ADDR0 8'h70 //TODO: DEFINE IF WE'RE IMPLEMENTING AO_RTC
//`define AO_RTC_ADDR1 8'h71 //TODO: DEFINE IF WE'RE IMPLEMENTING AO_RTC
//`define AO_RTC_ADDR2 8'h72 //TODO: DEFINE IF WE'RE IMPLEMENTING AO_RTC
//`define AO_RTC_ADDR3 8'h73 //TODO: DEFINE IF WE'RE IMPLEMENTING AO_RTC
//`define AO_RTC_ADDR4 8'h74 //TODO: DEFINE IF WE'RE IMPLEMENTING AO_RTC
#define AO_SEC_JTAG_SP_CTRL (0xff800000 + (0x0ac << 2))
#define SEC_AO_SEC_JTAG_SP_CTRL (0xff800000 + (0x0ac << 2))
#define P_AO_SEC_JTAG_SP_CTRL (volatile uint32_t *)(0xff800000 + (0x0ac << 2))
#define AO_SEC_JTAG_PWD_SP_0 (0xff800000 + (0x0ad << 2))
#define SEC_AO_SEC_JTAG_PWD_SP_0 (0xff800000 + (0x0ad << 2))
#define P_AO_SEC_JTAG_PWD_SP_0 (volatile uint32_t *)(0xff800000 + (0x0ad << 2))
#define AO_SEC_JTAG_PWD_SP_1 (0xff800000 + (0x0ae << 2))
#define SEC_AO_SEC_JTAG_PWD_SP_1 (0xff800000 + (0x0ae << 2))
#define P_AO_SEC_JTAG_PWD_SP_1 (volatile uint32_t *)(0xff800000 + (0x0ae << 2))
#define AO_SEC_JTAG_PWD_SP_2 (0xff800000 + (0x0af << 2))
#define SEC_AO_SEC_JTAG_PWD_SP_2 (0xff800000 + (0x0af << 2))
#define P_AO_SEC_JTAG_PWD_SP_2 (volatile uint32_t *)(0xff800000 + (0x0af << 2))
#define AO_SEC_JTAG_PWD_SP_3 (0xff800000 + (0x0b0 << 2))
#define SEC_AO_SEC_JTAG_PWD_SP_3 (0xff800000 + (0x0b0 << 2))
#define P_AO_SEC_JTAG_PWD_SP_3 (volatile uint32_t *)(0xff800000 + (0x0b0 << 2))
#define AO_SEC_JTAG_PWD_SP_CNTL (0xff800000 + (0x0b1 << 2))
#define SEC_AO_SEC_JTAG_PWD_SP_CNTL (0xff800000 + (0x0b1 << 2))
#define P_AO_SEC_JTAG_PWD_SP_CNTL (volatile uint32_t *)(0xff800000 + (0x0b1 << 2))
#define AO_SEC_JTAG_PWD_SP_ADDR0 (0xff800000 + (0x0b2 << 2))
#define SEC_AO_SEC_JTAG_PWD_SP_ADDR0 (0xff800000 + (0x0b2 << 2))
#define P_AO_SEC_JTAG_PWD_SP_ADDR0 (volatile uint32_t *)(0xff800000 + (0x0b2 << 2))
#define AO_SEC_JTAG_PWD_SP_ADDR1 (0xff800000 + (0x0b3 << 2))
#define SEC_AO_SEC_JTAG_PWD_SP_ADDR1 (0xff800000 + (0x0b3 << 2))
#define P_AO_SEC_JTAG_PWD_SP_ADDR1 (volatile uint32_t *)(0xff800000 + (0x0b3 << 2))
#define AO_SEC_JTAG_PWD_SP_ADDR2 (0xff800000 + (0x0b4 << 2))
#define SEC_AO_SEC_JTAG_PWD_SP_ADDR2 (0xff800000 + (0x0b4 << 2))
#define P_AO_SEC_JTAG_PWD_SP_ADDR2 (volatile uint32_t *)(0xff800000 + (0x0b4 << 2))
#define AO_SEC_JTAG_PWD_SP_ADDR3 (0xff800000 + (0x0b5 << 2))
#define SEC_AO_SEC_JTAG_PWD_SP_ADDR3 (0xff800000 + (0x0b5 << 2))
#define P_AO_SEC_JTAG_PWD_SP_ADDR3 (volatile uint32_t *)(0xff800000 + (0x0b5 << 2))
#define AO_SEC_JTAG_SCP_CTRL (0xff800000 + (0x0b6 << 2))
#define SEC_AO_SEC_JTAG_SCP_CTRL (0xff800000 + (0x0b6 << 2))
#define P_AO_SEC_JTAG_SCP_CTRL (volatile uint32_t *)(0xff800000 + (0x0b6 << 2))
#define AO_SEC_JTAG_PWD_SCP_0 (0xff800000 + (0x0b7 << 2))
#define SEC_AO_SEC_JTAG_PWD_SCP_0 (0xff800000 + (0x0b7 << 2))
#define P_AO_SEC_JTAG_PWD_SCP_0 (volatile uint32_t *)(0xff800000 + (0x0b7 << 2))
#define AO_SEC_JTAG_PWD_SCP_1 (0xff800000 + (0x0b8 << 2))
#define SEC_AO_SEC_JTAG_PWD_SCP_1 (0xff800000 + (0x0b8 << 2))
#define P_AO_SEC_JTAG_PWD_SCP_1 (volatile uint32_t *)(0xff800000 + (0x0b8 << 2))
#define AO_SEC_JTAG_PWD_SCP_2 (0xff800000 + (0x0b9 << 2))
#define SEC_AO_SEC_JTAG_PWD_SCP_2 (0xff800000 + (0x0b9 << 2))
#define P_AO_SEC_JTAG_PWD_SCP_2 (volatile uint32_t *)(0xff800000 + (0x0b9 << 2))
#define AO_SEC_JTAG_PWD_SCP_3 (0xff800000 + (0x0ba << 2))
#define SEC_AO_SEC_JTAG_PWD_SCP_3 (0xff800000 + (0x0ba << 2))
#define P_AO_SEC_JTAG_PWD_SCP_3 (volatile uint32_t *)(0xff800000 + (0x0ba << 2))
#define AO_SEC_JTAG_PWD_SCP_CNTL (0xff800000 + (0x0bb << 2))
#define SEC_AO_SEC_JTAG_PWD_SCP_CNTL (0xff800000 + (0x0bb << 2))
#define P_AO_SEC_JTAG_PWD_SCP_CNTL (volatile uint32_t *)(0xff800000 + (0x0bb << 2))
#define AO_SEC_JTAG_PWD_SCP_ADDR0 (0xff800000 + (0x0bc << 2))
#define SEC_AO_SEC_JTAG_PWD_SCP_ADDR0 (0xff800000 + (0x0bc << 2))
#define P_AO_SEC_JTAG_PWD_SCP_ADDR0 (volatile uint32_t *)(0xff800000 + (0x0bc << 2))
#define AO_SEC_JTAG_PWD_SCP_ADDR1 (0xff800000 + (0x0bd << 2))
#define SEC_AO_SEC_JTAG_PWD_SCP_ADDR1 (0xff800000 + (0x0bd << 2))
#define P_AO_SEC_JTAG_PWD_SCP_ADDR1 (volatile uint32_t *)(0xff800000 + (0x0bd << 2))
#define AO_SEC_JTAG_PWD_SCP_ADDR2 (0xff800000 + (0x0be << 2))
#define SEC_AO_SEC_JTAG_PWD_SCP_ADDR2 (0xff800000 + (0x0be << 2))
#define P_AO_SEC_JTAG_PWD_SCP_ADDR2 (volatile uint32_t *)(0xff800000 + (0x0be << 2))
#define AO_SEC_JTAG_PWD_SCP_ADDR3 (0xff800000 + (0x0bf << 2))
#define SEC_AO_SEC_JTAG_PWD_SCP_ADDR3 (0xff800000 + (0x0bf << 2))
#define P_AO_SEC_JTAG_PWD_SCP_ADDR3 (volatile uint32_t *)(0xff800000 + (0x0bf << 2))
#define M4_CPU_CNTL (0xff800000 + (0x0c0 << 2))
#define SEC_M4_CPU_CNTL (0xff800000 + (0x0c0 << 2))
#define P_M4_CPU_CNTL (volatile uint32_t *)(0xff800000 + (0x0c0 << 2))
#define M4_CPU_CNTL_NS (0xff800000 + (0x0c1 << 2))
#define SEC_M4_CPU_CNTL_NS (0xff800000 + (0x0c1 << 2))
#define P_M4_CPU_CNTL_NS (volatile uint32_t *)(0xff800000 + (0x0c1 << 2))
#define M4_CPU_CNTL2 (0xff800000 + (0x0c2 << 2))
#define SEC_M4_CPU_CNTL2 (0xff800000 + (0x0c2 << 2))
#define P_M4_CPU_CNTL2 (volatile uint32_t *)(0xff800000 + (0x0c2 << 2))
#define M4_CPU_CNTL3 (0xff800000 + (0x0c3 << 2))
#define SEC_M4_CPU_CNTL3 (0xff800000 + (0x0c3 << 2))
#define P_M4_CPU_CNTL3 (volatile uint32_t *)(0xff800000 + (0x0c3 << 2))
#define M4_CPU_CNTL4 (0xff800000 + (0x0c4 << 2))
#define SEC_M4_CPU_CNTL4 (0xff800000 + (0x0c4 << 2))
#define P_M4_CPU_CNTL4 (volatile uint32_t *)(0xff800000 + (0x0c4 << 2))
#define M4_CPU_CNTL5 (0xff800000 + (0x0c5 << 2))
#define SEC_M4_CPU_CNTL5 (0xff800000 + (0x0c5 << 2))
#define P_M4_CPU_CNTL5 (volatile uint32_t *)(0xff800000 + (0x0c5 << 2))
#define M4_CPU_TIMESTAMP (0xff800000 + (0x0c6 << 2))
#define SEC_M4_CPU_TIMESTAMP (0xff800000 + (0x0c6 << 2))
#define P_M4_CPU_TIMESTAMP (volatile uint32_t *)(0xff800000 + (0x0c6 << 2))
#define M4_CPU_TIMESTAMP2 (0xff800000 + (0x0c7 << 2))
#define SEC_M4_CPU_TIMESTAMP2 (0xff800000 + (0x0c7 << 2))
#define P_M4_CPU_TIMESTAMP2 (volatile uint32_t *)(0xff800000 + (0x0c7 << 2))
#define M4_CPU_STAT1 (0xff800000 + (0x0c8 << 2))
#define SEC_M4_CPU_STAT1 (0xff800000 + (0x0c8 << 2))
#define P_M4_CPU_STAT1 (volatile uint32_t *)(0xff800000 + (0x0c8 << 2))
#define M4_CPU_STAT2 (0xff800000 + (0x0c9 << 2))
#define SEC_M4_CPU_STAT2 (0xff800000 + (0x0c9 << 2))
#define P_M4_CPU_STAT2 (volatile uint32_t *)(0xff800000 + (0x0c9 << 2))
#define AO_CEC_STICKY_DATA0 (0xff800000 + (0x0ca << 2))
#define SEC_AO_CEC_STICKY_DATA0 (0xff800000 + (0x0ca << 2))
#define P_AO_CEC_STICKY_DATA0 (volatile uint32_t *)(0xff800000 + (0x0ca << 2))
#define AO_CEC_STICKY_DATA1 (0xff800000 + (0x0cb << 2))
#define SEC_AO_CEC_STICKY_DATA1 (0xff800000 + (0x0cb << 2))
#define P_AO_CEC_STICKY_DATA1 (volatile uint32_t *)(0xff800000 + (0x0cb << 2))
#define AO_CEC_STICKY_DATA2 (0xff800000 + (0x0cc << 2))
#define SEC_AO_CEC_STICKY_DATA2 (0xff800000 + (0x0cc << 2))
#define P_AO_CEC_STICKY_DATA2 (volatile uint32_t *)(0xff800000 + (0x0cc << 2))
#define AO_CEC_STICKY_DATA3 (0xff800000 + (0x0cd << 2))
#define SEC_AO_CEC_STICKY_DATA3 (0xff800000 + (0x0cd << 2))
#define P_AO_CEC_STICKY_DATA3 (volatile uint32_t *)(0xff800000 + (0x0cd << 2))
#define AO_CEC_STICKY_DATA4 (0xff800000 + (0x0ce << 2))
#define SEC_AO_CEC_STICKY_DATA4 (0xff800000 + (0x0ce << 2))
#define P_AO_CEC_STICKY_DATA4 (volatile uint32_t *)(0xff800000 + (0x0ce << 2))
#define AO_CEC_STICKY_DATA5 (0xff800000 + (0x0cf << 2))
#define SEC_AO_CEC_STICKY_DATA5 (0xff800000 + (0x0cf << 2))
#define P_AO_CEC_STICKY_DATA5 (volatile uint32_t *)(0xff800000 + (0x0cf << 2))
#define AO_CEC_STICKY_DATA6 (0xff800000 + (0x0d0 << 2))
#define SEC_AO_CEC_STICKY_DATA6 (0xff800000 + (0x0d0 << 2))
#define P_AO_CEC_STICKY_DATA6 (volatile uint32_t *)(0xff800000 + (0x0d0 << 2))
#define AO_CEC_STICKY_DATA7 (0xff800000 + (0x0d1 << 2))
#define SEC_AO_CEC_STICKY_DATA7 (0xff800000 + (0x0d1 << 2))
#define P_AO_CEC_STICKY_DATA7 (volatile uint32_t *)(0xff800000 + (0x0d1 << 2))
#define AO_SEC_SP_CFG0 (0xff800000 + (0x0e0 << 2))
#define SEC_AO_SEC_SP_CFG0 (0xff800000 + (0x0e0 << 2))
#define P_AO_SEC_SP_CFG0 (volatile uint32_t *)(0xff800000 + (0x0e0 << 2))
#define AO_SEC_SP_CFG1 (0xff800000 + (0x0e1 << 2))
#define SEC_AO_SEC_SP_CFG1 (0xff800000 + (0x0e1 << 2))
#define P_AO_SEC_SP_CFG1 (volatile uint32_t *)(0xff800000 + (0x0e1 << 2))
#define AO_SEC_SP_CFG2 (0xff800000 + (0x0e2 << 2))
#define SEC_AO_SEC_SP_CFG2 (0xff800000 + (0x0e2 << 2))
#define P_AO_SEC_SP_CFG2 (volatile uint32_t *)(0xff800000 + (0x0e2 << 2))
#define AO_SEC_SP_CFG3 (0xff800000 + (0x0e3 << 2))
#define SEC_AO_SEC_SP_CFG3 (0xff800000 + (0x0e3 << 2))
#define P_AO_SEC_SP_CFG3 (volatile uint32_t *)(0xff800000 + (0x0e3 << 2))
#define AO_SEC_SP_CFG4 (0xff800000 + (0x0e4 << 2))
#define SEC_AO_SEC_SP_CFG4 (0xff800000 + (0x0e4 << 2))
#define P_AO_SEC_SP_CFG4 (volatile uint32_t *)(0xff800000 + (0x0e4 << 2))
#define AO_SEC_SP_CFG5 (0xff800000 + (0x0e5 << 2))
#define SEC_AO_SEC_SP_CFG5 (0xff800000 + (0x0e5 << 2))
#define P_AO_SEC_SP_CFG5 (volatile uint32_t *)(0xff800000 + (0x0e5 << 2))
#define AO_SEC_SP_CFG6 (0xff800000 + (0x0e6 << 2))
#define SEC_AO_SEC_SP_CFG6 (0xff800000 + (0x0e6 << 2))
#define P_AO_SEC_SP_CFG6 (volatile uint32_t *)(0xff800000 + (0x0e6 << 2))
#define AO_SEC_SP_CFG7 (0xff800000 + (0x0e7 << 2))
#define SEC_AO_SEC_SP_CFG7 (0xff800000 + (0x0e7 << 2))
#define P_AO_SEC_SP_CFG7 (volatile uint32_t *)(0xff800000 + (0x0e7 << 2))
#define AO_SEC_SP_CFG8 (0xff800000 + (0x0e8 << 2))
#define SEC_AO_SEC_SP_CFG8 (0xff800000 + (0x0e8 << 2))
#define P_AO_SEC_SP_CFG8 (volatile uint32_t *)(0xff800000 + (0x0e8 << 2))
#define AO_SEC_SP_CFG9 (0xff800000 + (0x0e9 << 2))
#define SEC_AO_SEC_SP_CFG9 (0xff800000 + (0x0e9 << 2))
#define P_AO_SEC_SP_CFG9 (volatile uint32_t *)(0xff800000 + (0x0e9 << 2))
#define AO_SEC_SP_CFG10 (0xff800000 + (0x0ea << 2))
#define SEC_AO_SEC_SP_CFG10 (0xff800000 + (0x0ea << 2))
#define P_AO_SEC_SP_CFG10 (volatile uint32_t *)(0xff800000 + (0x0ea << 2))
#define AO_SEC_SP_CFG11 (0xff800000 + (0x0eb << 2))
#define SEC_AO_SEC_SP_CFG11 (0xff800000 + (0x0eb << 2))
#define P_AO_SEC_SP_CFG11 (volatile uint32_t *)(0xff800000 + (0x0eb << 2))
#define AO_SEC_SP_CFG12 (0xff800000 + (0x0ec << 2))
#define SEC_AO_SEC_SP_CFG12 (0xff800000 + (0x0ec << 2))
#define P_AO_SEC_SP_CFG12 (volatile uint32_t *)(0xff800000 + (0x0ec << 2))
#define AO_SEC_SP_CFG13 (0xff800000 + (0x0ed << 2))
#define SEC_AO_SEC_SP_CFG13 (0xff800000 + (0x0ed << 2))
#define P_AO_SEC_SP_CFG13 (volatile uint32_t *)(0xff800000 + (0x0ed << 2))
#define AO_SEC_SP_CFG14 (0xff800000 + (0x0ee << 2))
#define SEC_AO_SEC_SP_CFG14 (0xff800000 + (0x0ee << 2))
#define P_AO_SEC_SP_CFG14 (volatile uint32_t *)(0xff800000 + (0x0ee << 2))
#define AO_SEC_SP_CFG15 (0xff800000 + (0x0ef << 2))
#define SEC_AO_SEC_SP_CFG15 (0xff800000 + (0x0ef << 2))
#define P_AO_SEC_SP_CFG15 (volatile uint32_t *)(0xff800000 + (0x0ef << 2))
#define AO_TIMER_CTRL (0xff800000 + (0x0f0 << 2))
#define SEC_AO_TIMER_CTRL (0xff800000 + (0x0f0 << 2))
#define P_AO_TIMER_CTRL (volatile uint32_t *)(0xff800000 + (0x0f0 << 2))
#define AO_TIMER_SEC_SCP_CTRL (0xff800000 + (0x0f1 << 2))
#define SEC_AO_TIMER_SEC_SCP_CTRL (0xff800000 + (0x0f1 << 2))
#define P_AO_TIMER_SEC_SCP_CTRL (volatile uint32_t *)(0xff800000 + (0x0f1 << 2))
#define AO_TIMER_SEC_SP_CTRL (0xff800000 + (0x0f2 << 2))
#define SEC_AO_TIMER_SEC_SP_CTRL (0xff800000 + (0x0f2 << 2))
#define P_AO_TIMER_SEC_SP_CTRL (volatile uint32_t *)(0xff800000 + (0x0f2 << 2))
#define AO_TIMERA_REG (0xff800000 + (0x0f3 << 2))
#define SEC_AO_TIMERA_REG (0xff800000 + (0x0f3 << 2))
#define P_AO_TIMERA_REG (volatile uint32_t *)(0xff800000 + (0x0f3 << 2))
#define AO_TIMERA_CUR_REG (0xff800000 + (0x0f4 << 2))
#define SEC_AO_TIMERA_CUR_REG (0xff800000 + (0x0f4 << 2))
#define P_AO_TIMERA_CUR_REG (volatile uint32_t *)(0xff800000 + (0x0f4 << 2))
#define AO_TIMERB_REG (0xff800000 + (0x0f5 << 2))
#define SEC_AO_TIMERB_REG (0xff800000 + (0x0f5 << 2))
#define P_AO_TIMERB_REG (volatile uint32_t *)(0xff800000 + (0x0f5 << 2))
#define AO_TIMERB_CUR_REG (0xff800000 + (0x0f6 << 2))
#define SEC_AO_TIMERB_CUR_REG (0xff800000 + (0x0f6 << 2))
#define P_AO_TIMERB_CUR_REG (volatile uint32_t *)(0xff800000 + (0x0f6 << 2))
#define AO_TIMERC_REG (0xff800000 + (0x0f7 << 2))
#define SEC_AO_TIMERC_REG (0xff800000 + (0x0f7 << 2))
#define P_AO_TIMERC_REG (volatile uint32_t *)(0xff800000 + (0x0f7 << 2))
#define AO_TIMERC_CUR_REG (0xff800000 + (0x0f8 << 2))
#define SEC_AO_TIMERC_CUR_REG (0xff800000 + (0x0f8 << 2))
#define P_AO_TIMERC_CUR_REG (volatile uint32_t *)(0xff800000 + (0x0f8 << 2))
#define AO_TIMERE_REG (0xff800000 + (0x0f9 << 2))
#define SEC_AO_TIMERE_REG (0xff800000 + (0x0f9 << 2))
#define P_AO_TIMERE_REG (volatile uint32_t *)(0xff800000 + (0x0f9 << 2))
#define AO_TIMERE_HI_REG (0xff800000 + (0x0fa << 2))
#define SEC_AO_TIMERE_HI_REG (0xff800000 + (0x0fa << 2))
#define P_AO_TIMERE_HI_REG (volatile uint32_t *)(0xff800000 + (0x0fa << 2))
#define AO_TIMERF_REG (0xff800000 + (0x0fb << 2))
#define SEC_AO_TIMERF_REG (0xff800000 + (0x0fb << 2))
#define P_AO_TIMERF_REG (volatile uint32_t *)(0xff800000 + (0x0fb << 2))
#define AO_TIMERF_HI_REG (0xff800000 + (0x0fc << 2))
#define SEC_AO_TIMERF_HI_REG (0xff800000 + (0x0fc << 2))
#define P_AO_TIMERF_HI_REG (volatile uint32_t *)(0xff800000 + (0x0fc << 2))
#define AO_TIMERG_REG (0xff800000 + (0x0fd << 2))
#define SEC_AO_TIMERG_REG (0xff800000 + (0x0fd << 2))
#define P_AO_TIMERG_REG (volatile uint32_t *)(0xff800000 + (0x0fd << 2))
#define AO_TIMERG_HI_REG (0xff800000 + (0x0fe << 2))
#define SEC_AO_TIMERG_HI_REG (0xff800000 + (0x0fe << 2))
#define P_AO_TIMERG_HI_REG (volatile uint32_t *)(0xff800000 + (0x0fe << 2))
// ----------------------------
// PWM C-D
// ----------------------------
//#define AO_PWM_CD_REG_BASE 0x02
// APB4_DECODER_NON_SECURE_BASE 32'hFF802000
// APB4_DECODER_SECURE_BASE 32'hFF802000
#define AO_PWM_PWM_C (0xff802000 + (0x000 << 2))
#define SEC_AO_PWM_PWM_C (0xff802000 + (0x000 << 2))
#define P_AO_PWM_PWM_C (volatile uint32_t *)(0xff802000 + (0x000 << 2))
#define AO_PWM_PWM_D (0xff802000 + (0x001 << 2))
#define SEC_AO_PWM_PWM_D (0xff802000 + (0x001 << 2))
#define P_AO_PWM_PWM_D (volatile uint32_t *)(0xff802000 + (0x001 << 2))
#define AO_PWM_MISC_REG_CD (0xff802000 + (0x002 << 2))
#define SEC_AO_PWM_MISC_REG_CD (0xff802000 + (0x002 << 2))
#define P_AO_PWM_MISC_REG_CD (volatile uint32_t *)(0xff802000 + (0x002 << 2))
#define AO_PWM_DELTA_SIGMA_CD (0xff802000 + (0x003 << 2))
#define SEC_AO_PWM_DELTA_SIGMA_CD (0xff802000 + (0x003 << 2))
#define P_AO_PWM_DELTA_SIGMA_CD (volatile uint32_t *)(0xff802000 + (0x003 << 2))
#define AO_PWM_TIME_CD (0xff802000 + (0x004 << 2))
#define SEC_AO_PWM_TIME_CD (0xff802000 + (0x004 << 2))
#define P_AO_PWM_TIME_CD (volatile uint32_t *)(0xff802000 + (0x004 << 2))
#define AO_PWM_C2 (0xff802000 + (0x005 << 2))
#define SEC_AO_PWM_C2 (0xff802000 + (0x005 << 2))
#define P_AO_PWM_C2 (volatile uint32_t *)(0xff802000 + (0x005 << 2))
#define AO_PWM_D2 (0xff802000 + (0x006 << 2))
#define SEC_AO_PWM_D2 (0xff802000 + (0x006 << 2))
#define P_AO_PWM_D2 (volatile uint32_t *)(0xff802000 + (0x006 << 2))
#define AO_PWM_BLINK_CD (0xff802000 + (0x007 << 2))
#define SEC_AO_PWM_BLINK_CD (0xff802000 + (0x007 << 2))
#define P_AO_PWM_BLINK_CD (volatile uint32_t *)(0xff802000 + (0x007 << 2))
#define AO_PWM_LOCK_CD (0xff802000 + (0x008 << 2))
#define SEC_AO_PWM_LOCK_CD (0xff802000 + (0x008 << 2))
#define P_AO_PWM_LOCK_CD (volatile uint32_t *)(0xff802000 + (0x008 << 2))
// ----------------------------
// UART
// ----------------------------
//#define AO_UART_REG_BASE 0x03
// APB4_DECODER_NON_SECURE_BASE 32'hFF803000
// APB4_DECODER_SECURE_BASE 32'hFF803000
#define AO_UART_WFIFO (0xff803000 + (0x000 << 2))
#define SEC_AO_UART_WFIFO (0xff803000 + (0x000 << 2))
#define P_AO_UART_WFIFO (volatile uint32_t *)(0xff803000 + (0x000 << 2))
#define AO_UART_RFIFO (0xff803000 + (0x001 << 2))
#define SEC_AO_UART_RFIFO (0xff803000 + (0x001 << 2))
#define P_AO_UART_RFIFO (volatile uint32_t *)(0xff803000 + (0x001 << 2))
#define AO_UART_CONTROL (0xff803000 + (0x002 << 2))
#define SEC_AO_UART_CONTROL (0xff803000 + (0x002 << 2))
#define P_AO_UART_CONTROL (volatile uint32_t *)(0xff803000 + (0x002 << 2))
#define AO_UART_STATUS (0xff803000 + (0x003 << 2))
#define SEC_AO_UART_STATUS (0xff803000 + (0x003 << 2))
#define P_AO_UART_STATUS (volatile uint32_t *)(0xff803000 + (0x003 << 2))
#define AO_UART_MISC (0xff803000 + (0x004 << 2))
#define SEC_AO_UART_MISC (0xff803000 + (0x004 << 2))
#define P_AO_UART_MISC (volatile uint32_t *)(0xff803000 + (0x004 << 2))
#define AO_UART_REG5 (0xff803000 + (0x005 << 2))
#define SEC_AO_UART_REG5 (0xff803000 + (0x005 << 2))
#define P_AO_UART_REG5 (volatile uint32_t *)(0xff803000 + (0x005 << 2))
// ----------------------------
// UART2
// ----------------------------
//#define AO_UART2_REG_BASE 0x04
// APB4_DECODER_NON_SECURE_BASE 32'hFF804000
// APB4_DECODER_SECURE_BASE 32'hFF804000
#define AO_UART2_WFIFO (0xff804000 + (0x000 << 2))
#define SEC_AO_UART2_WFIFO (0xff804000 + (0x000 << 2))
#define P_AO_UART2_WFIFO (volatile uint32_t *)(0xff804000 + (0x000 << 2))
#define AO_UART2_RFIFO (0xff804000 + (0x001 << 2))
#define SEC_AO_UART2_RFIFO (0xff804000 + (0x001 << 2))
#define P_AO_UART2_RFIFO (volatile uint32_t *)(0xff804000 + (0x001 << 2))
#define AO_UART2_CONTROL (0xff804000 + (0x002 << 2))
#define SEC_AO_UART2_CONTROL (0xff804000 + (0x002 << 2))
#define P_AO_UART2_CONTROL (volatile uint32_t *)(0xff804000 + (0x002 << 2))
#define AO_UART2_STATUS (0xff804000 + (0x003 << 2))
#define SEC_AO_UART2_STATUS (0xff804000 + (0x003 << 2))
#define P_AO_UART2_STATUS (volatile uint32_t *)(0xff804000 + (0x003 << 2))
#define AO_UART2_MISC (0xff804000 + (0x004 << 2))
#define SEC_AO_UART2_MISC (0xff804000 + (0x004 << 2))
#define P_AO_UART2_MISC (volatile uint32_t *)(0xff804000 + (0x004 << 2))
#define AO_UART2_REG5 (0xff804000 + (0x005 << 2))
#define SEC_AO_UART2_REG5 (0xff804000 + (0x005 << 2))
#define P_AO_UART2_REG5 (volatile uint32_t *)(0xff804000 + (0x005 << 2))
// ----------------------------
// I2C Master (8)
// ----------------------------
//#define AO_I2C_M_REG_BASE 0x05
// APB4_DECODER_NON_SECURE_BASE 32'hFF805000
// APB4_DECODER_SECURE_BASE 32'hFF805000
#define AO_I2C_M_0_CONTROL_REG (0xff805000 + (0x000 << 2))
#define SEC_AO_I2C_M_0_CONTROL_REG (0xff805000 + (0x000 << 2))
#define P_AO_I2C_M_0_CONTROL_REG (volatile uint32_t *)(0xff805000 + (0x000 << 2))
#define AO_I2C_M_0_SLAVE_ADDR (0xff805000 + (0x001 << 2))
#define SEC_AO_I2C_M_0_SLAVE_ADDR (0xff805000 + (0x001 << 2))
#define P_AO_I2C_M_0_SLAVE_ADDR (volatile uint32_t *)(0xff805000 + (0x001 << 2))
#define AO_I2C_M_0_TOKEN_LIST0 (0xff805000 + (0x002 << 2))
#define SEC_AO_I2C_M_0_TOKEN_LIST0 (0xff805000 + (0x002 << 2))
#define P_AO_I2C_M_0_TOKEN_LIST0 (volatile uint32_t *)(0xff805000 + (0x002 << 2))
#define AO_I2C_M_0_TOKEN_LIST1 (0xff805000 + (0x003 << 2))
#define SEC_AO_I2C_M_0_TOKEN_LIST1 (0xff805000 + (0x003 << 2))
#define P_AO_I2C_M_0_TOKEN_LIST1 (volatile uint32_t *)(0xff805000 + (0x003 << 2))
#define AO_I2C_M_0_WDATA_REG0 (0xff805000 + (0x004 << 2))
#define SEC_AO_I2C_M_0_WDATA_REG0 (0xff805000 + (0x004 << 2))
#define P_AO_I2C_M_0_WDATA_REG0 (volatile uint32_t *)(0xff805000 + (0x004 << 2))
#define AO_I2C_M_0_WDATA_REG1 (0xff805000 + (0x005 << 2))
#define SEC_AO_I2C_M_0_WDATA_REG1 (0xff805000 + (0x005 << 2))
#define P_AO_I2C_M_0_WDATA_REG1 (volatile uint32_t *)(0xff805000 + (0x005 << 2))
#define AO_I2C_M_0_RDATA_REG0 (0xff805000 + (0x006 << 2))
#define SEC_AO_I2C_M_0_RDATA_REG0 (0xff805000 + (0x006 << 2))
#define P_AO_I2C_M_0_RDATA_REG0 (volatile uint32_t *)(0xff805000 + (0x006 << 2))
#define AO_I2C_M_0_RDATA_REG1 (0xff805000 + (0x007 << 2))
#define SEC_AO_I2C_M_0_RDATA_REG1 (0xff805000 + (0x007 << 2))
#define P_AO_I2C_M_0_RDATA_REG1 (volatile uint32_t *)(0xff805000 + (0x007 << 2))
#define AO_I2C_M_0_TIMEOUT_TH (0xff805000 + (0x008 << 2))
#define SEC_AO_I2C_M_0_TIMEOUT_TH (0xff805000 + (0x008 << 2))
#define P_AO_I2C_M_0_TIMEOUT_TH (volatile uint32_t *)(0xff805000 + (0x008 << 2))
// ----------------------------
// I2C Slave (3)
// ----------------------------
//#define AO_I2C_S_REG_BASE 0x06
// APB4_DECODER_NON_SECURE_BASE 32'hFF806000
// APB4_DECODER_SECURE_BASE 32'hFF806000
#define AO_I2C_S_CONTROL_REG (0xff806000 + (0x000 << 2))
#define SEC_AO_I2C_S_CONTROL_REG (0xff806000 + (0x000 << 2))
#define P_AO_I2C_S_CONTROL_REG (volatile uint32_t *)(0xff806000 + (0x000 << 2))
#define AO_I2C_S_SEND_REG (0xff806000 + (0x001 << 2))
#define SEC_AO_I2C_S_SEND_REG (0xff806000 + (0x001 << 2))
#define P_AO_I2C_S_SEND_REG (volatile uint32_t *)(0xff806000 + (0x001 << 2))
#define AO_I2C_S_RECV_REG (0xff806000 + (0x002 << 2))
#define SEC_AO_I2C_S_RECV_REG (0xff806000 + (0x002 << 2))
#define P_AO_I2C_S_RECV_REG (volatile uint32_t *)(0xff806000 + (0x002 << 2))
#define AO_I2C_S_CNTL1_REG (0xff806000 + (0x003 << 2))
#define SEC_AO_I2C_S_CNTL1_REG (0xff806000 + (0x003 << 2))
#define P_AO_I2C_S_CNTL1_REG (volatile uint32_t *)(0xff806000 + (0x003 << 2))
// ----------------------------
// PWM A-B
// ----------------------------
//#define AO_PWM_AB_REG_BASE 0x07
// APB4_DECODER_NON_SECURE_BASE 32'hFF807000
// APB4_DECODER_SECURE_BASE 32'hFF807000
#define AO_PWM_PWM_A (0xff807000 + (0x000 << 2))
#define SEC_AO_PWM_PWM_A (0xff807000 + (0x000 << 2))
#define P_AO_PWM_PWM_A (volatile uint32_t *)(0xff807000 + (0x000 << 2))
#define AO_PWM_PWM_B (0xff807000 + (0x001 << 2))
#define SEC_AO_PWM_PWM_B (0xff807000 + (0x001 << 2))
#define P_AO_PWM_PWM_B (volatile uint32_t *)(0xff807000 + (0x001 << 2))
#define AO_PWM_MISC_REG_AB (0xff807000 + (0x002 << 2))
#define SEC_AO_PWM_MISC_REG_AB (0xff807000 + (0x002 << 2))
#define P_AO_PWM_MISC_REG_AB (volatile uint32_t *)(0xff807000 + (0x002 << 2))
#define AO_PWM_DELTA_SIGMA_AB (0xff807000 + (0x003 << 2))
#define SEC_AO_PWM_DELTA_SIGMA_AB (0xff807000 + (0x003 << 2))
#define P_AO_PWM_DELTA_SIGMA_AB (volatile uint32_t *)(0xff807000 + (0x003 << 2))
#define AO_PWM_TIME_AB (0xff807000 + (0x004 << 2))
#define SEC_AO_PWM_TIME_AB (0xff807000 + (0x004 << 2))
#define P_AO_PWM_TIME_AB (volatile uint32_t *)(0xff807000 + (0x004 << 2))
#define AO_PWM_A2 (0xff807000 + (0x005 << 2))
#define SEC_AO_PWM_A2 (0xff807000 + (0x005 << 2))
#define P_AO_PWM_A2 (volatile uint32_t *)(0xff807000 + (0x005 << 2))
#define AO_PWM_B2 (0xff807000 + (0x006 << 2))
#define SEC_AO_PWM_B2 (0xff807000 + (0x006 << 2))
#define P_AO_PWM_B2 (volatile uint32_t *)(0xff807000 + (0x006 << 2))
#define AO_PWM_BLINK_AB (0xff807000 + (0x007 << 2))
#define SEC_AO_PWM_BLINK_AB (0xff807000 + (0x007 << 2))
#define P_AO_PWM_BLINK_AB (volatile uint32_t *)(0xff807000 + (0x007 << 2))
#define AO_PWM_LOCK_AB (0xff807000 + (0x008 << 2))
#define SEC_AO_PWM_LOCK_AB (0xff807000 + (0x008 << 2))
#define P_AO_PWM_LOCK_AB (volatile uint32_t *)(0xff807000 + (0x008 << 2))
// ----------------------------
// Multiformat IR Remote
// ----------------------------
//#define AO_MF_IR_DEC_REG_BASE 0x08
// APB4_DECODER_NON_SECURE_BASE 32'hFF808000
// APB4_DECODER_SECURE_BASE 32'hFF808000
#define AO_IR_DEC_LDR_ACTIVE (0xff808000 + (0x000 << 2))
#define SEC_AO_IR_DEC_LDR_ACTIVE (0xff808000 + (0x000 << 2))
#define P_AO_IR_DEC_LDR_ACTIVE (volatile uint32_t *)(0xff808000 + (0x000 << 2))
#define AO_IR_DEC_LDR_IDLE (0xff808000 + (0x001 << 2))
#define SEC_AO_IR_DEC_LDR_IDLE (0xff808000 + (0x001 << 2))
#define P_AO_IR_DEC_LDR_IDLE (volatile uint32_t *)(0xff808000 + (0x001 << 2))
#define AO_IR_DEC_LDR_REPEAT (0xff808000 + (0x002 << 2))
#define SEC_AO_IR_DEC_LDR_REPEAT (0xff808000 + (0x002 << 2))
#define P_AO_IR_DEC_LDR_REPEAT (volatile uint32_t *)(0xff808000 + (0x002 << 2))
#define AO_IR_DEC_BIT_0 (0xff808000 + (0x003 << 2))
#define SEC_AO_IR_DEC_BIT_0 (0xff808000 + (0x003 << 2))
#define P_AO_IR_DEC_BIT_0 (volatile uint32_t *)(0xff808000 + (0x003 << 2))
#define AO_IR_DEC_REG0 (0xff808000 + (0x004 << 2))
#define SEC_AO_IR_DEC_REG0 (0xff808000 + (0x004 << 2))
#define P_AO_IR_DEC_REG0 (volatile uint32_t *)(0xff808000 + (0x004 << 2))
#define AO_IR_DEC_FRAME (0xff808000 + (0x005 << 2))
#define SEC_AO_IR_DEC_FRAME (0xff808000 + (0x005 << 2))
#define P_AO_IR_DEC_FRAME (volatile uint32_t *)(0xff808000 + (0x005 << 2))
#define AO_IR_DEC_STATUS (0xff808000 + (0x006 << 2))
#define SEC_AO_IR_DEC_STATUS (0xff808000 + (0x006 << 2))
#define P_AO_IR_DEC_STATUS (volatile uint32_t *)(0xff808000 + (0x006 << 2))
#define AO_IR_DEC_REG1 (0xff808000 + (0x007 << 2))
#define SEC_AO_IR_DEC_REG1 (0xff808000 + (0x007 << 2))
#define P_AO_IR_DEC_REG1 (volatile uint32_t *)(0xff808000 + (0x007 << 2))
#define AO_MF_IR_DEC_LDR_ACTIVE (0xff808000 + (0x010 << 2))
#define SEC_AO_MF_IR_DEC_LDR_ACTIVE (0xff808000 + (0x010 << 2))
#define P_AO_MF_IR_DEC_LDR_ACTIVE (volatile uint32_t *)(0xff808000 + (0x010 << 2))
#define AO_MF_IR_DEC_LDR_IDLE (0xff808000 + (0x011 << 2))
#define SEC_AO_MF_IR_DEC_LDR_IDLE (0xff808000 + (0x011 << 2))
#define P_AO_MF_IR_DEC_LDR_IDLE (volatile uint32_t *)(0xff808000 + (0x011 << 2))
#define AO_MF_IR_DEC_LDR_REPEAT (0xff808000 + (0x012 << 2))
#define SEC_AO_MF_IR_DEC_LDR_REPEAT (0xff808000 + (0x012 << 2))
#define P_AO_MF_IR_DEC_LDR_REPEAT (volatile uint32_t *)(0xff808000 + (0x012 << 2))
#define AO_MF_IR_DEC_BIT_0 (0xff808000 + (0x013 << 2))
#define SEC_AO_MF_IR_DEC_BIT_0 (0xff808000 + (0x013 << 2))
#define P_AO_MF_IR_DEC_BIT_0 (volatile uint32_t *)(0xff808000 + (0x013 << 2))
#define AO_MF_IR_DEC_REG0 (0xff808000 + (0x014 << 2))
#define SEC_AO_MF_IR_DEC_REG0 (0xff808000 + (0x014 << 2))
#define P_AO_MF_IR_DEC_REG0 (volatile uint32_t *)(0xff808000 + (0x014 << 2))
#define AO_MF_IR_DEC_FRAME (0xff808000 + (0x015 << 2))
#define SEC_AO_MF_IR_DEC_FRAME (0xff808000 + (0x015 << 2))
#define P_AO_MF_IR_DEC_FRAME (volatile uint32_t *)(0xff808000 + (0x015 << 2))
#define AO_MF_IR_DEC_STATUS (0xff808000 + (0x016 << 2))
#define SEC_AO_MF_IR_DEC_STATUS (0xff808000 + (0x016 << 2))
#define P_AO_MF_IR_DEC_STATUS (volatile uint32_t *)(0xff808000 + (0x016 << 2))
#define AO_MF_IR_DEC_REG1 (0xff808000 + (0x017 << 2))
#define SEC_AO_MF_IR_DEC_REG1 (0xff808000 + (0x017 << 2))
#define P_AO_MF_IR_DEC_REG1 (volatile uint32_t *)(0xff808000 + (0x017 << 2))
#define AO_MF_IR_DEC_REG2 (0xff808000 + (0x018 << 2))
#define SEC_AO_MF_IR_DEC_REG2 (0xff808000 + (0x018 << 2))
#define P_AO_MF_IR_DEC_REG2 (volatile uint32_t *)(0xff808000 + (0x018 << 2))
#define AO_MF_IR_DEC_DURATN2 (0xff808000 + (0x019 << 2))
#define SEC_AO_MF_IR_DEC_DURATN2 (0xff808000 + (0x019 << 2))
#define P_AO_MF_IR_DEC_DURATN2 (volatile uint32_t *)(0xff808000 + (0x019 << 2))
#define AO_MF_IR_DEC_DURATN3 (0xff808000 + (0x01a << 2))
#define SEC_AO_MF_IR_DEC_DURATN3 (0xff808000 + (0x01a << 2))
#define P_AO_MF_IR_DEC_DURATN3 (volatile uint32_t *)(0xff808000 + (0x01a << 2))
#define AO_MF_IR_DEC_FRAME1 (0xff808000 + (0x01b << 2))
#define SEC_AO_MF_IR_DEC_FRAME1 (0xff808000 + (0x01b << 2))
#define P_AO_MF_IR_DEC_FRAME1 (volatile uint32_t *)(0xff808000 + (0x01b << 2))
#define AO_MF_IR_DEC_STATUS1 (0xff808000 + (0x01c << 2))
#define SEC_AO_MF_IR_DEC_STATUS1 (0xff808000 + (0x01c << 2))
#define P_AO_MF_IR_DEC_STATUS1 (volatile uint32_t *)(0xff808000 + (0x01c << 2))
#define AO_MF_IR_DEC_STATUS2 (0xff808000 + (0x01d << 2))
#define SEC_AO_MF_IR_DEC_STATUS2 (0xff808000 + (0x01d << 2))
#define P_AO_MF_IR_DEC_STATUS2 (volatile uint32_t *)(0xff808000 + (0x01d << 2))
#define AO_MF_IR_DEC_REG3 (0xff808000 + (0x01e << 2))
#define SEC_AO_MF_IR_DEC_REG3 (0xff808000 + (0x01e << 2))
#define P_AO_MF_IR_DEC_REG3 (volatile uint32_t *)(0xff808000 + (0x01e << 2))
#define AO_MF_IR_DEC_FRAME_RSV0 (0xff808000 + (0x01f << 2))
#define SEC_AO_MF_IR_DEC_FRAME_RSV0 (0xff808000 + (0x01f << 2))
#define P_AO_MF_IR_DEC_FRAME_RSV0 (volatile uint32_t *)(0xff808000 + (0x01f << 2))
#define AO_MF_IR_DEC_FRAME_RSV1 (0xff808000 + (0x020 << 2))
#define SEC_AO_MF_IR_DEC_FRAME_RSV1 (0xff808000 + (0x020 << 2))
#define P_AO_MF_IR_DEC_FRAME_RSV1 (volatile uint32_t *)(0xff808000 + (0x020 << 2))
#define AO_MF_IR_DEC_FILTE (0xff808000 + (0x021 << 2))
#define SEC_AO_MF_IR_DEC_FILTE (0xff808000 + (0x021 << 2))
#define P_AO_MF_IR_DEC_FILTE (volatile uint32_t *)(0xff808000 + (0x021 << 2))
#define AO_MF_IR_DEC_IRQ_CTL (0xff808000 + (0x022 << 2))
#define SEC_AO_MF_IR_DEC_IRQ_CTL (0xff808000 + (0x022 << 2))
#define P_AO_MF_IR_DEC_IRQ_CTL (volatile uint32_t *)(0xff808000 + (0x022 << 2))
#define AO_MF_IR_DEC_FIFO_CTL (0xff808000 + (0x023 << 2))
#define SEC_AO_MF_IR_DEC_FIFO_CTL (0xff808000 + (0x023 << 2))
#define P_AO_MF_IR_DEC_FIFO_CTL (volatile uint32_t *)(0xff808000 + (0x023 << 2))
#define AO_MF_IR_DEC_WIDTH_NEW (0xff808000 + (0x024 << 2))
#define SEC_AO_MF_IR_DEC_WIDTH_NEW (0xff808000 + (0x024 << 2))
#define P_AO_MF_IR_DEC_WIDTH_NEW (volatile uint32_t *)(0xff808000 + (0x024 << 2))
#define AO_MF_IR_DEC_REPEAT_DET (0xff808000 + (0x025 << 2))
#define SEC_AO_MF_IR_DEC_REPEAT_DET (0xff808000 + (0x025 << 2))
#define P_AO_MF_IR_DEC_REPEAT_DET (volatile uint32_t *)(0xff808000 + (0x025 << 2))
#define AO_IR_DEC_DEMOD_CNTL0 (0xff808000 + (0x030 << 2))
#define SEC_AO_IR_DEC_DEMOD_CNTL0 (0xff808000 + (0x030 << 2))
#define P_AO_IR_DEC_DEMOD_CNTL0 (volatile uint32_t *)(0xff808000 + (0x030 << 2))
#define AO_IR_DEC_DEMOD_CNTL1 (0xff808000 + (0x031 << 2))
#define SEC_AO_IR_DEC_DEMOD_CNTL1 (0xff808000 + (0x031 << 2))
#define P_AO_IR_DEC_DEMOD_CNTL1 (volatile uint32_t *)(0xff808000 + (0x031 << 2))
#define AO_IR_DEC_DEMOD_IIR_THD (0xff808000 + (0x032 << 2))
#define SEC_AO_IR_DEC_DEMOD_IIR_THD (0xff808000 + (0x032 << 2))
#define P_AO_IR_DEC_DEMOD_IIR_THD (volatile uint32_t *)(0xff808000 + (0x032 << 2))
#define AO_IR_DEC_DEMOD_THD0 (0xff808000 + (0x033 << 2))
#define SEC_AO_IR_DEC_DEMOD_THD0 (0xff808000 + (0x033 << 2))
#define P_AO_IR_DEC_DEMOD_THD0 (volatile uint32_t *)(0xff808000 + (0x033 << 2))
#define AO_IR_DEC_DEMOD_THD1 (0xff808000 + (0x034 << 2))
#define SEC_AO_IR_DEC_DEMOD_THD1 (0xff808000 + (0x034 << 2))
#define P_AO_IR_DEC_DEMOD_THD1 (volatile uint32_t *)(0xff808000 + (0x034 << 2))
#define AO_IR_DEC_DEMOD_SUM_CNT0 (0xff808000 + (0x035 << 2))
#define SEC_AO_IR_DEC_DEMOD_SUM_CNT0 (0xff808000 + (0x035 << 2))
#define P_AO_IR_DEC_DEMOD_SUM_CNT0 (volatile uint32_t *)(0xff808000 + (0x035 << 2))
#define AO_IR_DEC_DEMOD_SUM_CNT1 (0xff808000 + (0x036 << 2))
#define SEC_AO_IR_DEC_DEMOD_SUM_CNT1 (0xff808000 + (0x036 << 2))
#define P_AO_IR_DEC_DEMOD_SUM_CNT1 (volatile uint32_t *)(0xff808000 + (0x036 << 2))
#define AO_IR_DEC_DEMOD_CNT0 (0xff808000 + (0x037 << 2))
#define SEC_AO_IR_DEC_DEMOD_CNT0 (0xff808000 + (0x037 << 2))
#define P_AO_IR_DEC_DEMOD_CNT0 (volatile uint32_t *)(0xff808000 + (0x037 << 2))
#define AO_IR_DEC_DEMOD_CNT1 (0xff808000 + (0x038 << 2))
#define SEC_AO_IR_DEC_DEMOD_CNT1 (0xff808000 + (0x038 << 2))
#define P_AO_IR_DEC_DEMOD_CNT1 (volatile uint32_t *)(0xff808000 + (0x038 << 2))
// ---------------------------
// SAR ADC
// ---------------------------
//#define AO_SAR_ADC_REG_BASE 0x09
// APB4_DECODER_NON_SECURE_BASE 32'hFF809000
// APB4_DECODER_SECURE_BASE 32'hFF809000
#define AO_SAR_ADC_REG0 (0xff809000 + (0x000 << 2))
#define SEC_AO_SAR_ADC_REG0 (0xff809000 + (0x000 << 2))
#define P_AO_SAR_ADC_REG0 (volatile uint32_t *)(0xff809000 + (0x000 << 2))
#define AO_SAR_ADC_CHAN_LIST (0xff809000 + (0x001 << 2))
#define SEC_AO_SAR_ADC_CHAN_LIST (0xff809000 + (0x001 << 2))
#define P_AO_SAR_ADC_CHAN_LIST (volatile uint32_t *)(0xff809000 + (0x001 << 2))
#define AO_SAR_ADC_AVG_CNTL (0xff809000 + (0x002 << 2))
#define SEC_AO_SAR_ADC_AVG_CNTL (0xff809000 + (0x002 << 2))
#define P_AO_SAR_ADC_AVG_CNTL (volatile uint32_t *)(0xff809000 + (0x002 << 2))
#define AO_SAR_ADC_REG3 (0xff809000 + (0x003 << 2))
#define SEC_AO_SAR_ADC_REG3 (0xff809000 + (0x003 << 2))
#define P_AO_SAR_ADC_REG3 (volatile uint32_t *)(0xff809000 + (0x003 << 2))
#define AO_SAR_ADC_DELAY (0xff809000 + (0x004 << 2))
#define SEC_AO_SAR_ADC_DELAY (0xff809000 + (0x004 << 2))
#define P_AO_SAR_ADC_DELAY (volatile uint32_t *)(0xff809000 + (0x004 << 2))
#define AO_SAR_ADC_LAST_RD (0xff809000 + (0x005 << 2))
#define SEC_AO_SAR_ADC_LAST_RD (0xff809000 + (0x005 << 2))
#define P_AO_SAR_ADC_LAST_RD (volatile uint32_t *)(0xff809000 + (0x005 << 2))
#define AO_SAR_ADC_FIFO_RD (0xff809000 + (0x006 << 2))
#define SEC_AO_SAR_ADC_FIFO_RD (0xff809000 + (0x006 << 2))
#define P_AO_SAR_ADC_FIFO_RD (volatile uint32_t *)(0xff809000 + (0x006 << 2))
#define AO_SAR_ADC_AUX_SW (0xff809000 + (0x007 << 2))
#define SEC_AO_SAR_ADC_AUX_SW (0xff809000 + (0x007 << 2))
#define P_AO_SAR_ADC_AUX_SW (volatile uint32_t *)(0xff809000 + (0x007 << 2))
#define AO_SAR_ADC_CHAN_10_SW (0xff809000 + (0x008 << 2))
#define SEC_AO_SAR_ADC_CHAN_10_SW (0xff809000 + (0x008 << 2))
#define P_AO_SAR_ADC_CHAN_10_SW (volatile uint32_t *)(0xff809000 + (0x008 << 2))
#define AO_SAR_ADC_DETECT_IDLE_SW (0xff809000 + (0x009 << 2))
#define SEC_AO_SAR_ADC_DETECT_IDLE_SW (0xff809000 + (0x009 << 2))
#define P_AO_SAR_ADC_DETECT_IDLE_SW (volatile uint32_t *)(0xff809000 + (0x009 << 2))
#define AO_SAR_ADC_DELTA_10 (0xff809000 + (0x00a << 2))
#define SEC_AO_SAR_ADC_DELTA_10 (0xff809000 + (0x00a << 2))
#define P_AO_SAR_ADC_DELTA_10 (volatile uint32_t *)(0xff809000 + (0x00a << 2))
#define AO_SAR_ADC_REG11 (0xff809000 + (0x00b << 2))
#define SEC_AO_SAR_ADC_REG11 (0xff809000 + (0x00b << 2))
#define P_AO_SAR_ADC_REG11 (volatile uint32_t *)(0xff809000 + (0x00b << 2))
#define AO_SAR_ADC_REG12 (0xff809000 + (0x00c << 2))
#define SEC_AO_SAR_ADC_REG12 (0xff809000 + (0x00c << 2))
#define P_AO_SAR_ADC_REG12 (volatile uint32_t *)(0xff809000 + (0x00c << 2))
#define AO_SAR_ADC_REG13 (0xff809000 + (0x00d << 2))
#define SEC_AO_SAR_ADC_REG13 (0xff809000 + (0x00d << 2))
#define P_AO_SAR_ADC_REG13 (volatile uint32_t *)(0xff809000 + (0x00d << 2))
#define AO_SAR_ADC_CHNL01 (0xff809000 + (0x00e << 2))
#define SEC_AO_SAR_ADC_CHNL01 (0xff809000 + (0x00e << 2))
#define P_AO_SAR_ADC_CHNL01 (volatile uint32_t *)(0xff809000 + (0x00e << 2))
#define AO_SAR_ADC_CHNL23 (0xff809000 + (0x00f << 2))
#define SEC_AO_SAR_ADC_CHNL23 (0xff809000 + (0x00f << 2))
#define P_AO_SAR_ADC_CHNL23 (volatile uint32_t *)(0xff809000 + (0x00f << 2))
#define AO_SAR_ADC_CHNL45 (0xff809000 + (0x010 << 2))
#define SEC_AO_SAR_ADC_CHNL45 (0xff809000 + (0x010 << 2))
#define P_AO_SAR_ADC_CHNL45 (volatile uint32_t *)(0xff809000 + (0x010 << 2))
#define AO_SAR_ADC_CHNL67 (0xff809000 + (0x011 << 2))
#define SEC_AO_SAR_ADC_CHNL67 (0xff809000 + (0x011 << 2))
#define P_AO_SAR_ADC_CHNL67 (volatile uint32_t *)(0xff809000 + (0x011 << 2))
// ---------------------------
// MAIL BOX (M3/M4)
// ---------------------------
//#define AO_MAILBOX_REG_BASE 0x0a
// APB4_DECODER_NON_SECURE_BASE 32'hFF80a000
// APB4_DECODER_SECURE_BASE 32'hFF80a000
#define AO_MAILBOX_SET_0 (0xff80a000 + (0x001 << 2))
#define SEC_AO_MAILBOX_SET_0 (0xff80a000 + (0x001 << 2))
#define P_AO_MAILBOX_SET_0 (volatile uint32_t *)(0xff80a000 + (0x001 << 2))
#define AO_MAILBOX_STAT_0 (0xff80a000 + (0x002 << 2))
#define SEC_AO_MAILBOX_STAT_0 (0xff80a000 + (0x002 << 2))
#define P_AO_MAILBOX_STAT_0 (volatile uint32_t *)(0xff80a000 + (0x002 << 2))
#define AO_MAILBOX_CLR_0 (0xff80a000 + (0x003 << 2))
#define SEC_AO_MAILBOX_CLR_0 (0xff80a000 + (0x003 << 2))
#define P_AO_MAILBOX_CLR_0 (volatile uint32_t *)(0xff80a000 + (0x003 << 2))
#define AO_MAILBOX_SET_1 (0xff80a000 + (0x004 << 2))
#define SEC_AO_MAILBOX_SET_1 (0xff80a000 + (0x004 << 2))
#define P_AO_MAILBOX_SET_1 (volatile uint32_t *)(0xff80a000 + (0x004 << 2))
#define AO_MAILBOX_STAT_1 (0xff80a000 + (0x005 << 2))
#define SEC_AO_MAILBOX_STAT_1 (0xff80a000 + (0x005 << 2))
#define P_AO_MAILBOX_STAT_1 (volatile uint32_t *)(0xff80a000 + (0x005 << 2))
#define AO_MAILBOX_CLR_1 (0xff80a000 + (0x006 << 2))
#define SEC_AO_MAILBOX_CLR_1 (0xff80a000 + (0x006 << 2))
#define P_AO_MAILBOX_CLR_1 (volatile uint32_t *)(0xff80a000 + (0x006 << 2))
#define AO_MAILBOX_SET_2 (0xff80a000 + (0x007 << 2))
#define SEC_AO_MAILBOX_SET_2 (0xff80a000 + (0x007 << 2))
#define P_AO_MAILBOX_SET_2 (volatile uint32_t *)(0xff80a000 + (0x007 << 2))
#define AO_MAILBOX_STAT_2 (0xff80a000 + (0x008 << 2))
#define SEC_AO_MAILBOX_STAT_2 (0xff80a000 + (0x008 << 2))
#define P_AO_MAILBOX_STAT_2 (volatile uint32_t *)(0xff80a000 + (0x008 << 2))
#define AO_MAILBOX_CLR_2 (0xff80a000 + (0x009 << 2))
#define SEC_AO_MAILBOX_CLR_2 (0xff80a000 + (0x009 << 2))
#define P_AO_MAILBOX_CLR_2 (volatile uint32_t *)(0xff80a000 + (0x009 << 2))
#define AO_MAILBOX_SET_3 (0xff80a000 + (0x00a << 2))
#define SEC_AO_MAILBOX_SET_3 (0xff80a000 + (0x00a << 2))
#define P_AO_MAILBOX_SET_3 (volatile uint32_t *)(0xff80a000 + (0x00a << 2))
#define AO_MAILBOX_STAT_3 (0xff80a000 + (0x00b << 2))
#define SEC_AO_MAILBOX_STAT_3 (0xff80a000 + (0x00b << 2))
#define P_AO_MAILBOX_STAT_3 (volatile uint32_t *)(0xff80a000 + (0x00b << 2))
#define AO_MAILBOX_CLR_3 (0xff80a000 + (0x00c << 2))
#define SEC_AO_MAILBOX_CLR_3 (0xff80a000 + (0x00c << 2))
#define P_AO_MAILBOX_CLR_3 (volatile uint32_t *)(0xff80a000 + (0x00c << 2))
// ---------------------------
// RTC (4)
// ---------------------------
// Moved to the secure APB3 bus
// `define AO_RTC_ADDR0 8'hd0
// `define AO_RTC_ADDR1 8'hd1
// `define AO_RTC_ADDR2 8'hd2
// `define AO_RTC_ADDR3 8'hd3
// `define AO_RTC_ADDR4 8'hd4
//
// Closing file: ./ao_rti_reg.h
//
#endif // SECURE_APB_H
#define P_DMA_T0 (volatile uint32_t *)0xff63e000
#define P_DMA_T1 (volatile uint32_t *)0xff63e004
#define P_DMA_T2 (volatile uint32_t *)0xff63e008
#define P_DMA_T3 (volatile uint32_t *)0xff63e00c
#define P_DMA_T4 (volatile uint32_t *)0xff63e010
#define P_DMA_T5 (volatile uint32_t *)0xff63e014
#define P_DMA_STS0 (volatile uint32_t *)0xff63e020
#define P_DMA_STS1 (volatile uint32_t *)0xff63e024
#define P_DMA_STS2 (volatile uint32_t *)0xff63e028
#define P_DMA_STS3 (volatile uint32_t *)0xff63e02c
#define P_DMA_STS4 (volatile uint32_t *)0xff63e030
#define P_DMA_STS5 (volatile uint32_t *)0xff63e034
#define P_DMA_CFG (volatile uint32_t *)0xff63e040
#define P_DMA_SEC (volatile uint32_t *)0xff63e044