| #include <dt-bindings/clock/tegra30-car.h> |
| #include <dt-bindings/gpio/tegra-gpio.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| #include "skeleton.dtsi" |
| |
| / { |
| compatible = "nvidia,tegra30"; |
| interrupt-parent = <&intc>; |
| |
| intc: interrupt-controller@50041000 { |
| compatible = "arm,cortex-a9-gic"; |
| reg = <0x50041000 0x1000 |
| 0x50040100 0x0100>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| }; |
| |
| pcie-controller@00003000 { |
| compatible = "nvidia,tegra30-pcie"; |
| device_type = "pci"; |
| reg = <0x00003000 0x00000800 /* PADS registers */ |
| 0x00003800 0x00000200 /* AFI registers */ |
| 0x10000000 0x10000000>; /* configuration space */ |
| reg-names = "pads", "afi", "cs"; |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ |
| GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ |
| interrupt-names = "intr", "msi"; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| |
| bus-range = <0x00 0xff>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ |
| 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ |
| 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ |
| 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ |
| 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ |
| 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ |
| |
| clocks = <&tegra_car TEGRA30_CLK_PCIE>, |
| <&tegra_car TEGRA30_CLK_AFI>, |
| <&tegra_car TEGRA30_CLK_PCIEX>, |
| <&tegra_car TEGRA30_CLK_PLL_E>, |
| <&tegra_car TEGRA30_CLK_CML0>; |
| clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; |
| status = "disabled"; |
| |
| pci@1,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; |
| reg = <0x000800 0 0 0 0>; |
| status = "disabled"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| nvidia,num-lanes = <2>; |
| }; |
| |
| pci@2,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; |
| reg = <0x001000 0 0 0 0>; |
| status = "disabled"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| nvidia,num-lanes = <2>; |
| }; |
| |
| pci@3,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; |
| reg = <0x001800 0 0 0 0>; |
| status = "disabled"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| nvidia,num-lanes = <2>; |
| }; |
| }; |
| |
| tegra_car: clock { |
| compatible = "nvidia,tegra30-car"; |
| reg = <0x60006000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| apbdma: dma { |
| compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
| reg = <0x6000a000 0x1400>; |
| interrupts = <0 104 0x04 |
| 0 105 0x04 |
| 0 106 0x04 |
| 0 107 0x04 |
| 0 108 0x04 |
| 0 109 0x04 |
| 0 110 0x04 |
| 0 111 0x04 |
| 0 112 0x04 |
| 0 113 0x04 |
| 0 114 0x04 |
| 0 115 0x04 |
| 0 116 0x04 |
| 0 117 0x04 |
| 0 118 0x04 |
| 0 119 0x04 |
| 0 128 0x04 |
| 0 129 0x04 |
| 0 130 0x04 |
| 0 131 0x04 |
| 0 132 0x04 |
| 0 133 0x04 |
| 0 134 0x04 |
| 0 135 0x04 |
| 0 136 0x04 |
| 0 137 0x04 |
| 0 138 0x04 |
| 0 139 0x04 |
| 0 140 0x04 |
| 0 141 0x04 |
| 0 142 0x04 |
| 0 143 0x04>; |
| clocks = <&tegra_car 34>; |
| }; |
| |
| gpio: gpio@6000d000 { |
| compatible = "nvidia,tegra30-gpio"; |
| reg = <0x6000d000 0x1000>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| }; |
| |
| i2c@7000c000 { |
| compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| reg = <0x7000c000 0x100>; |
| interrupts = <0 38 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 12>, <&tegra_car 182>; |
| clock-names = "div-clk", "fast-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000c400 { |
| compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| reg = <0x7000c400 0x100>; |
| interrupts = <0 84 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 54>, <&tegra_car 182>; |
| clock-names = "div-clk", "fast-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000c500 { |
| compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| reg = <0x7000c500 0x100>; |
| interrupts = <0 92 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 67>, <&tegra_car 182>; |
| clock-names = "div-clk", "fast-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000c700 { |
| compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| reg = <0x7000c700 0x100>; |
| interrupts = <0 120 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 103>, <&tegra_car 182>; |
| clock-names = "div-clk", "fast-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000d000 { |
| compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| reg = <0x7000d000 0x100>; |
| interrupts = <0 53 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 47>, <&tegra_car 182>; |
| clock-names = "div-clk", "fast-clk"; |
| status = "disabled"; |
| }; |
| |
| uarta: serial@70006000 { |
| compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006000 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&tegra_car TEGRA30_CLK_UARTA>; |
| resets = <&tegra_car 6>; |
| reset-names = "serial"; |
| dmas = <&apbdma 8>, <&apbdma 8>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uartb: serial@70006040 { |
| compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006040 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&tegra_car TEGRA30_CLK_UARTB>; |
| resets = <&tegra_car 7>; |
| reset-names = "serial"; |
| dmas = <&apbdma 9>, <&apbdma 9>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uartc: serial@70006200 { |
| compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006200 0x100>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&tegra_car TEGRA30_CLK_UARTC>; |
| resets = <&tegra_car 55>; |
| reset-names = "serial"; |
| dmas = <&apbdma 10>, <&apbdma 10>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uartd: serial@70006300 { |
| compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006300 0x100>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&tegra_car TEGRA30_CLK_UARTD>; |
| resets = <&tegra_car 65>; |
| reset-names = "serial"; |
| dmas = <&apbdma 19>, <&apbdma 19>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uarte: serial@70006400 { |
| compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006400 0x100>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&tegra_car TEGRA30_CLK_UARTE>; |
| resets = <&tegra_car 66>; |
| reset-names = "serial"; |
| dmas = <&apbdma 20>, <&apbdma 20>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| spi@7000d400 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000d400 0x200>; |
| interrupts = <0 59 0x04>; |
| nvidia,dma-request-selector = <&apbdma 15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 41>; |
| status = "disabled"; |
| }; |
| |
| spi@7000d600 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000d600 0x200>; |
| interrupts = <0 82 0x04>; |
| nvidia,dma-request-selector = <&apbdma 16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 44>; |
| status = "disabled"; |
| }; |
| |
| spi@7000d800 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000d480 0x200>; |
| interrupts = <0 83 0x04>; |
| nvidia,dma-request-selector = <&apbdma 17>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 46>; |
| status = "disabled"; |
| }; |
| |
| spi@7000da00 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000da00 0x200>; |
| interrupts = <0 93 0x04>; |
| nvidia,dma-request-selector = <&apbdma 18>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 68>; |
| status = "disabled"; |
| }; |
| |
| spi@7000dc00 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000dc00 0x200>; |
| interrupts = <0 94 0x04>; |
| nvidia,dma-request-selector = <&apbdma 27>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 104>; |
| status = "disabled"; |
| }; |
| |
| spi@7000de00 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000de00 0x200>; |
| interrupts = <0 79 0x04>; |
| nvidia,dma-request-selector = <&apbdma 28>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 105>; |
| status = "disabled"; |
| }; |
| |
| sdhci@78000000 { |
| compatible = "nvidia,tegra30-sdhci"; |
| reg = <0x78000000 0x200>; |
| interrupts = <0 14 0x04>; |
| clocks = <&tegra_car 14>; |
| status = "disabled"; |
| }; |
| |
| sdhci@78000200 { |
| compatible = "nvidia,tegra30-sdhci"; |
| reg = <0x78000200 0x200>; |
| interrupts = <0 15 0x04>; |
| clocks = <&tegra_car 9>; |
| status = "disabled"; |
| }; |
| |
| sdhci@78000400 { |
| compatible = "nvidia,tegra30-sdhci"; |
| reg = <0x78000400 0x200>; |
| interrupts = <0 19 0x04>; |
| clocks = <&tegra_car 69>; |
| status = "disabled"; |
| }; |
| |
| sdhci@78000600 { |
| compatible = "nvidia,tegra30-sdhci"; |
| reg = <0x78000600 0x200>; |
| interrupts = <0 31 0x04>; |
| clocks = <&tegra_car 15>; |
| status = "disabled"; |
| }; |
| |
| usb@7d000000 { |
| compatible = "nvidia,tegra30-ehci"; |
| reg = <0x7d000000 0x4000>; |
| interrupts = <52>; |
| phy_type = "utmi"; |
| clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ |
| status = "disabled"; |
| }; |
| |
| usb@7d004000 { |
| compatible = "nvidia,tegra30-ehci"; |
| reg = <0x7d004000 0x4000>; |
| interrupts = <53>; |
| phy_type = "hsic"; |
| clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ |
| status = "disabled"; |
| }; |
| |
| usb@7d008000 { |
| compatible = "nvidia,tegra30-ehci"; |
| reg = <0x7d008000 0x4000>; |
| interrupts = <129>; |
| phy_type = "utmi"; |
| clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ |
| status = "disabled"; |
| }; |
| }; |
