blob: 306bcc9de56595d3a02c73a1ffbdc0204a14e2fa [file] [log] [blame]
// ----------------------------------------------------------------------
// This file is automatically generated from the script:
//
// ./create_headers_from_register_map_h.pl
//
// and was applied to the file
//
// ./register_map.h
//
// DO NOT EDIT!!!!!
// ----------------------------------------------------------------------
//
#include <asm/arch/regs.h>
#ifdef REGISTER_H
#else
#define REGISTER_H
#endif
// ----------------------------------------------------------------------
// This file is automatically generated from the script:
//
// ./create_headers_from_secure_apb4_h.pl
//
// and was applied to the file
//
// ./secure_apb4_ee.h ./ao_rti_reg.h
//
// DO NOT EDIT!!!!!
// ----------------------------------------------------------------------
//
#ifdef SECURE_APB_H
#else
#define SECURE_APB_H
//
// Reading file: ./secure_apb4_ee.h
//
// synopsys translate_off
// synopsys translate_on
//========================================================================
// MIPI_DSI_PHY
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF644000
// APB4_DECODER_SECURE_BASE 32'hFF644000
//`define MIPI_DSI_PHY_START 8'h00
//`define MIPI_DSI_PHY_END 16'hffff
#define MIPI_DSI_PHY_CTRL (0xff644000 + (0x000 << 2))
#define SEC_MIPI_DSI_PHY_CTRL (0xff644000 + (0x000 << 2))
#define P_MIPI_DSI_PHY_CTRL (volatile uint32_t *)(0xff644000 + (0x000 << 2))
#define MIPI_DSI_CHAN_CTRL (0xff644000 + (0x001 << 2))
#define SEC_MIPI_DSI_CHAN_CTRL (0xff644000 + (0x001 << 2))
#define P_MIPI_DSI_CHAN_CTRL (volatile uint32_t *)(0xff644000 + (0x001 << 2))
#define MIPI_DSI_CHAN_STS (0xff644000 + (0x002 << 2))
#define SEC_MIPI_DSI_CHAN_STS (0xff644000 + (0x002 << 2))
#define P_MIPI_DSI_CHAN_STS (volatile uint32_t *)(0xff644000 + (0x002 << 2))
#define MIPI_DSI_CLK_TIM (0xff644000 + (0x003 << 2))
#define SEC_MIPI_DSI_CLK_TIM (0xff644000 + (0x003 << 2))
#define P_MIPI_DSI_CLK_TIM (volatile uint32_t *)(0xff644000 + (0x003 << 2))
#define MIPI_DSI_HS_TIM (0xff644000 + (0x004 << 2))
#define SEC_MIPI_DSI_HS_TIM (0xff644000 + (0x004 << 2))
#define P_MIPI_DSI_HS_TIM (volatile uint32_t *)(0xff644000 + (0x004 << 2))
#define MIPI_DSI_LP_TIM (0xff644000 + (0x005 << 2))
#define SEC_MIPI_DSI_LP_TIM (0xff644000 + (0x005 << 2))
#define P_MIPI_DSI_LP_TIM (volatile uint32_t *)(0xff644000 + (0x005 << 2))
#define MIPI_DSI_ANA_UP_TIM (0xff644000 + (0x006 << 2))
#define SEC_MIPI_DSI_ANA_UP_TIM (0xff644000 + (0x006 << 2))
#define P_MIPI_DSI_ANA_UP_TIM (volatile uint32_t *)(0xff644000 + (0x006 << 2))
#define MIPI_DSI_INIT_TIM (0xff644000 + (0x007 << 2))
#define SEC_MIPI_DSI_INIT_TIM (0xff644000 + (0x007 << 2))
#define P_MIPI_DSI_INIT_TIM (volatile uint32_t *)(0xff644000 + (0x007 << 2))
#define MIPI_DSI_WAKEUP_TIM (0xff644000 + (0x008 << 2))
#define SEC_MIPI_DSI_WAKEUP_TIM (0xff644000 + (0x008 << 2))
#define P_MIPI_DSI_WAKEUP_TIM (volatile uint32_t *)(0xff644000 + (0x008 << 2))
#define MIPI_DSI_LPOK_TIM (0xff644000 + (0x009 << 2))
#define SEC_MIPI_DSI_LPOK_TIM (0xff644000 + (0x009 << 2))
#define P_MIPI_DSI_LPOK_TIM (volatile uint32_t *)(0xff644000 + (0x009 << 2))
#define MIPI_DSI_LP_WCHDOG (0xff644000 + (0x00a << 2))
#define SEC_MIPI_DSI_LP_WCHDOG (0xff644000 + (0x00a << 2))
#define P_MIPI_DSI_LP_WCHDOG (volatile uint32_t *)(0xff644000 + (0x00a << 2))
#define MIPI_DSI_ANA_CTRL (0xff644000 + (0x00b << 2))
#define SEC_MIPI_DSI_ANA_CTRL (0xff644000 + (0x00b << 2))
#define P_MIPI_DSI_ANA_CTRL (volatile uint32_t *)(0xff644000 + (0x00b << 2))
#define MIPI_DSI_CLK_TIM1 (0xff644000 + (0x00c << 2))
#define SEC_MIPI_DSI_CLK_TIM1 (0xff644000 + (0x00c << 2))
#define P_MIPI_DSI_CLK_TIM1 (volatile uint32_t *)(0xff644000 + (0x00c << 2))
#define MIPI_DSI_TURN_WCHDOG (0xff644000 + (0x00d << 2))
#define SEC_MIPI_DSI_TURN_WCHDOG (0xff644000 + (0x00d << 2))
#define P_MIPI_DSI_TURN_WCHDOG (volatile uint32_t *)(0xff644000 + (0x00d << 2))
#define MIPI_DSI_ULPS_CHECK (0xff644000 + (0x00e << 2))
#define SEC_MIPI_DSI_ULPS_CHECK (0xff644000 + (0x00e << 2))
#define P_MIPI_DSI_ULPS_CHECK (volatile uint32_t *)(0xff644000 + (0x00e << 2))
#define MIPI_DSI_TEST_CTRL0 (0xff644000 + (0x00f << 2))
#define SEC_MIPI_DSI_TEST_CTRL0 (0xff644000 + (0x00f << 2))
#define P_MIPI_DSI_TEST_CTRL0 (volatile uint32_t *)(0xff644000 + (0x00f << 2))
#define MIPI_DSI_TEST_CTRL1 (0xff644000 + (0x010 << 2))
#define SEC_MIPI_DSI_TEST_CTRL1 (0xff644000 + (0x010 << 2))
#define P_MIPI_DSI_TEST_CTRL1 (volatile uint32_t *)(0xff644000 + (0x010 << 2))
//========================================================================
// Temp sensor PLL
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF634800
// APB4_DECODER_SECURE_BASE 32'hFF634800
#define TS_PLL_CFG_REG1 (0xff634800 + (0x001 << 2))
#define SEC_TS_PLL_CFG_REG1 (0xff634800 + (0x001 << 2))
#define P_TS_PLL_CFG_REG1 (volatile uint32_t *)(0xff634800 + (0x001 << 2))
#define TS_PLL_CFG_REG2 (0xff634800 + (0x002 << 2))
#define SEC_TS_PLL_CFG_REG2 (0xff634800 + (0x002 << 2))
#define P_TS_PLL_CFG_REG2 (volatile uint32_t *)(0xff634800 + (0x002 << 2))
#define TS_PLL_CFG_REG3 (0xff634800 + (0x003 << 2))
#define SEC_TS_PLL_CFG_REG3 (0xff634800 + (0x003 << 2))
#define P_TS_PLL_CFG_REG3 (volatile uint32_t *)(0xff634800 + (0x003 << 2))
#define TS_PLL_CFG_REG4 (0xff634800 + (0x004 << 2))
#define SEC_TS_PLL_CFG_REG4 (0xff634800 + (0x004 << 2))
#define P_TS_PLL_CFG_REG4 (volatile uint32_t *)(0xff634800 + (0x004 << 2))
#define TS_PLL_CFG_REG5 (0xff634800 + (0x005 << 2))
#define SEC_TS_PLL_CFG_REG5 (0xff634800 + (0x005 << 2))
#define P_TS_PLL_CFG_REG5 (volatile uint32_t *)(0xff634800 + (0x005 << 2))
#define TS_PLL_CFG_REG6 (0xff634800 + (0x006 << 2))
#define SEC_TS_PLL_CFG_REG6 (0xff634800 + (0x006 << 2))
#define P_TS_PLL_CFG_REG6 (volatile uint32_t *)(0xff634800 + (0x006 << 2))
#define TS_PLL_CFG_REG7 (0xff634800 + (0x007 << 2))
#define SEC_TS_PLL_CFG_REG7 (0xff634800 + (0x007 << 2))
#define P_TS_PLL_CFG_REG7 (volatile uint32_t *)(0xff634800 + (0x007 << 2))
#define TS_PLL_STAT0 (0xff634800 + (0x010 << 2))
#define SEC_TS_PLL_STAT0 (0xff634800 + (0x010 << 2))
#define P_TS_PLL_STAT0 (volatile uint32_t *)(0xff634800 + (0x010 << 2))
#define TS_PLL_STAT1 (0xff634800 + (0x011 << 2))
#define SEC_TS_PLL_STAT1 (0xff634800 + (0x011 << 2))
#define P_TS_PLL_STAT1 (volatile uint32_t *)(0xff634800 + (0x011 << 2))
#define TS_PLL_STAT2 (0xff634800 + (0x012 << 2))
#define SEC_TS_PLL_STAT2 (0xff634800 + (0x012 << 2))
#define P_TS_PLL_STAT2 (volatile uint32_t *)(0xff634800 + (0x012 << 2))
#define TS_PLL_STAT3 (0xff634800 + (0x013 << 2))
#define SEC_TS_PLL_STAT3 (0xff634800 + (0x013 << 2))
#define P_TS_PLL_STAT3 (volatile uint32_t *)(0xff634800 + (0x013 << 2))
#define TS_PLL_STAT4 (0xff634800 + (0x014 << 2))
#define SEC_TS_PLL_STAT4 (0xff634800 + (0x014 << 2))
#define P_TS_PLL_STAT4 (volatile uint32_t *)(0xff634800 + (0x014 << 2))
#define TS_PLL_STAT5 (0xff634800 + (0x015 << 2))
#define SEC_TS_PLL_STAT5 (0xff634800 + (0x015 << 2))
#define P_TS_PLL_STAT5 (volatile uint32_t *)(0xff634800 + (0x015 << 2))
#define TS_PLL_STAT6 (0xff634800 + (0x016 << 2))
#define SEC_TS_PLL_STAT6 (0xff634800 + (0x016 << 2))
#define P_TS_PLL_STAT6 (volatile uint32_t *)(0xff634800 + (0x016 << 2))
#define TS_PLL_STAT7 (0xff634800 + (0x017 << 2))
#define SEC_TS_PLL_STAT7 (0xff634800 + (0x017 << 2))
#define P_TS_PLL_STAT7 (volatile uint32_t *)(0xff634800 + (0x017 << 2))
#define TS_PLL_STAT8 (0xff634800 + (0x018 << 2))
#define SEC_TS_PLL_STAT8 (0xff634800 + (0x018 << 2))
#define P_TS_PLL_STAT8 (volatile uint32_t *)(0xff634800 + (0x018 << 2))
#define TS_PLL_STAT9 (0xff634800 + (0x019 << 2))
#define SEC_TS_PLL_STAT9 (0xff634800 + (0x019 << 2))
#define P_TS_PLL_STAT9 (volatile uint32_t *)(0xff634800 + (0x019 << 2))
//========================================================================
// Temp sensor DDR
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF634C00
// APB4_DECODER_SECURE_BASE 32'hFF634C00
#define TS_DDR_CFG_REG1 (0xff634c00 + (0x001 << 2))
#define SEC_TS_DDR_CFG_REG1 (0xff634c00 + (0x001 << 2))
#define P_TS_DDR_CFG_REG1 (volatile uint32_t *)(0xff634c00 + (0x001 << 2))
#define TS_DDR_CFG_REG2 (0xff634c00 + (0x002 << 2))
#define SEC_TS_DDR_CFG_REG2 (0xff634c00 + (0x002 << 2))
#define P_TS_DDR_CFG_REG2 (volatile uint32_t *)(0xff634c00 + (0x002 << 2))
#define TS_DDR_CFG_REG3 (0xff634c00 + (0x003 << 2))
#define SEC_TS_DDR_CFG_REG3 (0xff634c00 + (0x003 << 2))
#define P_TS_DDR_CFG_REG3 (volatile uint32_t *)(0xff634c00 + (0x003 << 2))
#define TS_DDR_CFG_REG4 (0xff634c00 + (0x004 << 2))
#define SEC_TS_DDR_CFG_REG4 (0xff634c00 + (0x004 << 2))
#define P_TS_DDR_CFG_REG4 (volatile uint32_t *)(0xff634c00 + (0x004 << 2))
#define TS_DDR_CFG_REG5 (0xff634c00 + (0x005 << 2))
#define SEC_TS_DDR_CFG_REG5 (0xff634c00 + (0x005 << 2))
#define P_TS_DDR_CFG_REG5 (volatile uint32_t *)(0xff634c00 + (0x005 << 2))
#define TS_DDR_CFG_REG6 (0xff634c00 + (0x006 << 2))
#define SEC_TS_DDR_CFG_REG6 (0xff634c00 + (0x006 << 2))
#define P_TS_DDR_CFG_REG6 (volatile uint32_t *)(0xff634c00 + (0x006 << 2))
#define TS_DDR_CFG_REG7 (0xff634c00 + (0x007 << 2))
#define SEC_TS_DDR_CFG_REG7 (0xff634c00 + (0x007 << 2))
#define P_TS_DDR_CFG_REG7 (volatile uint32_t *)(0xff634c00 + (0x007 << 2))
#define TS_DDR_STAT0 (0xff634c00 + (0x010 << 2))
#define SEC_TS_DDR_STAT0 (0xff634c00 + (0x010 << 2))
#define P_TS_DDR_STAT0 (volatile uint32_t *)(0xff634c00 + (0x010 << 2))
#define TS_DDR_STAT1 (0xff634c00 + (0x011 << 2))
#define SEC_TS_DDR_STAT1 (0xff634c00 + (0x011 << 2))
#define P_TS_DDR_STAT1 (volatile uint32_t *)(0xff634c00 + (0x011 << 2))
#define TS_DDR_STAT2 (0xff634c00 + (0x012 << 2))
#define SEC_TS_DDR_STAT2 (0xff634c00 + (0x012 << 2))
#define P_TS_DDR_STAT2 (volatile uint32_t *)(0xff634c00 + (0x012 << 2))
#define TS_DDR_STAT3 (0xff634c00 + (0x013 << 2))
#define SEC_TS_DDR_STAT3 (0xff634c00 + (0x013 << 2))
#define P_TS_DDR_STAT3 (volatile uint32_t *)(0xff634c00 + (0x013 << 2))
#define TS_DDR_STAT4 (0xff634c00 + (0x014 << 2))
#define SEC_TS_DDR_STAT4 (0xff634c00 + (0x014 << 2))
#define P_TS_DDR_STAT4 (volatile uint32_t *)(0xff634c00 + (0x014 << 2))
#define TS_DDR_STAT5 (0xff634c00 + (0x015 << 2))
#define SEC_TS_DDR_STAT5 (0xff634c00 + (0x015 << 2))
#define P_TS_DDR_STAT5 (volatile uint32_t *)(0xff634c00 + (0x015 << 2))
#define TS_DDR_STAT6 (0xff634c00 + (0x016 << 2))
#define SEC_TS_DDR_STAT6 (0xff634c00 + (0x016 << 2))
#define P_TS_DDR_STAT6 (volatile uint32_t *)(0xff634c00 + (0x016 << 2))
#define TS_DDR_STAT7 (0xff634c00 + (0x017 << 2))
#define SEC_TS_DDR_STAT7 (0xff634c00 + (0x017 << 2))
#define P_TS_DDR_STAT7 (volatile uint32_t *)(0xff634c00 + (0x017 << 2))
#define TS_DDR_STAT8 (0xff634c00 + (0x018 << 2))
#define SEC_TS_DDR_STAT8 (0xff634c00 + (0x018 << 2))
#define P_TS_DDR_STAT8 (volatile uint32_t *)(0xff634c00 + (0x018 << 2))
#define TS_DDR_STAT9 (0xff634c00 + (0x019 << 2))
#define SEC_TS_DDR_STAT9 (0xff634c00 + (0x019 << 2))
#define P_TS_DDR_STAT9 (volatile uint32_t *)(0xff634c00 + (0x019 << 2))
//========================================================================
// Temp sensor GPU
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF635000
// APB4_DECODER_SECURE_BASE 32'hFF635000
//`define TS_GPU_CFG_REG1 8'h01
//`define TS_GPU_CFG_REG2 8'h02
//`define TS_GPU_CFG_REG3 8'h03
//`define TS_GPU_CFG_REG4 8'h04
//`define TS_GPU_CFG_REG5 8'h05
//`define TS_GPU_CFG_REG6 8'h06
//`define TS_GPU_CFG_REG7 8'h07
//`define TS_GPU_STAT0 8'h10
//`define TS_GPU_STAT1 8'h11
//`define TS_GPU_STAT2 8'h12
//`define TS_GPU_STAT3 8'h13
//`define TS_GPU_STAT4 8'h14
//`define TS_GPU_STAT5 8'h15
//`define TS_GPU_STAT6 8'h16
//`define TS_GPU_STAT7 8'h17
//`define TS_GPU_STAT8 8'h18
//`define TS_GPU_STAT9 8'h19
//========================================================================
// RNG
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF634000
// APB4_DECODER_SECURE_BASE 32'hFF634000
//========================================================================
// ACODEC
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF632000
// APB4_DECODER_SECURE_BASE 32'hFF632000
#define ACODEC_0 (0xff632000 + (0x000 << 2))
#define SEC_ACODEC_0 (0xff632000 + (0x000 << 2))
#define P_ACODEC_0 (volatile uint32_t *)(0xff632000 + (0x000 << 2))
#define ACODEC_1 (0xff632000 + (0x001 << 2))
#define SEC_ACODEC_1 (0xff632000 + (0x001 << 2))
#define P_ACODEC_1 (volatile uint32_t *)(0xff632000 + (0x001 << 2))
#define ACODEC_2 (0xff632000 + (0x002 << 2))
#define SEC_ACODEC_2 (0xff632000 + (0x002 << 2))
#define P_ACODEC_2 (volatile uint32_t *)(0xff632000 + (0x002 << 2))
#define ACODEC_3 (0xff632000 + (0x003 << 2))
#define SEC_ACODEC_3 (0xff632000 + (0x003 << 2))
#define P_ACODEC_3 (volatile uint32_t *)(0xff632000 + (0x003 << 2))
#define ACODEC_4 (0xff632000 + (0x004 << 2))
#define SEC_ACODEC_4 (0xff632000 + (0x004 << 2))
#define P_ACODEC_4 (volatile uint32_t *)(0xff632000 + (0x004 << 2))
#define ACODEC_5 (0xff632000 + (0x005 << 2))
#define SEC_ACODEC_5 (0xff632000 + (0x005 << 2))
#define P_ACODEC_5 (volatile uint32_t *)(0xff632000 + (0x005 << 2))
#define ACODEC_6 (0xff632000 + (0x006 << 2))
#define SEC_ACODEC_6 (0xff632000 + (0x006 << 2))
#define P_ACODEC_6 (volatile uint32_t *)(0xff632000 + (0x006 << 2))
#define ACODEC_7 (0xff632000 + (0x007 << 2))
#define SEC_ACODEC_7 (0xff632000 + (0x007 << 2))
#define P_ACODEC_7 (volatile uint32_t *)(0xff632000 + (0x007 << 2))
//========================================================================
// AML USB PHY A
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF636000
// APB4_DECODER_SECURE_BASE 32'hFF636000
#define AMLUSB_A0 (0xff636000 + (0x000 << 2))
#define SEC_AMLUSB_A0 (0xff636000 + (0x000 << 2))
#define P_AMLUSB_A0 (volatile uint32_t *)(0xff636000 + (0x000 << 2))
#define AMLUSB_A1 (0xff636000 + (0x001 << 2))
#define SEC_AMLUSB_A1 (0xff636000 + (0x001 << 2))
#define P_AMLUSB_A1 (volatile uint32_t *)(0xff636000 + (0x001 << 2))
#define AMLUSB_A2 (0xff636000 + (0x002 << 2))
#define SEC_AMLUSB_A2 (0xff636000 + (0x002 << 2))
#define P_AMLUSB_A2 (volatile uint32_t *)(0xff636000 + (0x002 << 2))
#define AMLUSB_A3 (0xff636000 + (0x003 << 2))
#define SEC_AMLUSB_A3 (0xff636000 + (0x003 << 2))
#define P_AMLUSB_A3 (volatile uint32_t *)(0xff636000 + (0x003 << 2))
#define AMLUSB_A4 (0xff636000 + (0x004 << 2))
#define SEC_AMLUSB_A4 (0xff636000 + (0x004 << 2))
#define P_AMLUSB_A4 (volatile uint32_t *)(0xff636000 + (0x004 << 2))
#define AMLUSB_A5 (0xff636000 + (0x005 << 2))
#define SEC_AMLUSB_A5 (0xff636000 + (0x005 << 2))
#define P_AMLUSB_A5 (volatile uint32_t *)(0xff636000 + (0x005 << 2))
#define AMLUSB_A6 (0xff636000 + (0x006 << 2))
#define SEC_AMLUSB_A6 (0xff636000 + (0x006 << 2))
#define P_AMLUSB_A6 (volatile uint32_t *)(0xff636000 + (0x006 << 2))
#define AMLUSB_A7 (0xff636000 + (0x007 << 2))
#define SEC_AMLUSB_A7 (0xff636000 + (0x007 << 2))
#define P_AMLUSB_A7 (volatile uint32_t *)(0xff636000 + (0x007 << 2))
#define AMLUSB_A8 (0xff636000 + (0x008 << 2))
#define SEC_AMLUSB_A8 (0xff636000 + (0x008 << 2))
#define P_AMLUSB_A8 (volatile uint32_t *)(0xff636000 + (0x008 << 2))
#define AMLUSB_A9 (0xff636000 + (0x009 << 2))
#define SEC_AMLUSB_A9 (0xff636000 + (0x009 << 2))
#define P_AMLUSB_A9 (volatile uint32_t *)(0xff636000 + (0x009 << 2))
#define AMLUSB_A10 (0xff636000 + (0x00a << 2))
#define SEC_AMLUSB_A10 (0xff636000 + (0x00a << 2))
#define P_AMLUSB_A10 (volatile uint32_t *)(0xff636000 + (0x00a << 2))
#define AMLUSB_A11 (0xff636000 + (0x00b << 2))
#define SEC_AMLUSB_A11 (0xff636000 + (0x00b << 2))
#define P_AMLUSB_A11 (volatile uint32_t *)(0xff636000 + (0x00b << 2))
#define AMLUSB_A12 (0xff636000 + (0x00c << 2))
#define SEC_AMLUSB_A12 (0xff636000 + (0x00c << 2))
#define P_AMLUSB_A12 (volatile uint32_t *)(0xff636000 + (0x00c << 2))
#define AMLUSB_A13 (0xff636000 + (0x00d << 2))
#define SEC_AMLUSB_A13 (0xff636000 + (0x00d << 2))
#define P_AMLUSB_A13 (volatile uint32_t *)(0xff636000 + (0x00d << 2))
#define AMLUSB_A14 (0xff636000 + (0x00e << 2))
#define SEC_AMLUSB_A14 (0xff636000 + (0x00e << 2))
#define P_AMLUSB_A14 (volatile uint32_t *)(0xff636000 + (0x00e << 2))
#define AMLUSB_A15 (0xff636000 + (0x00f << 2))
#define SEC_AMLUSB_A15 (0xff636000 + (0x00f << 2))
#define P_AMLUSB_A15 (volatile uint32_t *)(0xff636000 + (0x00f << 2))
#define AMLUSB_A16 (0xff636000 + (0x010 << 2))
#define SEC_AMLUSB_A16 (0xff636000 + (0x010 << 2))
#define P_AMLUSB_A16 (volatile uint32_t *)(0xff636000 + (0x010 << 2))
#define AMLUSB_A17 (0xff636000 + (0x011 << 2))
#define SEC_AMLUSB_A17 (0xff636000 + (0x011 << 2))
#define P_AMLUSB_A17 (volatile uint32_t *)(0xff636000 + (0x011 << 2))
#define AMLUSB_A18 (0xff636000 + (0x012 << 2))
#define SEC_AMLUSB_A18 (0xff636000 + (0x012 << 2))
#define P_AMLUSB_A18 (volatile uint32_t *)(0xff636000 + (0x012 << 2))
#define AMLUSB_A19 (0xff636000 + (0x013 << 2))
#define SEC_AMLUSB_A19 (0xff636000 + (0x013 << 2))
#define P_AMLUSB_A19 (volatile uint32_t *)(0xff636000 + (0x013 << 2))
#define AMLUSB_A20 (0xff636000 + (0x014 << 2))
#define SEC_AMLUSB_A20 (0xff636000 + (0x014 << 2))
#define P_AMLUSB_A20 (volatile uint32_t *)(0xff636000 + (0x014 << 2))
#define AMLUSB_A21 (0xff636000 + (0x015 << 2))
#define SEC_AMLUSB_A21 (0xff636000 + (0x015 << 2))
#define P_AMLUSB_A21 (volatile uint32_t *)(0xff636000 + (0x015 << 2))
#define AMLUSB_A22 (0xff636000 + (0x016 << 2))
#define SEC_AMLUSB_A22 (0xff636000 + (0x016 << 2))
#define P_AMLUSB_A22 (volatile uint32_t *)(0xff636000 + (0x016 << 2))
#define AMLUSB_A23 (0xff636000 + (0x017 << 2))
#define SEC_AMLUSB_A23 (0xff636000 + (0x017 << 2))
#define P_AMLUSB_A23 (volatile uint32_t *)(0xff636000 + (0x017 << 2))
#define AMLUSB_A24 (0xff636000 + (0x018 << 2))
#define SEC_AMLUSB_A24 (0xff636000 + (0x018 << 2))
#define P_AMLUSB_A24 (volatile uint32_t *)(0xff636000 + (0x018 << 2))
#define AMLUSB_A25 (0xff636000 + (0x019 << 2))
#define SEC_AMLUSB_A25 (0xff636000 + (0x019 << 2))
#define P_AMLUSB_A25 (volatile uint32_t *)(0xff636000 + (0x019 << 2))
#define AMLUSB_A26 (0xff636000 + (0x01a << 2))
#define SEC_AMLUSB_A26 (0xff636000 + (0x01a << 2))
#define P_AMLUSB_A26 (volatile uint32_t *)(0xff636000 + (0x01a << 2))
#define AMLUSB_A27 (0xff636000 + (0x01b << 2))
#define SEC_AMLUSB_A27 (0xff636000 + (0x01b << 2))
#define P_AMLUSB_A27 (volatile uint32_t *)(0xff636000 + (0x01b << 2))
#define AMLUSB_A28 (0xff636000 + (0x01c << 2))
#define SEC_AMLUSB_A28 (0xff636000 + (0x01c << 2))
#define P_AMLUSB_A28 (volatile uint32_t *)(0xff636000 + (0x01c << 2))
#define AMLUSB_A29 (0xff636000 + (0x01d << 2))
#define SEC_AMLUSB_A29 (0xff636000 + (0x01d << 2))
#define P_AMLUSB_A29 (volatile uint32_t *)(0xff636000 + (0x01d << 2))
#define AMLUSB_A30 (0xff636000 + (0x01e << 2))
#define SEC_AMLUSB_A30 (0xff636000 + (0x01e << 2))
#define P_AMLUSB_A30 (volatile uint32_t *)(0xff636000 + (0x01e << 2))
#define AMLUSB_A31 (0xff636000 + (0x01f << 2))
#define SEC_AMLUSB_A31 (0xff636000 + (0x01f << 2))
#define P_AMLUSB_A31 (volatile uint32_t *)(0xff636000 + (0x01f << 2))
//========================================================================
// AML USB PHY B
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF63A000
// APB4_DECODER_SECURE_BASE 32'hFF63A000
#define AMLUSB_B0 (0xff63a000 + (0x000 << 2))
#define SEC_AMLUSB_B0 (0xff63a000 + (0x000 << 2))
#define P_AMLUSB_B0 (volatile uint32_t *)(0xff63a000 + (0x000 << 2))
#define AMLUSB_B1 (0xff63a000 + (0x001 << 2))
#define SEC_AMLUSB_B1 (0xff63a000 + (0x001 << 2))
#define P_AMLUSB_B1 (volatile uint32_t *)(0xff63a000 + (0x001 << 2))
#define AMLUSB_B2 (0xff63a000 + (0x002 << 2))
#define SEC_AMLUSB_B2 (0xff63a000 + (0x002 << 2))
#define P_AMLUSB_B2 (volatile uint32_t *)(0xff63a000 + (0x002 << 2))
#define AMLUSB_B3 (0xff63a000 + (0x003 << 2))
#define SEC_AMLUSB_B3 (0xff63a000 + (0x003 << 2))
#define P_AMLUSB_B3 (volatile uint32_t *)(0xff63a000 + (0x003 << 2))
#define AMLUSB_B4 (0xff63a000 + (0x004 << 2))
#define SEC_AMLUSB_B4 (0xff63a000 + (0x004 << 2))
#define P_AMLUSB_B4 (volatile uint32_t *)(0xff63a000 + (0x004 << 2))
#define AMLUSB_B5 (0xff63a000 + (0x005 << 2))
#define SEC_AMLUSB_B5 (0xff63a000 + (0x005 << 2))
#define P_AMLUSB_B5 (volatile uint32_t *)(0xff63a000 + (0x005 << 2))
#define AMLUSB_B6 (0xff63a000 + (0x006 << 2))
#define SEC_AMLUSB_B6 (0xff63a000 + (0x006 << 2))
#define P_AMLUSB_B6 (volatile uint32_t *)(0xff63a000 + (0x006 << 2))
#define AMLUSB_B7 (0xff63a000 + (0x007 << 2))
#define SEC_AMLUSB_B7 (0xff63a000 + (0x007 << 2))
#define P_AMLUSB_B7 (volatile uint32_t *)(0xff63a000 + (0x007 << 2))
#define AMLUSB_B8 (0xff63a000 + (0x008 << 2))
#define SEC_AMLUSB_B8 (0xff63a000 + (0x008 << 2))
#define P_AMLUSB_B8 (volatile uint32_t *)(0xff63a000 + (0x008 << 2))
#define AMLUSB_B9 (0xff63a000 + (0x009 << 2))
#define SEC_AMLUSB_B9 (0xff63a000 + (0x009 << 2))
#define P_AMLUSB_B9 (volatile uint32_t *)(0xff63a000 + (0x009 << 2))
#define AMLUSB_B10 (0xff63a000 + (0x00a << 2))
#define SEC_AMLUSB_B10 (0xff63a000 + (0x00a << 2))
#define P_AMLUSB_B10 (volatile uint32_t *)(0xff63a000 + (0x00a << 2))
#define AMLUSB_B11 (0xff63a000 + (0x00b << 2))
#define SEC_AMLUSB_B11 (0xff63a000 + (0x00b << 2))
#define P_AMLUSB_B11 (volatile uint32_t *)(0xff63a000 + (0x00b << 2))
#define AMLUSB_B12 (0xff63a000 + (0x00c << 2))
#define SEC_AMLUSB_B12 (0xff63a000 + (0x00c << 2))
#define P_AMLUSB_B12 (volatile uint32_t *)(0xff63a000 + (0x00c << 2))
#define AMLUSB_B13 (0xff63a000 + (0x00d << 2))
#define SEC_AMLUSB_B13 (0xff63a000 + (0x00d << 2))
#define P_AMLUSB_B13 (volatile uint32_t *)(0xff63a000 + (0x00d << 2))
#define AMLUSB_B14 (0xff63a000 + (0x00e << 2))
#define SEC_AMLUSB_B14 (0xff63a000 + (0x00e << 2))
#define P_AMLUSB_B14 (volatile uint32_t *)(0xff63a000 + (0x00e << 2))
#define AMLUSB_B15 (0xff63a000 + (0x00f << 2))
#define SEC_AMLUSB_B15 (0xff63a000 + (0x00f << 2))
#define P_AMLUSB_B15 (volatile uint32_t *)(0xff63a000 + (0x00f << 2))
#define AMLUSB_B16 (0xff63a000 + (0x010 << 2))
#define SEC_AMLUSB_B16 (0xff63a000 + (0x010 << 2))
#define P_AMLUSB_B16 (volatile uint32_t *)(0xff63a000 + (0x010 << 2))
#define AMLUSB_B17 (0xff63a000 + (0x011 << 2))
#define SEC_AMLUSB_B17 (0xff63a000 + (0x011 << 2))
#define P_AMLUSB_B17 (volatile uint32_t *)(0xff63a000 + (0x011 << 2))
#define AMLUSB_B18 (0xff63a000 + (0x012 << 2))
#define SEC_AMLUSB_B18 (0xff63a000 + (0x012 << 2))
#define P_AMLUSB_B18 (volatile uint32_t *)(0xff63a000 + (0x012 << 2))
#define AMLUSB_B19 (0xff63a000 + (0x013 << 2))
#define SEC_AMLUSB_B19 (0xff63a000 + (0x013 << 2))
#define P_AMLUSB_B19 (volatile uint32_t *)(0xff63a000 + (0x013 << 2))
#define AMLUSB_B20 (0xff63a000 + (0x014 << 2))
#define SEC_AMLUSB_B20 (0xff63a000 + (0x014 << 2))
#define P_AMLUSB_B20 (volatile uint32_t *)(0xff63a000 + (0x014 << 2))
#define AMLUSB_B21 (0xff63a000 + (0x015 << 2))
#define SEC_AMLUSB_B21 (0xff63a000 + (0x015 << 2))
#define P_AMLUSB_B21 (volatile uint32_t *)(0xff63a000 + (0x015 << 2))
#define AMLUSB_B22 (0xff63a000 + (0x016 << 2))
#define SEC_AMLUSB_B22 (0xff63a000 + (0x016 << 2))
#define P_AMLUSB_B22 (volatile uint32_t *)(0xff63a000 + (0x016 << 2))
#define AMLUSB_B23 (0xff63a000 + (0x017 << 2))
#define SEC_AMLUSB_B23 (0xff63a000 + (0x017 << 2))
#define P_AMLUSB_B23 (volatile uint32_t *)(0xff63a000 + (0x017 << 2))
#define AMLUSB_B24 (0xff63a000 + (0x018 << 2))
#define SEC_AMLUSB_B24 (0xff63a000 + (0x018 << 2))
#define P_AMLUSB_B24 (volatile uint32_t *)(0xff63a000 + (0x018 << 2))
#define AMLUSB_B25 (0xff63a000 + (0x019 << 2))
#define SEC_AMLUSB_B25 (0xff63a000 + (0x019 << 2))
#define P_AMLUSB_B25 (volatile uint32_t *)(0xff63a000 + (0x019 << 2))
#define AMLUSB_B26 (0xff63a000 + (0x01a << 2))
#define SEC_AMLUSB_B26 (0xff63a000 + (0x01a << 2))
#define P_AMLUSB_B26 (volatile uint32_t *)(0xff63a000 + (0x01a << 2))
#define AMLUSB_B27 (0xff63a000 + (0x01b << 2))
#define SEC_AMLUSB_B27 (0xff63a000 + (0x01b << 2))
#define P_AMLUSB_B27 (volatile uint32_t *)(0xff63a000 + (0x01b << 2))
#define AMLUSB_B28 (0xff63a000 + (0x01c << 2))
#define SEC_AMLUSB_B28 (0xff63a000 + (0x01c << 2))
#define P_AMLUSB_B28 (volatile uint32_t *)(0xff63a000 + (0x01c << 2))
#define AMLUSB_B29 (0xff63a000 + (0x01d << 2))
#define SEC_AMLUSB_B29 (0xff63a000 + (0x01d << 2))
#define P_AMLUSB_B29 (volatile uint32_t *)(0xff63a000 + (0x01d << 2))
#define AMLUSB_B30 (0xff63a000 + (0x01e << 2))
#define SEC_AMLUSB_B30 (0xff63a000 + (0x01e << 2))
#define P_AMLUSB_B30 (volatile uint32_t *)(0xff63a000 + (0x01e << 2))
#define AMLUSB_B31 (0xff63a000 + (0x01f << 2))
#define SEC_AMLUSB_B31 (0xff63a000 + (0x01f << 2))
#define P_AMLUSB_B31 (volatile uint32_t *)(0xff63a000 + (0x01f << 2))
//========================================================================
// PERIPHS
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF634400
// APB4_DECODER_SECURE_BASE 32'hFF634400
// The following are handled by $periphs/rtl/periphs_reg.v
//`define PREG_CTLREG0_ADDR 8'h00
// ----------------------------
// ----------------------------
//`define PREG_JTAG_GPIO_ADDR 8'h0b // DWORD base address (0xc120002c >> 2)
// ----------------------------
// Pre-defined GPIO addresses
// ----------------------------
#define PREG_PAD_GPIO0_EN_N (0xff634400 + (0x010 << 2))
#define SEC_PREG_PAD_GPIO0_EN_N (0xff634400 + (0x010 << 2))
#define P_PREG_PAD_GPIO0_EN_N (volatile uint32_t *)(0xff634400 + (0x010 << 2))
#define PREG_PAD_GPIO0_O (0xff634400 + (0x011 << 2))
#define SEC_PREG_PAD_GPIO0_O (0xff634400 + (0x011 << 2))
#define P_PREG_PAD_GPIO0_O (volatile uint32_t *)(0xff634400 + (0x011 << 2))
#define PREG_PAD_GPIO0_I (0xff634400 + (0x012 << 2))
#define SEC_PREG_PAD_GPIO0_I (0xff634400 + (0x012 << 2))
#define P_PREG_PAD_GPIO0_I (volatile uint32_t *)(0xff634400 + (0x012 << 2))
// ----------------------------
#define PREG_PAD_GPIO1_EN_N (0xff634400 + (0x013 << 2))
#define SEC_PREG_PAD_GPIO1_EN_N (0xff634400 + (0x013 << 2))
#define P_PREG_PAD_GPIO1_EN_N (volatile uint32_t *)(0xff634400 + (0x013 << 2))
#define PREG_PAD_GPIO1_O (0xff634400 + (0x014 << 2))
#define SEC_PREG_PAD_GPIO1_O (0xff634400 + (0x014 << 2))
#define P_PREG_PAD_GPIO1_O (volatile uint32_t *)(0xff634400 + (0x014 << 2))
#define PREG_PAD_GPIO1_I (0xff634400 + (0x015 << 2))
#define SEC_PREG_PAD_GPIO1_I (0xff634400 + (0x015 << 2))
#define P_PREG_PAD_GPIO1_I (volatile uint32_t *)(0xff634400 + (0x015 << 2))
// ----------------------------
#define PREG_PAD_GPIO2_EN_N (0xff634400 + (0x016 << 2))
#define SEC_PREG_PAD_GPIO2_EN_N (0xff634400 + (0x016 << 2))
#define P_PREG_PAD_GPIO2_EN_N (volatile uint32_t *)(0xff634400 + (0x016 << 2))
#define PREG_PAD_GPIO2_O (0xff634400 + (0x017 << 2))
#define SEC_PREG_PAD_GPIO2_O (0xff634400 + (0x017 << 2))
#define P_PREG_PAD_GPIO2_O (volatile uint32_t *)(0xff634400 + (0x017 << 2))
#define PREG_PAD_GPIO2_I (0xff634400 + (0x018 << 2))
#define SEC_PREG_PAD_GPIO2_I (0xff634400 + (0x018 << 2))
#define P_PREG_PAD_GPIO2_I (volatile uint32_t *)(0xff634400 + (0x018 << 2))
// ----------------------------
#define PREG_PAD_GPIO3_EN_N (0xff634400 + (0x019 << 2))
#define SEC_PREG_PAD_GPIO3_EN_N (0xff634400 + (0x019 << 2))
#define P_PREG_PAD_GPIO3_EN_N (volatile uint32_t *)(0xff634400 + (0x019 << 2))
#define PREG_PAD_GPIO3_O (0xff634400 + (0x01a << 2))
#define SEC_PREG_PAD_GPIO3_O (0xff634400 + (0x01a << 2))
#define P_PREG_PAD_GPIO3_O (volatile uint32_t *)(0xff634400 + (0x01a << 2))
#define PREG_PAD_GPIO3_I (0xff634400 + (0x01b << 2))
#define SEC_PREG_PAD_GPIO3_I (0xff634400 + (0x01b << 2))
#define P_PREG_PAD_GPIO3_I (volatile uint32_t *)(0xff634400 + (0x01b << 2))
// ----------------------------
#define PREG_PAD_GPIO4_EN_N (0xff634400 + (0x01c << 2))
#define SEC_PREG_PAD_GPIO4_EN_N (0xff634400 + (0x01c << 2))
#define P_PREG_PAD_GPIO4_EN_N (volatile uint32_t *)(0xff634400 + (0x01c << 2))
#define PREG_PAD_GPIO4_O (0xff634400 + (0x01d << 2))
#define SEC_PREG_PAD_GPIO4_O (0xff634400 + (0x01d << 2))
#define P_PREG_PAD_GPIO4_O (volatile uint32_t *)(0xff634400 + (0x01d << 2))
#define PREG_PAD_GPIO4_I (0xff634400 + (0x01e << 2))
#define SEC_PREG_PAD_GPIO4_I (0xff634400 + (0x01e << 2))
#define P_PREG_PAD_GPIO4_I (volatile uint32_t *)(0xff634400 + (0x01e << 2))
// ----------------------------
#define PREG_PAD_GPIO5_EN_N (0xff634400 + (0x020 << 2))
#define SEC_PREG_PAD_GPIO5_EN_N (0xff634400 + (0x020 << 2))
#define P_PREG_PAD_GPIO5_EN_N (volatile uint32_t *)(0xff634400 + (0x020 << 2))
#define PREG_PAD_GPIO5_O (0xff634400 + (0x021 << 2))
#define SEC_PREG_PAD_GPIO5_O (0xff634400 + (0x021 << 2))
#define P_PREG_PAD_GPIO5_O (volatile uint32_t *)(0xff634400 + (0x021 << 2))
#define PREG_PAD_GPIO5_I (0xff634400 + (0x022 << 2))
#define SEC_PREG_PAD_GPIO5_I (0xff634400 + (0x022 << 2))
#define P_PREG_PAD_GPIO5_I (volatile uint32_t *)(0xff634400 + (0x022 << 2))
// ----------------------------
// ----------------------------
// Pad conntrols
// ----------------------------
//`define PAD_PULL_UP_REG6 8'h39
#define PAD_PULL_UP_REG0 (0xff634400 + (0x03a << 2))
#define SEC_PAD_PULL_UP_REG0 (0xff634400 + (0x03a << 2))
#define P_PAD_PULL_UP_REG0 (volatile uint32_t *)(0xff634400 + (0x03a << 2))
#define PAD_PULL_UP_REG1 (0xff634400 + (0x03b << 2))
#define SEC_PAD_PULL_UP_REG1 (0xff634400 + (0x03b << 2))
#define P_PAD_PULL_UP_REG1 (volatile uint32_t *)(0xff634400 + (0x03b << 2))
#define PAD_PULL_UP_REG2 (0xff634400 + (0x03c << 2))
#define SEC_PAD_PULL_UP_REG2 (0xff634400 + (0x03c << 2))
#define P_PAD_PULL_UP_REG2 (volatile uint32_t *)(0xff634400 + (0x03c << 2))
#define PAD_PULL_UP_REG3 (0xff634400 + (0x03d << 2))
#define SEC_PAD_PULL_UP_REG3 (0xff634400 + (0x03d << 2))
#define P_PAD_PULL_UP_REG3 (volatile uint32_t *)(0xff634400 + (0x03d << 2))
#define PAD_PULL_UP_REG4 (0xff634400 + (0x03e << 2))
#define SEC_PAD_PULL_UP_REG4 (0xff634400 + (0x03e << 2))
#define P_PAD_PULL_UP_REG4 (volatile uint32_t *)(0xff634400 + (0x03e << 2))
#define PAD_PULL_UP_REG5 (0xff634400 + (0x03f << 2))
#define SEC_PAD_PULL_UP_REG5 (0xff634400 + (0x03f << 2))
#define P_PAD_PULL_UP_REG5 (volatile uint32_t *)(0xff634400 + (0x03f << 2))
// ----------------------------
// Random (2)
// ----------------------------
//`define RAND64_ADDR0 8'h40 // DWORD base address (0xc1200138 >> 2)
//`define RAND64_ADDR1 8'h41 // DWORD base address (0xc120013c >> 2)
// ---------------------------
// Ethernet (1)
// ----------------------------
//`define PREG_ETHERNET_ADDR0 8'h42 // DWORD base address (0xc1200290 >> 2)
// ---------------------------
// AM_ANALOG_TOP
// ----------------------------
//`define PREG_AM_ANALOG_ADDR 8'h43 // DWORD base address (0xc1200298 >> 2)
// ---------------------------
// Mali55 (1)
// ----------------------------
//`define PREG_MALI_BYTE_CNTL 8'h44
// ---------------------------
// WIFI (1)
// ----------------------------
//`define PREG_WIFI_CNTL 8'h45
#define PAD_PULL_UP_EN_REG0 (0xff634400 + (0x048 << 2))
#define SEC_PAD_PULL_UP_EN_REG0 (0xff634400 + (0x048 << 2))
#define P_PAD_PULL_UP_EN_REG0 (volatile uint32_t *)(0xff634400 + (0x048 << 2))
#define PAD_PULL_UP_EN_REG1 (0xff634400 + (0x049 << 2))
#define SEC_PAD_PULL_UP_EN_REG1 (0xff634400 + (0x049 << 2))
#define P_PAD_PULL_UP_EN_REG1 (volatile uint32_t *)(0xff634400 + (0x049 << 2))
#define PAD_PULL_UP_EN_REG2 (0xff634400 + (0x04a << 2))
#define SEC_PAD_PULL_UP_EN_REG2 (0xff634400 + (0x04a << 2))
#define P_PAD_PULL_UP_EN_REG2 (volatile uint32_t *)(0xff634400 + (0x04a << 2))
#define PAD_PULL_UP_EN_REG3 (0xff634400 + (0x04b << 2))
#define SEC_PAD_PULL_UP_EN_REG3 (0xff634400 + (0x04b << 2))
#define P_PAD_PULL_UP_EN_REG3 (volatile uint32_t *)(0xff634400 + (0x04b << 2))
#define PAD_PULL_UP_EN_REG4 (0xff634400 + (0x04c << 2))
#define SEC_PAD_PULL_UP_EN_REG4 (0xff634400 + (0x04c << 2))
#define P_PAD_PULL_UP_EN_REG4 (volatile uint32_t *)(0xff634400 + (0x04c << 2))
#define PAD_PULL_UP_EN_REG5 (0xff634400 + (0x04d << 2))
#define SEC_PAD_PULL_UP_EN_REG5 (0xff634400 + (0x04d << 2))
#define P_PAD_PULL_UP_EN_REG5 (volatile uint32_t *)(0xff634400 + (0x04d << 2))
//`define PAD_PULL_UP_EN_REG6 8'h4e
// ---------------------------
#define PREG_ETH_REG0 (0xff634400 + (0x050 << 2))
#define SEC_PREG_ETH_REG0 (0xff634400 + (0x050 << 2))
#define P_PREG_ETH_REG0 (volatile uint32_t *)(0xff634400 + (0x050 << 2))
#define PREG_ETH_REG1 (0xff634400 + (0x051 << 2))
#define SEC_PREG_ETH_REG1 (0xff634400 + (0x051 << 2))
#define P_PREG_ETH_REG1 (volatile uint32_t *)(0xff634400 + (0x051 << 2))
#define PREG_NAND_CFG_KEY0 (0xff634400 + (0x052 << 2))
#define SEC_PREG_NAND_CFG_KEY0 (0xff634400 + (0x052 << 2))
#define P_PREG_NAND_CFG_KEY0 (volatile uint32_t *)(0xff634400 + (0x052 << 2))
#define PREG_NAND_CFG_KEY1 (0xff634400 + (0x053 << 2))
#define SEC_PREG_NAND_CFG_KEY1 (0xff634400 + (0x053 << 2))
#define P_PREG_NAND_CFG_KEY1 (volatile uint32_t *)(0xff634400 + (0x053 << 2))
#define PREG_VPU_SECURE0 (0xff634400 + (0x054 << 2))
#define SEC_PREG_VPU_SECURE0 (0xff634400 + (0x054 << 2))
#define P_PREG_VPU_SECURE0 (volatile uint32_t *)(0xff634400 + (0x054 << 2))
#define PREG_VPU_SECURE1 (0xff634400 + (0x055 << 2))
#define SEC_PREG_VPU_SECURE1 (0xff634400 + (0x055 << 2))
#define P_PREG_VPU_SECURE1 (volatile uint32_t *)(0xff634400 + (0x055 << 2))
#define PREG_ETH_REG2 (0xff634400 + (0x056 << 2))
#define SEC_PREG_ETH_REG2 (0xff634400 + (0x056 << 2))
#define P_PREG_ETH_REG2 (volatile uint32_t *)(0xff634400 + (0x056 << 2))
#define PREG_ETH_REG3 (0xff634400 + (0x057 << 2))
#define SEC_PREG_ETH_REG3 (0xff634400 + (0x057 << 2))
#define P_PREG_ETH_REG3 (volatile uint32_t *)(0xff634400 + (0x057 << 2))
#define PREG_ETH_REG4 (0xff634400 + (0x058 << 2))
#define SEC_PREG_ETH_REG4 (0xff634400 + (0x058 << 2))
#define P_PREG_ETH_REG4 (volatile uint32_t *)(0xff634400 + (0x058 << 2))
// ---------------------------
// Generic production test
// ----------------------------
#define PROD_TEST_REG0 (0xff634400 + (0x060 << 2))
#define SEC_PROD_TEST_REG0 (0xff634400 + (0x060 << 2))
#define P_PROD_TEST_REG0 (volatile uint32_t *)(0xff634400 + (0x060 << 2))
#define PROD_TEST_REG1 (0xff634400 + (0x061 << 2))
#define SEC_PROD_TEST_REG1 (0xff634400 + (0x061 << 2))
#define P_PROD_TEST_REG1 (volatile uint32_t *)(0xff634400 + (0x061 << 2))
#define PROD_TEST_REG2 (0xff634400 + (0x062 << 2))
#define SEC_PROD_TEST_REG2 (0xff634400 + (0x062 << 2))
#define P_PROD_TEST_REG2 (volatile uint32_t *)(0xff634400 + (0x062 << 2))
#define PROD_TEST_REG3 (0xff634400 + (0x063 << 2))
#define SEC_PROD_TEST_REG3 (0xff634400 + (0x063 << 2))
#define P_PROD_TEST_REG3 (volatile uint32_t *)(0xff634400 + (0x063 << 2))
// am_analog_top
// ----------------------------
//`define METAL_REVISION 8'h6a
//`define ADC_TOP_MISC 8'h6b
//`define DPLL_TOP_MISC 8'h6c
//`define ANALOG_TOP_MISC 8'h6d
//`define AM_ANALOG_TOP_REG0 8'h6e
//`define AM_ANALOG_TOP_REG1 8'h6f
// ---------------------------
// Sticky regs
// ----------------------------
#define PREG_STICKY_REG0 (0xff634400 + (0x070 << 2))
#define SEC_PREG_STICKY_REG0 (0xff634400 + (0x070 << 2))
#define P_PREG_STICKY_REG0 (volatile uint32_t *)(0xff634400 + (0x070 << 2))
#define PREG_STICKY_REG1 (0xff634400 + (0x071 << 2))
#define SEC_PREG_STICKY_REG1 (0xff634400 + (0x071 << 2))
#define P_PREG_STICKY_REG1 (volatile uint32_t *)(0xff634400 + (0x071 << 2))
#define PREG_STICKY_REG2 (0xff634400 + (0x072 << 2))
#define SEC_PREG_STICKY_REG2 (0xff634400 + (0x072 << 2))
#define P_PREG_STICKY_REG2 (volatile uint32_t *)(0xff634400 + (0x072 << 2))
#define PREG_STICKY_REG3 (0xff634400 + (0x073 << 2))
#define SEC_PREG_STICKY_REG3 (0xff634400 + (0x073 << 2))
#define P_PREG_STICKY_REG3 (volatile uint32_t *)(0xff634400 + (0x073 << 2))
#define PREG_STICKY_REG4 (0xff634400 + (0x074 << 2))
#define SEC_PREG_STICKY_REG4 (0xff634400 + (0x074 << 2))
#define P_PREG_STICKY_REG4 (volatile uint32_t *)(0xff634400 + (0x074 << 2))
#define PREG_STICKY_REG5 (0xff634400 + (0x075 << 2))
#define SEC_PREG_STICKY_REG5 (0xff634400 + (0x075 << 2))
#define P_PREG_STICKY_REG5 (volatile uint32_t *)(0xff634400 + (0x075 << 2))
#define PREG_STICKY_REG6 (0xff634400 + (0x076 << 2))
#define SEC_PREG_STICKY_REG6 (0xff634400 + (0x076 << 2))
#define P_PREG_STICKY_REG6 (volatile uint32_t *)(0xff634400 + (0x076 << 2))
#define PREG_STICKY_REG7 (0xff634400 + (0x077 << 2))
#define SEC_PREG_STICKY_REG7 (0xff634400 + (0x077 << 2))
#define P_PREG_STICKY_REG7 (volatile uint32_t *)(0xff634400 + (0x077 << 2))
#define PREG_STICKY_REG8 (0xff634400 + (0x078 << 2))
#define SEC_PREG_STICKY_REG8 (0xff634400 + (0x078 << 2))
#define P_PREG_STICKY_REG8 (volatile uint32_t *)(0xff634400 + (0x078 << 2))
#define PREG_STICKY_REG9 (0xff634400 + (0x079 << 2))
#define SEC_PREG_STICKY_REG9 (0xff634400 + (0x079 << 2))
#define P_PREG_STICKY_REG9 (volatile uint32_t *)(0xff634400 + (0x079 << 2))
//`define PREG_WRITE_ONCE_REG 8'h7e
// ---------------------------
// AM Ring Oscillator
// ----------------------------
#define AM_RING_OSC_REG0 (0xff634400 + (0x07f << 2))
#define SEC_AM_RING_OSC_REG0 (0xff634400 + (0x07f << 2))
#define P_AM_RING_OSC_REG0 (volatile uint32_t *)(0xff634400 + (0x07f << 2))
// Control whether to provide random number to HDMITX20
//`define HDMITX20_RNDNUM 8'h80
// ---------------------------
// Bus Monitoring
// ----------------------------
#define BUS_MONITOR_CNTL (0xff634400 + (0x081 << 2))
#define SEC_BUS_MONITOR_CNTL (0xff634400 + (0x081 << 2))
#define P_BUS_MONITOR_CNTL (volatile uint32_t *)(0xff634400 + (0x081 << 2))
#define BUS_MON0_ADDR (0xff634400 + (0x082 << 2))
#define SEC_BUS_MON0_ADDR (0xff634400 + (0x082 << 2))
#define P_BUS_MON0_ADDR (volatile uint32_t *)(0xff634400 + (0x082 << 2))
#define BUS_MON0_DATA (0xff634400 + (0x083 << 2))
#define SEC_BUS_MON0_DATA (0xff634400 + (0x083 << 2))
#define P_BUS_MON0_DATA (volatile uint32_t *)(0xff634400 + (0x083 << 2))
#define BUS_MON0_DATA_MSK (0xff634400 + (0x084 << 2))
#define SEC_BUS_MON0_DATA_MSK (0xff634400 + (0x084 << 2))
#define P_BUS_MON0_DATA_MSK (volatile uint32_t *)(0xff634400 + (0x084 << 2))
#define BUS_MON1_ADDR (0xff634400 + (0x085 << 2))
#define SEC_BUS_MON1_ADDR (0xff634400 + (0x085 << 2))
#define P_BUS_MON1_ADDR (volatile uint32_t *)(0xff634400 + (0x085 << 2))
#define BUS_MON1_DATA (0xff634400 + (0x086 << 2))
#define SEC_BUS_MON1_DATA (0xff634400 + (0x086 << 2))
#define P_BUS_MON1_DATA (volatile uint32_t *)(0xff634400 + (0x086 << 2))
#define BUS_MON1_DATA_MSK (0xff634400 + (0x087 << 2))
#define SEC_BUS_MON1_DATA_MSK (0xff634400 + (0x087 << 2))
#define P_BUS_MON1_DATA_MSK (volatile uint32_t *)(0xff634400 + (0x087 << 2))
#define ASYNC_FIFO_LOCK_ADR (0xff634400 + (0x088 << 2))
#define SEC_ASYNC_FIFO_LOCK_ADR (0xff634400 + (0x088 << 2))
#define P_ASYNC_FIFO_LOCK_ADR (volatile uint32_t *)(0xff634400 + (0x088 << 2))
#define SECE_TIMER_CTRL (0xff634400 + (0x089 << 2))
#define SEC_SECE_TIMER_CTRL (0xff634400 + (0x089 << 2))
#define P_SECE_TIMER_CTRL (volatile uint32_t *)(0xff634400 + (0x089 << 2))
#define SECE_TIMER_LOW (0xff634400 + (0x08a << 2))
#define SEC_SECE_TIMER_LOW (0xff634400 + (0x08a << 2))
#define P_SECE_TIMER_LOW (volatile uint32_t *)(0xff634400 + (0x08a << 2))
#define SECE_TIMER_HIG (0xff634400 + (0x08b << 2))
#define SEC_SECE_TIMER_HIG (0xff634400 + (0x08b << 2))
#define P_SECE_TIMER_HIG (volatile uint32_t *)(0xff634400 + (0x08b << 2))
// ---------------------------
// System CPU control registers
// ----------------------------
#define SYS_CPU_POR_CFG0 (0xff634400 + (0x090 << 2))
#define SEC_SYS_CPU_POR_CFG0 (0xff634400 + (0x090 << 2))
#define P_SYS_CPU_POR_CFG0 (volatile uint32_t *)(0xff634400 + (0x090 << 2))
#define SYS_CPU_POR_CFG1 (0xff634400 + (0x091 << 2))
#define SEC_SYS_CPU_POR_CFG1 (0xff634400 + (0x091 << 2))
#define P_SYS_CPU_POR_CFG1 (volatile uint32_t *)(0xff634400 + (0x091 << 2))
#define SYS_CPU_CFG0 (0xff634400 + (0x092 << 2))
#define SEC_SYS_CPU_CFG0 (0xff634400 + (0x092 << 2))
#define P_SYS_CPU_CFG0 (volatile uint32_t *)(0xff634400 + (0x092 << 2))
#define SYS_CPU_CFG1 (0xff634400 + (0x093 << 2))
#define SEC_SYS_CPU_CFG1 (0xff634400 + (0x093 << 2))
#define P_SYS_CPU_CFG1 (volatile uint32_t *)(0xff634400 + (0x093 << 2))
#define SYS_CPU_CFG2 (0xff634400 + (0x094 << 2))
#define SEC_SYS_CPU_CFG2 (0xff634400 + (0x094 << 2))
#define P_SYS_CPU_CFG2 (volatile uint32_t *)(0xff634400 + (0x094 << 2))
#define SYS_CPU_CFG3 (0xff634400 + (0x095 << 2))
#define SEC_SYS_CPU_CFG3 (0xff634400 + (0x095 << 2))
#define P_SYS_CPU_CFG3 (volatile uint32_t *)(0xff634400 + (0x095 << 2))
#define SYS_CPU_CFG4 (0xff634400 + (0x096 << 2))
#define SEC_SYS_CPU_CFG4 (0xff634400 + (0x096 << 2))
#define P_SYS_CPU_CFG4 (volatile uint32_t *)(0xff634400 + (0x096 << 2))
#define SYS_CPU_CFG5 (0xff634400 + (0x097 << 2))
#define SEC_SYS_CPU_CFG5 (0xff634400 + (0x097 << 2))
#define P_SYS_CPU_CFG5 (volatile uint32_t *)(0xff634400 + (0x097 << 2))
#define SYS_CPU_CFG6 (0xff634400 + (0x098 << 2))
#define SEC_SYS_CPU_CFG6 (0xff634400 + (0x098 << 2))
#define P_SYS_CPU_CFG6 (volatile uint32_t *)(0xff634400 + (0x098 << 2))
#define SYS_CPU_CFG7 (0xff634400 + (0x099 << 2))
#define SEC_SYS_CPU_CFG7 (0xff634400 + (0x099 << 2))
#define P_SYS_CPU_CFG7 (volatile uint32_t *)(0xff634400 + (0x099 << 2))
#define SYS_CPU_CFG8 (0xff634400 + (0x09a << 2))
#define SEC_SYS_CPU_CFG8 (0xff634400 + (0x09a << 2))
#define P_SYS_CPU_CFG8 (volatile uint32_t *)(0xff634400 + (0x09a << 2))
#define SYS_CPU_CFG9 (0xff634400 + (0x09b << 2))
#define SEC_SYS_CPU_CFG9 (0xff634400 + (0x09b << 2))
#define P_SYS_CPU_CFG9 (volatile uint32_t *)(0xff634400 + (0x09b << 2))
#define SYS_CPU_CFG10 (0xff634400 + (0x09c << 2))
#define SEC_SYS_CPU_CFG10 (0xff634400 + (0x09c << 2))
#define P_SYS_CPU_CFG10 (volatile uint32_t *)(0xff634400 + (0x09c << 2))
//`define SYS_CPU_CFG11 8'h9d
//`define SYS_CPU_CFG12 8'h9e
//`define SYS_CPU_CFG13 8'h9f
#define SYS_CPU_STATUS0 (0xff634400 + (0x0a0 << 2))
#define SEC_SYS_CPU_STATUS0 (0xff634400 + (0x0a0 << 2))
#define P_SYS_CPU_STATUS0 (volatile uint32_t *)(0xff634400 + (0x0a0 << 2))
#define SYS_CPU_STATUS1 (0xff634400 + (0x0a1 << 2))
#define SEC_SYS_CPU_STATUS1 (0xff634400 + (0x0a1 << 2))
#define P_SYS_CPU_STATUS1 (volatile uint32_t *)(0xff634400 + (0x0a1 << 2))
#define SYS_CPU_STATUS2 (0xff634400 + (0x0a2 << 2))
#define SEC_SYS_CPU_STATUS2 (0xff634400 + (0x0a2 << 2))
#define P_SYS_CPU_STATUS2 (volatile uint32_t *)(0xff634400 + (0x0a2 << 2))
#define SYS_CPU_STATUS3 (0xff634400 + (0x0a3 << 2))
#define SEC_SYS_CPU_STATUS3 (0xff634400 + (0x0a3 << 2))
#define P_SYS_CPU_STATUS3 (volatile uint32_t *)(0xff634400 + (0x0a3 << 2))
#define SYS_CPU_STATUS4 (0xff634400 + (0x0a4 << 2))
#define SEC_SYS_CPU_STATUS4 (0xff634400 + (0x0a4 << 2))
#define P_SYS_CPU_STATUS4 (volatile uint32_t *)(0xff634400 + (0x0a4 << 2))
#define SYS_CPU_STATUS5 (0xff634400 + (0x0a5 << 2))
#define SEC_SYS_CPU_STATUS5 (0xff634400 + (0x0a5 << 2))
#define P_SYS_CPU_STATUS5 (volatile uint32_t *)(0xff634400 + (0x0a5 << 2))
#define SYS_CPU_MISC (0xff634400 + (0x0a8 << 2))
#define SEC_SYS_CPU_MISC (0xff634400 + (0x0a8 << 2))
#define P_SYS_CPU_MISC (volatile uint32_t *)(0xff634400 + (0x0a8 << 2))
// ----------------------------
// Pin Mux (9)
// ----------------------------
#define PERIPHS_LOCK_PAD (0xff634400 + (0x0ae << 2))
#define SEC_PERIPHS_LOCK_PAD (0xff634400 + (0x0ae << 2))
#define P_PERIPHS_LOCK_PAD (volatile uint32_t *)(0xff634400 + (0x0ae << 2))
#define PERIPHS_LOCK_PIN_MUX (0xff634400 + (0x0af << 2))
#define SEC_PERIPHS_LOCK_PIN_MUX (0xff634400 + (0x0af << 2))
#define P_PERIPHS_LOCK_PIN_MUX (volatile uint32_t *)(0xff634400 + (0x0af << 2))
#define PERIPHS_PIN_MUX_0 (0xff634400 + (0x0b0 << 2))
#define SEC_PERIPHS_PIN_MUX_0 (0xff634400 + (0x0b0 << 2))
#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(0xff634400 + (0x0b0 << 2))
#define PERIPHS_PIN_MUX_1 (0xff634400 + (0x0b1 << 2))
#define SEC_PERIPHS_PIN_MUX_1 (0xff634400 + (0x0b1 << 2))
#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(0xff634400 + (0x0b1 << 2))
#define PERIPHS_PIN_MUX_2 (0xff634400 + (0x0b2 << 2))
#define SEC_PERIPHS_PIN_MUX_2 (0xff634400 + (0x0b2 << 2))
#define P_PERIPHS_PIN_MUX_2 (volatile uint32_t *)(0xff634400 + (0x0b2 << 2))
#define PERIPHS_PIN_MUX_3 (0xff634400 + (0x0b3 << 2))
#define SEC_PERIPHS_PIN_MUX_3 (0xff634400 + (0x0b3 << 2))
#define P_PERIPHS_PIN_MUX_3 (volatile uint32_t *)(0xff634400 + (0x0b3 << 2))
#define PERIPHS_PIN_MUX_4 (0xff634400 + (0x0b4 << 2))
#define SEC_PERIPHS_PIN_MUX_4 (0xff634400 + (0x0b4 << 2))
#define P_PERIPHS_PIN_MUX_4 (volatile uint32_t *)(0xff634400 + (0x0b4 << 2))
#define PERIPHS_PIN_MUX_5 (0xff634400 + (0x0b5 << 2))
#define SEC_PERIPHS_PIN_MUX_5 (0xff634400 + (0x0b5 << 2))
#define P_PERIPHS_PIN_MUX_5 (volatile uint32_t *)(0xff634400 + (0x0b5 << 2))
#define PERIPHS_PIN_MUX_6 (0xff634400 + (0x0b6 << 2))
#define SEC_PERIPHS_PIN_MUX_6 (0xff634400 + (0x0b6 << 2))
#define P_PERIPHS_PIN_MUX_6 (volatile uint32_t *)(0xff634400 + (0x0b6 << 2))
#define PERIPHS_PIN_MUX_7 (0xff634400 + (0x0b7 << 2))
#define SEC_PERIPHS_PIN_MUX_7 (0xff634400 + (0x0b7 << 2))
#define P_PERIPHS_PIN_MUX_7 (volatile uint32_t *)(0xff634400 + (0x0b7 << 2))
#define PERIPHS_PIN_MUX_8 (0xff634400 + (0x0b8 << 2))
#define SEC_PERIPHS_PIN_MUX_8 (0xff634400 + (0x0b8 << 2))
#define P_PERIPHS_PIN_MUX_8 (volatile uint32_t *)(0xff634400 + (0x0b8 << 2))
#define PERIPHS_PIN_MUX_9 (0xff634400 + (0x0b9 << 2))
#define SEC_PERIPHS_PIN_MUX_9 (0xff634400 + (0x0b9 << 2))
#define P_PERIPHS_PIN_MUX_9 (volatile uint32_t *)(0xff634400 + (0x0b9 << 2))
#define PERIPHS_PIN_MUX_A (0xff634400 + (0x0ba << 2))
#define SEC_PERIPHS_PIN_MUX_A (0xff634400 + (0x0ba << 2))
#define P_PERIPHS_PIN_MUX_A (volatile uint32_t *)(0xff634400 + (0x0ba << 2))
#define PERIPHS_PIN_MUX_B (0xff634400 + (0x0bb << 2))
#define SEC_PERIPHS_PIN_MUX_B (0xff634400 + (0x0bb << 2))
#define P_PERIPHS_PIN_MUX_B (volatile uint32_t *)(0xff634400 + (0x0bb << 2))
#define PERIPHS_PIN_MUX_C (0xff634400 + (0x0bc << 2))
#define SEC_PERIPHS_PIN_MUX_C (0xff634400 + (0x0bc << 2))
#define P_PERIPHS_PIN_MUX_C (volatile uint32_t *)(0xff634400 + (0x0bc << 2))
#define PERIPHS_PIN_MUX_D (0xff634400 + (0x0bd << 2))
#define SEC_PERIPHS_PIN_MUX_D (0xff634400 + (0x0bd << 2))
#define P_PERIPHS_PIN_MUX_D (volatile uint32_t *)(0xff634400 + (0x0bd << 2))
#define PERIPHS_PIN_MUX_E (0xff634400 + (0x0be << 2))
#define SEC_PERIPHS_PIN_MUX_E (0xff634400 + (0x0be << 2))
#define P_PERIPHS_PIN_MUX_E (volatile uint32_t *)(0xff634400 + (0x0be << 2))
#define PERIPHS_PIN_MUX_F (0xff634400 + (0x0bf << 2))
#define SEC_PERIPHS_PIN_MUX_F (0xff634400 + (0x0bf << 2))
#define P_PERIPHS_PIN_MUX_F (volatile uint32_t *)(0xff634400 + (0x0bf << 2))
#define EFUSE_CFG_LOCK (0xff634400 + (0x0c0 << 2))
#define SEC_EFUSE_CFG_LOCK (0xff634400 + (0x0c0 << 2))
#define P_EFUSE_CFG_LOCK (volatile uint32_t *)(0xff634400 + (0x0c0 << 2))
#define EFUSE_CLK_A53_CFG01 (0xff634400 + (0x0c1 << 2))
#define SEC_EFUSE_CLK_A53_CFG01 (0xff634400 + (0x0c1 << 2))
#define P_EFUSE_CLK_A53_CFG01 (volatile uint32_t *)(0xff634400 + (0x0c1 << 2))
#define EFUSE_CLK_A53_CFG2 (0xff634400 + (0x0c2 << 2))
#define SEC_EFUSE_CLK_A53_CFG2 (0xff634400 + (0x0c2 << 2))
#define P_EFUSE_CLK_A53_CFG2 (volatile uint32_t *)(0xff634400 + (0x0c2 << 2))
#define EFUSE_CLK_ENCP_CFG0 (0xff634400 + (0x0c3 << 2))
#define SEC_EFUSE_CLK_ENCP_CFG0 (0xff634400 + (0x0c3 << 2))
#define P_EFUSE_CLK_ENCP_CFG0 (volatile uint32_t *)(0xff634400 + (0x0c3 << 2))
#define EFUSE_CLK_MALI_CFG0 (0xff634400 + (0x0c4 << 2))
#define SEC_EFUSE_CLK_MALI_CFG0 (0xff634400 + (0x0c4 << 2))
#define P_EFUSE_CLK_MALI_CFG0 (volatile uint32_t *)(0xff634400 + (0x0c4 << 2))
#define EFUSE_CLK_HEVCB_CFG0 (0xff634400 + (0x0c5 << 2))
#define SEC_EFUSE_CLK_HEVCB_CFG0 (0xff634400 + (0x0c5 << 2))
#define P_EFUSE_CLK_HEVCB_CFG0 (volatile uint32_t *)(0xff634400 + (0x0c5 << 2))
#define PAD_DS_REG0A (0xff634400 + (0x0d0 << 2))
#define SEC_PAD_DS_REG0A (0xff634400 + (0x0d0 << 2))
#define P_PAD_DS_REG0A (volatile uint32_t *)(0xff634400 + (0x0d0 << 2))
#define PAD_DS_REG1A (0xff634400 + (0x0d1 << 2))
#define SEC_PAD_DS_REG1A (0xff634400 + (0x0d1 << 2))
#define P_PAD_DS_REG1A (volatile uint32_t *)(0xff634400 + (0x0d1 << 2))
#define PAD_DS_REG2A (0xff634400 + (0x0d2 << 2))
#define SEC_PAD_DS_REG2A (0xff634400 + (0x0d2 << 2))
#define P_PAD_DS_REG2A (volatile uint32_t *)(0xff634400 + (0x0d2 << 2))
#define PAD_DS_REG2B (0xff634400 + (0x0d3 << 2))
#define SEC_PAD_DS_REG2B (0xff634400 + (0x0d3 << 2))
#define P_PAD_DS_REG2B (volatile uint32_t *)(0xff634400 + (0x0d3 << 2))
#define PAD_DS_REG3A (0xff634400 + (0x0d4 << 2))
#define SEC_PAD_DS_REG3A (0xff634400 + (0x0d4 << 2))
#define P_PAD_DS_REG3A (volatile uint32_t *)(0xff634400 + (0x0d4 << 2))
#define PAD_DS_REG4A (0xff634400 + (0x0d5 << 2))
#define SEC_PAD_DS_REG4A (0xff634400 + (0x0d5 << 2))
#define P_PAD_DS_REG4A (volatile uint32_t *)(0xff634400 + (0x0d5 << 2))
#define PAD_DS_REG5A (0xff634400 + (0x0d6 << 2))
#define SEC_PAD_DS_REG5A (0xff634400 + (0x0d6 << 2))
#define P_PAD_DS_REG5A (volatile uint32_t *)(0xff634400 + (0x0d6 << 2))
//========================================================================
// RESET_SEC - Registers
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF64E000
// APB4_DECODER_SECURE_BASE 32'hFF64E000
#define RESET0_SEC_REGISTER (0xff64e000 + (0x000 << 2))
#define SEC_RESET0_SEC_REGISTER (0xff64e000 + (0x000 << 2))
#define P_RESET0_SEC_REGISTER (volatile uint32_t *)(0xff64e000 + (0x000 << 2))
#define RESET1_SEC_REGISTER (0xff64e000 + (0x001 << 2))
#define SEC_RESET1_SEC_REGISTER (0xff64e000 + (0x001 << 2))
#define P_RESET1_SEC_REGISTER (volatile uint32_t *)(0xff64e000 + (0x001 << 2))
#define RESET2_SEC_REGISTER (0xff64e000 + (0x002 << 2))
#define SEC_RESET2_SEC_REGISTER (0xff64e000 + (0x002 << 2))
#define P_RESET2_SEC_REGISTER (volatile uint32_t *)(0xff64e000 + (0x002 << 2))
#define RESET0_SEC_LEVEL (0xff64e000 + (0x010 << 2))
#define SEC_RESET0_SEC_LEVEL (0xff64e000 + (0x010 << 2))
#define P_RESET0_SEC_LEVEL (volatile uint32_t *)(0xff64e000 + (0x010 << 2))
#define RESET1_SEC_LEVEL (0xff64e000 + (0x011 << 2))
#define SEC_RESET1_SEC_LEVEL (0xff64e000 + (0x011 << 2))
#define P_RESET1_SEC_LEVEL (volatile uint32_t *)(0xff64e000 + (0x011 << 2))
#define RESET2_SEC_LEVEL (0xff64e000 + (0x012 << 2))
#define SEC_RESET2_SEC_LEVEL (0xff64e000 + (0x012 << 2))
#define P_RESET2_SEC_LEVEL (volatile uint32_t *)(0xff64e000 + (0x012 << 2))
#define RESET0_SEC_MASK (0xff64e000 + (0x020 << 2))
#define SEC_RESET0_SEC_MASK (0xff64e000 + (0x020 << 2))
#define P_RESET0_SEC_MASK (volatile uint32_t *)(0xff64e000 + (0x020 << 2))
#define RESET1_SEC_MASK (0xff64e000 + (0x021 << 2))
#define SEC_RESET1_SEC_MASK (0xff64e000 + (0x021 << 2))
#define P_RESET1_SEC_MASK (volatile uint32_t *)(0xff64e000 + (0x021 << 2))
#define RESET2_SEC_MASK (0xff64e000 + (0x022 << 2))
#define SEC_RESET2_SEC_MASK (0xff64e000 + (0x022 << 2))
#define P_RESET2_SEC_MASK (volatile uint32_t *)(0xff64e000 + (0x022 << 2))
//========================================================================
// AUDIO locker - Registers
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF64a000
// APB4_DECODER_SECURE_BASE 32'hFF64a000
#define AUD_LOCK_EN (0xff64a000 + (0x000 << 2))
#define SEC_AUD_LOCK_EN (0xff64a000 + (0x000 << 2))
#define P_AUD_LOCK_EN (volatile uint32_t *)(0xff64a000 + (0x000 << 2))
#define AUD_LOCK_SW_RESET (0xff64a000 + (0x001 << 2))
#define SEC_AUD_LOCK_SW_RESET (0xff64a000 + (0x001 << 2))
#define P_AUD_LOCK_SW_RESET (volatile uint32_t *)(0xff64a000 + (0x001 << 2))
#define AUD_LOCK_SW_LATCH (0xff64a000 + (0x002 << 2))
#define SEC_AUD_LOCK_SW_LATCH (0xff64a000 + (0x002 << 2))
#define P_AUD_LOCK_SW_LATCH (volatile uint32_t *)(0xff64a000 + (0x002 << 2))
#define AUD_LOCK_HW_LATCH (0xff64a000 + (0x003 << 2))
#define SEC_AUD_LOCK_HW_LATCH (0xff64a000 + (0x003 << 2))
#define P_AUD_LOCK_HW_LATCH (volatile uint32_t *)(0xff64a000 + (0x003 << 2))
#define AUD_LOCK_REFCLK_SRC (0xff64a000 + (0x004 << 2))
#define SEC_AUD_LOCK_REFCLK_SRC (0xff64a000 + (0x004 << 2))
#define P_AUD_LOCK_REFCLK_SRC (volatile uint32_t *)(0xff64a000 + (0x004 << 2))
#define AUD_LOCK_REFCLK_LAT_INT (0xff64a000 + (0x005 << 2))
#define SEC_AUD_LOCK_REFCLK_LAT_INT (0xff64a000 + (0x005 << 2))
#define P_AUD_LOCK_REFCLK_LAT_INT (volatile uint32_t *)(0xff64a000 + (0x005 << 2))
#define AUD_LOCK_IMCLK_LAT_INT (0xff64a000 + (0x006 << 2))
#define SEC_AUD_LOCK_IMCLK_LAT_INT (0xff64a000 + (0x006 << 2))
#define P_AUD_LOCK_IMCLK_LAT_INT (volatile uint32_t *)(0xff64a000 + (0x006 << 2))
#define AUD_LOCK_OMCLK_LAT_INT (0xff64a000 + (0x007 << 2))
#define SEC_AUD_LOCK_OMCLK_LAT_INT (0xff64a000 + (0x007 << 2))
#define P_AUD_LOCK_OMCLK_LAT_INT (volatile uint32_t *)(0xff64a000 + (0x007 << 2))
#define AUD_LOCK_REFCLK_DS_INT (0xff64a000 + (0x008 << 2))
#define SEC_AUD_LOCK_REFCLK_DS_INT (0xff64a000 + (0x008 << 2))
#define P_AUD_LOCK_REFCLK_DS_INT (volatile uint32_t *)(0xff64a000 + (0x008 << 2))
#define AUD_LOCK_IMCLK_DS_INT (0xff64a000 + (0x009 << 2))
#define SEC_AUD_LOCK_IMCLK_DS_INT (0xff64a000 + (0x009 << 2))
#define P_AUD_LOCK_IMCLK_DS_INT (volatile uint32_t *)(0xff64a000 + (0x009 << 2))
#define AUD_LOCK_OMCLK_DS_INT (0xff64a000 + (0x00a << 2))
#define SEC_AUD_LOCK_OMCLK_DS_INT (0xff64a000 + (0x00a << 2))
#define P_AUD_LOCK_OMCLK_DS_INT (volatile uint32_t *)(0xff64a000 + (0x00a << 2))
#define AUD_LOCK_INT_CLR (0xff64a000 + (0x00b << 2))
#define SEC_AUD_LOCK_INT_CLR (0xff64a000 + (0x00b << 2))
#define P_AUD_LOCK_INT_CLR (volatile uint32_t *)(0xff64a000 + (0x00b << 2))
#define AUD_LOCK_GCLK_CTRL (0xff64a000 + (0x00c << 2))
#define SEC_AUD_LOCK_GCLK_CTRL (0xff64a000 + (0x00c << 2))
#define P_AUD_LOCK_GCLK_CTRL (volatile uint32_t *)(0xff64a000 + (0x00c << 2))
#define AUD_LOCK_INT_CTRL (0xff64a000 + (0x00d << 2))
#define SEC_AUD_LOCK_INT_CTRL (0xff64a000 + (0x00d << 2))
#define P_AUD_LOCK_INT_CTRL (volatile uint32_t *)(0xff64a000 + (0x00d << 2))
#define RO_REF2IMCLK_CNT_L (0xff64a000 + (0x010 << 2))
#define SEC_RO_REF2IMCLK_CNT_L (0xff64a000 + (0x010 << 2))
#define P_RO_REF2IMCLK_CNT_L (volatile uint32_t *)(0xff64a000 + (0x010 << 2))
#define RO_REF2IMCLK_CNT_H (0xff64a000 + (0x011 << 2))
#define SEC_RO_REF2IMCLK_CNT_H (0xff64a000 + (0x011 << 2))
#define P_RO_REF2IMCLK_CNT_H (volatile uint32_t *)(0xff64a000 + (0x011 << 2))
#define RO_REF2OMCLK_CNT_L (0xff64a000 + (0x012 << 2))
#define SEC_RO_REF2OMCLK_CNT_L (0xff64a000 + (0x012 << 2))
#define P_RO_REF2OMCLK_CNT_L (volatile uint32_t *)(0xff64a000 + (0x012 << 2))
#define RO_REF2OMCLK_CNT_H (0xff64a000 + (0x013 << 2))
#define SEC_RO_REF2OMCLK_CNT_H (0xff64a000 + (0x013 << 2))
#define P_RO_REF2OMCLK_CNT_H (volatile uint32_t *)(0xff64a000 + (0x013 << 2))
#define RO_IMCLK2REF_CNT_L (0xff64a000 + (0x014 << 2))
#define SEC_RO_IMCLK2REF_CNT_L (0xff64a000 + (0x014 << 2))
#define P_RO_IMCLK2REF_CNT_L (volatile uint32_t *)(0xff64a000 + (0x014 << 2))
#define RO_IMCLK2REF_CNT_H (0xff64a000 + (0x015 << 2))
#define SEC_RO_IMCLK2REF_CNT_H (0xff64a000 + (0x015 << 2))
#define P_RO_IMCLK2REF_CNT_H (volatile uint32_t *)(0xff64a000 + (0x015 << 2))
#define RO_OMCLK2REF_CNT_L (0xff64a000 + (0x016 << 2))
#define SEC_RO_OMCLK2REF_CNT_L (0xff64a000 + (0x016 << 2))
#define P_RO_OMCLK2REF_CNT_L (volatile uint32_t *)(0xff64a000 + (0x016 << 2))
#define RO_OMCLK2REF_CNT_H (0xff64a000 + (0x017 << 2))
#define SEC_RO_OMCLK2REF_CNT_H (0xff64a000 + (0x017 << 2))
#define P_RO_OMCLK2REF_CNT_H (volatile uint32_t *)(0xff64a000 + (0x017 << 2))
#define RO_REFCLK_PKG_CNT (0xff64a000 + (0x018 << 2))
#define SEC_RO_REFCLK_PKG_CNT (0xff64a000 + (0x018 << 2))
#define P_RO_REFCLK_PKG_CNT (volatile uint32_t *)(0xff64a000 + (0x018 << 2))
#define RO_IMCLK_PKG_CNT (0xff64a000 + (0x019 << 2))
#define SEC_RO_IMCLK_PKG_CNT (0xff64a000 + (0x019 << 2))
#define P_RO_IMCLK_PKG_CNT (volatile uint32_t *)(0xff64a000 + (0x019 << 2))
#define RO_OMCLK_PKG_CNT (0xff64a000 + (0x01a << 2))
#define SEC_RO_OMCLK_PKG_CNT (0xff64a000 + (0x01a << 2))
#define P_RO_OMCLK_PKG_CNT (volatile uint32_t *)(0xff64a000 + (0x01a << 2))
#define RO_AUD_LOCK_INT_STATUS (0xff64a000 + (0x01b << 2))
#define SEC_RO_AUD_LOCK_INT_STATUS (0xff64a000 + (0x01b << 2))
#define P_RO_AUD_LOCK_INT_STATUS (volatile uint32_t *)(0xff64a000 + (0x01b << 2))
//========================================================================
// AUDIO - Registers
//========================================================================
// APB4_DECODER_NON_SECURE_BASE 32'hFF642000
// APB4_DECODER_SECURE_BASE 32'hFF642000
#define EE_AUDIO_CLK_GATE_EN (0xff642000 + (0x000 << 2))
#define SEC_EE_AUDIO_CLK_GATE_EN (0xff642000 + (0x000 << 2))
#define P_EE_AUDIO_CLK_GATE_EN (volatile uint32_t *)(0xff642000 + (0x000 << 2))
#define EE_AUDIO_MCLK_A_CTRL (0xff642000 + (0x001 << 2))
#define SEC_EE_AUDIO_MCLK_A_CTRL (0xff642000 + (0x001 << 2))
#define P_EE_AUDIO_MCLK_A_CTRL (volatile uint32_t *)(0xff642000 + (0x001 << 2))
#define EE_AUDIO_MCLK_B_CTRL (0xff642000 + (0x002 << 2))
#define SEC_EE_AUDIO_MCLK_B_CTRL (0xff642000 + (0x002 << 2))
#define P_EE_AUDIO_MCLK_B_CTRL (volatile uint32_t *)(0xff642000 + (0x002 << 2))
#define EE_AUDIO_MCLK_C_CTRL (0xff642000 + (0x003 << 2))
#define SEC_EE_AUDIO_MCLK_C_CTRL (0xff642000 + (0x003 << 2))
#define P_EE_AUDIO_MCLK_C_CTRL (volatile uint32_t *)(0xff642000 + (0x003 << 2))
#define EE_AUDIO_MCLK_D_CTRL (0xff642000 + (0x004 << 2))
#define SEC_EE_AUDIO_MCLK_D_CTRL (0xff642000 + (0x004 << 2))
#define P_EE_AUDIO_MCLK_D_CTRL (volatile uint32_t *)(0xff642000 + (0x004 << 2))
#define EE_AUDIO_MCLK_E_CTRL (0xff642000 + (0x005 << 2))
#define SEC_EE_AUDIO_MCLK_E_CTRL (0xff642000 + (0x005 << 2))
#define P_EE_AUDIO_MCLK_E_CTRL (volatile uint32_t *)(0xff642000 + (0x005 << 2))
#define EE_AUDIO_MCLK_F_CTRL (0xff642000 + (0x006 << 2))
#define SEC_EE_AUDIO_MCLK_F_CTRL (0xff642000 + (0x006 << 2))
#define P_EE_AUDIO_MCLK_F_CTRL (volatile uint32_t *)(0xff642000 + (0x006 << 2))
#define EE_AUDIO_PAD_CTRL0 (0xff642000 + (0x007 << 2))
#define SEC_EE_AUDIO_PAD_CTRL0 (0xff642000 + (0x007 << 2))
#define P_EE_AUDIO_PAD_CTRL0 (volatile uint32_t *)(0xff642000 + (0x007 << 2))
#define EE_AUDIO_PAD_CTRL1 (0xff642000 + (0x008 << 2))
#define SEC_EE_AUDIO_PAD_CTRL1 (0xff642000 + (0x008 << 2))
#define P_EE_AUDIO_PAD_CTRL1 (volatile uint32_t *)(0xff642000 + (0x008 << 2))
#define EE_AUDIO_SW_RESET (0xff642000 + (0x009 << 2))
#define SEC_EE_AUDIO_SW_RESET (0xff642000 + (0x009 << 2))
#define P_EE_AUDIO_SW_RESET (volatile uint32_t *)(0xff642000 + (0x009 << 2))
#define EE_AUDIO_MST_A_SCLK_CTRL0 (0xff642000 + (0x010 << 2))
#define SEC_EE_AUDIO_MST_A_SCLK_CTRL0 (0xff642000 + (0x010 << 2))
#define P_EE_AUDIO_MST_A_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x010 << 2))
#define EE_AUDIO_MST_A_SCLK_CTRL1 (0xff642000 + (0x011 << 2))
#define SEC_EE_AUDIO_MST_A_SCLK_CTRL1 (0xff642000 + (0x011 << 2))
#define P_EE_AUDIO_MST_A_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x011 << 2))
#define EE_AUDIO_MST_B_SCLK_CTRL0 (0xff642000 + (0x012 << 2))
#define SEC_EE_AUDIO_MST_B_SCLK_CTRL0 (0xff642000 + (0x012 << 2))
#define P_EE_AUDIO_MST_B_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x012 << 2))
#define EE_AUDIO_MST_B_SCLK_CTRL1 (0xff642000 + (0x013 << 2))
#define SEC_EE_AUDIO_MST_B_SCLK_CTRL1 (0xff642000 + (0x013 << 2))
#define P_EE_AUDIO_MST_B_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x013 << 2))
#define EE_AUDIO_MST_C_SCLK_CTRL0 (0xff642000 + (0x014 << 2))
#define SEC_EE_AUDIO_MST_C_SCLK_CTRL0 (0xff642000 + (0x014 << 2))
#define P_EE_AUDIO_MST_C_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x014 << 2))
#define EE_AUDIO_MST_C_SCLK_CTRL1 (0xff642000 + (0x015 << 2))
#define SEC_EE_AUDIO_MST_C_SCLK_CTRL1 (0xff642000 + (0x015 << 2))
#define P_EE_AUDIO_MST_C_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x015 << 2))
#define EE_AUDIO_MST_D_SCLK_CTRL0 (0xff642000 + (0x016 << 2))
#define SEC_EE_AUDIO_MST_D_SCLK_CTRL0 (0xff642000 + (0x016 << 2))
#define P_EE_AUDIO_MST_D_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x016 << 2))
#define EE_AUDIO_MST_D_SCLK_CTRL1 (0xff642000 + (0x017 << 2))
#define SEC_EE_AUDIO_MST_D_SCLK_CTRL1 (0xff642000 + (0x017 << 2))
#define P_EE_AUDIO_MST_D_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x017 << 2))
#define EE_AUDIO_MST_E_SCLK_CTRL0 (0xff642000 + (0x018 << 2))
#define SEC_EE_AUDIO_MST_E_SCLK_CTRL0 (0xff642000 + (0x018 << 2))
#define P_EE_AUDIO_MST_E_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x018 << 2))
#define EE_AUDIO_MST_E_SCLK_CTRL1 (0xff642000 + (0x019 << 2))
#define SEC_EE_AUDIO_MST_E_SCLK_CTRL1 (0xff642000 + (0x019 << 2))
#define P_EE_AUDIO_MST_E_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x019 << 2))
#define EE_AUDIO_MST_F_SCLK_CTRL0 (0xff642000 + (0x01a << 2))
#define SEC_EE_AUDIO_MST_F_SCLK_CTRL0 (0xff642000 + (0x01a << 2))
#define P_EE_AUDIO_MST_F_SCLK_CTRL0 (volatile uint32_t *)(0xff642000 + (0x01a << 2))
#define EE_AUDIO_MST_F_SCLK_CTRL1 (0xff642000 + (0x01b << 2))
#define SEC_EE_AUDIO_MST_F_SCLK_CTRL1 (0xff642000 + (0x01b << 2))
#define P_EE_AUDIO_MST_F_SCLK_CTRL1 (volatile uint32_t *)(0xff642000 + (0x01b << 2))
#define EE_AUDIO_CLK_TDMIN_A_CTRL (0xff642000 + (0x020 << 2))
#define SEC_EE_AUDIO_CLK_TDMIN_A_CTRL (0xff642000 + (0x020 << 2))
#define P_EE_AUDIO_CLK_TDMIN_A_CTRL (volatile uint32_t *)(0xff642000 + (0x020 << 2))
#define EE_AUDIO_CLK_TDMIN_B_CTRL (0xff642000 + (0x021 << 2))
#define SEC_EE_AUDIO_CLK_TDMIN_B_CTRL (0xff642000 + (0x021 << 2))
#define P_EE_AUDIO_CLK_TDMIN_B_CTRL (volatile uint32_t *)(0xff642000 + (0x021 << 2))
#define EE_AUDIO_CLK_TDMIN_C_CTRL (0xff642000 + (0x022 << 2))
#define SEC_EE_AUDIO_CLK_TDMIN_C_CTRL (0xff642000 + (0x022 << 2))
#define P_EE_AUDIO_CLK_TDMIN_C_CTRL (volatile uint32_t *)(0xff642000 + (0x022 << 2))
#define EE_AUDIO_CLK_TDMIN_LB_CTRL (0xff642000 + (0x023 << 2))
#define SEC_EE_AUDIO_CLK_TDMIN_LB_CTRL (0xff642000 + (0x023 << 2))
#define P_EE_AUDIO_CLK_TDMIN_LB_CTRL (volatile uint32_t *)(0xff642000 + (0x023 << 2))
#define EE_AUDIO_CLK_TDMOUT_A_CTRL (0xff642000 + (0x024 << 2))
#define SEC_EE_AUDIO_CLK_TDMOUT_A_CTRL (0xff642000 + (0x024 << 2))
#define P_EE_AUDIO_CLK_TDMOUT_A_CTRL (volatile uint32_t *)(0xff642000 + (0x024 << 2))
#define EE_AUDIO_CLK_TDMOUT_B_CTRL (0xff642000 + (0x025 << 2))
#define SEC_EE_AUDIO_CLK_TDMOUT_B_CTRL (0xff642000 + (0x025 << 2))
#define P_EE_AUDIO_CLK_TDMOUT_B_CTRL (volatile uint32_t *)(0xff642000 + (0x025 << 2))
#define EE_AUDIO_CLK_TDMOUT_C_CTRL (0xff642000 + (0x026 << 2))
#define SEC_EE_AUDIO_CLK_TDMOUT_C_CTRL (0xff642000 + (0x026 << 2))
#define P_EE_AUDIO_CLK_TDMOUT_C_CTRL (volatile uint32_t *)(0xff642000 + (0x026 << 2))
#define EE_AUDIO_CLK_SPDIFIN_CTRL (0xff642000 + (0x027 << 2))
#define SEC_EE_AUDIO_CLK_SPDIFIN_CTRL (0xff642000 + (0x027 << 2))
#define P_EE_AUDIO_CLK_SPDIFIN_CTRL (volatile uint32_t *)(0xff642000 + (0x027 << 2))
#define EE_AUDIO_CLK_SPDIFOUT_CTRL (0xff642000 + (0x028 << 2))
#define SEC_EE_AUDIO_CLK_SPDIFOUT_CTRL (0xff642000 + (0x028 << 2))
#define P_EE_AUDIO_CLK_SPDIFOUT_CTRL (volatile uint32_t *)(0xff642000 + (0x028 << 2))
#define EE_AUDIO_CLK_RESAMPLE_CTRL (0xff642000 + (0x029 << 2))
#define SEC_EE_AUDIO_CLK_RESAMPLE_CTRL (0xff642000 + (0x029 << 2))
#define P_EE_AUDIO_CLK_RESAMPLE_CTRL (volatile uint32_t *)(0xff642000 + (0x029 << 2))
#define EE_AUDIO_CLK_LOCKER_CTRL (0xff642000 + (0x02a << 2))
#define SEC_EE_AUDIO_CLK_LOCKER_CTRL (0xff642000 + (0x02a << 2))
#define P_EE_AUDIO_CLK_LOCKER_CTRL (volatile uint32_t *)(0xff642000 + (0x02a << 2))
#define EE_AUDIO_CLK_PDMIN_CTRL0 (0xff642000 + (0x02b << 2))
#define SEC_EE_AUDIO_CLK_PDMIN_CTRL0 (0xff642000 + (0x02b << 2))
#define P_EE_AUDIO_CLK_PDMIN_CTRL0 (volatile uint32_t *)(0xff642000 + (0x02b << 2))
#define EE_AUDIO_CLK_PDMIN_CTRL1 (0xff642000 + (0x02c << 2))
#define SEC_EE_AUDIO_CLK_PDMIN_CTRL1 (0xff642000 + (0x02c << 2))
#define P_EE_AUDIO_CLK_PDMIN_CTRL1 (volatile uint32_t *)(0xff642000 + (0x02c << 2))
#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL (0xff642000 + (0x02d << 2))
#define SEC_EE_AUDIO_CLK_SPDIFOUT_B_CTRL (0xff642000 + (0x02d << 2))
#define P_EE_AUDIO_CLK_SPDIFOUT_B_CTRL (volatile uint32_t *)(0xff642000 + (0x02d << 2))
#define EE_AUDIO_TODDR_A_CTRL0 (0xff642000 + (0x040 << 2))
#define SEC_EE_AUDIO_TODDR_A_CTRL0 (0xff642000 + (0x040 << 2))
#define P_EE_AUDIO_TODDR_A_CTRL0 (volatile uint32_t *)(0xff642000 + (0x040 << 2))
#define EE_AUDIO_TODDR_A_CTRL1 (0xff642000 + (0x041 << 2))
#define SEC_EE_AUDIO_TODDR_A_CTRL1 (0xff642000 + (0x041 << 2))
#define P_EE_AUDIO_TODDR_A_CTRL1 (volatile uint32_t *)(0xff642000 + (0x041 << 2))
#define EE_AUDIO_TODDR_A_START_ADDR (0xff642000 + (0x042 << 2))
#define SEC_EE_AUDIO_TODDR_A_START_ADDR (0xff642000 + (0x042 << 2))
#define P_EE_AUDIO_TODDR_A_START_ADDR (volatile uint32_t *)(0xff642000 + (0x042 << 2))
#define EE_AUDIO_TODDR_A_FINISH_ADDR (0xff642000 + (0x043 << 2))
#define SEC_EE_AUDIO_TODDR_A_FINISH_ADDR (0xff642000 + (0x043 << 2))
#define P_EE_AUDIO_TODDR_A_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x043 << 2))
#define EE_AUDIO_TODDR_A_INT_ADDR (0xff642000 + (0x044 << 2))
#define SEC_EE_AUDIO_TODDR_A_INT_ADDR (0xff642000 + (0x044 << 2))
#define P_EE_AUDIO_TODDR_A_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x044 << 2))
#define EE_AUDIO_TODDR_A_STATUS1 (0xff642000 + (0x045 << 2))
#define SEC_EE_AUDIO_TODDR_A_STATUS1 (0xff642000 + (0x045 << 2))
#define P_EE_AUDIO_TODDR_A_STATUS1 (volatile uint32_t *)(0xff642000 + (0x045 << 2))
#define EE_AUDIO_TODDR_A_STATUS2 (0xff642000 + (0x046 << 2))
#define SEC_EE_AUDIO_TODDR_A_STATUS2 (0xff642000 + (0x046 << 2))
#define P_EE_AUDIO_TODDR_A_STATUS2 (volatile uint32_t *)(0xff642000 + (0x046 << 2))
#define EE_AUDIO_TODDR_A_START_ADDRB (0xff642000 + (0x047 << 2))
#define SEC_EE_AUDIO_TODDR_A_START_ADDRB (0xff642000 + (0x047 << 2))
#define P_EE_AUDIO_TODDR_A_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x047 << 2))
#define EE_AUDIO_TODDR_A_FINISH_ADDRB (0xff642000 + (0x048 << 2))
#define SEC_EE_AUDIO_TODDR_A_FINISH_ADDRB (0xff642000 + (0x048 << 2))
#define P_EE_AUDIO_TODDR_A_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x048 << 2))
#define EE_AUDIO_TODDR_A_INIT_ADDR (0xff642000 + (0x049 << 2))
#define SEC_EE_AUDIO_TODDR_A_INIT_ADDR (0xff642000 + (0x049 << 2))
#define P_EE_AUDIO_TODDR_A_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x049 << 2))
#define EE_AUDIO_TODDR_B_CTRL0 (0xff642000 + (0x050 << 2))
#define SEC_EE_AUDIO_TODDR_B_CTRL0 (0xff642000 + (0x050 << 2))
#define P_EE_AUDIO_TODDR_B_CTRL0 (volatile uint32_t *)(0xff642000 + (0x050 << 2))
#define EE_AUDIO_TODDR_B_CTRL1 (0xff642000 + (0x051 << 2))
#define SEC_EE_AUDIO_TODDR_B_CTRL1 (0xff642000 + (0x051 << 2))
#define P_EE_AUDIO_TODDR_B_CTRL1 (volatile uint32_t *)(0xff642000 + (0x051 << 2))
#define EE_AUDIO_TODDR_B_START_ADDR (0xff642000 + (0x052 << 2))
#define SEC_EE_AUDIO_TODDR_B_START_ADDR (0xff642000 + (0x052 << 2))
#define P_EE_AUDIO_TODDR_B_START_ADDR (volatile uint32_t *)(0xff642000 + (0x052 << 2))
#define EE_AUDIO_TODDR_B_FINISH_ADDR (0xff642000 + (0x053 << 2))
#define SEC_EE_AUDIO_TODDR_B_FINISH_ADDR (0xff642000 + (0x053 << 2))
#define P_EE_AUDIO_TODDR_B_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x053 << 2))
#define EE_AUDIO_TODDR_B_INT_ADDR (0xff642000 + (0x054 << 2))
#define SEC_EE_AUDIO_TODDR_B_INT_ADDR (0xff642000 + (0x054 << 2))
#define P_EE_AUDIO_TODDR_B_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x054 << 2))
#define EE_AUDIO_TODDR_B_STATUS1 (0xff642000 + (0x055 << 2))
#define SEC_EE_AUDIO_TODDR_B_STATUS1 (0xff642000 + (0x055 << 2))
#define P_EE_AUDIO_TODDR_B_STATUS1 (volatile uint32_t *)(0xff642000 + (0x055 << 2))
#define EE_AUDIO_TODDR_B_STATUS2 (0xff642000 + (0x056 << 2))
#define SEC_EE_AUDIO_TODDR_B_STATUS2 (0xff642000 + (0x056 << 2))
#define P_EE_AUDIO_TODDR_B_STATUS2 (volatile uint32_t *)(0xff642000 + (0x056 << 2))
#define EE_AUDIO_TODDR_B_START_ADDRB (0xff642000 + (0x057 << 2))
#define SEC_EE_AUDIO_TODDR_B_START_ADDRB (0xff642000 + (0x057 << 2))
#define P_EE_AUDIO_TODDR_B_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x057 << 2))
#define EE_AUDIO_TODDR_B_FINISH_ADDRB (0xff642000 + (0x058 << 2))
#define SEC_EE_AUDIO_TODDR_B_FINISH_ADDRB (0xff642000 + (0x058 << 2))
#define P_EE_AUDIO_TODDR_B_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x058 << 2))
#define EE_AUDIO_TODDR_B_INIT_ADDR (0xff642000 + (0x059 << 2))
#define SEC_EE_AUDIO_TODDR_B_INIT_ADDR (0xff642000 + (0x059 << 2))
#define P_EE_AUDIO_TODDR_B_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x059 << 2))
#define EE_AUDIO_TODDR_C_CTRL0 (0xff642000 + (0x060 << 2))
#define SEC_EE_AUDIO_TODDR_C_CTRL0 (0xff642000 + (0x060 << 2))
#define P_EE_AUDIO_TODDR_C_CTRL0 (volatile uint32_t *)(0xff642000 + (0x060 << 2))
#define EE_AUDIO_TODDR_C_CTRL1 (0xff642000 + (0x061 << 2))
#define SEC_EE_AUDIO_TODDR_C_CTRL1 (0xff642000 + (0x061 << 2))
#define P_EE_AUDIO_TODDR_C_CTRL1 (volatile uint32_t *)(0xff642000 + (0x061 << 2))
#define EE_AUDIO_TODDR_C_START_ADDR (0xff642000 + (0x062 << 2))
#define SEC_EE_AUDIO_TODDR_C_START_ADDR (0xff642000 + (0x062 << 2))
#define P_EE_AUDIO_TODDR_C_START_ADDR (volatile uint32_t *)(0xff642000 + (0x062 << 2))
#define EE_AUDIO_TODDR_C_FINISH_ADDR (0xff642000 + (0x063 << 2))
#define SEC_EE_AUDIO_TODDR_C_FINISH_ADDR (0xff642000 + (0x063 << 2))
#define P_EE_AUDIO_TODDR_C_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x063 << 2))
#define EE_AUDIO_TODDR_C_INT_ADDR (0xff642000 + (0x064 << 2))
#define SEC_EE_AUDIO_TODDR_C_INT_ADDR (0xff642000 + (0x064 << 2))
#define P_EE_AUDIO_TODDR_C_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x064 << 2))
#define EE_AUDIO_TODDR_C_STATUS1 (0xff642000 + (0x065 << 2))
#define SEC_EE_AUDIO_TODDR_C_STATUS1 (0xff642000 + (0x065 << 2))
#define P_EE_AUDIO_TODDR_C_STATUS1 (volatile uint32_t *)(0xff642000 + (0x065 << 2))
#define EE_AUDIO_TODDR_C_STATUS2 (0xff642000 + (0x066 << 2))
#define SEC_EE_AUDIO_TODDR_C_STATUS2 (0xff642000 + (0x066 << 2))
#define P_EE_AUDIO_TODDR_C_STATUS2 (volatile uint32_t *)(0xff642000 + (0x066 << 2))
#define EE_AUDIO_TODDR_C_START_ADDRB (0xff642000 + (0x067 << 2))
#define SEC_EE_AUDIO_TODDR_C_START_ADDRB (0xff642000 + (0x067 << 2))
#define P_EE_AUDIO_TODDR_C_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x067 << 2))
#define EE_AUDIO_TODDR_C_FINISH_ADDRB (0xff642000 + (0x068 << 2))
#define SEC_EE_AUDIO_TODDR_C_FINISH_ADDRB (0xff642000 + (0x068 << 2))
#define P_EE_AUDIO_TODDR_C_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x068 << 2))
#define EE_AUDIO_TODDR_C_INIT_ADDR (0xff642000 + (0x069 << 2))
#define SEC_EE_AUDIO_TODDR_C_INIT_ADDR (0xff642000 + (0x069 << 2))
#define P_EE_AUDIO_TODDR_C_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x069 << 2))
#define EE_AUDIO_FRDDR_A_CTRL0 (0xff642000 + (0x070 << 2))
#define SEC_EE_AUDIO_FRDDR_A_CTRL0 (0xff642000 + (0x070 << 2))
#define P_EE_AUDIO_FRDDR_A_CTRL0 (volatile uint32_t *)(0xff642000 + (0x070 << 2))
#define EE_AUDIO_FRDDR_A_CTRL1 (0xff642000 + (0x071 << 2))
#define SEC_EE_AUDIO_FRDDR_A_CTRL1 (0xff642000 + (0x071 << 2))
#define P_EE_AUDIO_FRDDR_A_CTRL1 (volatile uint32_t *)(0xff642000 + (0x071 << 2))
#define EE_AUDIO_FRDDR_A_START_ADDR (0xff642000 + (0x072 << 2))
#define SEC_EE_AUDIO_FRDDR_A_START_ADDR (0xff642000 + (0x072 << 2))
#define P_EE_AUDIO_FRDDR_A_START_ADDR (volatile uint32_t *)(0xff642000 + (0x072 << 2))
#define EE_AUDIO_FRDDR_A_FINISH_ADDR (0xff642000 + (0x073 << 2))
#define SEC_EE_AUDIO_FRDDR_A_FINISH_ADDR (0xff642000 + (0x073 << 2))
#define P_EE_AUDIO_FRDDR_A_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x073 << 2))
#define EE_AUDIO_FRDDR_A_INT_ADDR (0xff642000 + (0x074 << 2))
#define SEC_EE_AUDIO_FRDDR_A_INT_ADDR (0xff642000 + (0x074 << 2))
#define P_EE_AUDIO_FRDDR_A_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x074 << 2))
#define EE_AUDIO_FRDDR_A_STATUS1 (0xff642000 + (0x075 << 2))
#define SEC_EE_AUDIO_FRDDR_A_STATUS1 (0xff642000 + (0x075 << 2))
#define P_EE_AUDIO_FRDDR_A_STATUS1 (volatile uint32_t *)(0xff642000 + (0x075 << 2))
#define EE_AUDIO_FRDDR_A_STATUS2 (0xff642000 + (0x076 << 2))
#define SEC_EE_AUDIO_FRDDR_A_STATUS2 (0xff642000 + (0x076 << 2))
#define P_EE_AUDIO_FRDDR_A_STATUS2 (volatile uint32_t *)(0xff642000 + (0x076 << 2))
#define EE_AUDIO_FRDDR_A_START_ADDRB (0xff642000 + (0x077 << 2))
#define SEC_EE_AUDIO_FRDDR_A_START_ADDRB (0xff642000 + (0x077 << 2))
#define P_EE_AUDIO_FRDDR_A_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x077 << 2))
#define EE_AUDIO_FRDDR_A_FINISH_ADDRB (0xff642000 + (0x078 << 2))
#define SEC_EE_AUDIO_FRDDR_A_FINISH_ADDRB (0xff642000 + (0x078 << 2))
#define P_EE_AUDIO_FRDDR_A_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x078 << 2))
#define EE_AUDIO_FRDDR_A_INIT_ADDR (0xff642000 + (0x079 << 2))
#define SEC_EE_AUDIO_FRDDR_A_INIT_ADDR (0xff642000 + (0x079 << 2))
#define P_EE_AUDIO_FRDDR_A_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x079 << 2))
#define EE_AUDIO_FRDDR_B_CTRL0 (0xff642000 + (0x080 << 2))
#define SEC_EE_AUDIO_FRDDR_B_CTRL0 (0xff642000 + (0x080 << 2))
#define P_EE_AUDIO_FRDDR_B_CTRL0 (volatile uint32_t *)(0xff642000 + (0x080 << 2))
#define EE_AUDIO_FRDDR_B_CTRL1 (0xff642000 + (0x081 << 2))
#define SEC_EE_AUDIO_FRDDR_B_CTRL1 (0xff642000 + (0x081 << 2))
#define P_EE_AUDIO_FRDDR_B_CTRL1 (volatile uint32_t *)(0xff642000 + (0x081 << 2))
#define EE_AUDIO_FRDDR_B_START_ADDR (0xff642000 + (0x082 << 2))
#define SEC_EE_AUDIO_FRDDR_B_START_ADDR (0xff642000 + (0x082 << 2))
#define P_EE_AUDIO_FRDDR_B_START_ADDR (volatile uint32_t *)(0xff642000 + (0x082 << 2))
#define EE_AUDIO_FRDDR_B_FINISH_ADDR (0xff642000 + (0x083 << 2))
#define SEC_EE_AUDIO_FRDDR_B_FINISH_ADDR (0xff642000 + (0x083 << 2))
#define P_EE_AUDIO_FRDDR_B_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x083 << 2))
#define EE_AUDIO_FRDDR_B_INT_ADDR (0xff642000 + (0x084 << 2))
#define SEC_EE_AUDIO_FRDDR_B_INT_ADDR (0xff642000 + (0x084 << 2))
#define P_EE_AUDIO_FRDDR_B_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x084 << 2))
#define EE_AUDIO_FRDDR_B_STATUS1 (0xff642000 + (0x085 << 2))
#define SEC_EE_AUDIO_FRDDR_B_STATUS1 (0xff642000 + (0x085 << 2))
#define P_EE_AUDIO_FRDDR_B_STATUS1 (volatile uint32_t *)(0xff642000 + (0x085 << 2))
#define EE_AUDIO_FRDDR_B_STATUS2 (0xff642000 + (0x086 << 2))
#define SEC_EE_AUDIO_FRDDR_B_STATUS2 (0xff642000 + (0x086 << 2))
#define P_EE_AUDIO_FRDDR_B_STATUS2 (volatile uint32_t *)(0xff642000 + (0x086 << 2))
#define EE_AUDIO_FRDDR_B_START_ADDRB (0xff642000 + (0x087 << 2))
#define SEC_EE_AUDIO_FRDDR_B_START_ADDRB (0xff642000 + (0x087 << 2))
#define P_EE_AUDIO_FRDDR_B_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x087 << 2))
#define EE_AUDIO_FRDDR_B_FINISH_ADDRB (0xff642000 + (0x088 << 2))
#define SEC_EE_AUDIO_FRDDR_B_FINISH_ADDRB (0xff642000 + (0x088 << 2))
#define P_EE_AUDIO_FRDDR_B_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x088 << 2))
#define EE_AUDIO_FRDDR_B_INIT_ADDR (0xff642000 + (0x089 << 2))
#define SEC_EE_AUDIO_FRDDR_B_INIT_ADDR (0xff642000 + (0x089 << 2))
#define P_EE_AUDIO_FRDDR_B_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x089 << 2))
#define EE_AUDIO_FRDDR_C_CTRL0 (0xff642000 + (0x090 << 2))
#define SEC_EE_AUDIO_FRDDR_C_CTRL0 (0xff642000 + (0x090 << 2))
#define P_EE_AUDIO_FRDDR_C_CTRL0 (volatile uint32_t *)(0xff642000 + (0x090 << 2))
#define EE_AUDIO_FRDDR_C_CTRL1 (0xff642000 + (0x091 << 2))
#define SEC_EE_AUDIO_FRDDR_C_CTRL1 (0xff642000 + (0x091 << 2))
#define P_EE_AUDIO_FRDDR_C_CTRL1 (volatile uint32_t *)(0xff642000 + (0x091 << 2))
#define EE_AUDIO_FRDDR_C_START_ADDR (0xff642000 + (0x092 << 2))
#define SEC_EE_AUDIO_FRDDR_C_START_ADDR (0xff642000 + (0x092 << 2))
#define P_EE_AUDIO_FRDDR_C_START_ADDR (volatile uint32_t *)(0xff642000 + (0x092 << 2))
#define EE_AUDIO_FRDDR_C_FINISH_ADDR (0xff642000 + (0x093 << 2))
#define SEC_EE_AUDIO_FRDDR_C_FINISH_ADDR (0xff642000 + (0x093 << 2))
#define P_EE_AUDIO_FRDDR_C_FINISH_ADDR (volatile uint32_t *)(0xff642000 + (0x093 << 2))
#define EE_AUDIO_FRDDR_C_INT_ADDR (0xff642000 + (0x094 << 2))
#define SEC_EE_AUDIO_FRDDR_C_INT_ADDR (0xff642000 + (0x094 << 2))
#define P_EE_AUDIO_FRDDR_C_INT_ADDR (volatile uint32_t *)(0xff642000 + (0x094 << 2))
#define EE_AUDIO_FRDDR_C_STATUS1 (0xff642000 + (0x095 << 2))
#define SEC_EE_AUDIO_FRDDR_C_STATUS1 (0xff642000 + (0x095 << 2))
#define P_EE_AUDIO_FRDDR_C_STATUS1 (volatile uint32_t *)(0xff642000 + (0x095 << 2))
#define EE_AUDIO_FRDDR_C_STATUS2 (0xff642000 + (0x096 << 2))
#define SEC_EE_AUDIO_FRDDR_C_STATUS2 (0xff642000 + (0x096 << 2))
#define P_EE_AUDIO_FRDDR_C_STATUS2 (volatile uint32_t *)(0xff642000 + (0x096 << 2))
#define EE_AUDIO_FRDDR_C_START_ADDRB (0xff642000 + (0x097 << 2))
#define SEC_EE_AUDIO_FRDDR_C_START_ADDRB (0xff642000 + (0x097 << 2))
#define P_EE_AUDIO_FRDDR_C_START_ADDRB (volatile uint32_t *)(0xff642000 + (0x097 << 2))
#define EE_AUDIO_FRDDR_C_FINISH_ADDRB (0xff642000 + (0x098 << 2))
#define SEC_EE_AUDIO_FRDDR_C_FINISH_ADDRB (0xff642000 + (0x098 << 2))
#define P_EE_AUDIO_FRDDR_C_FINISH_ADDRB (volatile uint32_t *)(0xff642000 + (0x098 << 2))
#define EE_AUDIO_FRDDR_C_INIT_ADDR (0xff642000 + (0x099 << 2))
#define SEC_EE_AUDIO_FRDDR_C_INIT_ADDR (0xff642000 + (0x099 << 2))
#define P_EE_AUDIO_FRDDR_C_INIT_ADDR (volatile uint32_t *)(0xff642000 + (0x099 << 2))
#define EE_AUDIO_ARB_CTRL (0xff642000 + (0x0a0 << 2))
#define SEC_EE_AUDIO_ARB_CTRL (0xff642000 + (0x0a0 << 2))
#define P_EE_AUDIO_ARB_CTRL (volatile uint32_t *)(0xff642000 + (0x0a0 << 2))
#define EE_AUDIO_LB_CTRL0 (0xff642000 + (0x0b0 << 2))
#define SEC_EE_AUDIO_LB_CTRL0 (0xff642000 + (0x0b0 << 2))
#define P_EE_AUDIO_LB_CTRL0 (volatile uint32_t *)(0xff642000 + (0x0b0 << 2))
#define EE_AUDIO_LB_CTRL1 (0xff642000 + (0x0b1 << 2))
#define SEC_EE_AUDIO_LB_CTRL1 (0xff642000 + (0x0b1 << 2))
#define P_EE_AUDIO_LB_CTRL1 (volatile uint32_t *)(0xff642000 + (0x0b1 << 2))
#define EE_AUDIO_LB_DAT_CH_ID0 (0xff642000 + (0x0b2 << 2))
#define SEC_EE_AUDIO_LB_DAT_CH_ID0 (0xff642000 + (0x0b2 << 2))
#define P_EE_AUDIO_LB_DAT_CH_ID0 (volatile uint32_t *)(0xff642000 + (0x0b2 << 2))
#define EE_AUDIO_LB_DAT_CH_ID1 (0xff642000 + (0x0b3 << 2))
#define SEC_EE_AUDIO_LB_DAT_CH_ID1 (0xff642000 + (0x0b3 << 2))
#define P_EE_AUDIO_LB_DAT_CH_ID1 (volatile uint32_t *)(0xff642000 + (0x0b3 << 2))
#define EE_AUDIO_LB_LB_CH_ID0 (0xff642000 + (0x0b4 << 2))
#define SEC_EE_AUDIO_LB_LB_CH_ID0 (0xff642000 + (0x0b4 << 2))
#define P_EE_AUDIO_LB_LB_CH_ID0 (volatile uint32_t *)(0xff642000 + (0x0b4 << 2))
#define EE_AUDIO_LB_LB_CH_ID1 (0xff642000 + (0x0b5 << 2))
#define SEC_EE_AUDIO_LB_LB_CH_ID1 (0xff642000 + (0x0b5 << 2))
#define P_EE_AUDIO_LB_LB_CH_ID1 (volatile uint32_t *)(0xff642000 + (0x0b5 << 2))
#define EE_AUDIO_LB_STS (0xff642000 + (0x0b6 << 2))
#define SEC_EE_AUDIO_LB_STS (0xff642000 + (0x0b6 << 2))
#define P_EE_AUDIO_LB_STS (volatile uint32_t *)(0xff642000 + (0x0b6 << 2))
#define EE_AUDIO_TDMIN_A_CTRL (0xff642000 + (0x0c0 << 2))
#define SEC_EE_AUDIO_TDMIN_A_CTRL (0xff642000 + (0x0c0 << 2))
#define P_EE_AUDIO_TDMIN_A_CTRL (volatile uint32_t *)(0xff642000 + (0x0c0 << 2))
#define EE_AUDIO_TDMIN_A_SWAP (0xff642000 + (0x0c1 << 2))
#define SEC_EE_AUDIO_TDMIN_A_SWAP (0xff642000 + (0x0c1 << 2))
#define P_EE_AUDIO_TDMIN_A_SWAP (volatile uint32_t *)(0xff642000 + (0x0c1 << 2))
#define EE_AUDIO_TDMIN_A_MASK0 (0xff642000 + (0x0c2 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MASK0 (0xff642000 + (0x0c2 << 2))
#define P_EE_AUDIO_TDMIN_A_MASK0 (volatile uint32_t *)(0xff642000 + (0x0c2 << 2))
#define EE_AUDIO_TDMIN_A_MASK1 (0xff642000 + (0x0c3 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MASK1 (0xff642000 + (0x0c3 << 2))
#define P_EE_AUDIO_TDMIN_A_MASK1 (volatile uint32_t *)(0xff642000 + (0x0c3 << 2))
#define EE_AUDIO_TDMIN_A_MASK2 (0xff642000 + (0x0c4 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MASK2 (0xff642000 + (0x0c4 << 2))
#define P_EE_AUDIO_TDMIN_A_MASK2 (volatile uint32_t *)(0xff642000 + (0x0c4 << 2))
#define EE_AUDIO_TDMIN_A_MASK3 (0xff642000 + (0x0c5 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MASK3 (0xff642000 + (0x0c5 << 2))
#define P_EE_AUDIO_TDMIN_A_MASK3 (volatile uint32_t *)(0xff642000 + (0x0c5 << 2))
#define EE_AUDIO_TDMIN_A_STAT (0xff642000 + (0x0c6 << 2))
#define SEC_EE_AUDIO_TDMIN_A_STAT (0xff642000 + (0x0c6 << 2))
#define P_EE_AUDIO_TDMIN_A_STAT (volatile uint32_t *)(0xff642000 + (0x0c6 << 2))
#define EE_AUDIO_TDMIN_A_MUTE_VAL (0xff642000 + (0x0c7 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MUTE_VAL (0xff642000 + (0x0c7 << 2))
#define P_EE_AUDIO_TDMIN_A_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0c7 << 2))
#define EE_AUDIO_TDMIN_A_MUTE0 (0xff642000 + (0x0c8 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MUTE0 (0xff642000 + (0x0c8 << 2))
#define P_EE_AUDIO_TDMIN_A_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0c8 << 2))
#define EE_AUDIO_TDMIN_A_MUTE1 (0xff642000 + (0x0c9 << 2))
#define SEC_EE_AUDIO_TDMIN_A_MUTE1 (0xff642000 + (0x0c9 << 2))
#define P_EE_AUDIO_TDMIN_A_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0c9 << 2))
#define EE_AUDIO_TDMIN_A_MUTE2 (0xff642000 + (0x0ca << 2))
#define SEC_EE_AUDIO_TDMIN_A_MUTE2 (0xff642000 + (0x0ca << 2))
#define P_EE_AUDIO_TDMIN_A_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0ca << 2))
#define EE_AUDIO_TDMIN_A_MUTE3 (0xff642000 + (0x0cb << 2))
#define SEC_EE_AUDIO_TDMIN_A_MUTE3 (0xff642000 + (0x0cb << 2))
#define P_EE_AUDIO_TDMIN_A_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0cb << 2))
#define EE_AUDIO_TDMIN_B_CTRL (0xff642000 + (0x0d0 << 2))
#define SEC_EE_AUDIO_TDMIN_B_CTRL (0xff642000 + (0x0d0 << 2))
#define P_EE_AUDIO_TDMIN_B_CTRL (volatile uint32_t *)(0xff642000 + (0x0d0 << 2))
#define EE_AUDIO_TDMIN_B_SWAP (0xff642000 + (0x0d1 << 2))
#define SEC_EE_AUDIO_TDMIN_B_SWAP (0xff642000 + (0x0d1 << 2))
#define P_EE_AUDIO_TDMIN_B_SWAP (volatile uint32_t *)(0xff642000 + (0x0d1 << 2))
#define EE_AUDIO_TDMIN_B_MASK0 (0xff642000 + (0x0d2 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MASK0 (0xff642000 + (0x0d2 << 2))
#define P_EE_AUDIO_TDMIN_B_MASK0 (volatile uint32_t *)(0xff642000 + (0x0d2 << 2))
#define EE_AUDIO_TDMIN_B_MASK1 (0xff642000 + (0x0d3 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MASK1 (0xff642000 + (0x0d3 << 2))
#define P_EE_AUDIO_TDMIN_B_MASK1 (volatile uint32_t *)(0xff642000 + (0x0d3 << 2))
#define EE_AUDIO_TDMIN_B_MASK2 (0xff642000 + (0x0d4 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MASK2 (0xff642000 + (0x0d4 << 2))
#define P_EE_AUDIO_TDMIN_B_MASK2 (volatile uint32_t *)(0xff642000 + (0x0d4 << 2))
#define EE_AUDIO_TDMIN_B_MASK3 (0xff642000 + (0x0d5 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MASK3 (0xff642000 + (0x0d5 << 2))
#define P_EE_AUDIO_TDMIN_B_MASK3 (volatile uint32_t *)(0xff642000 + (0x0d5 << 2))
#define EE_AUDIO_TDMIN_B_STAT (0xff642000 + (0x0d6 << 2))
#define SEC_EE_AUDIO_TDMIN_B_STAT (0xff642000 + (0x0d6 << 2))
#define P_EE_AUDIO_TDMIN_B_STAT (volatile uint32_t *)(0xff642000 + (0x0d6 << 2))
#define EE_AUDIO_TDMIN_B_MUTE_VAL (0xff642000 + (0x0d7 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MUTE_VAL (0xff642000 + (0x0d7 << 2))
#define P_EE_AUDIO_TDMIN_B_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0d7 << 2))
#define EE_AUDIO_TDMIN_B_MUTE0 (0xff642000 + (0x0d8 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MUTE0 (0xff642000 + (0x0d8 << 2))
#define P_EE_AUDIO_TDMIN_B_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0d8 << 2))
#define EE_AUDIO_TDMIN_B_MUTE1 (0xff642000 + (0x0d9 << 2))
#define SEC_EE_AUDIO_TDMIN_B_MUTE1 (0xff642000 + (0x0d9 << 2))
#define P_EE_AUDIO_TDMIN_B_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0d9 << 2))
#define EE_AUDIO_TDMIN_B_MUTE2 (0xff642000 + (0x0da << 2))
#define SEC_EE_AUDIO_TDMIN_B_MUTE2 (0xff642000 + (0x0da << 2))
#define P_EE_AUDIO_TDMIN_B_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0da << 2))
#define EE_AUDIO_TDMIN_B_MUTE3 (0xff642000 + (0x0db << 2))
#define SEC_EE_AUDIO_TDMIN_B_MUTE3 (0xff642000 + (0x0db << 2))
#define P_EE_AUDIO_TDMIN_B_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0db << 2))
#define EE_AUDIO_TDMIN_C_CTRL (0xff642000 + (0x0e0 << 2))
#define SEC_EE_AUDIO_TDMIN_C_CTRL (0xff642000 + (0x0e0 << 2))
#define P_EE_AUDIO_TDMIN_C_CTRL (volatile uint32_t *)(0xff642000 + (0x0e0 << 2))
#define EE_AUDIO_TDMIN_C_SWAP (0xff642000 + (0x0e1 << 2))
#define SEC_EE_AUDIO_TDMIN_C_SWAP (0xff642000 + (0x0e1 << 2))
#define P_EE_AUDIO_TDMIN_C_SWAP (volatile uint32_t *)(0xff642000 + (0x0e1 << 2))
#define EE_AUDIO_TDMIN_C_MASK0 (0xff642000 + (0x0e2 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MASK0 (0xff642000 + (0x0e2 << 2))
#define P_EE_AUDIO_TDMIN_C_MASK0 (volatile uint32_t *)(0xff642000 + (0x0e2 << 2))
#define EE_AUDIO_TDMIN_C_MASK1 (0xff642000 + (0x0e3 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MASK1 (0xff642000 + (0x0e3 << 2))
#define P_EE_AUDIO_TDMIN_C_MASK1 (volatile uint32_t *)(0xff642000 + (0x0e3 << 2))
#define EE_AUDIO_TDMIN_C_MASK2 (0xff642000 + (0x0e4 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MASK2 (0xff642000 + (0x0e4 << 2))
#define P_EE_AUDIO_TDMIN_C_MASK2 (volatile uint32_t *)(0xff642000 + (0x0e4 << 2))
#define EE_AUDIO_TDMIN_C_MASK3 (0xff642000 + (0x0e5 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MASK3 (0xff642000 + (0x0e5 << 2))
#define P_EE_AUDIO_TDMIN_C_MASK3 (volatile uint32_t *)(0xff642000 + (0x0e5 << 2))
#define EE_AUDIO_TDMIN_C_STAT (0xff642000 + (0x0e6 << 2))
#define SEC_EE_AUDIO_TDMIN_C_STAT (0xff642000 + (0x0e6 << 2))
#define P_EE_AUDIO_TDMIN_C_STAT (volatile uint32_t *)(0xff642000 + (0x0e6 << 2))
#define EE_AUDIO_TDMIN_C_MUTE_VAL (0xff642000 + (0x0e7 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MUTE_VAL (0xff642000 + (0x0e7 << 2))
#define P_EE_AUDIO_TDMIN_C_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0e7 << 2))
#define EE_AUDIO_TDMIN_C_MUTE0 (0xff642000 + (0x0e8 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MUTE0 (0xff642000 + (0x0e8 << 2))
#define P_EE_AUDIO_TDMIN_C_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0e8 << 2))
#define EE_AUDIO_TDMIN_C_MUTE1 (0xff642000 + (0x0e9 << 2))
#define SEC_EE_AUDIO_TDMIN_C_MUTE1 (0xff642000 + (0x0e9 << 2))
#define P_EE_AUDIO_TDMIN_C_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0e9 << 2))
#define EE_AUDIO_TDMIN_C_MUTE2 (0xff642000 + (0x0ea << 2))
#define SEC_EE_AUDIO_TDMIN_C_MUTE2 (0xff642000 + (0x0ea << 2))
#define P_EE_AUDIO_TDMIN_C_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0ea << 2))
#define EE_AUDIO_TDMIN_C_MUTE3 (0xff642000 + (0x0eb << 2))
#define SEC_EE_AUDIO_TDMIN_C_MUTE3 (0xff642000 + (0x0eb << 2))
#define P_EE_AUDIO_TDMIN_C_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0eb << 2))
#define EE_AUDIO_TDMIN_LB_CTRL (0xff642000 + (0x0f0 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_CTRL (0xff642000 + (0x0f0 << 2))
#define P_EE_AUDIO_TDMIN_LB_CTRL (volatile uint32_t *)(0xff642000 + (0x0f0 << 2))
#define EE_AUDIO_TDMIN_LB_SWAP (0xff642000 + (0x0f1 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_SWAP (0xff642000 + (0x0f1 << 2))
#define P_EE_AUDIO_TDMIN_LB_SWAP (volatile uint32_t *)(0xff642000 + (0x0f1 << 2))
#define EE_AUDIO_TDMIN_LB_MASK0 (0xff642000 + (0x0f2 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MASK0 (0xff642000 + (0x0f2 << 2))
#define P_EE_AUDIO_TDMIN_LB_MASK0 (volatile uint32_t *)(0xff642000 + (0x0f2 << 2))
#define EE_AUDIO_TDMIN_LB_MASK1 (0xff642000 + (0x0f3 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MASK1 (0xff642000 + (0x0f3 << 2))
#define P_EE_AUDIO_TDMIN_LB_MASK1 (volatile uint32_t *)(0xff642000 + (0x0f3 << 2))
#define EE_AUDIO_TDMIN_LB_MASK2 (0xff642000 + (0x0f4 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MASK2 (0xff642000 + (0x0f4 << 2))
#define P_EE_AUDIO_TDMIN_LB_MASK2 (volatile uint32_t *)(0xff642000 + (0x0f4 << 2))
#define EE_AUDIO_TDMIN_LB_MASK3 (0xff642000 + (0x0f5 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MASK3 (0xff642000 + (0x0f5 << 2))
#define P_EE_AUDIO_TDMIN_LB_MASK3 (volatile uint32_t *)(0xff642000 + (0x0f5 << 2))
#define EE_AUDIO_TDMIN_LB_STAT (0xff642000 + (0x0f6 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_STAT (0xff642000 + (0x0f6 << 2))
#define P_EE_AUDIO_TDMIN_LB_STAT (volatile uint32_t *)(0xff642000 + (0x0f6 << 2))
#define EE_AUDIO_TDMIN_LB_MUTE_VAL (0xff642000 + (0x0f7 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MUTE_VAL (0xff642000 + (0x0f7 << 2))
#define P_EE_AUDIO_TDMIN_LB_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x0f7 << 2))
#define EE_AUDIO_TDMIN_LB_MUTE0 (0xff642000 + (0x0f8 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MUTE0 (0xff642000 + (0x0f8 << 2))
#define P_EE_AUDIO_TDMIN_LB_MUTE0 (volatile uint32_t *)(0xff642000 + (0x0f8 << 2))
#define EE_AUDIO_TDMIN_LB_MUTE1 (0xff642000 + (0x0f9 << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MUTE1 (0xff642000 + (0x0f9 << 2))
#define P_EE_AUDIO_TDMIN_LB_MUTE1 (volatile uint32_t *)(0xff642000 + (0x0f9 << 2))
#define EE_AUDIO_TDMIN_LB_MUTE2 (0xff642000 + (0x0fa << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MUTE2 (0xff642000 + (0x0fa << 2))
#define P_EE_AUDIO_TDMIN_LB_MUTE2 (volatile uint32_t *)(0xff642000 + (0x0fa << 2))
#define EE_AUDIO_TDMIN_LB_MUTE3 (0xff642000 + (0x0fb << 2))
#define SEC_EE_AUDIO_TDMIN_LB_MUTE3 (0xff642000 + (0x0fb << 2))
#define P_EE_AUDIO_TDMIN_LB_MUTE3 (volatile uint32_t *)(0xff642000 + (0x0fb << 2))
#define EE_AUDIO_SPDIFIN_CTRL0 (0xff642000 + (0x100 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL0 (0xff642000 + (0x100 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL0 (volatile uint32_t *)(0xff642000 + (0x100 << 2))
#define EE_AUDIO_SPDIFIN_CTRL1 (0xff642000 + (0x101 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL1 (0xff642000 + (0x101 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL1 (volatile uint32_t *)(0xff642000 + (0x101 << 2))
#define EE_AUDIO_SPDIFIN_CTRL2 (0xff642000 + (0x102 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL2 (0xff642000 + (0x102 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL2 (volatile uint32_t *)(0xff642000 + (0x102 << 2))
#define EE_AUDIO_SPDIFIN_CTRL3 (0xff642000 + (0x103 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL3 (0xff642000 + (0x103 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL3 (volatile uint32_t *)(0xff642000 + (0x103 << 2))
#define EE_AUDIO_SPDIFIN_CTRL4 (0xff642000 + (0x104 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL4 (0xff642000 + (0x104 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL4 (volatile uint32_t *)(0xff642000 + (0x104 << 2))
#define EE_AUDIO_SPDIFIN_CTRL5 (0xff642000 + (0x105 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL5 (0xff642000 + (0x105 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL5 (volatile uint32_t *)(0xff642000 + (0x105 << 2))
#define EE_AUDIO_SPDIFIN_CTRL6 (0xff642000 + (0x106 << 2))
#define SEC_EE_AUDIO_SPDIFIN_CTRL6 (0xff642000 + (0x106 << 2))
#define P_EE_AUDIO_SPDIFIN_CTRL6 (volatile uint32_t *)(0xff642000 + (0x106 << 2))
#define EE_AUDIO_SPDIFIN_STAT0 (0xff642000 + (0x107 << 2))
#define SEC_EE_AUDIO_SPDIFIN_STAT0 (0xff642000 + (0x107 << 2))
#define P_EE_AUDIO_SPDIFIN_STAT0 (volatile uint32_t *)(0xff642000 + (0x107 << 2))
#define EE_AUDIO_SPDIFIN_STAT1 (0xff642000 + (0x108 << 2))
#define SEC_EE_AUDIO_SPDIFIN_STAT1 (0xff642000 + (0x108 << 2))
#define P_EE_AUDIO_SPDIFIN_STAT1 (volatile uint32_t *)(0xff642000 + (0x108 << 2))
#define EE_AUDIO_SPDIFIN_STAT2 (0xff642000 + (0x109 << 2))
#define SEC_EE_AUDIO_SPDIFIN_STAT2 (0xff642000 + (0x109 << 2))
#define P_EE_AUDIO_SPDIFIN_STAT2 (volatile uint32_t *)(0xff642000 + (0x109 << 2))
#define EE_AUDIO_SPDIFIN_MUTE_VAL (0xff642000 + (0x10a << 2))
#define SEC_EE_AUDIO_SPDIFIN_MUTE_VAL (0xff642000 + (0x10a << 2))
#define P_EE_AUDIO_SPDIFIN_MUTE_VAL (volatile uint32_t *)(0xff642000 + (0x10a << 2))
#define EE_AUDIO_RESAMPLE_CTRL0 (0xff642000 + (0x110 << 2))
#define SEC_EE_AUDIO_RESAMPLE_CTRL0 (0xff642000 + (0x110 << 2))
#define P_EE_AUDIO_RESAMPLE_CTRL0 (volatile uint32_t *)(0xff642000 + (0x110 << 2))
#define EE_AUDIO_RESAMPLE_CTRL1 (0xff642000 + (0x111 << 2))
#define SEC_EE_AUDIO_RESAMPLE_CTRL1 (0xff642000 + (0x111 << 2))
#define P_EE_AUDIO_RESAMPLE_CTRL1 (volatile uint32_t *)(0xff642000 + (0x111 << 2))
#define EE_AUDIO_RESAMPLE_CTRL2 (0xff642000 + (0x112 << 2))
#define SEC_EE_AUDIO_RESAMPLE_CTRL2 (0xff642000 + (0x112 << 2))
#define P_EE_AUDIO_RESAMPLE_CTRL2 (volatile uint32_t *)(0xff642000 + (0x112 << 2))
#define EE_AUDIO_RESAMPLE_CTRL3 (0xff642000 + (0x113 << 2))
#define SEC_EE_AUDIO_RESAMPLE_CTRL3 (0xff642000 + (0x113 << 2))
#define P_EE_AUDIO_RESAMPLE_CTRL3 (volatile uint32_t *)(0xff642000 + (0x113 << 2))
#define EE_AUDIO_RESAMPLE_COEF0 (0xff642000 + (0x114 << 2))
#define SEC_EE_AUDIO_RESAMPLE_COEF0 (0xff642000 + (0x114 << 2))
#define P_EE_AUDIO_RESAMPLE_COEF0 (volatile uint32_t *)(0xff642000 + (0x114 << 2))
#define EE_AUDIO_RESAMPLE_COEF1 (0xff642000 + (0x115 << 2))
#define SEC_EE_AUDIO_RESAMPLE_COEF1 (0xff642000 + (0x115 << 2))
#define P_EE_AUDIO_RESAMPLE_COEF1 (volatile uint32_t *)(0xff642000 + (0x115 << 2))
#define EE_AUDIO_RESAMPLE_COEF2 (0xff642000 + (0x116 << 2))
#define SEC_EE_AUDIO_RESAMPLE_COEF2 (0xff642000 + (0x116 << 2))
#define P_EE_AUDIO_RESAMPLE_COEF2 (volatile uint32_t *)(0xff642000 + (0x116 << 2))
#define EE_AUDIO_RESAMPLE_COEF3 (0xff642000 + (0x117 << 2))
#define SEC_EE_AUDIO_RESAMPLE_COEF3 (0xff642000 + (0x117 << 2))
#define P_EE_AUDIO_RESAMPLE_COEF3 (volatile uint32_t *)(0xff642000 + (0x117 << 2))
#define EE_AUDIO_RESAMPLE_COEF4 (0xff642000 + (0x118 << 2))
#define SEC_EE_AUDIO_RESAMPLE_COEF4 (0xff642000 + (0x118 << 2))
#define P_EE_AUDIO_RESAMPLE_COEF4 (volatile uint32_t *)(0xff642000 + (0x118 << 2))
#define EE_AUDIO_RESAMPLE_STATUS1 (0xff642000 + (0x119 << 2))
#define SEC_EE_AUDIO_RESAMPLE_STATUS1 (0xff642000 + (0x119 << 2))
#define P_EE_AUDIO_RESAMPLE_STATUS1 (volatile uint32_t *)(0xff642000 + (0x119 << 2))
#define EE_AUDIO_SPDIFOUT_STAT (0xff642000 + (0x120 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_STAT (0xff642000 + (0x120 << 2))
#define P_EE_AUDIO_SPDIFOUT_STAT (volatile uint32_t *)(0xff642000 + (0x120 << 2))
#define EE_AUDIO_SPDIFOUT_GAIN0 (0xff642000 + (0x121 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_GAIN0 (0xff642000 + (0x121 << 2))
#define P_EE_AUDIO_SPDIFOUT_GAIN0 (volatile uint32_t *)(0xff642000 + (0x121 << 2))
#define EE_AUDIO_SPDIFOUT_GAIN1 (0xff642000 + (0x122 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_GAIN1 (0xff642000 + (0x122 << 2))
#define P_EE_AUDIO_SPDIFOUT_GAIN1 (volatile uint32_t *)(0xff642000 + (0x122 << 2))
#define EE_AUDIO_SPDIFOUT_CTRL0 (0xff642000 + (0x123 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CTRL0 (0xff642000 + (0x123 << 2))
#define P_EE_AUDIO_SPDIFOUT_CTRL0 (volatile uint32_t *)(0xff642000 + (0x123 << 2))
#define EE_AUDIO_SPDIFOUT_CTRL1 (0xff642000 + (0x124 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CTRL1 (0xff642000 + (0x124 << 2))
#define P_EE_AUDIO_SPDIFOUT_CTRL1 (volatile uint32_t *)(0xff642000 + (0x124 << 2))
#define EE_AUDIO_SPDIFOUT_PREAMB (0xff642000 + (0x125 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_PREAMB (0xff642000 + (0x125 << 2))
#define P_EE_AUDIO_SPDIFOUT_PREAMB (volatile uint32_t *)(0xff642000 + (0x125 << 2))
#define EE_AUDIO_SPDIFOUT_SWAP (0xff642000 + (0x126 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_SWAP (0xff642000 + (0x126 << 2))
#define P_EE_AUDIO_SPDIFOUT_SWAP (volatile uint32_t *)(0xff642000 + (0x126 << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS0 (0xff642000 + (0x127 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS0 (0xff642000 + (0x127 << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS0 (volatile uint32_t *)(0xff642000 + (0x127 << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS1 (0xff642000 + (0x128 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS1 (0xff642000 + (0x128 << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS1 (volatile uint32_t *)(0xff642000 + (0x128 << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS2 (0xff642000 + (0x129 << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS2 (0xff642000 + (0x129 << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS2 (volatile uint32_t *)(0xff642000 + (0x129 << 2))
#define EE_AUDIO_SPDIFOUT_CHSTS3 (0xff642000 + (0x12a << 2))
#define SEC_EE_AUDIO_SPDIFOUT_CHSTS3 (0xff642000 + (0x12a << 2))
#define P_EE_AUDIO_SPDIFOUT_CHSTS3 (volatile uint32_t *)(0xff642000 + (