arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) 2024 Marek Vasut <marex@denx.de>
 */

#include <dt-bindings/clock/stm32mp13-clksrc.h>
#include "stm32mp13-u-boot.dtsi"
#include "stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi"
#include "stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi"

/ {
	aliases {
		eeprom0 = &eeprom0;
		eeprom0wl = &eeprom0wl;
	};

	config {
		dh,ddr3-coding-gpios = <&gpiod 5 0>, <&gpiod 9 0>;
		dh,som-coding-gpios = <&gpioa 13 0>, <&gpioi 1 0>;
		u-boot,mmc-env-offset = <0x3fc000>;
		u-boot,mmc-env-offset-redundant = <0x3fc000>;
	};
};

&etzpc {
	compatible = "simple-bus";
};

&flash0 {
	bootph-all;

	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "fsbl1";
			reg = <0x00000000 0x00040000>;
		};
		partition@40000 {
			label = "fsbl2";
			reg = <0x00040000 0x00040000>;
		};
		partition@80000 {
			label = "u-boot";
			reg = <0x00080000 0x00360000>;
		};
		partition@3e0000 {
			label = "u-boot-env-a";
			reg = <0x003e0000 0x00010000>;
		};
		partition@3f0000 {
			label = "u-boot-env-b";
			reg = <0x003f0000 0x00010000>;
		};
	};
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins_a>;
};

&qspi {
	bootph-all;
};

&qspi_clk_pins_a {
	bootph-all;
	pins {
		bootph-all;
	};
};

&qspi_bk1_pins_a {
	bootph-all;
	pins {
		bootph-all;
	};
};

&qspi_cs1_pins_a {
	bootph-all;
	pins {
		bootph-all;
	};
};

&pinctrl {
	bootph-all;
	i2c3_pins_a: i2c3-0 {
		bootph-all;
		pins {
			bootph-all;
			pinmux = <STM32_PINMUX('B', 8, AF5)>, /* I2C3_SCL */
				 <STM32_PINMUX('H', 14, AF4)>; /* I2C3_SDA */
			bias-disable;
			drive-open-drain;
			slew-rate = <0>;
		};
	};
};

#if !defined(CONFIG_TFABOOT)
&rcc {
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>;

	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MLAHBS_PLL3
		CLK_PLL12_HSE
		CLK_PLL3_HSE
		CLK_PLL4_HSE
		CLK_CKPER_HSE
		CLK_RTC_LSE
		CLK_MCO1_LSI
		CLK_MCO2_HSI
	>;

	st,clkdiv = <
		0 /*AXI*/
		0 /*MLHAB*/
		1 /*APB1*/
		1 /*APB2*/
		1 /*APB3*/
		1 /*APB4*/
		2 /*APB5*/
		1 /*APB6*/
		0 /*RTC*/
	>;

	st,pkcs = <
		CLK_I2C12_HSI
		CLK_I2C3_HSI
		CLK_QSPI_PLL3R
		CLK_SAES_AXI
		CLK_SDMMC1_PLL3R
		CLK_SDMMC2_PLL3R
		CLK_STGEN_HSE
		CLK_UART2_HSI
		CLK_UART4_HSI
		CLK_USBO_USBPHY
		CLK_USBPHY_HSE
	>;

	/*
	 * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
	 * frac = < f >;
	 *
	 * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
	 * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
	 * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
	 * XTAL = 24 MHz
	 *
	 * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
	 *   P = VCO / (P + 1)
	 *   Q = VCO / (Q + 1)
	 *   R = VCO / (R + 1)
	 */

	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
	pll2: st,pll@1 {
		compatible = "st,stm32mp1-pll";
		reg = <1>;
		cfg = < 2 65 1 1 0 PQR(1,1,1) >;
		frac = < 0x1400 >;
		bootph-all;
	};

	/* VCO = 600 MHz => P = 200, Q = 150, R = 200 */
	pll3: st,pll@2 {
		compatible = "st,stm32mp1-pll";
		reg = <2>;
		cfg = < 2 74 2 3 2 PQR(1,1,1) >;
		bootph-all;
	};

	/* VCO = 750.0 MHz => P = 125, Q = 83, R = 75 */
	pll4: st,pll@3 {
		compatible = "st,stm32mp1-pll";
		reg = <3>;
		cfg = < 3 124 5 8 9 PQR(1,1,1) >;
		bootph-all;
	};
};
#endif

&reg11 {
	regulator-always-on;
};

&reg18 {
	regulator-always-on;
};

&sdmmc1 {
	status = "disabled";
};

&usbotg_hs {
	u-boot,force-b-session-valid;
};

&vddcpu {
	bootph-all;
};

&vdd_ddr {
	bootph-all;
};

&vdd {
	bootph-all;
};

&vddcore {
	bootph-all;
};

&vref_ddr {
	bootph-all;
};