| /* SPDX-License-Identifier: GPL-2.0+ */ | |
| /* | |
| * Copyright 2018 - AmLogic, Inc. | |
| * Copyright 2023 (C) SberDevices, Inc. | |
| */ | |
| #ifndef _ARCH_MESON_CLOCK_A1_H_ | |
| #define _ARCH_MESON_CLOCK_A1_H_ | |
| /* | |
| * Clock controller register offsets | |
| */ | |
| #define A1_SYS_OSCIN_CTRL 0x0 | |
| #define A1_SYS_CLK_CTRL0 0x10 | |
| #define A1_SYS_CLK_EN0 0x1c | |
| #define A1_SAR_ADC_CLK_CTR 0xc0 | |
| #define A1_SPIFC_CLK_CTRL 0xd8 | |
| #define A1_USB_BUSCLK_CTRL 0xdc | |
| #define A1_SD_EMMC_CLK_CTRL 0xe0 | |
| #define A1_ANACTRL_FIXPLL_CTRL0 0x0 | |
| #endif /* _ARCH_MESON_CLOCK_A1_H_ */ |