| |
| /* |
| * board/amlogic/txl_skt_v1/txl_skt_v1.c |
| * |
| * Copyright (C) 2015 Amlogic, Inc. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2 of the License, or |
| * (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, but WITHOUT |
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| * more details. |
| * |
| * You should have received a copy of the GNU General Public License along |
| * with this program; if not, write to the Free Software Foundation, Inc., |
| * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| */ |
| |
| #include <common.h> |
| #include <malloc.h> |
| #include <errno.h> |
| #include <environment.h> |
| #include <fdt_support.h> |
| #include <libfdt.h> |
| #include <asm/arch/secure_apb.h> |
| #ifdef CONFIG_SYS_I2C_AML |
| #include <aml_i2c.h> |
| #endif |
| #ifdef CONFIG_AML_VPU |
| #include <vpu.h> |
| #endif |
| #include <vpp.h> |
| #ifdef CONFIG_AML_V2_FACTORY_BURN |
| #include <amlogic/aml_v2_burning.h> |
| #endif// #ifdef CONFIG_AML_V2_FACTORY_BURN |
| #ifdef CONFIG_AML_HDMITX20 |
| #include <amlogic/hdmi.h> |
| #endif |
| #ifdef CONFIG_AML_LCD |
| #include <amlogic/aml_lcd.h> |
| #endif |
| #include <asm/arch/eth_setup.h> |
| #include <phy.h> |
| #include <asm-generic/gpio.h> |
| #include <dm.h> |
| #include <amlogic/spifc.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| //new static eth setup |
| struct eth_board_socket* eth_board_skt; |
| |
| |
| int serial_set_pin_port(unsigned long port_base) |
| { |
| //UART in "Always On Module" |
| //GPIOAO_0==tx,GPIOAO_1==rx |
| //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11); |
| return 0; |
| } |
| |
| int dram_init(void) |
| { |
| gd->ram_size = PHYS_SDRAM_1_SIZE; |
| return 0; |
| } |
| |
| /* secondary_boot_func |
| * this function should be write with asm, here, is is only for compiling pass |
| * */ |
| void secondary_boot_func(void) |
| { |
| } |
| void internalPhyConfig(struct phy_device *phydev) |
| { |
| /*Enable Analog and DSP register Bank access by*/ |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); |
| /*Write Analog register 23*/ |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417); |
| /*Enable fractional PLL*/ |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B); |
| //Programme fraction FR_PLL_DIV1 |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D); |
| //## programme fraction FR_PLL_DiV1 |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C); |
| } |
| |
| |
| static void setup_net_chip(void) |
| { |
| eth_aml_reg0_t eth_reg0; |
| |
| eth_reg0.d32 = 0; |
| eth_reg0.b.phy_intf_sel = 4; |
| eth_reg0.b.rx_clk_rmii_invert = 0; |
| eth_reg0.b.rgmii_tx_clk_src = 0; |
| eth_reg0.b.rgmii_tx_clk_phase = 0; |
| eth_reg0.b.rgmii_tx_clk_ratio = 0; |
| eth_reg0.b.phy_ref_clk_enable = 0; |
| eth_reg0.b.clk_rmii_i_invert = 1; |
| eth_reg0.b.clk_en = 1; |
| eth_reg0.b.adj_enable = 0; |
| eth_reg0.b.adj_setup = 0; |
| eth_reg0.b.adj_delay = 0; |
| eth_reg0.b.adj_skew = 0; |
| eth_reg0.b.cali_start = 0; |
| eth_reg0.b.cali_rise = 0; |
| eth_reg0.b.cali_sel = 0; |
| eth_reg0.b.rgmii_rx_reuse = 0; |
| eth_reg0.b.eth_urgent = 0; |
| setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode |
| *P_PREG_ETH_REG2 = 0x10110181; |
| *P_PREG_ETH_REG3 = 0xe409087f; |
| setbits_le32(HHI_GCLK_MPEG1,1<<3); |
| /* power on memory */ |
| clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2)); |
| |
| } |
| |
| extern struct eth_board_socket* eth_board_setup(char *name); |
| extern int designware_initialize(ulong base_addr, u32 interface); |
| |
| int board_eth_init(bd_t *bis) |
| { |
| setup_net_chip(); |
| udelay(1000); |
| designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII); |
| return 0; |
| } |
| |
| #if CONFIG_AML_SD_EMMC |
| #include <mmc.h> |
| #include <asm/arch/sd_emmc.h> |
| static int sd_emmc_init(unsigned port) |
| { |
| switch (port) |
| { |
| case SDIO_PORT_A: |
| break; |
| case SDIO_PORT_B: |
| //todo add card detect |
| //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6 |
| break; |
| case SDIO_PORT_C: |
| //enable pull up |
| //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0); |
| break; |
| default: |
| break; |
| } |
| |
| return cpu_sd_emmc_init(port); |
| } |
| |
| static void sd_emmc_pwr_prepare(unsigned port) |
| { |
| cpu_sd_emmc_pwr_prepare(port); |
| } |
| |
| static void sd_emmc_pwr_on(unsigned port) |
| { |
| switch (port) |
| { |
| case SDIO_PORT_A: |
| break; |
| case SDIO_PORT_B: |
| // clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8 |
| // clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); |
| /// @todo NOT FINISH |
| break; |
| case SDIO_PORT_C: |
| break; |
| default: |
| break; |
| } |
| return; |
| } |
| static void sd_emmc_pwr_off(unsigned port) |
| { |
| /// @todo NOT FINISH |
| switch (port) |
| { |
| case SDIO_PORT_A: |
| break; |
| case SDIO_PORT_B: |
| // setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8 |
| // clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); |
| break; |
| case SDIO_PORT_C: |
| break; |
| default: |
| break; |
| } |
| return; |
| } |
| |
| // #define CONFIG_TSD 1 |
| static void board_mmc_register(unsigned port) |
| { |
| struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port); |
| if (aml_priv == NULL) |
| return; |
| |
| aml_priv->sd_emmc_init=sd_emmc_init; |
| aml_priv->sd_emmc_detect=sd_emmc_detect; |
| aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off; |
| aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on; |
| aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare; |
| aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info))); |
| |
| if (NULL == aml_priv->desc_buf) |
| printf(" desc_buf Dma alloc Fail!\n"); |
| else |
| printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf); |
| |
| sd_emmc_register(aml_priv); |
| } |
| int board_mmc_init(bd_t *bis) |
| { |
| #ifdef CONFIG_VLSI_EMULATOR |
| //board_mmc_register(SDIO_PORT_A); |
| #else |
| //board_mmc_register(SDIO_PORT_B); |
| #endif |
| board_mmc_register(SDIO_PORT_B); |
| board_mmc_register(SDIO_PORT_C); |
| // board_mmc_register(SDIO_PORT_B1); |
| return 0; |
| } |
| |
| #ifdef CONFIG_SYS_I2C_AML |
| #if 0 |
| static void board_i2c_set_pinmux(void){ |
| /*********************************************/ |
| /* | I2C_Master_AO |I2C_Slave | */ |
| /*********************************************/ |
| /* | I2C_SCK | I2C_SCK_SLAVE | */ |
| /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */ |
| /*********************************************/ |
| /* | I2C_SDA | I2C_SDA_SLAVE | */ |
| /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */ |
| /*********************************************/ |
| |
| //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO |
| clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23))); |
| //enable I2C MASTER AO pins |
| setbits_le32(P_AO_RTI_PIN_MUX_REG, |
| (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT)); |
| |
| udelay(10); |
| }; |
| #endif |
| struct aml_i2c_platform g_aml_i2c_plat = { |
| .wait_count = 1000000, |
| .wait_ack_interval = 5, |
| .wait_read_interval = 5, |
| .wait_xfer_interval = 5, |
| .master_no = AML_I2C_MASTER_AO, |
| .use_pio = 0, |
| .master_i2c_speed = AML_I2C_SPPED_400K, |
| .master_ao_pinmux = { |
| .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG, |
| .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT, |
| .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG, |
| .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT, |
| } |
| }; |
| #if 0 |
| static void board_i2c_init(void) |
| { |
| //set I2C pinmux with PCB board layout |
| board_i2c_set_pinmux(); |
| |
| //Amlogic I2C controller initialized |
| //note: it must be call before any I2C operation |
| aml_i2c_init(); |
| |
| udelay(10); |
| } |
| #endif |
| #endif |
| #endif |
| |
| #if defined(CONFIG_BOARD_EARLY_INIT_F) |
| int board_early_init_f(void){ |
| /*add board early init function here*/ |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_USB_XHCI_AMLOGIC_GXL |
| #include <asm/arch/usb-new.h> |
| #include <asm/arch/gpio.h> |
| #define CONFIG_GXL_USB_U2_PORT_NUM 4 |
| #define CONFIG_GXL_USB_U3_PORT_NUM 0 |
| |
| struct amlogic_usb_config g_usb_config_GXL_skt={ |
| CONFIG_GXL_XHCI_BASE, |
| USB_ID_MODE_HARDWARE, |
| NULL,//gpio_set_vbus_power, //set_vbus_power |
| CONFIG_GXL_USB_PHY2_BASE, |
| CONFIG_GXL_USB_PHY3_BASE, |
| CONFIG_GXL_USB_U2_PORT_NUM, |
| CONFIG_GXL_USB_U3_PORT_NUM, |
| }; |
| #endif /*CONFIG_USB_XHCI_AMLOGIC*/ |
| |
| #ifdef CONFIG_AML_HDMITX20 |
| static void hdmi_tx_set_hdmi_5v(void) |
| { |
| } |
| #endif |
| |
| #ifdef CONFIG_AML_SPIFC |
| /* |
| * BOOT_4: NOR_D:reg7[13], clr reg7[31] reg7[22] |
| * BOOT_5: NOR_Q:reg7[12], clr reg7[31] reg7[21] |
| * BOOT_6: NOR_C:reg7[11], clr reg7[31] reg7[20] |
| * BOOT_11: NOR_CS:reg7[10],clr reg7[28] |
| */ |
| #define SPIFC_NUM_CS 1 |
| static int spifc_cs_gpios[SPIFC_NUM_CS] = {49/*BOOT_11*/}; |
| |
| static int spifc_pinctrl_enable(void *pinctrl, bool enable) |
| { |
| unsigned int val; |
| |
| val = readl(P_PERIPHS_PIN_MUX_7); |
| val &= ~((1<<13)|(1<<12)|(1<<11)|(1<<10)); |
| if (enable) { |
| val |= (1<<13)|(1<<12)|(1<<11); |
| val &= ~((1<<31)|(1<<28)|(1<<22)|(1<<21)|(1<<20)); |
| } |
| writel(val, P_PERIPHS_PIN_MUX_7); |
| return 0; |
| } |
| |
| static const struct spifc_platdata spifc_platdata = { |
| .reg = 0xffd14000, |
| .mem_map = 0xfb000000, |
| .pinctrl_enable = spifc_pinctrl_enable, |
| .num_chipselect = SPIFC_NUM_CS, |
| .cs_gpios = spifc_cs_gpios, |
| }; |
| |
| U_BOOT_DEVICE(spifc) = { |
| .name = "spifc", |
| .platdata = &spifc_platdata, |
| }; |
| #endif /* CONFIG_AML_SPIFC */ |
| |
| extern void aml_pwm_cal_init(int mode); |
| |
| int board_init(void) |
| { |
| #ifdef CONFIG_AML_V2_FACTORY_BURN |
| aml_try_factory_usb_burning(0, gd->bd); |
| #endif// #ifdef CONFIG_AML_V2_FACTORY_BURN |
| aml_pwm_cal_init(0); |
| #ifdef CONFIG_USB_XHCI_AMLOGIC_GXL |
| board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST); |
| #endif /*CONFIG_USB_XHCI_AMLOGIC*/ |
| |
| #ifdef CONFIG_AML_NAND |
| extern int amlnf_init(unsigned char flag); |
| amlnf_init(0); |
| #endif |
| return 0; |
| } |
| |
| #ifdef CONFIG_BOARD_LATE_INIT |
| int board_late_init(void){ |
| //update env before anyone using it |
| run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\ |
| "if test ${reboot_mode} = factory_reset; then "\ |
| "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0); |
| run_command("if itest ${upgrade_step} == 1; then "\ |
| "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); |
| /*add board late init function here*/ |
| int ret; |
| ret = run_command("store dtb read $dtb_mem_addr", 1); |
| if (ret) { |
| printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__); |
| #ifdef CONFIG_DTB_MEM_ADDR |
| char cmd[64]; |
| printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR); |
| sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR); |
| ret = run_command(cmd, 1); |
| if (ret) { |
| printf("%s(): %s fail\n", __func__, cmd); |
| } |
| #endif |
| } |
| |
| /* load unifykey */ |
| run_command("keyunify init 0x1234", 0); |
| |
| #ifdef CONFIG_AML_VPU |
| vpu_probe(); |
| #endif |
| vpp_init(); |
| #ifdef CONFIG_AML_HDMITX20 |
| hdmi_tx_set_hdmi_5v(); |
| hdmi_tx_init(); |
| #endif |
| #ifdef CONFIG_AML_LCD |
| lcd_probe(); |
| #endif |
| |
| #ifdef CONFIG_AML_V2_FACTORY_BURN |
| /*aml_try_factory_sdcard_burning(0, gd->bd);*/ |
| #endif// #ifdef CONFIG_AML_V2_FACTORY_BURN |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_AML_TINY_USBTOOL |
| int usb_get_update_result(void) |
| { |
| unsigned long upgrade_step; |
| upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16); |
| printf("upgrade_step = %d\n", (int)upgrade_step); |
| if (upgrade_step == 1) |
| { |
| run_command("defenv", 1); |
| run_command("setenv upgrade_step 2", 1); |
| run_command("saveenv", 1); |
| return 0; |
| } |
| else |
| { |
| return -1; |
| } |
| } |
| #endif |
| |
| phys_size_t get_effective_memsize(void) |
| { |
| // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 |
| #if defined(CONFIG_SYS_MEM_TOP_HIDE) |
| return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; |
| #else |
| return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4); |
| #endif |
| } |